Electronic device

Abstract

To obtain an electronic apparatus in which a signal is transmitted in an excellent quality between a memory chip and a controller chip.SOLUTION: A memory chip 1 comprises: a first terminal block 11-1 for a signal of a first byte of a first channel; a second terminal block 11-2 for a signal of a second byte of the first channel; a third terminal block 12-1 for a signal of the first byte of a second channel; and a fourth terminal block 12-2 for a signal of the second byte of the second channel. A multilayer substrate 3 comprises: a first wiring group; a second wiring group; a third wiring group; and a fourth wiring group, which electrically connect each of the first terminal block 11-1, the second terminal block 11-2, the third terminal block 12-1, the fourth terminal block 12-1, and a controller chip 2. Then, the first wiring group and the fourth wiring group are mounted onto a first specific layer of a plurality of wiring layers of the multilayer substrate 3. The second wiring group and the third wiring group are mounted onto a second specific layer that is different from the first specific layer of the plurality of wiring layers.SELECTED DRAWING: Figure 3

Description

[Technical field]

[0001] The present invention relates to an electronic device. [Background technology]

[0002] In a certain electronic device, a DDR memory chip and a memory controller chip are mounted on a multi-layer board, and the two are electrically connected by wiring in a plurality of wiring layers (see, for example, Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] JP 2017-33993 A Summary of the Invention [Problem to be solved by the invention]

[0004] In a multi-channel memory chip, the number of signal lines electrically connecting the memory chip and the controller chip increases, which shortens the distance between the signal lines, making crosstalk more likely to occur and potentially reducing the quality of signals transmitted between the memory chip and the controller chip.

[0005] The present invention has been made in consideration of the above problems, and has an object to provide an electronic device in which signals are transmitted with good quality between a memory chip and a controller chip. [Means for solving the problem]

[0006] The electronic device according to the present invention includes a multilayer substrate having a plurality of wiring layers, a memory chip mounted on the multilayer substrate, and a controller chip mounted on the multilayer substrate. The memory chip includes a first terminal group for a first byte signal of a first channel, a second terminal group for a second byte signal of the first channel, a third terminal group for a first byte signal of a second channel, and a fourth terminal group for a second byte signal of the second channel. The multilayer substrate includes a first wiring group electrically connecting the first terminal group to the controller chip, a second wiring group electrically connecting the second terminal group to the controller chip, a third wiring group electrically connecting the third terminal group to the controller chip, and a fourth wiring group electrically connecting the fourth terminal group to the controller chip. The first wiring group and the fourth wiring group are mounted on a first specific layer of the plurality of wiring layers, and the second wiring group and the third wiring group are mounted on a second specific layer different from the first specific layer of the plurality of wiring layers. Furthermore, it includes at least one of the following configurations (A) and (B). (A) The memory chip includes a first side facing the controller chip and two second sides vertically extending from both ends of the first side. In the first specific layer, at least a part of at least one of the first wiring group and the fourth wiring group is disposed via the second side, and the remaining parts of the first wiring group and the fourth wiring group are disposed via the first side. In the second specific layer, at least a part of at least one of the second wiring group and the third wiring group is disposed via the second side, and the remaining parts of the second wiring group and the third wiring group are disposed via the first side. (B) The memory chip includes a fifth terminal group for signals common to the first byte and the second byte of the first channel and a sixth terminal group for signals common to the first byte and the second byte of the second channel. The multilayer substrate further includes a fifth wiring group electrically connecting the fifth terminal group and the controller chip and a sixth wiring group electrically connecting the sixth terminal group and the controller chip. The fifth wiring group and the sixth wiring group are mounted on a wiring layer different from the first specific layer and the second specific layer. Effect of the Invention

[0007] According to the present invention, an electronic device can be obtained in which signals are transmitted with good quality between a memory chip and a controller chip.

[0008] The above and other objects, features and advantages of the present invention will become more apparent from the following detailed description taken in conjunction with the accompanying drawings. [Brief description of the drawings]

[0009]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

[0010] Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

[0011] Fig. 1 is a perspective view showing the configuration of an electronic device according to an embodiment of the present invention. The electronic device shown in Fig. 1 includes a memory chip 1, a controller chip 2, and a multi-layer substrate 3. The multi-layer substrate 3 has multiple wiring layers (e.g., six or eight layers), and the memory chip 1 and the controller chip 2 are mounted on (the first layer of) the multi-layer substrate 3. The controller chip 2 is an ASIC (Application Specific Integrated Circuit) that transmits and receives various signals to and from the memory chip 1 and reads and writes data from and to the memory chip 1.

[0012] Fig. 2 is a top view illustrating the arrangement position of controller chip 2 with respect to memory chips on multilayer substrate 3 of the electronic device shown in Fig. 1. Fig. 3 is a top view illustrating the arrangement positions of terminal groups of memory chip 1 and controller chip 2 in Fig. 2.

[0013] As shown in FIG. 2, the memory chip 1 includes a first terminal group 11-1 for signals of the first byte Byte0 of the first channel ch0, a second terminal group 11-2 for signals of the second byte Byte1 of the first channel ch0, a third terminal group 12-1 for signals of the first byte Byte0 of the second channel ch1, and a fourth terminal group 12-2 for signals of the second byte Byte1 of the second channel ch1.

[0014] Furthermore, the memory chip 1 has a fifth terminal group 11-3 for signals common to the first byte Byte0 and the second byte Byte1 of the first channel ch0, and a sixth terminal group 12-3 for signals common to the first byte Byte0 and the second byte Byte1 of the second channel ch1.

[0015] Memory chip 1 is a substantially rectangular plate-like chip, and has ball terminals of terminal groups 11-1, 11-2, 12-1, and 12-2 on its back surface. Terminal groups 11-1 and 11-2 are arranged along the short side surfaces of memory chip 1, terminal groups 12-1 and 12-2 are arranged along the short side surfaces of memory chip 1, terminal groups 11-1 and 12-1 are arranged along the long side surfaces of memory chip 1, and terminal groups 11-2 and 12-2 are arranged along the long side surfaces of memory chip 1.

[0016] 2, the controller chip 2 includes a terminal group 2a for interfacing with the memory chip 1. The controller chip 2 is a plate-like chip having a substantially rectangular (or substantially square) shape, and includes ball terminals of the terminal group 2a. The terminal group 2a is disposed on the back surface of the controller chip 2, adjacent to a specific side surface of the substantially rectangular (or substantially square) shape.

[0017] Specifically, as shown in FIG. 3, the terminal group 2a includes a terminal group 21-1, a terminal group 21-2, a terminal group 21-3, a terminal group 21-3a, a terminal group 22-1, a terminal group 22-2, a terminal group 22-3, a terminal group 22-3a, and a terminal group .

[0018] Terminal group 21-1 is a terminal group for signals of a first byte Byte0 of a first channel ch0 of memory chip 1, and corresponds to first terminal group 11-1 of memory chip 1. Terminal group 21-2 is a terminal group for signals of a second byte Byte1 of a first channel ch0 of memory chip 1, and corresponds to second terminal group 11-2 of memory chip 1.

[0019] The terminal group 21-3 is a terminal group for signals common to the first byte Byte0 and the second byte Byte1 of the first channel ch0 of the memory chip 1, and corresponds to a part of the fifth terminal group 11-3 of the memory chip 1.

[0020] The terminal group 21-3a is a terminal group for a clock signal common to the first byte Byte0 and the second byte Byte1 of the first channel ch0 of the memory chip 1, and corresponds to a part of the fifth terminal group 11-3 of the memory chip 1.

[0021] Terminal group 22-1 is a terminal group for signals of the first byte Byte0 of the second channel ch1 of memory chip 1, and corresponds to third terminal group 12-1 of memory chip 1. Terminal group 22-2 is a terminal group for signals of the second byte Byte1 of the second channel ch1 of memory chip 1, and corresponds to fourth terminal group 12-2 of memory chip 1.

[0022] Terminal group 22-3 is a terminal group for signals common to the first byte Byte0 and the second byte Byte1 of second channel ch1 of memory chip 1, and corresponds to a part of sixth terminal group 12-3 of memory chip 1.

[0023] Terminal group 22-3a is a terminal group for a clock signal common to the first byte Byte0 and the second byte Byte1 of the second channel ch1 of memory chip 1, and corresponds to a part of sixth terminal group 12-3 of memory chip 1.

[0024] The terminal group 23 is a terminal group for grounding.

[0025] Memory chip 1 is then placed on multilayer substrate 3 so that the above-mentioned side surface of controller chip 2 and the longitudinal direction of memory chip 1 are approximately parallel. The longitudinal size of memory chip 1 is also smaller than the above-mentioned size of controller chip 2. By placing memory chip 1 in this manner, the wiring between them is distributed along the longitudinal direction of memory chip 1, which increases the distance between the wiring and reduces crosstalk.

[0026] On the other hand, multilayer substrate 3 includes a first wiring group that electrically connects first terminal group 11-1 and controller chip 2 (terminal group 21-1), a second wiring group that electrically connects second terminal group 11-2 and controller chip 2 (terminal group 21-2), a third wiring group that electrically connects third terminal group 12-1 and controller chip 2 (terminal group 22-1), and a fourth wiring group that electrically connects fourth terminal group and controller chip 2 (terminal group 22-2). The first wiring group, second wiring group, third wiring group, and fourth wiring group are mounted on specific wiring layers in multilayer substrate 3 as described later.

[0027] The first wiring group and the fourth wiring group are implemented in one (single) wiring layer among multiple wiring layers in the multi-layer substrate 3, and the second wiring group and the third wiring group are implemented in one (single) wiring layer among multiple wiring layers in the multi-layer substrate 3, which is different from the wiring layer of the first wiring group and the fourth wiring group.

[0028] In this embodiment, these wiring layers are each internal wiring layers (i.e., wiring layers other than the wiring layers at both ends in the thickness direction of the multilayer substrate 3) among the multiple wiring layers in the multilayer substrate 3. By using these wiring layers as internal wiring layers, the impedance characteristics of the wiring in these wiring layers become closer, and the difference in the amount of signal delay becomes smaller.

[0029] In this embodiment, when the multilayer substrate 3 is an eight-layer substrate, the first wiring group and the fourth wiring group are mounted on one of the third layer and the sixth layer, and the second wiring group and the third wiring group are mounted on the other of the third layer and the sixth layer. Also, in this embodiment, when the multilayer substrate 3 is a six-layer substrate, the first wiring group and the fourth wiring group are mounted on one of the third layer and the fourth layer, and the second wiring group and the third wiring group are mounted on the other of the third layer and the fourth layer. Note that the wiring layer on which the memory chip 1 and the controller 2 are mounted is the first layer, and the bottom layer is the sixth layer (in the case of a six-layer substrate) or the eighth layer (in the case of an eight-layer substrate). Also, an insulating layer is provided between two adjacent wiring layers.

[0030] In this embodiment, the memory chip 1 is an LPDDR4 (Low Power Double Data Rate 4) memory chip, the first terminal group 11-1 includes terminals for DQS / DQ / DM signals of the first byte Byte0 of the first channel ch0, the second terminal group 11-2 includes terminals for DQS / DQ / DM signals of the second byte Byte1 of the first channel ch0, the third terminal group 12-1 includes terminals for DQS / DQ / DM signals of the first byte Byte0 of the second channel ch1, and the fourth terminal group 12-2 includes terminals for DQS / DQ / DM signals of the second byte Byte1 of the second channel ch1.

[0031] It should be noted that the DQS signal is a data strobe signal, the DQ signal is a data bus signal, and the DM signal is a data mask signal; these signals are signals for data transmission.

[0032] Fig. 4 is a top view illustrating the wiring groups (first wiring group and fourth wiring group) of the DQS / DQ / DM signal of the first byte of the first channel and the DQS / DQ / DM signal of the second byte of the second channel. Fig. 5 is a top view illustrating the wiring groups (second wiring group and third wiring group) of the DQS / DQ / DM signal of the second byte of the first channel and the DQS / DQ / DM signal of the first byte of the second channel.

[0033] As shown in FIG. 4, the first wiring group 31 and the fourth wiring group 34 are implemented in one wiring layer (first specific layer), and as shown in FIG. 5, the second wiring group 32 and the third wiring group 33 are implemented in another wiring layer (second specific layer).

[0034] Further, the memory chip 1 has a first side surface 1a facing the controller chip 2 and two second side surfaces 1b extending perpendicularly from both ends of the first side surface 1a. In the first specific layer, as shown in FIG. 4, at least a part of at least one of the first wiring group 31 and the fourth wiring group 34 (only the fourth wiring group 34 in FIG. 4) is disposed via the second side surface 1b, and the remaining parts of the first wiring group 31 and the fourth wiring group 34 are disposed via the first side surface 1a. In the second specific layer, as shown in FIG. 5, at least a part of at least one of the second wiring group 32 and the third wiring group 33 (only the second wiring group 32 in FIG. 5) is disposed via the second side surface 1b, and the remaining parts of the second wiring group 32 and the third wiring group 33 are disposed via the first side surface 1a.

[0035] On the other hand, multilayer substrate 3 further includes a fifth wiring group that electrically connects fifth terminal group 11-3 and controller chip 2 (terminal groups 21-3, 21-3a) and a sixth wiring group that electrically connects sixth terminal group 12-3 and controller chip 2 (terminal groups 22-3, 22-3a). The fifth wiring group and the sixth wiring group are mounted on specific wiring layers in multilayer substrate 3 as described below.

[0036] In this embodiment, the fifth wiring group and the sixth wiring group are mounted on a wiring layer different from the wiring layer on which the above-mentioned first wiring group, second wiring group, third wiring group, and fourth wiring group are provided.

[0037] In this embodiment, the memory chip 1 is an LPDDR4 memory chip, the fifth terminal group 11-3 includes terminals for CA / CS / CKE / ODT signals and clock signals common to the first byte Byte0 and the second byte Byte1 of the first channel ch0, and the sixth terminal group 12-3 includes terminals for CA / CS / CKE / ODT signals and clock signals common to the first byte Byte0 and the second byte Byte1 of the second channel ch1.

[0038] Note that the CA signal is a command address signal, the CS signal is a chip select signal, the CKE signal is a clock enable signal, and the ODT signal is an on / off control signal for the on-die termination of the CA signal; these signals are setting signals.

[0039] Fig. 6 is a top view illustrating a wiring group of a clock signal common to the first byte and the second byte of the first channel and a wiring group of a clock signal common to the first byte and the second byte of the second channel. Fig. 7 is a top view illustrating a wiring group of a CA / CS / CKE / ODT signal common to the first byte and the second byte of the first channel and a wiring group of a CA / CS / CKE / ODT signal common to the first byte and the second byte of the second channel.

[0040] 6, among the fifth and sixth wiring groups, the wirings 35a and 36a for the clock signals for the first channel ch0 and the second channel ch1 are mounted on the first layer. Since the clock signal is a high-frequency signal, the wirings 35a and 36a are mounted on the first layer to prevent reflection at the via holes.

[0041] Also, as shown in FIG. 7, among the fifth and sixth wiring groups, wiring groups 35, 36 for CA / CS / CKE / ODT signals for the first channel ch0 and the second channel ch1 are implemented on the bottom layer (the sixth layer in the case of a six-layer board or the eighth layer in the case of an eight-layer board).

[0042] The wiring groups in the wiring layers other than the first layer are electrically connected to the corresponding terminal groups using via holes.

[0043] As described above, according to the above embodiment, the memory chip 1 includes the first terminal group 11-1 for signals of the first byte Byte0 of the first channel ch0, the second terminal group 11-2 for signals of the second byte Byte1 of the first channel ch0, the third terminal group 12-1 for signals of the first byte Byte0 of the second channel ch1, and the fourth terminal group 12-2 for signals of the second byte Byte1 of the second channel ch1. The multilayer substrate 3 includes a first wiring group 31 electrically connecting the first terminal group 11-1 and the controller chip 2, a second wiring group 32 electrically connecting the second terminal group 11-2 and the controller chip 2, a third wiring group 33 electrically connecting the third terminal group 12-1 and the controller chip 2, and a fourth wiring group 34 electrically connecting the fourth terminal group 12-2 and the controller chip 2. The first wiring group 31 and the fourth wiring group 34 are mounted on a first specific layer among the multiple wiring layers of the multilayer substrate 3, and the second wiring group 32 and the third wiring group 33 are mounted on a second specific layer different from the first specific layer among the multiple wiring layers.

[0044] As a result, the first wiring group 31, the second wiring group 32, the third wiring group 33, and the fourth wiring group 34 are arranged in a dispersed manner, thereby reducing crosstalk and transmitting signals with good quality between the memory chip 1 and the controller chip 2.

[0045] It should be noted that various changes and modifications to the above-described embodiments will be apparent to those skilled in the art. Such changes and modifications may be made without departing from the spirit and scope of the subject matter and without diminishing its intended advantages. In other words, such changes and modifications are intended to be included within the scope of the claims. [Industrial Applicability]

[0046] The present invention is applicable to, for example, electronic devices having DDR memories. [Explanation of symbols]

[0047] 1 Memory chip 2 Controller chip 3 Multilayer board 11-1 1st terminal group 11-2 2nd terminal group 11-3 5th terminal group 12-1 3rd terminal group 12-2 4th terminal group 12-3 6th terminal group 31 1st wiring group 32 2nd wiring group 33 Third wiring group 34 4th wiring group 35 Wiring group (part of an example of the fifth wiring group) 35a Wiring (part of an example of the fifth wiring group) 36 Wiring group (part of an example of the sixth wiring group) 36a Wiring (part of an example of the sixth wiring group)

Claims

1. A multilayer substrate having a plurality of wiring layers; A memory chip mounted on the multilayer substrate; A controller chip mounted on the multilayer substrate, the memory chip comprises a first terminal group for signals of a first byte of a first channel, a second terminal group for signals of a second byte of the first channel, a third terminal group for signals of a first byte of a second channel, and a fourth terminal group for signals of a second byte of the second channel; the multilayer substrate includes a first wiring group electrically connecting the first terminal group and the controller chip, a second wiring group electrically connecting the second terminal group and the controller chip, a third wiring group electrically connecting the third terminal group and the controller chip, and a fourth wiring group electrically connecting the fourth terminal group and the controller chip, the first wiring group and the fourth wiring group are mounted on a first specific layer of the plurality of wiring layers; the second wiring group and the third wiring group are mounted on a second specific layer of the plurality of wiring layers that is different from the first specific layer; the memory chip has a first side facing the controller chip and two second sides extending perpendicularly from either end of the first side; In the first specific layer, at least a portion of at least one of the first wiring group and the fourth wiring group is disposed via the second side surface side, and remaining portions of the first wiring group and the fourth wiring group are disposed via the first side surface side, In the second specific layer, at least a part of at least one of the second wiring group and the third wiring group is disposed via the second side surface side, and the remaining part of the second wiring group and the third wiring group is disposed via the first side surface side; An electronic device characterized by:

2. 2. The electronic device according to claim 1, wherein the first specific layer and the second specific layer are inner wiring layers among the plurality of wiring layers.

3. A multilayer substrate having a plurality of wiring layers; A memory chip mounted on the multilayer substrate; A controller chip mounted on the multilayer substrate, the memory chip comprises a first terminal group for signals of a first byte of a first channel, a second terminal group for signals of a second byte of the first channel, a third terminal group for signals of a first byte of a second channel, and a fourth terminal group for signals of a second byte of the second channel; the multilayer substrate includes a first wiring group electrically connecting the first terminal group and the controller chip, a second wiring group electrically connecting the second terminal group and the controller chip, a third wiring group electrically connecting the third terminal group and the controller chip, and a fourth wiring group electrically connecting the fourth terminal group and the controller chip, the first wiring group and the fourth wiring group are mounted on a first specific layer of the plurality of wiring layers; the second wiring group and the third wiring group are mounted on a second specific layer of the plurality of wiring layers that is different from the first specific layer; the memory chip includes a fifth terminal group for signals common to the first byte and the second byte of the first channel, and a sixth terminal group for signals common to the first byte and the second byte of the second channel; the multilayer substrate further includes a fifth wiring group electrically connecting the fifth terminal group and the controller chip, and a sixth wiring group electrically connecting the sixth terminal group and the controller chip, the fifth wiring group and the sixth wiring group are mounted on a wiring layer different from the first specific layer and the second specific layer; An electronic device characterized by:

4. The memory chip is a LPDDR4 memory chip, the first terminal group includes a terminal for a DQ signal of the first byte of the first channel; the second terminal group includes a terminal for a DQ signal of the second byte of the first channel; the third terminal group includes a terminal for a DQ signal of the first byte of the second channel, the fourth terminal group includes a terminal for a DQ signal of the second byte of the second channel; 4. The electronic device according to claim 1, wherein:

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