Semiconductor device and its manufacturing method

Abstract

To provide a semiconductor device with excellent reliability.SOLUTION: A semiconductor device has a substrate 2 having flexibility, a thin-film transistor 3 disposed on one side of the substrate 2, a protection layer 4 disposed to cover the thin-film transistor 3, a planarization layer 5 disposed on the other surface side of the substrate 2, through-through electrodes 6a, 6b, 6c disposed through the substrate 2 and the planarization layer 5, and a wiring layer 7a, 7b, 7c disposed on the planarization layer 5 and electrically connected to the thin-film transistor 3 through the through-through electrodes 6a, 6b, 6c, and a groove 14 is notched around the thin-film transistor 3.SELECTED DRAWING: Figure 2

Description

[Technical field]

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof. [Background technology]

[0002] For example, there is a tiling display formed by arranging multiple panel units. Tiling displays have the advantage that they can be made in a variety of sizes, shapes, and aspect ratios (see, for example, Non-Patent Documents 1 and 2 below).

[0003] However, in the case of a typical panel unit, it is necessary to form signal wiring electrically connected to thin film transistors (TFTs) on the periphery of the panel unit, making it difficult to eliminate the bezel. Therefore, when such panel units are arranged to form a tiling display, there is an issue that the seams between the panel units become noticeable due to the bezel.

[0004] As a solution to such problems, a semiconductor device called a three-dimensional wiring TFT has been proposed, in which signal wiring, etc. is arranged on the back side of the panel unit, and the TFT on the front side of the panel unit is electrically connected to the signal wiring, etc. via a through electrode that penetrates the panel unit. This makes it possible to realize a bezel-less panel unit that does not require signal wiring, etc., on the periphery of the panel unit, and to form a seamless (unnoticeable) tiling display.

[0005] In recent years, the development of elemental technologies for such bezel-less panel units has been progressing. For example, a three-dimensional wiring TFT (semiconductor device) has been developed in which an extremely thin polyimide (PI) film substrate is used, signal wiring, etc. is arranged on the back side of the film substrate, and the TFT on the front side of the film substrate and the signal wiring, etc. are electrically connected via a through electrode that penetrates the film substrate (for example, see Non-Patent Document 3 below).

[0006] When manufacturing such a three-dimensional wiring TFT, the TFT is formed while forming a base film (such as a silicon nitride film) and a gate insulating film (such as a silicon oxide film) on the front side of the film substrate. Meanwhile, through holes, three-dimensional wiring, back electrodes, etc. are formed by processing the back side of the film substrate. [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] D. Nakamura et al., SID 2015 DIGEST, pp.1031-1034 (2015) [Non-Patent Document 2] G. Biwa et al., SID 2019 DIGEST, pp.121-124 (2019) [Non-Patent Document 3] Tsuji et al., Proceedings of the 2021 Institute of Electronics, Information and Communication Engineers General Conference, p.28 (2021) Summary of the Invention [Problem to be solved by the invention]

[0008] Incidentally, when processing the back surface side of the above-mentioned film substrate, it is necessary to invert the front and back surfaces of the film substrate to expose the back surface of the film substrate.

[0009] Specifically, a film substrate is formed on a first glass substrate, and after forming TFTs on the front side of this film substrate, a second glass substrate is attached to the front side of the substrate via an adhesive layer. The first glass substrate is then peeled off and removed from the back side of the film substrate by irradiation with laser light L. This makes it possible to process the film substrate from the back side.

[0010] However, when the film substrate formed on the first glass substrate is transferred to the second glass substrate, the film substrate may stretch partially due to stress generated in the undercoat film and gate insulating film formed on the front side of the film substrate, and wrinkles may occur. Such wrinkles occur in random locations and directions due to the floating of the film substrate.

[0011] Therefore, if wrinkles occur at a position on the film substrate that overlaps with the TFT in a planar view, processing from the back side of the film substrate (forming through holes, three-dimensional wiring, back electrodes, etc.) becomes difficult, making it impossible to form the above-mentioned three-dimensional wiring TFT.

[0012] The present invention has been proposed in view of the above-mentioned conventional circumstances, and has an object to provide a semiconductor device having excellent reliability and a method for manufacturing such a semiconductor device with improved yield when manufacturing such a semiconductor device. [Means for solving the problem]

[0013] In order to achieve the above object, the present invention provides the following means. [1] A flexible substrate; A thin film transistor disposed on one surface side of the substrate; a protective layer disposed to cover the thin film transistor; a planarization layer disposed on the other surface side of the substrate; a through electrode disposed in a state of penetrating the substrate and the planarization layer; a wiring layer disposed on the planarization layer and electrically connected to the thin film transistor via the through electrode; The semiconductor device further comprises a groove that cuts out a periphery of the thin film transistor. [2] The semiconductor device according to [1], wherein the grooves are provided along each of the four directions surrounding the thin film transistor. [3] The semiconductor device according to [2], wherein the groove portion is provided so as to surround the thin film transistor. [4] The semiconductor device according to any one of [1] to [3], wherein the protective layer is provided in a state of being embedded in the groove. [5] The thin film transistor includes a semiconductor layer, a gate electrode arranged to intersect with the semiconductor layer, an insulating layer arranged between the semiconductor layer and the gate electrode, and a source electrode and a drain electrode arranged on both sides of the gate electrode of the semiconductor layer, The semiconductor device according to any one of claims [1] to [4], characterized in that the wiring layer and the through electrode are provided corresponding to each of the gate electrode, the source electrode, and the drain electrode. [6] The semiconductor device according to [5], wherein the groove portion is provided to a depth sufficient to divide the insulating layer in a thickness direction. [7] The semiconductor layer includes an oxide semiconductor, the insulating layer includes an inorganic oxide film, The semiconductor device according to [5] or [6], wherein the protective layer includes an organic film. [8] The semiconductor device according to any one of the above [1] to [7], wherein the substrate is a film substrate having a thickness of 15 μm or less. [9] The semiconductor device according to any one of [1] to [8], wherein wrinkles are formed in positions along the groove portion except for an area of ​​the substrate that overlaps with the thin film transistor in a planar view.

[10] forming a flexible substrate on a first support substrate; forming a thin film transistor on one surface of the substrate; forming a groove portion by cutting out a periphery of the thin film transistor; forming a protective layer covering the thin film transistor; attaching a second support substrate onto the protective layer via an adhesive layer; peeling off the first support substrate; forming a planarization layer on the other surface side of the substrate; forming a through electrode penetrating the substrate and the planarization layer; forming a wiring layer on the planarization layer, the wiring layer being electrically connected to the thin film transistor via the through electrode; and peeling off the second support substrate. Effect of the Invention

[0014] As described above, according to the present invention, it is possible to provide a semiconductor device having excellent reliability, and a method for manufacturing such a semiconductor device with improved yield when manufacturing such a semiconductor device. [Brief description of the drawings]

[0015] [Figure 1] 1 is a plan view showing a configuration of a semiconductor device according to an embodiment of the present invention; [Diagram 2] 2 is a cross-sectional view of the semiconductor device taken along line AA shown in FIG. [Diagram 3] 3A to 3C are cross-sectional views for sequentially illustrating the manufacturing process of the semiconductor device shown in FIG. 2. [Figure 4] 3A to 3C are cross-sectional views for sequentially illustrating manufacturing steps of the semiconductor device shown in FIG. 2. [Diagram 5] 3A to 3C are cross-sectional views for sequentially illustrating the manufacturing process of the semiconductor device shown in FIG. 2. [Figure 6] 3A to 3C are cross-sectional views for sequentially illustrating manufacturing steps of the semiconductor device shown in FIG. 2. [Figure 7] 3A to 3C are cross-sectional views for sequentially illustrating the manufacturing process of the semiconductor device shown in FIG. 2. [Figure 8] 3A to 3C are cross-sectional views for sequentially illustrating the manufacturing process of the semiconductor device shown in FIG. 2. [Figure 9] 3A to 3C are cross-sectional views for sequentially illustrating the manufacturing process of the semiconductor device shown in FIG. 2. [Figure 10] 3A to 3C are cross-sectional views for sequentially illustrating manufacturing steps of the semiconductor device shown in FIG. 2. [Figure 11]3A to 3C are cross-sectional views for sequentially illustrating the manufacturing process of the semiconductor device shown in FIG. 2. [Figure 12] 3A to 3C are cross-sectional views for sequentially illustrating the manufacturing process of the semiconductor device shown in FIG. 2. [Figure 13] 1. FIG. 4 is a plan view showing another example of the configuration of the groove portion included in the semiconductor device shown in FIG. [Figure 14] 4 is a plan view showing the distribution of wrinkles generated in the semiconductor device of Example 1. FIG. [Figure 15] 13 is a plan view showing the distribution of wrinkles generated in the semiconductor device of Comparative Example 1. FIG. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0016] Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings. In addition, the drawings used in the following description may show characteristic parts in an enlarged scale for the sake of convenience in order to make the characteristics easier to understand, and the dimensional ratios of each component may not necessarily be the same as in reality. Furthermore, the materials, dimensions, etc. exemplified in the following description are merely examples, and the present invention is not necessarily limited to them, and may be appropriately modified and implemented within the scope of the present invention.

[0017] (Semiconductor Device) First, as one embodiment of the present invention, a semiconductor device 1 shown in, for example, FIGS. 1 and 2 will be described. Fig. 1 is a plan view showing the configuration of the semiconductor device 1. Fig. 2 is a cross-sectional view of the semiconductor device 1 taken along line AA shown in Fig. 1.

[0018] As shown in Figures 1 and 2, the semiconductor device 1 of this embodiment comprises a flexible substrate 2, a thin film transistor (hereinafter referred to as "TFT") 3 arranged on one surface (front surface) of the substrate 2, a protective layer 4 arranged to cover the TFT 3, a planarization layer 5 arranged on the other surface (rear surface) of the substrate 2, through electrodes 6a, 6b, and 6c arranged to penetrate the substrate 2 and the planarization layer 5, and wiring layers 7a, 7b, and 7c arranged on the planarization layer 5 and electrically connected to the TFT 3 via the through electrode 6.

[0019] The semiconductor device 1 of this embodiment is preferably used as a three-dimensional wiring TFT for driving a flexible display such as a liquid crystal display panel, an organic electroluminescence (EL) display panel, etc. This makes it possible to realize a bezel-less panel unit that does not require signal wiring or the like to be formed on the periphery of the panel unit, and to form a seamless (unnoticeable) tiling display.

[0020] In the semiconductor device 1 of the present embodiment, a configuration in which a plurality of TFTs 3 are arranged in a matrix on the surface of the substrate 2 is illustrated as an example, but the present invention is not necessarily limited to this configuration.

[0021] The substrate 2 is a film substrate having a thickness of 15 μm or less, and may be a film substrate made of resin (plastic), such as polyimide (PI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), etc. The lower limit of the thickness of the substrate 2 is about 2 μm.

[0022] The TFT3 has a semiconductor layer 8, a gate electrode 9 arranged so as to intersect with the semiconductor layer 8, an insulating layer 10 arranged between the semiconductor layer 8 and the gate electrode 9, and a source electrode 11 and a drain electrode 12 arranged on either side of the gate electrode of the semiconductor layer 8.

[0023] The insulating layer 10 is formed by sequentially laminating an undercoat film 10a formed on the substrate 2 and a gate insulating film 10b covering the gate electrode 9 formed on the undercoat film 10a.

[0024] The undercoat film 10a is provided to improve adhesion to the substrate 2 and to enhance the barrier properties of the substrate 2. The undercoat film 10a is made of, for example, silicon nitride (SiN x ) film and silicon oxide (SiO 2 ) or a laminate film thereof can be used.

[0025] The gate insulating film 10b is provided to insulate the semiconductor layer 8 from the gate electrode 9 and to apply a voltage to the semiconductor layer 8 via the gate electrode 9. The gate insulating film 10b is made of, for example, silicon nitride (SiN x ) film and silicon oxide (SiO 2 ) or a laminate film thereof can be used.

[0026] The semiconductor layer 8 is disposed on the gate insulating film 10b overlapping with the gate electrode 9 in a plan view, and forms an active layer in which a channel is formed. For the semiconductor layer 8, for example, an oxide semiconductor containing at least indium, tin, zinc, and oxygen (In-Sn-Zn-O) as main components, or an oxide semiconductor containing at least indium, gallium, zinc, and oxygen (In-Ga-Zn-O) can be used.

[0027] The gate electrode 9 is disposed on the base film 10a. For the gate electrode 9, for example, a metal such as titanium (Ti), chromium (Cr), aluminum (Al), molybdenum (Mo), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, or a conductive film in which two or more kinds of these metals are laminated can be used.

[0028] The source electrode 11 and the drain electrode 12 are disposed continuously on the semiconductor layer 8 and the gate insulating film 10b, respectively. For the source electrode 11 and the drain electrode 12, for example, a metal such as titanium (Ti), chromium (Cr), aluminum (Al), molybdenum (Mo), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, or a conductive film in which two or more kinds of these metals are laminated can be used.

[0029] In the TFT3 of this embodiment, the semiconductor layer 8 is provided on the gate insulating film 10b that covers the above-mentioned gate electrode 9, but the gate electrode 9 may be provided on the gate insulating film 10b that covers the semiconductor layer 8.

[0030] The protective layer 4 is provided to protect the TFT 3. For the protective layer 4, an organic film such as an epoxy resin, an olefin resin, an acrylic resin, or a polyimide resin can be used.

[0031] The planarization layer 5 is provided to planarize the back surface side of the substrate 2. For example, an organic film such as an epoxy resin, an olefin resin, an acrylic resin, or a polyimide resin can be used.

[0032] The through electrodes 6a, 6b, 6c are provided corresponding to each of the gate electrode 9, the source electrode 11, and the drain electrode 12. Specifically, at a position corresponding to the gate electrode 9, the through electrode 6a is provided in a state of being embedded in a hole 13a that penetrates the underlayer film 10a, the substrate 2, and the planarization layer 5. On the other hand, at positions corresponding to the source electrode 11 and the drain electrode 12, the through electrodes 6b, 6c are provided in a state of being embedded in holes 13b, 13c that penetrate the gate insulating film 10b, the underlayer film 10a, the substrate 2, and the planarization layer 5, respectively.

[0033] The through electrodes 6a, 6b, 6c are formed by embedding a conductive material such as a metal or an alloy thereof, such as titanium (Ti), chromium (Cr), aluminum (Al), molybdenum (Mo), gold (Au), silver (Ag), or copper (Cu), into the holes 13c, 13b, 13c.

[0034] The wiring layers 7a, 7b, 7c are provided corresponding to each of the gate electrode 9, the source electrode 11, and the drain electrode 12. Specifically, at a position corresponding to the gate electrode 9, the wiring layer 7a electrically connected to the gate electrode 9 via the through electrode 6a is provided. On the other hand, at positions corresponding to the source electrode 11 and the drain electrode 12, the wiring layers 7b, 7c electrically connected to the source electrode 11 and the drain electrode 12 via the through electrodes 6b, 6c, respectively, are provided.

[0035] The wiring layer 7 may be made of a metal such as titanium (Ti), chromium (Cr), aluminum (Al), molybdenum (Mo), gold (Au), silver (Ag), copper (Cu), or an alloy thereof, or a conductive film in which two or more of these metals are stacked.

[0036] Incidentally, in the semiconductor device 1 of this embodiment, a groove 14 is provided that cuts out the periphery of the TFT 3. The groove 14 is provided along each of the four directions surrounding the TFT 3. The groove 14 is provided in a state surrounding the TFT 3. Since the semiconductor device 1 of this embodiment has a configuration in which a plurality of TFTs 3 are arranged in a matrix on the surface of the substrate 2, a plurality of grooves 14 that separate adjacent TFTs 3 are arranged in a lattice pattern.

[0037] The groove 14 is provided to a depth sufficient to divide at least the insulating layer 10 (the base film 10a and the gate insulating film 10b) in the thickness direction. The protective layer 4 is provided in a state of being embedded in the groove 14.

[0038] (Method of manufacturing a semiconductor device) Next, a method for manufacturing the semiconductor device 1 will be described with reference to FIGS. 3 to 12 are cross-sectional views for sequentially explaining the manufacturing process of the semiconductor device 1. As shown in FIG.

[0039] 3, a flexible substrate 2 is formed on a first support substrate 21. Specifically, a glass substrate is used as the first support substrate 21, and a coating liquid containing a resin material that will become the substrate 2 is applied onto the first support substrate 21 by spin coating to form a coating film, and then the coating film is dried to form the substrate 2.

[0040] 4, the TFT 3 is formed on one surface (front surface) of the substrate 2. Specifically, an undercoat film 10a, a gate electrode 9, a gate insulating film 10b, a semiconductor layer 8, a source electrode 11, and a drain electrode 12 are formed in this order on the substrate 2 using a normal semiconductor manufacturing process.

[0041] 5, grooves 14 are formed by cutting out the periphery of the TFT 3. Specifically, a plurality of grooves 14 are formed by dry etching, arranged in a lattice pattern, to a depth sufficient to divide the insulating layer 10 (base film 10a and gate insulating film 10b) in the thickness direction and separating adjacent TFTs 3.

[0042] 6, a protective layer 4 is formed to cover the TFT 3. Specifically, a coating liquid containing the organic material that will become the protective layer 4 is applied by spin coating onto the first support substrate 21 to form a coating film, and then the coating film is dried to form the protective layer 4. In this way, the protective layer 4 is formed so as to cover the surface of the first support substrate 21 while being embedded in the grooves 14.

[0043] 7, a second support substrate 22 is attached onto the protective layer 4 via an adhesive layer S. Specifically, a glass substrate is used for the second support substrate 22, and a fix film is used for the adhesive layer S, so that the second support substrate 22 is attached onto the protective layer 4 via the adhesive layer S.

[0044] Next, the first support substrate 21 is peeled off, as shown in Fig. 8. Specifically, using laser lift-off, a laser beam is irradiated from the first support substrate 21 side to ablate the interface between the substrate 2 and the first support substrate 21, thereby removing the first support substrate 21 peeled off from the substrate 2.

[0045] 9, a planarization layer 5 is formed on the other surface (rear surface) of the substrate 2. Specifically, a coating liquid containing an organic material that will become the planarization layer 5 is applied onto the second support substrate 22 by spin coating to form a coating film, and then the coating film is dried to form the planarization layer 5.

[0046] Next, as shown in FIG. 10, through electrodes 6a, 6b, and 6c that penetrate the substrate 2 and the planarization layer 5 are formed. Specifically, after forming hole portions 13a, 13b, and 13c by dry etching at positions corresponding to the gate electrode 9, the source electrode 11, and the drain electrode 12, respectively, the through electrodes 6a, 6b, and 6c are formed by embedding a conductive material that becomes the above-described through electrodes 6a, 6b, and 6c into these hole portions 13a, 13b, and 13c.

[0047] Next, as shown in FIG. 11, a wiring layer 7 that is electrically connected to the TFT 3 through the through electrode 6 is formed on the planarization layer 5. Specifically, wiring layer portions 7a, 7b, and 7c that are electrically connected to the gate electrode 9, the source electrode 11, and the drain electrode 12 through the through electrodes 6a, 6b, and 6c, respectively, are formed at positions corresponding to the gate electrode 9, the source electrode 11, and the drain electrode 12.

[0048] Next, as shown in FIG. 12, the second support substrate 22 peeled off together with the adhesive layer S from the protective layer 4 is removed. By going through the above steps, the semiconductor device 1 can be manufactured.

[0049] In the manufacturing method of the semiconductor device 1 of the present embodiment, by forming the groove portion 14 that notches the periphery of the above-described TFT 3, when the first support substrate 21 is peeled off from the substrate 2, wrinkles are formed at positions along the groove portion 14 excluding the region (the region inside the groove portion) that overlaps with the TFT 3 of the substrate 2 in a plan view.

[0050] That is, in this manufacturing method of the semiconductor device 1, when transferring the substrate 2 formed on the first support substrate 21 to the second support substrate 22, it is possible to control the generation location and direction of wrinkles generated due to the floating of the substrate 2.

[0051] Thereby, it is possible to prevent wrinkles from occurring at positions that overlap with the TFT 3 of the substrate 2 in a plan view, and it is possible to accurately form the through electrodes 6a, 6b, 6c and the wiring layer portions 7a, 7b, 7c by processing from the back side of the substrate 2.

[0052] As described above, in the semiconductor device 1 of this embodiment, by providing the groove portion 14 that cuts out the periphery of the above-mentioned TFT 3, it is possible to improve the reliability of the semiconductor device 1 while preventing wrinkles from occurring in the area that overlaps with the TFT 3 of the substrate 2 in a planar view (the area inside the groove portion 14).

[0053] Moreover, the method for manufacturing the semiconductor device 1 of this embodiment makes it possible to manufacture such highly reliable semiconductor devices 1 with good yield.

[0054] The present invention is not necessarily limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the semiconductor device 1, the above-mentioned groove portion 14 is configured to surround the TFT 3, but it may also be configured such that multiple groove portions 14 (four per TFT 3 in FIG. 13) are provided separated around the TFT 3, as shown in FIG. 13.

[0055] Specifically, in the configuration shown in FIG. 13, a plurality of grooves 14 are provided along each of the four directions (top, bottom, left, right) surrounding the TFT 3, and adjacent grooves are provided at the four corners of the TFT 3 so as to be spaced apart from each other.

[0056] This configuration also makes it possible to improve the reliability of the semiconductor device 1 while preventing wrinkles from occurring in the region of the substrate 2 that overlaps with the TFT 3 in a plan view (the region inside the groove 14). EXAMPLES

[0057] The effects of the present invention will be more clearly understood by the following examples. Note that the present invention is not limited to the following examples, and can be modified as appropriate without departing from the spirit and scope of the present invention.

[0058] Example 1 In Example 1, first, a coating liquid containing polyimide was applied onto a first glass substrate by spin coating to form a coating film, and then the coating film was dried to form a film substrate having a thickness of 2 μm.

[0059] Next, 192 TFTs (16 × 12) were formed in a matrix on the film substrate. For the TFTs, a 50 nm thick undercoat film made of silicon nitride was formed on the film substrate by sputtering, a 100 nm thick gate electrode made of molybdenum alloy was formed on the undercoat film by sputtering, a 200 nm thick gate insulating film made of silicon oxide was formed on the undercoat film by sputtering, and a 30 nm thick semiconductor layer made of In-Sn-Zn-O was formed on the gate insulating film by sputtering. After that, a heat treatment was performed in the atmosphere at 300°C for 1 hour using a hot plate, and then a 50 nm thick source electrode and drain electrode made of molybdenum alloy were formed.

[0060] Next, a plurality of grooves were formed by dry etching, arranged in a lattice pattern, to a depth sufficient to divide the base film and the gate insulating film in the thickness direction, and to separate adjacent TFTs.

[0061] Next, an organic insulating film was applied onto the first glass substrate by spin coating to form a protective layer having a thickness of 1.4 μm, followed by heat treatment at 150° C. for 1 hour in the atmosphere.

[0062] Next, a second glass substrate was attached onto the protective layer 4 using a fix film.

[0063] Next, the first glass substrate that had been peeled off from the film substrate was removed by laser lift-off, by irradiating the first glass substrate side with an ultraviolet (UV) laser having a wavelength of 355 nm.

[0064] Next, an organic insulating film was applied onto the second glass substrate by spin coating to form a planarizing layer having a thickness of 1.4 μm, followed by heat treatment at 150° C. for 1 hour in the atmosphere.

[0065] Next, holes were formed by dry etching at positions corresponding to the gate electrode, source electrode, and drain electrode, and then a molybdenum alloy was filled into these holes to form through electrodes.

[0066] Next, wiring layers of a molybdenum alloy having a thickness of 200 nm were formed by sputtering at positions corresponding to the gate electrode, source electrode, and drain electrode.

[0067] Next, the second glass substrate peeled off together with the fix film from the protective layer was removed to produce the semiconductor device of Example 1. The distribution of wrinkles T generated in the semiconductor device of Example 1 is shown in FIG. 14. In FIG. 14, the same reference numerals are used for the same parts as those in the semiconductor device 1.

[0068] In the semiconductor device of Example 1, as shown in Fig. 14, when the film substrate formed on the first glass substrate is transferred to the second glass substrate, wrinkles T caused by lifting of the film substrate are formed at positions along the grooves except for the area (the area inside the grooves) that overlaps with the TFT of the film substrate in a plan view. That is, in the semiconductor device of Example 1, the location and direction of wrinkles T are controlled by the grooves.

[0069] Furthermore, in the semiconductor device of Example 1, out of the 192 TFTs, the number of TFTs in which wrinkles occurred in the area overlapping the TFT in a planar view (the area inside the groove portion) was 4, which is an occurrence rate of approximately 2%.

[0070] Comparative Example 1 In Comparative Example 1, a semiconductor device was fabricated in the same manner as in Example 1, except that the step of forming the grooves described above was omitted. The distribution of wrinkles T generated in the semiconductor device of Comparative Example 1 is shown in Fig. 15. In Fig. 15, the same reference numerals are used to denote the same parts as in the semiconductor device 1 described above.

[0071] In the semiconductor device of Comparative Example 1, as shown in Figure 15, when the film substrate formed on the first glass substrate is transferred to the second glass substrate, wrinkles T caused by the floating of the film substrate are formed in random locations and directions.

[0072] In addition, in the semiconductor device of Comparative Example 1, of the 192 TFTs, the number of TFTs in which wrinkles occurred in the area overlapping the TFT in a planar view (the area inside the groove) was 102, which is approximately 53%.

[0073] As described above, in the semiconductor device of Example 1, by providing a groove portion that cuts out the periphery of the above-mentioned TFT, it is possible to significantly suppress the occurrence of wrinkles T in the area that overlaps with the TFT of the film substrate in a planar view, compared to the semiconductor device of Comparative Example 1. [Explanation of symbols]

[0074] REFERENCE SIGNS LIST 1...Semiconductor device 2...Substrate 3...Thin film transistor (TFT) 4...Protective layer 5...Planarization layer 6a, 6b, 6c...Through electrodes 7a, 7b, 7c...Wiring layer 8...Semiconductor layer 9...Gate electrode 10...Insulating layer 10a...Base film 10b...Gate insulating film 11...Source electrode 12...Drain electrode 13a, 13b, 13c...Hole 14...Groove 21...First support substrate 22...Second support substrate T...Wrinkle S...Adhesive layer

Claims

1. A flexible substrate; A thin film transistor disposed on one surface side of the substrate; a protective layer disposed to cover the thin film transistor; a planarization layer disposed on the other surface side of the substrate; a through electrode disposed in a state of penetrating the substrate and the planarization layer; a wiring layer disposed on the planarization layer and electrically connected to the thin film transistor via the through electrode; The semiconductor device further comprises a groove that cuts out a periphery of the thin film transistor.

2. 2. The semiconductor device according to claim 1, wherein the grooves are provided along the four sides surrounding the thin film transistor.

3. 3. The semiconductor device according to claim 2, wherein the groove portion is provided so as to surround the thin film transistor.

4. 4. The semiconductor device according to claim 1, wherein the protective layer is provided in a state of being embedded in the groove.

5. The thin film transistor includes a semiconductor layer, a gate electrode arranged to intersect with the semiconductor layer, an insulating layer arranged between the semiconductor layer and the gate electrode, and a source electrode and a drain electrode arranged on both sides of the gate electrode of the semiconductor layer, 5. The semiconductor device according to claim 1, wherein the wiring layer and the through electrode are provided corresponding to the gate electrode, the source electrode, and the drain electrode, respectively.

6. 6. The semiconductor device according to claim 5, wherein the groove is provided to a depth sufficient to divide the insulating layer in a thickness direction.

7. the semiconductor layer includes an oxide semiconductor, the insulating layer includes an inorganic oxide film, 7. The semiconductor device according to claim 5, wherein the protective layer includes an organic film.

8. 8. The semiconductor device according to claim 1, wherein the substrate is a film substrate having a thickness of 15 μm or less.

9. 9. The semiconductor device according to claim 1, wherein wrinkles are formed in the substrate at positions along the groove portion except for an area overlapping with the thin film transistor in a plan view.

10. forming a flexible substrate on a first support substrate; forming a thin film transistor on one surface of the substrate; forming a groove portion by cutting out a periphery of the thin film transistor; forming a protective layer covering the thin film transistor; attaching a second support substrate onto the protective layer via an adhesive layer; peeling off the first support substrate; forming a planarization layer on the other surface side of the substrate; forming a through electrode penetrating the substrate and the planarization layer; forming a wiring layer on the planarization layer, the wiring layer being electrically connected to the thin film transistor via the through electrode; and peeling off the second support substrate.

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