Formation of Semiconductor Devices within Silicon Carbide

Abstract

To provide a semiconductor device in a silicon carbide.SOLUTION: A method includes: a step of providing a first layer (101) of an epitaxial silicon carbide supported by a silicon carbide base (130); a step of providing a second layer (102) of the epitaxial silicon carbide on the first layer; a step of forming a plurality of semiconductor devices (105, 105-1, 105-2, and 105-3) in the second layer (102); and a step of separating the base (130) from the second layer (102) in the first layer (101). The first layer (101) has a plurality of gaps.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Various examples of the present invention generally relate to the formation of semiconductor devices within silicon carbide. More particularly, various examples of the present invention relate to techniques that enable the reuse of silicon carbide substrates.

Background Art

[0002] Power semiconductor devices have the ability to switch high voltages and / or high currents. Thus, power semiconductor devices have applications in various fields such as high voltage DC transmission in, for example, offshore wind power plants, smart grid components, railway traction, etc.

[0003] Power semiconductor devices are often formed of silicon carbide (SiC). SiC is a semiconductor material having a relatively wide bandgap. This promotes the ability to switch high voltages and / or high currents.

Prior Art Documents

Non-Patent Documents

[0004]

Non-Patent Document 1

Non-Patent Document 2

[0005] One drawback of currently available SiC power semiconductor devices is their high cost (at least in comparison to silicon semiconductors), which is caused, for example, by high substrate prices and / or relatively low manufacturing yields. Accordingly, there is a need for advanced techniques for forming semiconductor devices in SiC.

Means for Solving the Problem

[0006] Method embodiments include providing a first layer of SiC. The first layer is supported by a SiC substrate. The method also includes providing a second layer of epitaxial SiC on the first layer. The method also includes forming a plurality of semiconductor devices within the second layer. The method also includes separating the substrate from the second layer within the first layer. The first layer includes a plurality of voids.

[0007] Method embodiments include providing a first layer of porous SiC supported by a SiC substrate. The method also includes providing a second layer of epitaxial SiC on the first layer. The method also includes forming a plurality of semiconductor devices within the second layer. The method also includes separating the substrate from the second layer within the first layer.

[0008] Wafer embodiments include a SiC substrate and a layer of SiC supported by the SiC substrate. The layer includes a plurality of voids.

[0009] Wafer embodiments include a SiC substrate and a porous layer of SiC supported by the SiC substrate.

[0010] It should be understood that the above-described features, as well as those described hereinafter, can be used not only in the individual combinations shown, but also in other combinations, or in isolation, without departing from the scope of the invention.

Brief Description of the Drawings

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Best Mode for Carrying Out the Invention

[0012] Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail. It should be understood that the following description of the embodiments should not be construed in a limiting sense. The scope of the present invention is not intended to be limited by the embodiments or drawings described hereinafter, and these embodiments and drawings are merely for illustrative purposes.

[0013] The drawings are to be regarded as being schematic representations and elements shown in the drawings are not necessarily shown to scale. Rather, the various elements are represented so that their function and general purpose will be apparent to those skilled in the art.

[0014] Hereinafter, a technique for providing a semiconductor device within a wide bandgap semiconductor material will be described. The semiconductor device is defined within a semiconductor material provided on or supported by a substrate. Hereinafter, when the semiconductor device is "defined in" the semiconductor material, this may mean that the semiconductor device includes and / or is based on the material.

[0015] As used herein, the term "horizontal direction" is intended to describe a direction that is substantially parallel to the first or main horizontal plane of the semiconductor substrate or body. This may be, for example, the surface of a wafer or die. Also, often the horizontal direction is also referred to as the lateral direction.

[0016] As used herein, the term "vertical direction" is intended to describe a direction that is substantially perpendicular to the first surface, i.e., parallel to the vertical direction of the first surface of the semiconductor substrate or body.

[0017] A semiconductor device can be implemented by a two-terminal device such as a diode, for example. Also, the semiconductor device may be a three-terminal device such as, for example, a field effect transistor (FET), specifically, a metal oxide semiconductor field effect transistor (MOSFET), an insulated gate bipolar transistor (IGBT), a junction field effect transistor (JFET), and a thyristor. Further, the semiconductor device can also include more than three terminals.

[0018] Hereinafter, various examples of steps for processing a wide bandgap semiconductor material will be described. The term "wide bandgap semiconductor material" as used herein is intended to represent a semiconductor material having a bandgap greater than 1 eV. Wide bandgap semiconductor materials such as SiC or gallium nitride (GaN) each have a high breakdown electric field strength (e.g., at least 2.5 MV / cm) and a high critical avalanche electric field strength. Therefore, in comparison with semiconductor materials having a relatively small bandgap, it is possible to select the doping of the semiconductor region to be relatively high, and as a result, the on-state resistance value Ron (also referred to as the on-resistance Ron) is reduced. In the following, the examples are mainly described in relation to SiC as a wide bandgap semiconductor material, but similar techniques can be easily applied to other types or kinds of wide bandgap semiconductor materials.

[0019] In various examples described herein, the semiconductor device defined within SiC may be a power semiconductor device. The term "power semiconductor device" as used herein is intended to represent a semiconductor device on a single chip having the switching ability of high voltage (specifically, at least 250 V, or at least 600 V) and high current. In other words, a power semiconductor device is typically intended for high current, usually within the range of amperes.

[0020] The semiconductor device can be formed within an epitaxial layer of SiC provided on a SiC substrate. This layer will hereinafter be referred to as the device layer.

[0021] In principle, the device layer can include sub-layers. For example, a sub-layer can implement the drain region of the semiconductor device. The drain region can be highly doped. The thickness of the drain region may be such as to impart sufficient structural stability to the die obtained when separating the device layer from the substrate. For example, the thickness of the drain region may range from at least 2 μm to a maximum of 200 μm, or from at least 10 μm to a maximum of 100 μm, or from at least 20 μm to a maximum of 50 μm. Optionally, a further sub-layer of the device layer can implement a buffer region. For example, in the case of an FET as a semiconductor device, an n-doped buffer layer can be implemented by individual sub-layers. In the case of a diode as a semiconductor device, the n-doped buffer layer can correspond to a contact layer. In the case of a bipolar diode, an n-doped backside emitter region can be implemented by individual sub-layers. A further sub-layer can implement a drift region.

[0022] The device layer can be provided by using an epitaxial growth process to obtain crystalline SiC for high charge carrier mobility. Generally, the growth rate of the epitaxial growth process may vary across the thickness of the device layer, i.e., along the vertical direction, for example, vary for each different sub-layer.

[0023] To form the semiconductor device, front-side processing can be implemented. In this case, one or more electrical contacts can be formed for electrical contact with different regions. For example, in the case of an FET as a semiconductor device, a source contact, a drain contact, and a gate contact can be formed.

[0024] According to the reference implementation form, in particular, when obtaining a semiconductor device on a die of a specific thickness, for example, removal of a large portion of the substrate may be required through grinding. The removed material can be discarded. Due to the relatively high cost of the SiC substrate, as a result, at least in comparison with silicon, the unit cost / semiconductor device can be relatively high. This cost can be significantly reduced, for example, by allowing reuse of the substrate.

[0025] Hereinafter, techniques for promoting the reuse of the SiC substrate multiple times will be described. That is, a plurality of sets of semiconductor devices can be sequentially formed on the SiC substrate. Each set of semiconductor devices can include an array of laterally spaced semiconductor devices. By separating each set of semiconductor devices from the substrate, the substrate can then be reused to form further sets of semiconductor devices. Thereby, by reusing the SiC substrate for a plurality of sets of semiconductor layers, the unit cost / semiconductor device can be reduced.

[0026] One limitation of semiconductor devices based on SiC is the tendency to result in a high defect density in the SiC substrate. For example, defects can diffuse and propagate during current conduction by the semiconductor device. Stacking defects are an example of such defects. Such a phenomenon is called bipolar degradation. See, for example, (Non-Patent Document 1). Stacking defects can result in an increase in the ON-state resistance value Ron in a transistor or an increase in the forward voltage in a diode. Such defects can reduce the yield in the manufacture of semiconductor devices. As a result, also in this case, the unit cost / semiconductor device increases. In addition, the operational reliability of the semiconductor device can also deteriorate.

[0027] Typically, the defect density may require countermeasures to avoid malfunction of semiconductor devices. In one example, such defects can be suppressed by implementing a highly doped buffer region between the substrate and the epitaxial layer of SiC on which the semiconductor device is formed. This buffer region promotes a high recombination rate of positively charged electrical carriers (holes) injected from the front side of the die. Thereby, the growth of stacking defects can be suppressed. See (Non-Patent Document 2). In this case, a porous layer of SiC is provided between the epitaxial SiC layer and the substrate. Thereby, the density of defects in the epitaxial SiC layer can be significantly reduced when compared to the density of defects in the substrate.

[0028] Hereinafter, a technique for promoting suppression of the propagation of any crystal defects in the substrate into the device layer will be described. Thereby, it is possible to increase the yield in the manufacture of semiconductor devices, which is also useful for reducing the unit cost / semiconductor device as a result. Furthermore, the likelihood of failure of the semiconductor device during use can also be reduced.

[0029] In various examples described herein, such effects can be achieved by bonding the substrate and the device layer with a further layer. This layer will hereinafter be referred to as the interface layer.

[0030] The interface layer is supported by the substrate. For example, the interface layer can be defined in a state adjacent to the front side of the substrate. For example, the interface layer can be defined within the substrate in a state adjacent to the front side. Alternatively, instead of or in addition to this, the interface layer may be defined on the substrate in a state adjacent to the front side, that is, the interface layer may be provided on top of the substrate by using a growth process. There may be no other layers between the substrate and the interface layer. For example, in some embodiments, the interface layer may not be attached to the substrate using an adhesive or the like.

[0031] The lateral dimension of the interface layer can correspond to the lateral dimension of the substrate. For example, the interface layer can extend laterally across the entire front side of the substrate, or at least across 90% of the area of the front side of the substrate.

[0032] The vertical dimension of the interface layer, that is, the thickness of the interface layer, can be in the range from at least 1 μm to, for example, up to 50 μm, such as at least 2 μm, or for example, at least 5 μm, and up to, for example, a maximum of 25 μm, or for example, a maximum of 10 μm. The thickness of the interface layer can be at most 50% of the thickness of the device layer, optionally at most 20% of the thickness of the device layer, and further optionally at most 5% of the thickness of the device layer.

[0033] The vertical dimension of the substrate can be in the range of 100 μm to 800 μm, such as in the range of 200 μm to 500 μm.

[0034] In principle, the thickness of the interface layer may be small when compared to the thickness of the substrate. For example, the thickness of the interface layer may not exceed 20% of the substrate, or optionally 10%.

[0035] The material of the interface layer can correspond to that of the substrate and / or the device layer. Usually, the substrate, the interface layer, and the device layer are made of SiC. The term "made of" should be understood within the normal manufacturing tolerances and does not exclude the presence of impurities and / or dopants. The interface layer can be made of epitaxial SiC, but this is not essential. In some scenarios, the atomic order of SiC may vary between the substrate, the interface layer, and the device layer. For example, the substrate, the interface layer, and the device layer could all contain SiC in a crystalline form, but, for example, of different polytypes. Also, the substrate, the interface layer, and the device layer could all contain SiC in a crystalline form and in the same polytype.

[0036] In principle, crystalline SiC for the device layer and, optionally, for the interface layer can be provided by using an epitaxial growth process in the various examples described herein. This can include steps using chemical vapor deposition (CVD) and / or sublimation epitaxy. For example, it is possible to utilize a step-controlled epitaxial growth process; see, for example, (Non-Patent Document 3). Such a step-controlled epitaxial growth process typically depends on the off-orientation direction in relation to the crystal plane of the substrate. For example, in the case of 4H-SiC, this crystal plane can be the SiC(1,1,-2,0) plane. Usually, in the case of 4H-SiC, the off-direction has an angle of 4° to 5° with the SiC(1,1,-2,0) plane. Crystal growth is implemented on the terraces or islands on the surface of the material. The absorbed CVD species are incorporated within the steps of such terraces.

[0037] The interface layer can be designed to provide various functions. For example, the interface layer can be designed to suppress the propagation of defects such as stacking defects and / or dislocations from the substrate into the device layer. Alternatively, instead of or in addition to this, the interface layer can also be designed to facilitate the reuse of the substrate in a further process of forming a further semiconductor device by enabling the separation of the substrate from the device layer.

[0038] Accordingly, the method includes the step of providing an interface layer of SiC. The interface layer is supported by a SiC substrate. The method also includes the step of providing a device layer of epitaxial SiC on the interface layer. The method also includes the step of forming a plurality of semiconductor devices within the second layer. The method also includes the step of separating the substrate from the second layer within the first layer.

[0039] To provide such functions, there are various design options available for the interface layer. For example, the interface layer can include a plurality of cavities. The cavities can be defined within the material of the interface layer.

[0040] In the various examples described herein, different types of cavities can be relied upon. In one example, the cavities can be defined by a porous interface layer. Such a porous interface layer can be obtained from electrochemical etching, such as photoelectrochemical etching. In this case, the use of epitaxial SiC is not usually essential. Usually, the aggregate of pores in such a porous interface layer may not show a preferred direction or an order in any large order. Rather, the pores in the porous layer can show a statistical distribution of size and / or shape and / or orientation. The pores could form an interconnected network. In other words, the porous layer could be a sponge-type porous layer.

[0041] In another example, the cavity can be implemented by a void. The voids typically have a tailored size and / or shape and / or orientation. For example, the voids can be defined in a top-down process by using precisely controlled process parameters. Thus, while the voids can also exhibit a distribution of size and / or shape and / or orientation, the width of such a distribution may be significantly smaller than the width of the corresponding distribution in the pores of the reference porous layer. Specifically, the voids may be aligned with a preferred direction and can exhibit an order from largest to smallest.

[0042] In any case, within the interface layer, providing cavities, such as pores and / or voids for example, can assist in reducing the defect density within the device layer. Also, the reduction in the structural rigidity and / or stability of the interface layer induced by the cavities will support the separation of the substrate from the device layer.

[0043] The following examples will be described below. Example 1. The method comprises - providing a first layer (101) of silicon carbide (e.g., epitaxial silicon carbide) supported by a silicon carbide substrate (130); - providing a second layer (102) of epitaxial silicon carbide on the first layer (101); - forming a plurality of semiconductor devices (105, 105-1, 105-2, 105-3) within the second layer (102); - separating the substrate (130) from the second layer (102) in the first layer (101); and wherein in this case, the first layer (101) has a plurality of voids (150).

[0044] Example 2. The method of Example 1, wherein In this case, the step of providing the first layer (101) includes the step of using a trench filling process (2101) to define a plurality of voids (150).

[0045] Example 3. The method of Example 2, wherein in this case, the trench filling process (2101) has at least one of dry etching of a trench (160) defined by lithography, damage implantation of the trench (160), and electrochemical etching of the trench (160).

[0046] Example 4. The method of any one of the above examples, wherein in this case, the step of providing the first layer (101) has the step of using an epitaxial growth process.

[0047] Example 5. The method of Example 2 or 3 and Example 4, wherein in this case, the epitaxial growth process used to provide the first layer (101) is a step-controlled epitaxial growth process using an off-orientation direction (161) in relation to the crystal plane of the substrate (130), in this case, the trench (160) of the trench filling process (2101) has an angle (162) of at least 1°, optionally at least 5°, and further optionally at least 85° with respect to the off-orientation direction (161).

[0048] Example 6. The method of Example 4 or 5, wherein in this case, the growth rate of the step-controlled epitaxial growth process of the first layer (101) is within a lateral overgrowth region (965) to enclose the voids (150) of the plurality of voids (150).

[0049] Example 7. The method of any one of the above examples, wherein in this case, the step of providing the first layer (101) has the step of using a reflow process. In this case, the temperature of the reflow process is within the lateral closure region so as to surround the voids (150) of the plurality of voids (150).

[0050] Example 8. A method according to any one of the above examples, wherein the step of providing the first layer (101) has a step of etching the ridges (152) between adjacent voids (150) of the plurality of voids (150).

[0051] Example 9. A method according to any one of the above examples, wherein in this case, the first layer (101) has a first sub-layer (101-1) having a first void density (301) and further has a second sub-layer (101-2) having a second void density (302), wherein in this case, the first sub-layer (101-1) of the first layer (101) is disposed between the second sub-layer (101-2) of the first layer (101) and the substrate (130), wherein in this case, the first void density (301) is greater than the second void density (302).

[0052] Example 10. A method according to any one of the above examples, wherein in this case, the step of providing the second layer (102) has a step of using an epitaxial growth process, wherein in this case, the second layer (102) has a first sub-layer (102-1) and a second sub-layer (102-2), wherein in this case, the first sub-layer (102-1) of the second layer (102) is disposed between the second sub-layer (102-2) of the second layer (102) and the first layer (101), wherein in this case, the growth rate (312-1) of the epitaxial growth process of the first sub-layer (102-1) of the second layer (102) is smaller than the growth rate (312-2) of the epitaxial growth process of the second sub-layer (102-2) of the second layer (102).

[0053] Example 11. A method according to any one of the above examples, In this case, the voids (150) of the plurality of voids (150) have an elongated shape, In this case, the longitudinal axes (151) of the voids (150) in the plurality of voids (150) are aligned with each other.

[0054] Example 12. A method according to any one of the above examples, In this case, the voids (150) of the plurality of voids (150) are arranged in a lateral pattern defined within the first layer (101).

[0055] Example 13. A method according to any one of the above examples, In this case, the first layer (101) has a dopant that defines the resistivity of the first layer (101), and the resistivity of this first layer (101) is smaller than the resistivity of the substrate (130).

[0056] Example 14. A method according to any one of the above examples, - A step of planarizing the first layer (101) before the step of providing the second layer (102), further comprising.

[0057] Example 15. A method according to any one of the above examples, In this case, the first layer (101) contains a light-absorbing material, In this case, the step of separating the second layer (102) from the substrate (130) has a step of damaging the first layer (101) using laser light (250) absorbed by the light-absorbing material.

[0058] Example 16. The method of Example 15, In this case, the light-absorbing material has at least one of a dopant and at least one carbon layer obtained from the annealing process used to provide the first layer (101).

[0059] Example 17. A method according to any one of the above examples, In this case, the step of separating the second layer (102) from the substrate (130) is, - injecting a fluid into a plurality of voids (150) and cooling the fluid below its freezing point; - a high-speed pressure change, and - micro electrical discharge machining in the first layer (101), having at least one of.

[0060] Example 18. A method according to any one of the above examples, - providing a protective material at a vertical edge etched in the second layer (102); further comprising.

[0061] Example 19. A method according to any one of the above examples, - dicing the second layer (102) in the vertical direction to singulate semiconductor devices (105, 105-1, 105-2, 105-3) of a plurality of semiconductor devices (105, 105-1, 105-2, 105-3); further comprising, wherein the second layer (102) is diced before the step of separating the substrate (130) from the second layer (102).

[0062] Example 20. A method according to any one of the above examples, - depositing a backside metallization layer on the remaining portion of the first layer (101) after separating the substrate (130) from the second layer (102); further comprising.

[0063] Example 21. A method according to any one of the above examples, wherein the first layer (101) is provided at a first growth rate (311-1, 311-2), wherein the second layer (102) is provided at a second growth rate (312-1, 312-2), wherein the first growth rate is smaller than the second growth rate.

[0064] Example 22. A method - providing a first layer (101) of porous silicon carbide; - providing a second layer (102) of epitaxial silicon carbide on the first layer (101); - forming a plurality of semiconductor devices (105, 105-1, 105-2, 105-3) within the second layer (102); - separating the substrate (130) from the second layer (102) in the first layer (101); and having.

[0065] Example 23. A method according to any one of the above examples, wherein the thickness (102A) of the second layer (102) is at least 20 μm, optionally at least 50 μm, or wherein the thickness (102A) of the second layer (102) is at most 30 μm, optionally at most 20 μm.

[0066] Example 24. A method according to any one of the above examples, - defining a drift region of a plurality of semiconductor devices (105, 105-1, 105-2, 105-3) within the second layer (102); - defining a drain region or a backside emitter region of a plurality of semiconductor devices (105, 105-1, 105-2, 105-3) within the second layer (102); and further having. The thickness of the drain region or the backside emitter region may be greater than or less than the thickness of the drift region.

[0067] Example 25. A method according to any one of the above examples, wherein the step of providing the first layer (101) comprises using an electrochemical etching process.

[0068] Example 26. A wafer comprising - a silicon carbide substrate (130); - A first layer (101) of silicon carbide supported by a silicon carbide substrate (130), having, in this case, the first layer (101) has a plurality of voids (150).

[0069] Example 27. A wafer according to Example 26, - A second layer (102) of epitaxial silicon carbide having drift regions of a plurality of semiconductor devices and further having drain regions or backside emitter regions of the plurality of semiconductor devices, further having. The thickness of the drain region or the backside emitter region may be greater than or less than the thickness of the drift region.

[0070] Example 28. A wafer according to Example 26 or Example 27, in this case, the thickness (102A) of the second layer (102) is at least 20 μm, optionally at least 50 μm, or in this case, the thickness (102A) of the second layer (102) is at most 30 μm, optionally at most 20 μm.

[0071] The above examples can be combined with each other to provide further examples. For example, even in the scenario where the first layer contains pores, it would be possible to apply techniques for separating the second layer from the substrate described in the context of a first layer containing voids. Further techniques described in the context of the above methods can be applied to examples related to wafers. For example, a wafer can be manufactured using such methods.

[0072] FIG. 1 is a flowchart of a method according to various examples. The method according to FIG. 1 corresponds to an exemplary process according to the techniques described herein.

[0073] In block 1001, a first layer is provided. The first layer is supported by a substrate. The first layer can be provided within or on the substrate. The substrate is provided by a wafer.

[0074] The first layer corresponds to the interface layer described above. For example, the interface layer can include a plurality of cavities implemented by pores or voids, for example.

[0075] In the scenario where the interface layer includes a plurality of voids, the interface layer can be provided by using an epitaxial growth process. Thus, the interface layer can be manufactured from epitaxial SiC. Another option is to define the interface layer within a substrate also manufactured from epitaxial SiC, but in such a scenario, a dedicated epitaxial growth process for providing the interface layer may not be required.

[0076] In a further scenario where the interface layer has pores, the interface layer can be provided by using electrochemical etching. In such an example, electrochemical etching based on water-soluble hydrofluoric acid (HF) can include several additives such as surfactants, ethanol, isopropanol, etc. The concentration of HF is usually in the range of less than 50% by volume. The ratio between water-soluble HF and the additives can be 3:1, 2:1, 1:2, 1:1, 3:1, 1:4 (measured by weight). Depending on the voltage conditions for anodization, it is possible to use a voltage of less than 100V, or in some cases, an even lower voltage (less than 10V) can also be used depending on whether the process is carried out under additional UV illumination. The pore density of the porous layer (often also referred to as the porosity) can be set by the current density. For example, the normal current density is 10 μA / cm 2 ~100 mA / cm 2It is within the range. The pore density is a measure of the empty space within the material of the interface layer. Usually, this is defined as the ratio of the volume of the empty material to the total volume and can thus vary between 0% and 100%.

[0077] After etching, rinsing and drying can be carried out. In principle, the interface layer could be manufactured from 4H-SiC polytype. Specifically, in such a configuration, when the (0001) silicon plane faces outwards (when compared with the carbon plane of TIFF0007683057000001.tif13161), electrochemical etching could be carried out. Another option would be to manufacture the interface layer from 6H-SiC polytype.

[0078] Next, in block 1002, a second layer is provided. The second layer is provided on the interface layer. The second layer corresponds to the device layer described above.

[0079] Block 1002 can include an epitaxial growth process for depositing a drain region such as an n-doped drain region, a buffer region such as an n-doped buffer region, and / or a backside emitter region on the interface. For a device having a blocking capability of less than 3.5 kV, the thickness of the drain region or the backside emitter region may be greater than the thickness of the drift region.

[0080] Block 1002 can include an epitaxial growth process for depositing a drift region.

[0081] Block 1002 can include pre-treatment with hydrogen to facilitate a growth process without defects. See, for example, (Non-Patent Document 4).

[0082] In block 1003, a plurality of semiconductor devices are formed within the device layer. This can include front-side processing that defines the body region, source region, emitter region, and / or electrical contacts of the semiconductor device.

[0083] In block 1004, the substrate is separated from the device layer at the interface layer. This can include the step of supporting the device layer on the carrier prior to applying a force to trigger the separation.

[0084] Block 1004 results in one or more dies or chips that include a plurality of semiconductor devices. Also, block 1004 results in the remaining portion of the substrate. For example, any remaining portion of the interface layer on the substrate can be removed, e.g., by grinding or polishing. For example, ultra-high-speed polishing can be utilized.

[0085] In optional block 1005, a backside metallization layer is deposited on the backside of one or more dies obtained from block 1004. Typically, the backside metallization layer can be deposited on the remaining portion of the interface layer that is attached to the device layer after the separation step.

[0086] Block 1005 is optional. In some scenarios, instead of performing block 1005, it is possible to provide dopants within the interface layer in block 1001, thereby making the resistivity of the interface layer smaller than the resistivity of the substrate. As a result, the remaining portion of the interface layer adjacent to the device layer can exhibit a high conductivity that promotes ohmic backside contact. The increased roughness of the backside provided by the remaining interface layer can contribute to the reduction of the contact resistance value.

[0087] The method of FIG. 1 promotes the suppression of defect propagation from the substrate to the device layer. This corresponds to an improvement in the crystal quality of the device layer when compared to the crystal quality of the substrate, and as a result, the use of substrates with a reasonable defect density is promoted. Usually, SiC substrates with particularly low defect density are relatively expensive when compared to SiC substrates with a relatively high defect density. In the techniques described herein, the interface layer can improve the defect density, and thus it may not be necessary to rely on particularly high-quality substrates. The voids within the interface layer halt or reduce the propagation of extended stacking defects and other defects.

[0088] What is indicated by the dashed arrow in FIG. 1 is the possibility of reusing the substrate. Specifically, the remaining portion of the substrate obtained from the execution of block 1004 can be used as an input for further iterations of blocks 1001 - 1005. Depending on the level of material wear / iteration, multiple iterations are supported by reusing a single substrate, and this can potentially be any number. In some examples, it may be possible to provide a further layer of epitaxial SiC after the separation of the substrate in block 1004 to compensate for material wear. Thereby, the initial thickness of the substrate can be maintained.

[0089] In connection with the schematic diagram of FIG. 2, further details of the process defined by the method of FIG. 1 will be described.

[0090] FIG. 2 shows aspects in relation to the processing of SiC according to various examples.

[0091] In process step 2001, a substrate 130 is provided. Shown in FIG. 2 is the vertical direction z along which the thickness 133 of the substrate is defined. Also shown are the front side 131 and the back side 132 of the substrate 130.

[0092] In process step 2002, the interface layer 101 is provided on the substrate 130. The interface layer 101 is adjacent to the front side 131. The interface layer 101 includes cavities. For example, the interface layer 101 may be a porous layer or may include voids.

[0093] The interface layer 101 is provided by using a growth process, such as an epitaxial growth process for example. Usually, the thickness of the interface layer may range from at least 1 μm to a maximum of 50 μm, or may range from at least 2 μm to a maximum of 10 μm.

[0094] After block 2002, the silicon surface can face upward.

[0095] After using the growth process and before process step 2003, the interface layer 101 could be planarized.

[0096] In process step 2003, the device layer 102 is provided on the interface layer 101. Usually, the thickness 102A of the device layer 102 may be at least 10 μm, and optionally may be at least 50 μm, or at least 100 μm, or at least 150 μm.

[0097] In other examples, in process step 2003, a particularly small thickness of the device layer 102 may be provided. For example, the thickness 102A of the device layer 102 may be at most 30 μm, or may be at most 20 μm.

[0098] In principle, there may be a tendency to dimension the thickness of the device layer 102 as small as possible, but as large as necessary if required. Various properties of the semiconductor device may depend on the thickness of the device layer 102, and specifically, a trade-off situation may occur. (i) A relatively small thickness can provide relatively good thermal properties, for example, heat can be dissipated relatively efficiently to the carrier or heat sink. (ii) A relatively small thickness can enable relatively fast and cost-efficient processing. (iii) A relatively large thickness can, for example, increase the breakdown voltage of the transistors implemented by the semiconductor device. (iv) A relatively large thickness can provide an increase in structural stability for the resulting chip when separating the device layer 102 from the substrate 130. (v) A relatively large thickness may result in a relatively large Ron.

[0099] The device layer 102 is provided by using an epitaxial growth process. The growth rate of the growth process for providing the device layer 102 can be greater than the growth rate of the growth process for providing the interface layer 101. As a result, a large thickness 2003A of the device layer 102 can be promoted.

[0100] For example, a high-quality epitaxial growth process for providing the interface layer 101 can promote a large growth rate of the growth process for providing the device layer 102. The planarization of the interface layer 101 can further support the large growth rate for providing the device layer 102. Options for planarizing the surface include chemical mechanical planarization, polishing, and damage etching. All of these promote a form of the device layer 102 that supports a low defect density and a high yield of the semiconductor device 105 formed in process step 2004.

[0101] The step of providing the device layer 102 can include the step of defining a drift region for the semiconductor device 105 formed in process step 2004.

[0102] In process step 2004, the semiconductor device 105 is formed within the device layer 102. This includes steps such as forming electrical contacts and the like.

[0103] In process step 2005, the front-side carrier 106 is attached to the device layer 102. In the example of FIG. 2, the front-side carrier 106 remains attached to the device layer 102, but in other examples (not shown in FIG. 2), the front-side carrier 106 may be removed, for example, in process step 2007.

[0104] In process step 2006, the device layer 102 is separated from the substrate 130 in the interface layer 101. A break 171 is shown in FIG. 2.

[0105] In principle, there are various options available for the step that results in the break 171 for separating the substrate 130.

[0106] In a first option, as shown in FIG. 2, a back-side laser process can be utilized. In this case, the laser light 250 is irradiated onto the back side 132 of the substrate 130, resulting in damage to the interface layer 101 due to light absorption and heating. This is facilitated by the transparency of the SiC of the substrate 130 in relation to the laser light 250. The damage to the interface layer 101 further reduces the structural rigidity of the interface layer 101, and as a result, the break 171 is ultimately obtained.

[0107] To further improve such damage, the interface layer 101 could include a light-absorbing material. As a result, the substrate 130 can be separated from the device layer 102 by using the laser light 250 absorbed by the light-absorbing material. A dopant can be used as the light-absorbing material. Also, for example, one or more carbon layers, such as graphene, can be used as the light-absorbing material. For example, such carbon atoms could be obtained from the annealing process applied to the interface layer 101 in process step 2002. When the light-absorbing material is provided within the interface layer 101, it may not be necessary to focus the laser light 250 so that the maximum intensity is observed in the interface layer 101. Rather, the absorption in the interface layer 101 can be increased by the light-absorbing material instead of the spatially varying intensity of the laser light 250. As a result, the complexity of process step 2006 is reduced.

[0108] In a second option, at least a portion of a cold split process may be used to promote the break 171, i.e., to trigger the separation of the substrate 130 from the device layer 102. See, for example, (Non-Patent Document 5). In this case, for example, a layer containing one or more polymers can be deposited on the front side of the device layer 102. The polymer can have a different coefficient of thermal expansion from the substrate 130. As a result, upon cooling, the change in the length and / or volume of the polymer induces mechanical stress that leads to the break 171. Generally, due to the reduction in the structural rigidity of the interface layer 101, even the mechanical stress induced by the change in the length of such a polymer layer may be sufficient to lead to separation, and as a result, further use of the backside laser process may not be necessary. Thus, the backside laser process is generally optional.

[0109] In a third option, the step of separating the substrate 130 may instead, or in addition, include the step of injecting a fluid into the voids of the interface layer 101. The fluid can then be cooled below its freezing point. The expansion of the fluid upon transition to the solid state can also induce mechanical stresses associated with the break 171. For example, water in a fluid or gaseous state can be used.

[0110] In a fourth option, the step of separating the substrate 130 may instead, or in addition, include water jet treatment.

[0111] In a fifth option, the step of separating the substrate 130 may instead, or in addition, include micro electrical discharge machining (μEDM) within the interface layer 101.

[0112] In a sixth option, the step of separating the substrate 130 may instead, or in addition, include the step of applying a rapid change in pressure to induce stress.

[0113] In process step 2007, the backside metallization layer 107 is provided at the backside 132 on the remaining portion of the interface layer 101. Again, this is optional. Alternatively, instead, the interface layer may be removed.

[0114] In process step 2008, vertical dicing of the device layer 102 is implemented to singulate the semiconductor device 105. Individual KERF structures can be used to define the dicing lines 172.

[0115] In the scenario of FIG. 2, the dicing in process step 2008 is after the separation of the substrate 130 that occurs in process step 2006. In other examples, the step of singulating the semiconductor device 105 by dicing can also be performed before the step of separating the substrate 130 from the device layer 102, such as, for example, before process step 2006 or after process step 2005.

[0116] FIG. 3 shows aspects in relation to the processing of SiC according to various examples.

[0117] The processing of FIG. 3 generally corresponds to the processing of FIG. 2. For example, process step 2011 corresponds to process step 2001. Process step 2013 corresponds to process step 2003. Process step 2014 corresponds to process step 2004. Process step 2015 corresponds to process step 2005. Process step 2016 corresponds to process step 2006. Process step 2017 corresponds to process step 2007. Process step 2018 corresponds to process step 2008.

[0118] In process step 2012, the interface layer 101, unlike in process step 2002, is not provided as an epitaxial layer on the substrate 130 by using a growth process, but rather is provided within the substrate 130. For example, by appropriately structuring the upper layer of the substrate 130, voids can be defined within the upper layer of the substrate 130.

[0119] FIG. 4 is a flowchart of a method according to various examples. For example, the method of FIG. 4 can be utilized in relation to block 1001 of FIG. 1 to provide the interface layer 101.

[0120] Specifically, FIG. 4 shows aspects in relation to the definition of a plurality of voids within the interface layer 101.

[0121] The method starts with block 1011, which is an optional block. In block 1011, an epitaxial growth process, specifically a step-controlled epitaxial growth process, is being executed. Crystalline SiC is being deposited on a substrate (see process step 2002 in FIG. 2). In other implementations, the interface layer may be defined within the substrate, such that there is no need to deposit any further material on top of the substrate (see process 2012 in FIG. 3).

[0122] Next, in block 1012, an etching mask is defined by lithography, for example, by using a resist and its exposure. The etching mask defines the shape of the trench. FIG. 5 shows an exemplary etching mask 165. A longitudinally shaped trench 160 is shown. FIG. 5 is a plan view, and the lateral plane of the wafer corresponds to the drawing plane.

[0123] Specifically, trench 160 has an angle 162 with respect to the off-orientation direction 161 of the step-controlled epitaxial growth process of block 1011. For example, angle 162 may be at least 1°, optionally at least 5°, and further optionally at least 85°. For example, the angle may be 90° ± 5°.

[0124] Referring back to FIG. 4, next, in block 1013, trench 160 is being etched. In this case, one or more of dry etching, damage implantation, and electrochemical etching can be used to define trench 160. The material is locally removed where SiC is not protected by masking material 165 (e.g., photoresist and / or hard mask).

[0125] In block 1014, an epitaxial growth process is used again to deposit SiC. Before the step of depositing the material, the etching mask 165 is removed. By using the epitaxial growth process, the trench is filled, which is why blocks 1012 - 1014 are often referred to as the trench filling process 2101. Thus, as can be understood, the step of providing the interface layer 101 may include the step of using the trench filling process 2101.

[0126] In some examples, it may be possible to implement multiple repetitions of the trench filling process 2101, as indicated by the dashed arrows in FIG. 4. This can provide two or more sub - layers to the interface layer 101.

[0127] The step of using the trench filling process 2101 facilitates the step of defining voids within the interface layer 101. FIG. 6 shows details in relation to the voids 150.

[0128] FIG. 6 shows an aspect in relation to the interface layer 101 including a plurality of voids 150. FIG. 6 is a cross - sectional view along the vertical direction z and line X - X of FIG. 5. Shown in FIG. 6 is the trench 160 defined by the trench filling process 2101.

[0129] In FIG. 6, a void 150 is associated with a trench 160. The void 150 is a result of overgrowth of the trench 160 when depositing material at block 1014 of FIG. 4. Thus, the void 150 is provided in a top-down process and indicates a preferred direction. For example, as shown in FIG. 6, the longitudinal axis 151 of the void 150 is aligned with each other. This alignment is induced by the geometric shape and configuration of the etching mask 165. Similarly, the etching mask 165 induces the configuration of the void 150 also in a lateral pattern along the trench 160. The void 150 has an elongated shape along the z direction. The void 150 has a droplet shape. Thus, the void 150 is different from the pores of a porous layer which are usually spherical.

[0130] As can be understood, in the example of FIG. 6, the voids 150 do not form an interconnected network (sponge-type cavities). In some examples, it may be desirable to define the voids 150 so as to form an interconnected network. For example, if adjacent voids are connected to each other and / or in cases where the voids extend along the entire wafer in a direction perpendicular to the z direction so as to reach the edge of the wafer, a fluid can be injected that promotes separation of the substrate 130 by cooling the fluid below its freezing point. There are various options available to define the voids 150 so as to form an interconnected network. According to one exemplary option, it would be possible to pause the growth process of block 1014 of FIG. 4 and, while paused, etch the protrusions 152 of the still-open voids 150. This etching may include oxidation of the material and subsequent treatment of the oxidized material with hydrofluoric acid.

[0131] In some cases, the etching of such protrusions 152 can be used not to form an interconnected network, but rather to further reduce the structural stability of the interface layer 101 by expanding the volume of the individual voids 150. As a result, the step of separating the device layer 102 from the substrate 130 in the interface layer 101 is further facilitated.

[0132] In principle, when depositing material in block 1014 of FIG. 4, various options are available to facilitate the formation of voids 150. These options can be used alone or in combination with each other.

[0133] A first option for facilitating the formation of voids 150 involves an appropriate selection of the angle 162 (see FIG. 5). Typically, setting the magnitude of the angle 162 in the range of 4° to 90° can assist in promoting the encapsulation of voids.

[0134] A second option for facilitating the formation of voids 150 involves the step of using a reflow process. In this case, the voids 150 are encapsulated by the lateral redistribution of the deposited SiC material. For such redistribution, the growth process can be interrupted. The process parameters for promoting the redistribution have at least one of a high temperature, a low pressure, and an appropriate gas atmosphere, such as having hydrogen. The temperature can be set to be located within the lateral closure region to encapsulate the voids 150.

[0135] In a third option for facilitating the formation of voids, the process parameters of the growth process can be set within the lateral overgrowth region. This is shown in connection with FIG. 7.

[0136] FIG. 7 shows an aspect in relation to process parameters of the epitaxial growth process of block 1014. In the scenario of FIG. 7, the epitaxial growth process is a CVD process including specific flow rates of reactants, where hydrogen chloride acid or hydrogen chloride (HCl) is the vertical axis and silane (SiH4) is the horizontal axis. As shown in FIG. 7, the normal region 965 for overgrowth to define the void 150 depends on a relatively large flow rate of silane and a relatively small flow rate of HCl. This generally results in a small growth rate of material deposition. Generally, the growth rate of the epitaxial growth process of block 1014 can be set to be located within the lateral overgrowth region 965 that encloses the void 150. See, for example, (Non-Patent Document 6).

[0137] FIG. 8 shows an aspect in relation to the void density as a function of the vertical position. In the scenario of FIG. 8, the interface layer 101 includes two sub-layers 101-1 and 101-2 (see the dashed arrows in FIG. 4) obtained from, for example, multiple repetitions of a trench filling process. The sub-layer 101-1 is adjacent to the substrate 130, and the sub-layer 101-2 is adjacent to the device layer 102.

[0138] The void density generally may correspond to the ratio between (i) the volume in which the SiC material does not exist within the interface layer due to voids, and (ii) the total volume of the interface layer. Another measure related to the void density is the ratio between (i) the volume in which the SiC material exists within the interface layer, and (ii) the total volume of the interface layer.

[0139] For example, in various examples described herein, the ratio between (i) the volume in which the SiC material exists within the interface layer and (ii) the total volume of the interface layer may be in the range of 10% to 90%, or optionally in the range of 30% to 70%.

[0140] As shown in the figure, sub-layer 101-1 has a relatively high void density 301 when compared with the void density 302 of sub-layer 101-2.

[0141] At a general level, there may be a tendency for the void densities 301, 302 to decrease as the distance to the substrate 130 along the vertical Z direction increases. Thereby, the seed state for the epitaxial growth of the device layer 102 can be improved. Specifically, the morphology can be improved.

[0142] The different void densities 301, 302 can be realized, for example, by changing the lateral pitch between adjacent trenches 160 and / or by changing the lateral geometric filling rate of the trenches 160. The void densities 301, 302 can also be changed by changing the growth rate of the epitaxial growth process used to fill the trenches 160. Details regarding the relationship with the growth rate will be described in FIG. 9.

[0143] FIG. 9 shows the aspect in relation to the growth rate as a function of the vertical position.

[0144] In FIG. 9, the interface layer 101 includes sub-layers 101-1, 101-2. The device layer 102 also includes sub-layers 102-1, 102-2.

[0145] As shown in FIG. 9, the growth rates 311-1, 311-2, 312-1, 312-2 are increasing as the distance to the substrate 130 along the vertical Z direction increases. The increase in the growth rate in the scenario of FIG. 9 is correlated with the sub-layers 101-1, 101-2, 102-1, 102-2.

[0146] As a general trend, the growth rate can increase with an increase in the distance to the substrate 130 along the vertical Z direction, for example, within the interface layer 101 and / or within the device layer 102. This can help avoid the propagation of the disrupted surface morphology caused by the voids 150 within the interface layer 101. As a result, high-quality semiconductor devices 105 are promoted.

[0147] As can be understood, the average growth rates 312-1, 312-2 of the device layer 102 are greater than the average growth rates 311-1, 311-2 of the interface layer 101. This is useful for reducing the processing time because usually the thickness of the device layer 102 significantly exceeds the thickness of the interface layer 101.

[0148] Figures 10 and 11 show aspects in relation to the singulation of semiconductor devices 105-1 to 105-3. Specifically, Figures 10 and 11 show aspects in relation to the protection of semiconductor devices 105-1 to 105-3.

[0149] In this case, the edge region 172 is etched. Then, a protective material 180, such as glass, epoxy, or another oxide, is pressed into the edge region 172 to cover the individual vertical edges of the edge region 172. Then, dicing for singulating the semiconductor devices 105-1 to 105-3 is implemented along the edge region 172. This provides edge passivation / edge protection.

[0150] The formation of the semiconductor devices 105, 105-1 to 105-3 can vary in the various examples described herein. For example, the concept of so-called "high dynamic durability" (HDR) can be implemented to improve the turn-off durability of the device by reducing the free charge carrier density of the device within the area of the junction termination in the on-state of the device. In this case, a small area along the later-defined dicing edge can be locally oxidized. Subsequently, epitaxial lateral overgrowth can be applied to these locally oxidized areas. These areas, on the one hand, need to be small enough to promote defect-free epitaxial lateral overgrowth, while on the other hand, the distance between adjacent areas needs to be small enough so that the injection of free charge carriers from the back side of the die is effectively suppressed.

[0151] A further possible modification to the formation of the semiconductor device includes that 105, 105-1 to 105-3 form cavities, such as pores and / or voids, within the device layer 102. This is shown in relation to FIG. 12.

[0152] FIG. 12 schematically shows aspects in relation to the definition of voids within device layer 102. For example, pores can be defined within regions 178 confined laterally within device layer 102, for example, by using electrochemical etching. These regions 178 can be aligned with KERF 179 along which dicing is implemented to singulate semiconductor devices 105-1 to 105-3. For example, the vertical thickness 178A of these regions 178 may be greater than the thickness of device layer 102 (not shown in FIG. 12). In another example (see FIG. 12), the vertical thickness 178A of these regions is less than the thickness 102A of device layer 102 so as to provide mechanical stabilization thereby. Optionally, after defining voids within region 178, it is possible to deposit an epitaxial growth layer of SiC (see FIG. 12. In this case, region 178 does not extend completely up to the front side of device layer 102). The voids within region 178 facilitate singulation of semiconductor devices 105-1 to 105-3 along KERF 179, for example, by applying appropriate mechanical stress. Dicing implementation may become unnecessary. Edge quality can be improved.

[0153] FIG. 13 schematically shows aspects in relation to interface layer 102 having porous SiC. FIG. 13 is a cross-sectional view of interface layer 102 perpendicular to the z direction, i.e., within the xy plane. FIG. 13 shows pores 601 at different z positions (z1 and z2), the z positions being offset by a distance less than the average pore size 602 (note that not all pores 601 are labeled in FIG. 13 for clarity).

[0154] As shown in FIG. 13, the pores 601 form an interconnected network (sponge-type pores). This means that, on average, the number of interconnected pores 601 is significantly greater than 1, for example, greater than 10, or greater than 100, etc. Channels are formed between adjacent pores 601.

[0155] The pores 601 can, for example, on average, have a spherical shape, i.e., can have an average aspect ratio of 1. Some individual pores in the aggregate of pores 601 may have an aspect ratio deviating from 1, i.e., its length along the x direction is different from its length along the y direction (this aspect ratio is often also referred to as elongation or eccentricity). This means that the pores can have a relatively long extension in the vertical direction rather than in the lateral direction. The semiconductor structure between the pores can, for example, have a structure like a stalactite.

[0156] FIG. 14 schematically shows an aspect in relation to the interface layer 102 having porous SiC. The example of FIG. 14 generally corresponds to the example of FIG. 13. However, in the example of FIG. 14, the pore density is reduced when compared to the scenario of FIG. 13. Also, when compared to the example of FIG. 13, the average pore size 602 is also relatively smaller in the example of FIG. 14.

[0157] The pore density can generally correspond to the ratio between (i), i.e., the volume in which the SiC material is not present in the interface layer due to the pores, and (ii) the total volume of the interface layer. Another measure related to the pore density is the ratio between (i) the volume in which the SiC material is present in the interface layer and (ii) the total volume of the interface layer.

[0158] For example, in various examples described herein, the ratio between (i) the volume in which the SiC material is present within the interface layer and (ii) the total volume of the interface layer may range from 10% to 90%, or alternatively, optionally, may range from 30% to 70%.

[0159] In FIG. 14, the pore density and pore size are configured such that an interconnected network of pores 601 is not formed.

[0160] By using an appropriate process for preparing the porous interface layer 102, it is possible to adapt such and other structural properties of the pores 601. For example, the size and / or density of the pores 601 can be adjusted by adjusting the current density of the electrochemical etching. In some examples, this is used to prepare multiple sub-layers of the interface layer 102 having different pore densities and / or pore sizes. FIG. 15 shows a corresponding scenario.

[0161] FIG. 15 shows the aspect in relation to the pore density as a function of the vertical position. In the scenario of FIG. 15, the interface layer 101 includes two sub-layers 101-1, 101-2 (for example, obtained from multiple repetitions of an electrochemical etching process having adjusted process parameters). The sub-layer 101-1 is adjacent to the substrate 130, and the sub-layer 101-2 is adjacent to the device layer 102.

[0162] As shown, the sub-layer 101-1 has a relatively high pore density 801 when compared to the pore density 802 of the sub-layer 101-2.

[0163] At a general level, there may be a tendency for the pore densities 801, 802 to decrease with an increase in the distance along the vertical Z-direction to the substrate 130. Thereby, the seed state for the epitaxial growth of the device layer 102 can be improved. Specifically, the morphology can be improved.

[0164] For example, by changing the current density of electrochemical etching, various pore densities 801, 802 can be realized.

[0165] For example, the sublayer 101-1 can have a pore density in the range of 40% to 70%, while the sublayer 101-2 can have a pore density in the range of 10% to 50%.

[0166] In some examples, the sublayer 101-1 can form an interconnected network of pores 601, while the sublayer 101-2 may not need to form an interconnected network of pores 601.

[0167] For example, the thickness 101-1A of the sublayer 101-1 may be in the range of 0.5 μm to 50 μm. The thickness 101-2A may be in the range of 0.2 μm to 20 μm. Therefore, the sublayer 101-2 can have a relatively small vertical extent when compared to the sublayer 101-1.

[0168] In summary, various techniques for promoting the formation of semiconductor devices within an epitaxial SiC device layer have been described. The device layer is provided on an interface layer that includes cavities such as pores or voids. The interface layer is provided on a SiC substrate or is defined within the SiC substrate in a state close to its front side.

[0169] These techniques facilitate the manufacture of high-quality and high-yield power semiconductor devices. For example, the device layer can include a layer stack including a drain or emitter region, and optionally, a buffer region, a drift region, a p-doped body region, and / or a source region or a front-side emitter, depending on the specific type of semiconductor device.

[0170] The interface layer provides a function in relation to a barrier against the propagation of functions and / or defects in relation to the separation of the substrate from the device layer.

[0171] If necessary, the following examples have been described.

[0172] The present invention has been illustrated and described in relation to specific preferred embodiments, but those skilled in the art will envision equivalents and modifications in the context of reference and understanding of this specification. The present invention includes all such equivalents and modifications and is limited only by the scope of the appended claims.

[0173] For illustrative purposes, various techniques in relation to the separation of the device layer from the substrate in the interface layer have been described in the scenario where the interface layer contains voids. Similar techniques can be readily applied to the scenario where the interface layer contains pores.

[0174] For further illustrative purposes, various techniques have been described in relation to a method including the step of providing a device layer and an interface layer. Individual wafers can be obtained from such a method, in which case the wafers have structural properties characterized by such a method.

[0175] For further illustrative purposes, various techniques have been described where a trench filling process is used to define voids within an epitaxial growth layer of SiC as the device layer. The trench filling process can also be used in the context of a scenario where the device layer is defined within a substrate.

[0176] For further illustrative purposes, various techniques have been described in relation to a device layer having a relatively large thickness, for example, at least 20 μm. Similar techniques can also be provided for a relatively thin device layer having a thickness of up to 20 μm, for example.

[0177] For purposes of further illustration, various scenarios have been described in the context of SiC as a semiconductor material, but similar techniques can also be implemented in other types and kinds of wide bandgap semiconductor materials such as, for example, GaN.

Explanation of Signs

[0178] 101 First layer 101-1 First sublayer 101-2 Second sublayer 102 Second layer 102-1 First sublayer 102-2 Second sublayer 102A Thickness of the second layer 105, 105-1, 105-2, 105-3 Semiconductor devices 130 Substrate 150 Void 151 Longitudinal axis 152 Protrusion 160 Trench 161 Off-orientation direction 162 Angle 165 Lateral overgrowth region 250 Laser light 301 First void density 302 Second void density 311-1, 311-2 First growth rate 312-1, 312-2 Second growth rate 601 Pore 801 First pore density 802 Second pore density 2101 Trench filling process

Claims

1. - providing a first layer (101) of porous silicon carbide supported by a silicon carbide substrate (130); - providing a second layer (102) of epitaxial silicon carbide on said first layer (101); - forming a plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in said second layer (102); - depositing on said second layer (102) a layer comprising one or more polymers having a thermal expansion coefficient different from that of said silicon carbide substrate (130); - cooling said layer(s) comprising one or more polymers, said silicon carbide substrate (130), said first layer (101) and said second layer (102) and changing the length and / or volume of said layer(s) comprising one or more polymers to induce mechanical stresses in said first layer (101), resulting in a fracture in the middle part of said first layer (101) and separating said substrate (130) from said second layer (102) such that a part of said first layer (101) remains together with said second layer (102); The method according to claim 1,

2. the thickness (102A) of the second layer (102) is at least 20 μm; or The method of claim 1, wherein the thickness (102A) of the second layer (102) is at most 30 μm.

3. The method of claim 1 or 2, wherein the porous silicon carbide of the first layer (101) forms an interconnected network of pores (601).

4. The first layer (101) has a first sub-layer (101-1) having a first pore density (801) and further has a second sub-layer (101-2) having a second pore density (802); the first sub-layer (101-1) of the first layer (101) is disposed between the second sub-layer (101-2) of the first layer (101) and the substrate (130); The method according to any one of claims 1 to 3, wherein the first pore density (801) is greater than the second pore density (802).

5. The method according to any one of claims 1 to 4, wherein the step of providing the first layer (101) comprises using an epitaxial growth process.

6. The method of any one of claims 1 to 5, wherein the step of providing the first layer (101) comprises using an electrochemical etching process.

7. providing the second layer (102) comprises using an epitaxial growth process; The second layer (102) has a first sub-layer (102-1) and a second sub-layer (102-2), the first sub-layer (102-1) of the second layer (102) is disposed between the second sub-layer (102-2) of the second layer (102) and the first layer (101); 7. The method according to any one of claims 1 to 6, wherein a growth rate (312-1) of the epitaxial growth process of the first sub-layer (102-1) of the second layer (102) is smaller than a growth rate (312-2) of the epitaxial growth process of the second sub-layer (102-2) of the second layer (102).

8. 8. The method of claim 1, wherein the first layer (101) comprises a dopant that defines a resistivity of the first layer (101), the resistivity of the first layer (101) being less than a resistivity of the substrate (130).

9. The method according to any one of claims 1 to 8, further comprising the step of planarising the first layer (101) prior to the step of providing the second layer (102).

10. The method of any one of claims 1 to 9, further comprising the step of providing a protective material at vertical edges etched in the second layer (102).

11. - dicing said second layer (102) in a vertical direction to singulate said semiconductor devices (105, 105-1, 105-2, 105-3) of said plurality of semiconductor devices (105, 105-1, 105-2, 105-3), The method of any one of claims 1 to 10, wherein the second layer (102) is diced prior to the step of separating the substrate (130) from the second layer (102).

12. 12. The method of claim 1, further comprising, after the step of separating the substrate (130) from the second layer (102), depositing a backside metallization layer (107) on the portion of the first layer (101) that remains with the second layer (102).

13. said first layer (101) being provided at a first growth rate (311-1, 311-2); the second layer (102) is provided at a second growth rate (312-1, 312-2); 13. The method of claim 1, wherein the first growth rate is less than the second growth rate.

14. - defining drift regions of said plurality of semiconductor devices (105, 105-1, 105-2, 105-3) in said second layer (102); - defining in said second layer (102) drain or backside emitter regions of said plurality of semiconductor devices (105, 105-1, 105-2, 105-3); Further comprising: The method according to claim 1 , wherein the thickness of the drain region or the back-side emitter region is greater than the thickness of the drift region.

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