Silicon carbide semiconductor device and method of manufacturing the same

Abstract

To suppress deterioration in characteristic of a SiC semiconductor device.SOLUTION: A silicon carbide semiconductor device comprises: a semiconductor substrate 10 which has a drift layer 12, a base layer 13 formed on a front layer part of the drift layer 12, an impurity region 14 that is formed on the front layer part of the base layer 13, and has an impurity concentration higher than that of the drift layer 12, and a high concentration layer 11 that is formed on the side opposite to the base layer 13 across the drift layer 12, and has an impurity concentration higher than that of the drift layer 12, and is constituted of a SiC; and a plurality of trench gates having a gate insulation film 17 that is formed on a wall surface of a trench 16 penetrated through the base layer 13 and the impurity region 14 to reach the drift layer 12, and a gate electrode 18 formed on the gate insulation firm 17. The trench 16 has a construction that a bottom surface 16a includes a part in a round shape. Further, a one surface 10a of the semiconductor substrate 10 has a construction having a one surface convex part 102 in a round shape which is convex at a part positioned between the adjacent trenches 16.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a SiC semiconductor device having a trench gate structure and composed of silicon carbide (hereinafter also simply referred to as SiC), and a method for manufacturing the same.

Background Art

[0002] Conventionally, a SiC semiconductor device having a trench gate structure has been proposed (see, for example, Patent Document 1). Specifically, in this SiC semiconductor device, a base layer is formed on a drift layer, and a source region is formed in the surface layer portion of the base layer. Further, a drain region is disposed on the opposite side of the base layer with the drift layer interposed therebetween. And, in this SiC semiconductor device, a semiconductor substrate is constituted including a drain region, a drift layer, a base layer, a source region, and the like.

[0003] Further, in this SiC semiconductor device, a trench is formed that penetrates the source region and the base layer and reaches the drift layer, and a gate insulating film and a gate electrode are sequentially formed in the trench to form a trench gate structure. An upper electrode electrically connected to the source region and the base layer is formed on the base layer, and a lower electrode electrically connected to the drain layer is formed on the drain layer.

[0004] And, in this SiC semiconductor device, in order to suppress the occurrence of electric field concentration on the bottom surface side of the trench, the bottom surface of the trench is formed in a round shape.

[0005] The trench in this SiC semiconductor device is formed as follows. That is, after forming a base layer, a source region, etc. on a semiconductor substrate, a trench is formed so as to reach the drift layer. Next, an epitaxial layer is grown in the trench to make the bottom surface of the trench round. Subsequently, the epitaxial layer formed on the side surface of the trench is removed by etching to expose the source region and the base layer from the wall surface of the trench. Thereafter, generally, a semiconductor manufacturing process is performed, and a gate insulating film, a gate electrode, an upper electrode, a lower electrode, etc. are formed in order, whereby the above SiC semiconductor device is manufactured.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0007] However, in the above - described trench formation method, the characteristics of the SiC semiconductor device may deteriorate. That is, when removing the epitaxial layer disposed on the side surface of the trench, if the etching is excessive, the wall surface of the trench may be damaged, and the channel mobility may decrease, etc., resulting in a deterioration of the characteristics of the SiC semiconductor device. Also, when removing the epitaxial layer disposed on the side surface of the trench, if the etching is insufficient, the epitaxial layer may remain on the side surface of the trench, resulting in threshold fluctuations or the source region and the drift region being directly connected via the epitaxial layer, thereby reducing the characteristics of the SiC semiconductor device.

[0008] In view of the above points, an object of the present invention is to provide an SiC semiconductor device and a manufacturing method thereof that can suppress a deterioration in the characteristics of the SiC semiconductor device.

Means for Solving the Problems

[0009] In claim 1 for achieving the above object, there is provided a SiC semiconductor device having a trench gate structure, comprising a drift layer (12) of a first conductivity type, a base layer (13) of a second conductivity type formed on the surface layer portion of the drift layer, an impurity region (14) of the first conductivity type formed on the surface layer portion of the base layer and having a higher impurity concentration than the drift layer, and a high-concentration layer (11) of the first conductivity type or the second conductivity type formed on the side opposite to the base layer with the drift layer interposed therebetween and having a higher impurity concentration than the drift layer. One surface (10a) is formed on the surface side of the base layer, and the other surface (10b) is formed on the surface side of the high-concentration layer. The semiconductor substrate (10) is made of SiC. A plurality of trench gate structures each having a gate insulating film (17) formed on the wall surface of a trench (16) that penetrates the base layer and the impurity region to reach the drift layer, and a gate electrode (18) formed on the gate insulating film. A first electrode (20) is disposed on one side and electrically connected to the base layer and the impurity region, and a second electrode (21) is disposed on the other side and electrically connected to the high-concentration layer. The trench has a portion where the bottom surface (16a) is round-shaped, and one surface of the semiconductor substrate has a round-shaped one-surface convex portion (102) that bulges at a portion located between adjacent trenches. wherein the drift layer is configured by laminating a first drift layer (121) and a second drift layer (122) in this order from the high-concentration layer side, the trench is formed in a state where the bottom surface is located in the second drift layer, and an internal recess (131) is formed in a portion of the first drift layer that faces the bottom surface of the trench on the surface (121a) on the second drift layer side.

[0010] According to this, since the bottom surface of the trench is round-shaped, it is possible to suppress the occurrence of electric field concentration in the vicinity of the bottom surface of the trench. Further, such a trench is formed by digging a round-shaped one-surface concave portion after forming a one-surface uneven structure on one surface of the semiconductor substrate. For this reason, it is not necessary to perform a step of forming an epitaxial layer on the wall surface of the trench and removing the epitaxial layer by etching, so that it is possible to suppress a decrease in the characteristics of the SiC semiconductor device.

[0011] Furthermore, in this SiC semiconductor device, a portion of one surface of the semiconductor substrate located between trenches has a round-shaped one-sided convex portion. Therefore, compared with the case where one surface of the semiconductor substrate is planarized, the contact area between the first electrode and one surface of the semiconductor substrate can be increased, and the contact resistance can be reduced.

[0012] Also, claim 5 is a manufacturing method related to the SiC semiconductor device according to any one of claims 1 to 4 and includes preparing a constituent substrate (200) that constitutes a drift layer, performing etching on the constituent substrate to form an internal concave portion (131), thereby forming an internal concavo-convex structure (130) including the internal convex portion (132) of a portion different from the internal concave portion and the internal concave portion, epitaxially growing a constituent layer (210) on the constituent substrate to form a semiconductor substrate, so that a portion located on the internal concave portion on one surface of the semiconductor substrate becomes a round-shaped one-sided concave portion (101) and a portion located on the internal convex portion becomes a round-shaped one-sided convex portion (102), forming a trench including a portion that becomes a one-sided concave portion in the one-sided concavo-convex structure, thereby forming a trench whose bottom surface has a round shape inheriting the shape of the one-sided concave portion, and making a portion located between the trenches on one surface include the one-sided convex portion.

[0013] According to this, since the bottom surface of the trench has a round shape, a SiC semiconductor device can be manufactured in which electric field concentration is suppressed in the vicinity of the bottom surface of the trench. Further, by forming a trench in a portion that becomes a one-sided concave portion in the one-sided concavo-convex structure of the semiconductor substrate, the bottom surface of the trench has a round shape. Therefore, it is not necessary to perform a step of forming an epitaxial layer on the wall surface of the trench and removing the epitaxial layer by etching, and a SiC semiconductor device in which deterioration of characteristics is suppressed can be manufactured.

[0014] Furthermore, in this manufacturing method, a SiC semiconductor device is manufactured such that a convex portion on one side having a round shape is disposed at a portion located between trenches on one side of the semiconductor substrate. Therefore, compared with the case where one side of the semiconductor substrate is planarized, a SiC semiconductor device can be manufactured in which the contact area between the first electrode and one side of the semiconductor substrate is increased and the contact resistance is reduced.

[0015] Note that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

Figure 3A

Figure 3B

Figure 3C

Figure 3D

Figure 3E

Figure 4A

Figure 4B

Figure 5

Figure 6

Figure 7

Figure 8

Mode for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals and described.

[0018] (First Embodiment) The first embodiment will be described with reference to the drawings. The SiC semiconductor device of this embodiment is preferably mounted on a vehicle such as an automobile and applied as a device for driving various electronic devices for the vehicle. Further, in this embodiment, a SiC semiconductor device in which an inversion-type MOSFET having a trench gate structure is formed will be described. In this embodiment, the configuration of the cell region in which a MOSFET (abbreviation for Metal Oxide Semiconductor Field Effect Transistor) is formed will be described. However, in an actual SiC semiconductor device, an outer peripheral region in which an FLR (abbreviation for Field Limiting Ring) structure or the like is formed is provided so as to surround the cell region.

[0019] Hereinafter, one direction in the plane direction of the substrate 11 to be described later will be defined as the X-axis direction, a direction intersecting one direction in the plane direction of the substrate will be defined as the Y-axis direction, and a direction orthogonal to the X-axis direction and the Y-axis direction will be defined as the Z-axis direction for description. In this embodiment, the X-axis direction and the Y-axis direction are orthogonal to each other. Further, although not particularly limited, for example, the X-axis direction is the <11-20> direction. When indicating the crystal orientation, originally a bar (-) should be attached above the desired number, but due to the expression limitation based on the electronic application, here a bar is attached in front of the desired number.

[0020] As shown in FIGS. 1 and 2, the SiC semiconductor device is configured using a semiconductor substrate 10. Specifically, the SiC semiconductor device is an n-type made of SiC+ It includes a substrate 11 of type 19 / cm 3 and has a thickness of about 300 μm. In this embodiment, the substrate 11 constitutes the drain region and corresponds to the high-concentration layer.

[0021] On the surface of the substrate 11, a drift layer 12 is formed. The drift layer 12 of this embodiment is composed of a first drift layer 121 and a second drift layer 122 laminated in order from the substrate 11 side.

[0022] In the first drift layer 121, an internal concavo-convex structure 130 is formed with a plurality of internal recesses 131 formed on the surface 121a opposite to the substrate 11 side, and the portion between the internal recesses 131 serving as internal protrusions 132. In this embodiment, the internal recesses 131 are formed in a plurality of lines extending along the Y-axis direction on the surface 121a of the first drift layer 121 and arranged at equal intervals in the X-axis direction to form a stripe shape. And since the internal protrusions 132 are composed of the portions between the internal recesses 131, a plurality of them extend along the Y-axis direction and are arranged at equal intervals in the X-axis direction to form a stripe shape. Also, as will be described later, the internal concavo-convex structure 130 is formed by forming the internal recesses 131 by dry etching. For this reason, the side surfaces of the internal recesses 131 and the internal protrusions 132 are substantially perpendicular to the bottom surface of the internal recesses 131 and the protruding surface of the internal protrusions 132.

[0023] On the drift layer 12, a p-type base layer 13 is formed. The base layer 13 has, for example, a p-type impurity concentration of 3.0×10 17 / cm 3 or less.

[0024] In the surface layer portion of the base layer 13, an n + -type source region 14 and a p +A contact region 15 of the type is formed. In the present embodiment, the source region 14 and the contact region 15 are alternately formed along the longitudinal direction (i.e., the Y-axis direction) of a trench 16 described later. In the present embodiment, the source region 14 corresponds to an impurity region. Also, the contact region 15 can also be said to be an impurity region.

[0025] The source region 14 has an n-type impurity concentration in the surface layer portion, that is, a surface concentration of, for example, 1.0×10 21 / cm 3 It is set as follows. The contact region 15 has a p-type impurity concentration in the surface layer portion, that is, a surface concentration of, for example, 1.0×10 21 / cm 3 It is set as follows.

[0026] In the present embodiment, as described above, the semiconductor substrate 10 is configured to include the substrate 11, the drift layer 12, the base layer 13, the source region 14, the contact region 15, and the like. And in the present embodiment, one surface 10a of the semiconductor substrate 10 is composed of the source region 14 and the contact region 15, and the other surface 10b of the semiconductor substrate 10 is composed of the substrate 11.

[0027] A plurality of trenches 16 are formed in the semiconductor substrate 10 so as to penetrate the source region 14, the contact region 15, and the base layer 13 and reach the drift layer 12. Specifically, the plurality of trenches 16 are extended so as to extend along the Y-axis direction, and are formed in a stripe shape by being arranged at equal intervals in the X-axis direction. Also, the trench 16 of the present embodiment is formed such that the bottom surface 16a is located within the second drift layer 122, and is formed to include a portion where the bottom surface 16a faces the internal recess 131.

[0028] Here, although it will be described in detail later, as shown in FIG. 3C, the semiconductor substrate 10 of the present embodiment is configured by disposing a constituent layer 210 formed of an epitaxial layer on the first drift layer 121. And one surface 10a of the semiconductor substrate 10 is in a state where a one-surface uneven structure 100 formed due to the internal uneven structure 130 is formed. However, this one-surface uneven structure 100 has a round shape that is smoother than the internal uneven structure 130 in the process of growing the epitaxial layer.

[0029] And, as shown in FIG. 3E, the trench 16 of the present embodiment is configured by digging down a portion that becomes the one-surface concave portion 101 in the one-surface uneven structure 100. For this reason, the bottom surface 16a of each trench 16 has a round shape that inherits the shape of the one-surface concave portion 101. That is, the bottom surface 16a of each trench 16 has a rounded shape with a curved surface. And by forming the trench 16 in this way, the portion of the one surface 10a of the semiconductor substrate 10 located between the trenches 16 has a one-surface convex portion 102 that bulges more than the opening of the trench 16 and has a round shape.

[0030] Note that the trench 16 of the present embodiment is formed such that the bottom surface 16a is located in the second drift layer 122, but it may be formed such that the bottom surface 16a is located in the first drift layer 121.

[0031] And, as shown in FIG. 1, a gate insulating film 17 is formed on the inner wall surface of the trench 16, and a gate electrode 18 formed of doped Poly-Si or the like is formed on the gate insulating film 17. Thereby, a trench gate structure is configured. Although not particularly limited, the gate insulating film 17 is formed by thermally oxidizing the inner wall surface of the trench 16 or performing a CVD (abbreviation for chemical vapor deposition) method. And the gate insulating film 17 has a thickness of about 100 nm both on the side surface side and the bottom surface side of the trench 16.

[0032] On one surface 10a of the semiconductor substrate 10, an interlayer insulating film 19 is formed so as to cover the gate electrode 18, the gate insulating film 17, etc. The interlayer insulating film 19 is composed of BPSG (abbreviation for Borophosphosilicate Glass) or the like.

[0033] In the interlayer insulating film 19, a contact hole 19a for exposing the source region 14 and the contact region 15 is formed. Note that the pattern of the contact hole 19a is arbitrary, and examples thereof include a pattern in which a plurality of square ones are arranged, a pattern in which rectangular line-shaped ones are arranged, or a pattern in which line-shaped ones are arranged side by side. In the present embodiment, the contact hole 19a is in a line shape along the longitudinal direction of the trench 16.

[0034] On the interlayer insulating film 19, an upper electrode 20 that is electrically connected to the source region 14 and the contact region 15 through the contact hole 19a is formed. Note that in the present embodiment, the upper electrode 20 corresponds to the first electrode.

[0035] The upper electrode 20 of the present embodiment is composed of, for example, a plurality of metals such as Ni / Al. And the portion that contacts the portion constituting the n-type SiC (that is, the source region 14) among the plurality of metals is composed of a metal capable of forming an ohmic contact with the n-type SiC. Also, at least the portion that contacts the p-type SiC (that is, the contact region 15) among the plurality of metals is composed of a metal capable of forming an ohmic contact with the p-type SiC.

[0036] Here, in the present embodiment, as described above, the portion of the one surface 10a of the semiconductor substrate 10 that is located between the trenches 16 is in a state of having a one-surface convex portion 102 and has a round shape that bulges more than the opening of the trench 16. Therefore, compared with the case where the one surface 10a of the semiconductor substrate 10 is a flat surface, the contact area between the upper electrode 20 and the source region 14 and the contact region 15 can be improved, and the contact resistance can be reduced.

[0037] On the other surface 10b side of the semiconductor substrate 10, a lower electrode 21 electrically connected to the substrate 11 is formed. In the present embodiment, the lower electrode 21 corresponds to the second electrode.

[0038] In the SiC semiconductor device of this embodiment, a MOSFET having a trench gate structure of an n-channel type inversion mode is configured by such a structure. In the present embodiment, the n-type, n + type corresponds to the first conductivity type, and the p-type, p + type corresponds to the second conductivity type.

[0039] In such a SiC semiconductor device, when the gate voltage applied to the gate electrode 18 is equal to or higher than the threshold voltage of the insulated gate structure, a current flows between the upper electrode 20 and the lower electrode 21, and it becomes an on state. Also, in such a SiC semiconductor device, when the gate voltage applied to the gate electrode 18 is less than the threshold voltage, no current flows between the upper electrode 20 and the lower electrode 21, and it becomes an off state.

[0040] Next, a method for manufacturing the above SiC semiconductor device will be described with reference to FIGS. 3A to 3E.

[0041] First, as shown in FIG. 3A, a constituent substrate 200 on which a first drift layer 121 is epitaxially grown is prepared on the substrate 11.

[0042] Next, as shown in FIG. 3B, dry etching such as RIE (abbreviation for Reactive Ion Etching) is performed on the constituent substrate 200 using a mask (not shown) to form the internal recess 131 having the above shape on the surface 121a of the first drift layer 121. Thereby, an internal concavo-convex structure 130 composed of the internal recess 131 and the internal protrusion 132 is formed on the surface 121a of the first drift layer 121.

[0043] Subsequently, as shown in FIG. 3C, the constituent layer 210 is epitaxially grown to form the semiconductor substrate 10. In this case, since the internal uneven structure 130 is formed on the surface 121a of the first drift layer 121, a surface uneven structure 100 due to the internal uneven structure 130 is formed on one surface 10a of the semiconductor substrate 10. Specifically, in the surface uneven structure 100, the portion located on the internal concave portion 131 in the internal uneven structure 130 becomes the surface concave portion 101, and the portion located on the internal convex portion 132 in the internal uneven structure 130 becomes the surface convex portion 102.

[0044] Further, the surface uneven structure 100 is formed due to the internal uneven structure 130 by epitaxially growing the constituent layer 210. Therefore, as shown in FIGS. 4A and 4B, the surface uneven structure 100 is composed of a curved surface (that is, a curved surface with a large radius of curvature) having a smooth round uneven structure. That is, the surface uneven structure 100 is configured by connecting a surface concave portion 101 having a round shape recessed toward the substrate 11 side and a surface convex portion 102 having a round shape bulging on the side opposite to the substrate 11 side. Also, in the surface uneven structure 100, the height difference (that is, the height) between the surface concave portion 101 and the surface convex portion 102 is smaller than the height difference between the internal concave portion 131 and the internal convex portion 132 in the internal uneven structure 130. FIGS. 4A and 4B are diagrams showing the results of height measurement by an atomic force microscope (that is, AFM). Further, the constituent layer 210 of the present embodiment is arranged in accordance with the impurity concentration of the second drift layer 122.

[0045] Next, as shown in FIG. 3D, impurities are appropriately ion-implanted using a mask (not shown) on one surface 10a of the semiconductor substrate 10 to form the base layer 13, the source region 14, and the contact region 15. When the constituent layer 210 is formed with an impurity concentration lower than the impurity concentration of the second drift layer 122, the second drift layer 122 may be formed by ion-implanting impurities into the portion that becomes the second drift layer 122.

[0046] Subsequently, as shown in FIG. 3E, dry etching such as RIE is performed on one surface 10a of the semiconductor substrate 10 using a mask (not shown), and a trench 16 is formed in a portion that becomes the one surface concave portion 101 in the one surface uneven structure 100. As a result, since the bottom surface 16a of the trench 16 depends on the shape of the one surface concave portion 101, it is formed in a round shape. And the portion located between the trenches 16 on the one surface 10a of the semiconductor substrate 10 has a one surface convex portion 102 that is a round shape raised more than the opening of the trench 16.

[0047] Although not particularly shown thereafter, a general semiconductor manufacturing process is performed to form a gate insulating film 17, a gate electrode 18, an interlayer insulating film 19, an upper electrode 20, a lower electrode 21, etc., whereby the SiC semiconductor device shown in FIG. 1 above is manufactured.

[0048] According to the present embodiment described above, since the bottom surface 16a of the trench 16 is formed in a round shape, it is possible to suppress the occurrence of electric field concentration in the vicinity of the bottom surface 16a of the trench 16. Further, the trench 16 is formed in a portion that becomes the one surface concave portion 101 in the one surface uneven structure 100 of the semiconductor substrate 10, so that the bottom surface 16a is formed in a round shape. For this reason, it is not necessary to perform a step of forming an epitaxial layer on the wall surface of the trench 16 and removing the epitaxial layer by etching. Therefore, it is possible to suppress damage to the wall surface of the trench 16 and the remaining of the epitaxial layer on the wall surface of the trench 16, and to suppress deterioration of the characteristics of the SiC semiconductor device.

[0049] By the way, it has also been proposed to perform a heat treatment after forming the trench 16 to make the bottom surface 16a of the trench 16 round. However, in this method, there is a possibility that silicon may escape or surface bunching may occur during the heat treatment, and the roughness of the exposed surface may deteriorate, resulting in a possibility of deterioration of the characteristics of the SiC semiconductor device. However, in the manufacturing method of the SiC semiconductor device in the present embodiment, since it is not necessary to perform a heat treatment after forming the trench 16, the bottom surface 16a of the trench 16 can be formed in a round shape without deteriorating the roughness of the exposed surface.

[0050] Further, a portion of one surface 10a of the semiconductor substrate 10 located between the trenches 16 has a one-surface convex portion 102 having a round shape that bulges more than the opening of the trench 16. Therefore, compared with the case where the one surface 10a of the semiconductor substrate 10 is planarized, the contact area between the upper electrode 20 and the one surface 10a of the semiconductor substrate 10 (that is, the source region 14 and the contact region 15) can be increased, and the contact resistance can be reduced.

[0051] (1) In the present embodiment, the internal concave portion 131 extends along the Y-axis direction, and the one-surface concave portion 101 also extends along the Y-axis direction. The trench 16 is formed by digging down the one-surface concave portion 101 located on the internal concave portion 131. Therefore, the bottom surface 16a of the trench 16 has a round shape along the Y-axis direction, and more portions having a round shape can be formed.

[0052] (Modification of the First Embodiment) A modification of the first embodiment will be described. In the above first embodiment, as shown in FIG. 5, the internal concavo-convex structure 130 may be configured such that a plurality of internal concave portions 131 and internal convex portions 132 extend along the X-axis direction and are arranged at equal intervals in the Y-axis direction to form a stripe shape. In this case, since the one-surface concavo-convex structure 100 is configured due to the internal concavo-convex structure 130, a plurality of one-surface concave portions 101 and one-surface convex portions 102 extend along the X-axis direction and are arranged at equal intervals in the Y-axis direction to form a stripe shape. That is, the one-surface concavo-convex structure 100 extends in a direction intersecting the longitudinal direction of the trench 16. Even such a semiconductor substrate 10 includes a portion formed by digging down a portion that becomes the one-surface concave portion 101 in the bottom surface 16a of the trench 16, and the bottom surface 16a formed in this portion has a round shape. Note that FIG. 5 is a perspective cross-sectional view in which the gate insulating film 17, the gate electrode 18, the interlayer insulating film 19, the upper electrode 20, etc. are omitted.

[0053] Further, although not particularly illustrated, the internal concavo-convex structure 130 may be configured such that a plurality of internal concave portions 131 and internal convex portions 132 extend along the X-axis direction and the Y-axis direction and are arranged at equal intervals in the X-axis direction and the Y-axis direction. That is, the internal concavo-convex structure 130 may be formed such that the internal convex portions 132 are scattered in a dot shape. Even if the internal concavo-convex structure 130 is configured in this way, a concavo-convex structure 100 on one surface 10a of the semiconductor substrate 10 is formed due to the internal concavo-convex structure 130, and the bottom surface 16a of the trench 16 can have a portion with a round shape.

[0054] (Second Embodiment) The second embodiment will be described. In this embodiment, the number of trenches is changed compared to the first embodiment. Since the other aspects are the same as those of the first embodiment, the description is omitted here.

[0055] In the SiC semiconductor device of this embodiment, as shown in FIG. 6, the trenches 16 are formed with thinning. That is, a portion that becomes a concave portion 101 on one surface is also arranged in a portion of the semiconductor substrate 10 located between the trenches 16. Specifically, the concave portion 101 on one surface is arranged on the side opposite to the trench 16 with the convex portion 102 on one surface interposed therebetween. Note that FIG. 6 is a perspective cross-sectional view in which the gate insulating film 17, the gate electrode 18, the interlayer insulating film 19, the upper electrode 20, etc. are omitted.

[0056] According to the present embodiment described above, since the trench 16 is formed by digging down a portion that becomes the concave portion 101 on one surface, the same effects as those of the first embodiment can be obtained.

[0057] (1) In this embodiment, the trenches 16 are formed with thinning. Therefore, the portion located between adjacent trenches 16 can be widened. Accordingly, the contact area between the upper electrode 20 and the one surface 10a of the semiconductor substrate 10 can be further improved, and the contact resistance can be further reduced.

[0058] (Third Embodiment) A third embodiment will be described. This embodiment is formed by forming a first deep layer and a second deep layer with respect to the first embodiment. Since other aspects are the same as those of the first embodiment, the description thereof will be omitted here.

[0059] In the SiC semiconductor device of this embodiment, as shown in FIG. 7, a p-type first deep layer 31 is formed in the first drift layer 121. Specifically, the first deep layer 31 is formed from the bottom surface 16a of the internal recess 131 toward the substrate 11 side. Further, a plurality of the first deep layers 31 are extended along the Y-axis direction and are arranged at equal intervals in the X-axis direction so as to be in a stripe shape.

[0060] In addition, a second deep layer 32 is formed in the semiconductor substrate 10. The second deep layer 32 is formed from the second drift layer 122 to the first drift layer 121 so as to connect the first deep layer 31 and the base layer 13. In this embodiment, the second deep layer 32 extends in a direction intersecting the longitudinal direction of the first deep layer 31. Specifically, the second deep layer 32 extends with the X-axis direction as the longitudinal direction and has a layout in which a plurality of them are alternately arranged in the Y-axis direction.

[0061] The above is the configuration of the SiC semiconductor device in this embodiment. In such a SiC semiconductor device, when it is in the off state, an electric field is applied between the drain and the gate, and although the bottom surface 16a of the trench 16 has a round shape, electric field concentration may occur at the bottom of the gate insulating film 17. However, in the SiC semiconductor device of this embodiment, a first deep layer 31 connected to the base layer 13 is formed at a position deeper than the trench 16. Therefore, the depletion layer formed between the first deep layer 31 and the drift layer 12 suppresses the rise of the equipotential line due to the influence of the drain voltage, and it becomes difficult for a high electric field to enter the gate insulating film 17. Therefore, in this embodiment, it is possible to further suppress the gate insulating film 17 from being broken.

[0062] Next, a method for manufacturing the SiC semiconductor device will be described.

[0063] When manufacturing the SiC semiconductor device of the present embodiment, after performing the process of FIG. 3B to form the internal uneven structure 130, as shown in FIG. 8, the mask 40 used when forming the internal recess 131 is used as the mask for ion implantation as it is. Then, using this mask 40, p-type impurities are ion-implanted into the first drift layer 121 to form the first deep layer 31. After that, when performing the process of FIG. 3D, by ion-implanting p-type impurities to form the second deep layer 32, the SiC semiconductor device shown in FIG. 7 is manufactured.

[0064] According to the present embodiment described above, since the trench 16 is formed by digging down the portion that becomes the one-sided recess 101, the same effect as the first embodiment can be obtained.

[0065] (1) In the present embodiment, the first deep layer 31 connected to the base layer 13 is formed at a position deeper than the trench 16. Therefore, when the SiC semiconductor device is in the off state, the destruction of the gate insulating film 17 can be further suppressed.

[0066] (Other Embodiments) Although the present disclosure has been described in accordance with the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure also includes various modifications and modifications within the equivalent scope. In addition, various combinations and forms, and further, other combinations and forms including only one element, more, or less thereof, are within the scope and spirit of the present disclosure.

[0067] For example, in each of the above embodiments, an n-channel type MOSFET with a trench gate structure having an n-type first conductivity type and a p-type second conductivity type was taken as an example for explanation. However, this is merely an example, and other semiconductor device structures, for example, a p-channel type MOSFET with a trench gate structure in which the conductivity types of the respective components are inverted with respect to the n-channel type, may also be used. Furthermore, the semiconductor device may be configured such that, in addition to the MOSFET, an IGBT having a similar structure is formed. In the case of the IGBT, it is the same as the vertical MOSFET described in the first embodiment except that the n + type substrate 11 is changed to a p + type collector layer.

[0068] In each of the above embodiments, the arrangement shapes of the source region 14 and the contact region 15 can be appropriately changed. For example, the source region 14 may be formed so as to be in contact with the side surface of the trench 16, and the contact region 15 may be formed on the side opposite to the trench 16 with the source region 14 interposed therebetween. That is, the source region 14 and the contact region 15 may be arranged side by side in the X-axis direction.

[0069] And the SiC semiconductor devices of the above embodiments may be combined. For example, the second embodiment and the third embodiment may be combined so that the trenches 16 are formed with thinning.

Explanation of Reference Numerals

[0070] 10 Semiconductor substrate 10a One surface 11 Substrate (high-concentration layer) 12 Drift layer 13 Base layer 14 Source region (impurity region) 16 Trench 17 Gate insulating film 18 Gate electrode 20 Upper electrode (first electrode) 21 Lower electrode (second electrode) 102 One-surface convex portion

Claims

1. A silicon carbide semiconductor device having a trench gate structure, comprising: an n-type drift layer (12), a p-type base layer (13) formed on the surface layer portion of the drift layer, a p-type impurity region (14) formed on the surface layer portion of the base layer and having a higher impurity concentration than the drift layer, and a high-concentration layer (11) of p-type or n-type formed on the side opposite to the base layer with the drift layer interposed therebetween and having a higher impurity concentration than the drift layer; a semiconductor substrate (10) made of silicon carbide, having one surface (10a) formed on the side of the base layer and the other surface (10b) formed on the side of the high-concentration layer; a plurality of the trench gate structures each having a gate insulating film (17) formed on the wall surface of a trench (16) penetrating through the base layer and the impurity region to reach the drift layer, and a gate electrode (18) formed on the gate insulating film; a first electrode (20) disposed on the one surface side and electrically connected to the base layer and the impurity region; a second electrode (21) disposed on the other surface side and electrically connected to the high-concentration layer; wherein the trench has a portion with a round bottom surface (16a); wherein one surface of the semiconductor substrate has a round-shaped one surface convex portion (102) bulging at a portion located between adjacent trenches; wherein the drift layer is composed of an n-type first drift layer (121) and an n-type second drift layer (122) laminated in this order from the high-concentration layer side; wherein the trench is formed with the bottom surface located in the second drift layer; a silicon carbide semiconductor device, wherein an internal concave portion (131) is formed at a portion of the surface (121a) of the first drift layer on the second drift layer side, which faces the bottom surface of the trench.

2. The internal concave portion extends along one direction in the plane direction of the semiconductor substrate. The trench extends along the one direction. The silicon carbide semiconductor device according to claim 1.

3. One surface of the semiconductor substrate has a portion which is round-shaped and recessed at a portion located between adjacent trenches, and forms a one surface concave portion (101) located on the side opposite to the trench with the one surface convex portion interposed therebetween. The silicon carbide semiconductor device according to claim 2.

4. In the drift layer, a first deep layer (31) of a second conductivity type, which is formed from the bottom surface of the internal recess toward the high-concentration layer side and is formed in a state separated from the trench, and a second deep layer (32) of a second conductivity type that connects the base layer and the first deep layer are formed. The silicon carbide semiconductor device according to any one of claims 1 to 3.

5. A semiconductor substrate (10) made of silicon carbide, having a drift layer (12) of a first conductivity type, a base layer (13) of a second conductivity type formed on the surface layer portion of the drift layer, and an impurity region (14) of a first conductivity type formed on the surface layer portion of the base layer and having a higher impurity concentration than the drift layer, and a high-concentration layer (11) of a first conductivity type or a second conductivity type formed on the side opposite to the base layer with the drift layer interposed therebetween and having a higher impurity concentration than the drift layer, wherein one surface (10a) is formed on the surface on the base layer side and the other surface (10b) is formed on the surface on the high-concentration layer side. A plurality of trench gate structures having a gate insulating film (17) formed on the wall surface of a trench (16) that penetrates the base layer and the impurity region and reaches the drift layer, and a gate electrode (18) formed on the gate insulating film. A first electrode (20) disposed on the one surface side and electrically connected to the base layer and the impurity region. A second electrode (21) disposed on the other surface side and electrically connected to the high-concentration layer. The trench has a portion where the bottom surface (16a) is round-shaped. A method of manufacturing a silicon carbide semiconductor device, wherein one surface of the semiconductor substrate has a round-shaped one surface convex portion (102) that bulges at a portion located between adjacent trenches. Preparing a constituent substrate (200) that constitutes the drift layer. Etching the constituent substrate to form an internal recess (131), thereby forming an internal concavo-convex structure (130) including the internal convex portion (132) of a portion different from the internal recess. Epitaxially growing a constituent layer (210) on the constituent substrate to form the semiconductor substrate, thereby forming a one surface concavo-convex structure (100) in which a portion located on the internal recess on one surface of the semiconductor substrate becomes a round-shaped one surface concave portion (101) and a portion located on the internal convex portion becomes a round-shaped one surface convex portion (102). A method of manufacturing a silicon carbide semiconductor device, which includes forming a trench by forming the trench to include a portion that becomes the one-side concave portion of the one-side concavo-convex structure, so that the bottom surface of the trench has a round shape inheriting the shape of the one-side concave portion, and configuring a portion located between the trenches on the one-side to include the one-side convex portion.

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