Semiconductor device and method of manufacturing the same

Abstract

To easily increase the impurity concentration in an ion-implanted layer while variations in characteristics of a semiconductor device are suppressed.SOLUTION: A substrate device includes a semiconductor substrate 10 having one surface 10a and the other surface 10b, and a semiconductor element including ion-implanted layers 15, 22, and 23 formed on the semiconductor substrate 10, and the ion-implanted layers 15, 22, and 23 are made to contain a rare gas element and a first conductivity type impurity or a second conductivity type impurity.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device having an ion implantation layer and a method for manufacturing the same.

Background Art

[0002] Conventionally, a semiconductor device having an ion implantation layer and a method for manufacturing the same have been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor device, a semiconductor substrate having a drift layer is provided, a base layer is formed on one surface side of the semiconductor substrate, and a source region and a contact region are formed in a surface layer portion of the base layer. Further, a trench is formed in the semiconductor substrate so as to penetrate the source region and the base layer. Then, a trench gate structure is configured by disposing a gate insulating film and a gate electrode in the trench.

[0003] A drain region is disposed on the other surface side of the semiconductor substrate. An upper electrode is disposed on one surface side of the semiconductor substrate so as to be electrically connected to the source region and the contact region. A lower electrode is disposed on the other surface side of the semiconductor substrate so as to be electrically connected to the drain region.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Incidentally, in the above semiconductor device, the source region and the contact region are constituted by an ion implantation layer formed by ion implantation. And, in order to reduce the contact resistance with the upper electrode, it is desirable to increase the impurity concentration on one side. That is, in the above semiconductor device, it is desirable to increase the impurity concentration of at least a part of the ion implantation layer.

[0006] In this case, in order to increase the impurity concentration on one side of the source region and the contact region, for example, it is conceivable to increase the dose amount when performing ion implantation. Here, the ion implantation layer is formed by performing a heat treatment after ion implantation, and the implanted impurities enter into the vacancies (that is, defects) formed during ion implantation and are activated. However, when trying to increase the impurity concentration by increasing the dose amount, although it can be made higher compared to the case where the dose amount is small, the activation rate does not increase, so there is a possibility that the variation in the formed defects may cause a large variation in the impurity concentration, and the characteristics of the semiconductor device may vary.

[0007] Also, when manufacturing a semiconductor device, new defects may be introduced during the manufacturing process. For this reason, in the manufacturing method of the above semiconductor device, due to the variation in the defects that can be introduced, even if ion implantation is performed with the same dose amount, the activation rate of the impurities changes, and the characteristics of the semiconductor device may vary due to the variation in the impurity concentration.

[0008] In view of the above points, an object of the present invention is to provide a semiconductor device and a manufacturing method thereof that can easily increase the impurity concentration of the ion implantation layer while suppressing variations in the characteristics of the semiconductor device.

Means for Solving the Problems

[0009] Claim 1 for achieving the above object and 3A semiconductor device in which a semiconductor element is formed, comprising: a semiconductor substrate (10) having one surface (10a) and the other surface (10b); and a semiconductor element including ion implantation layers (15, 22, 23) formed on the semiconductor substrate, wherein the ion implantation layers are formed of a noble gas element and an impurity of a first conductivity type or an impurity of a second conductivity type. Claim 1 has an electrode (29) disposed on one surface of a semiconductor substrate. In the semiconductor substrate, connection regions (22, 23) connected to the electrode are formed on the one surface side. The connection regions are composed of ion implantation layers, and the portion on the electrode side has a higher impurity concentration than the portion on the side opposite to the electrode side. , The semiconductor substrate has a drift layer (19) of a first conductivity type, a base layer (21) of a second conductivity type formed on the surface layer portion of the drift layer, a first impurity region (22) of the first conductivity type as a connection region formed on the surface layer portion of the base layer and having a higher impurity concentration than the drift layer, a second impurity region (23) of the second conductivity type as a connection region formed on the surface layer portion of the base layer and having a higher impurity concentration than the base layer, and a high-concentration layer (11) of the first conductivity type or the second conductivity type formed on the side opposite to the base layer with the drift layer interposed therebetween and having a higher impurity concentration than the drift layer. One surface of the semiconductor substrate is composed of the first impurity region and the second impurity region, and the electrode is disposed on one surface of the semiconductor substrate and connected to the first impurity region and the second impurity region. Claim 3: The semiconductor substrate has a drift layer (19) of a first conductivity type, a base layer (21) of a second conductivity type formed on the surface layer portion of the drift layer, a first impurity region (22) of the first conductivity type formed on the surface layer portion of the base layer and having a higher impurity concentration than the drift layer, a second impurity region (23) of the second conductivity type formed on the surface layer portion of the base layer and having a higher impurity concentration than the base layer, and a high-concentration layer (11) of the first conductivity type or the second conductivity type formed on the side opposite to the base layer with the drift layer interposed therebetween and having a higher impurity concentration than the drift layer. It has a trench gate structure having a gate insulating film (26) formed on the wall surface of a trench (25) that penetrates the base layer and the first impurity region and reaches the drift layer, and a gate electrode (27) formed on the gate insulating film. It also has a first deep layer (15) of the second conductivity type formed below the trench in the drift layer and separated from the trench, and a second deep layer (18) of the second conductivity type connecting the base layer and the first deep layer. The first deep layer is composed of an ion implantation layer and is configured to have a high-concentration peak (P) on the one surface side of the semiconductor substrate with a higher impurity concentration than the portion on the side opposite to the one surface side.

[0010] According to this, the ion implantation layer is formed of an impurity and a noble gas element. Therefore, each impurity is easily activated, and variations in the impurity concentration can be suppressed, so that variations in the characteristics of the semiconductor device can be suppressed. Further, since each impurity is easily activated, the impurity concentration can be increased without increasing the dose amount.

[0011] Further, when manufacturing the semiconductor device, new defects are introduced during the manufacturing process, and the activation rate is likely to vary due to the defects. However, since the ion implantation layer is formed of a noble gas element, it is easy to make the influence of the noble gas element dominant in the activation rate of the impurity. Therefore, the activation rate can be stabilized, and variations in the characteristics of the semiconductor device can be suppressed.

[0012] Further, claim 4 is a method for manufacturing the semiconductor device according to claim in 1 , comprising: ion implanting an impurity of a first conductivity type or an impurity of a second conductivity type and a noble gas element to form a constituent layer (150a, 220a, 230a); and performing an activation process by heat treatment to activate the impurity in the constituent layer to form an ion implantation layer. Claim 5 is a method for manufacturing the semiconductor device according to Claim 3. Claims 4 and 5

[0013] ​According to this, the ion implantation layer is configured to include an impurity and a noble gas element. Therefore, the impurity is likely to be activated, and variations in the impurity concentration can be suppressed, so that a semiconductor device with suppressed variations in characteristics can be manufactured. Further, since each impurity is likely to be activated, a semiconductor device with a high impurity concentration can be manufactured without increasing the dose amount.

[0014] In addition, when manufacturing a semiconductor device, new defects are introduced during the manufacturing process, and the activation rate is likely to vary due to these defects. However, since the ion implantation layer is configured to include a noble gas element, it is easy to make the influence of the noble gas element dominant over the activation rate of the impurity. Therefore, the activation rate can be stabilized, and a semiconductor device with suppressed variations in characteristics can be manufactured.

[0015] Note that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments below.

Brief Description of the Drawings

[0016]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 4E

Figure 4F

Figure 4G

Figure 4H

Figure 5

Figure 6

Mode for Carrying Out the Invention

[0017] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are identical or equivalent to each other will be denoted by the same reference numerals and described.

[0018] (First Embodiment) The first embodiment will be described with reference to the drawings. The semiconductor device of this embodiment is preferably applied, for example, as a device mounted on a vehicle such as an automobile and for driving various electronic devices for the vehicle. Further, in this embodiment, a silicon carbide (hereinafter also referred to as SiC) semiconductor device in which an inversion-type MOSFET having a trench gate structure is formed will be described. In this embodiment, the configuration of the cell region in which the MOSFET of the SiC semiconductor device is formed will be described, but an actual SiC semiconductor device is provided with an outer peripheral region in which an FLR (abbreviation for Field Limiting Ring) structure or the like is formed so as to surround the cell region.

[0019] Also, hereinafter, one direction in the plane direction of the substrate 11 to be described later is defined as the X-axis direction, a direction intersecting one direction in the plane direction of the substrate is defined as the Y-axis direction, and a direction orthogonal to the X-axis direction and the Y-axis direction is defined as the Z-axis direction for explanation. Note that in the present embodiment, the X-axis direction and the Y-axis direction are orthogonal to each other. Also, the Z-axis direction in the present embodiment corresponds to the depth direction of the semiconductor substrate 10 to be described later, and also corresponds to the stacking direction of the drift layer 19 and the base layer 21 to be described later.

[0020] As shown in FIG. 1, the SiC semiconductor device is configured using a semiconductor substrate 10. Specifically, the SiC semiconductor device includes an n- + type substrate 11 made of SiC. In the present embodiment, as the substrate 11, for example, it has an off-angle of 0 to 8° with respect to the (0001) Si plane, and the n-type impurity concentration such as nitrogen or phosphorus is 1.0×10 19 / cm 3 and has a thickness of about 300 μm. Note that the substrate 11 constitutes a drain region in the present embodiment and corresponds to a high-concentration layer.

[0021] On the surface of the substrate 11, an n- - type buffer layer 12 made of SiC is formed. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. And the buffer layer 12 has an n-type impurity concentration that is the impurity concentration between the substrate 11 and the low-concentration layer 13 to be described later, and has a thickness of about 1 μm.

[0022] On the surface of the buffer layer 12, for example, an n-type impurity concentration is 5.0 to 10.0×10 15 / cm 3 and an n- - type low-concentration layer 13 made of SiC with a thickness of about 10 to 15 μm is formed. This low-concentration layer 13 may have a constant impurity concentration in the Z-axis direction, but it is preferably given a concentration distribution gradient such that the side of the low-concentration layer 13 closer to the substrate 11 has a higher concentration than the side farther from the substrate 11. For example, in the low-concentration layer 13, the impurity concentration of a portion about 3 to 5 μm from the surface of the substrate 11 is 2.0×1015 / cm 3 It is preferably made higher than other portions of the same degree. By adopting such a configuration, the internal resistance of the low-concentration layer 13 can be reduced, and the on-resistance can be reduced.

[0023] A JFET portion 14 and a first deep layer 15 are formed in the surface layer portion of the low-concentration layer 13. In the present embodiment, the JFET portion 14 and the first deep layer 15 each extend along the X-axis direction and have linear portions alternately arranged in the Y-axis direction. That is, the JFET portion 14 and the first deep layer 15 are each formed in a stripe shape extending along the X-axis direction in the normal direction to the surface of the substrate 11, and they are configured to have a layout in which they are alternately arranged along the Y-axis direction. Note that the normal direction to the surface of the substrate 11 can also be described as when viewed from the normal direction to the surface of the substrate 11. Further, the normal direction to the surface of the substrate 11 is also the direction along the stacking direction of the drift layer 19 and the base layer 21 described later.

[0024] The JFET portion 14 is of n-type with an impurity concentration higher than that of the low-concentration layer 13, and the depth is 0.3 to 1.5 μm. In the present embodiment, the JFET portion 14 has an n-type impurity concentration of 7.0×10 16 ~5.0×10 17 / cm 3 The first deep layer 15 is composed of an ion implantation layer formed by ion implantation and contains a rare gas element and a p-type impurity. The impurity concentration of the first deep layer 15 will be described later.

[0025] In addition, the first deep layer 15 of the present embodiment is formed shallower than the JFET portion 14. That is, the first deep layer 15 is formed such that the bottom is located within the JFET portion 14. In other words, the first deep layer 15 is formed such that the JFET portion 14 is located between the first deep layer 15 and the low-concentration layer 13.

[0026] On the JFET section 14 and the first deep layer 15, a current dispersion layer 17, a second deep layer 18, a base layer 21, a source region 22, a contact region 23, etc. are formed.

[0027] The current dispersion layer 17 is of n-type and is formed so as to be connected to the JFET section 14. For this reason, in the present embodiment, the low-concentration layer 13, the JFET section 14, and the current dispersion layer 17 are connected, and the drift layer 19 is constituted by these. And the first deep layer 15 is in a state of being formed within the drift layer 19.

[0028] The second deep layer 18 is of p-type and has the same thickness as the current dispersion layer 17. Also, the second deep layer 18 is formed so as to be connected to the first deep layer 15.

[0029] And the current dispersion layer 17 and the second deep layer 18 extend in a direction intersecting the longitudinal direction of the stripe-shaped portion of the JFET section 14 or the first deep layer 15. In the present embodiment, the current dispersion layer 17 and the second deep layer 18 extend with the Y-axis direction as the longitudinal direction and have a layout in which a plurality of them are arranged alternately in the X-axis direction. Note that the formation pitch of the current dispersion layer 17 and the second deep layer 18 is adjusted to the formation pitch of the trench gate structure described later, and the second deep layer 18 is formed so as to sandwich the trench 25 described later.

[0030] The base layer 21 is of p-type and is formed on the current dispersion layer 17 and the second deep layer 18. For this reason, the first deep layer 15 is in a state of being connected to the base layer 21 via the second deep layer 18.

[0031] The source region 22 is of n + -type and is formed in the surface layer portion of the base layer 21. The contact region 23 is of p +It is of a type and is formed on the surface layer portion of the base layer 21. Specifically, the source region 22 is formed so as to be in contact with the side surface of a trench 25 described later, and the contact region 23 is formed on the side opposite to the trench 25 described later with the source region 22 interposed therebetween. In this embodiment, the source region 22 and the contact region 23 correspond to a connection region, the source region 22 corresponds to a first impurity region, and the contact region 23 corresponds to a second impurity region.

[0032] The base layer 21 has, for example, a p-type impurity concentration of 3.0×10 17 / cm 3 or less. Also, the base layer 21 of this embodiment is formed, for example, by ion implantation or the like. The source region 22 is composed of an ion implantation layer formed by ion implantation and is composed of a noble gas element and an n-type impurity. The contact region 23 is composed of an ion implantation layer formed by ion implantation and is composed of a noble gas element and a p-type impurity. Note that the impurity concentrations of the source region 22 and the contact region 23 will be described later.

[0033] In this embodiment, as described above, the semiconductor substrate 10 is configured to include the substrate 11, the buffer layer 12, the low-concentration layer 13, the JFET portion 14, the first deep layer 15, the current dispersion layer 17, the second deep layer 18, the base layer 21, the source region 22, the contact region 23, and the like. And since the semiconductor substrate 10 is configured as described above, it can be said that the semiconductor substrate 10 is made of SiC. Also, in this embodiment, one surface 10a of the semiconductor substrate 10 is composed of the source region 22 and the contact region 23, and the other surface 10b of the semiconductor substrate 10 is composed of the substrate 11.

[0034] In the semiconductor substrate 10, for example, trenches 25 having a width of 1.4 to 2.0 μm are formed so as to penetrate through the source region 22, the base layer 21, etc. and reach the current dispersion layer 17, and the bottom surface is positioned within the current dispersion layer 17. Note that the trenches 25 are formed so as not to reach the JFET portion 14 and the first deep layer 15. That is, the trenches 25 are formed such that the JFET portion 14 and the first deep layer 15 are positioned below the bottom surface and separated from the trenches 25.

[0035] Also, although only one trench 25 is shown in FIG. 1, actually, a plurality of trenches 25 are extended along the Y-axis direction and arranged at equal intervals in the X-axis direction to form a stripe shape. That is, in the present embodiment, the trenches 25 are formed such that the longitudinal direction is orthogonal to the longitudinal direction of the first deep layer 15. Further, the trenches 25 are formed so as to be sandwiched by the second deep layer 18 in the stacking direction of the drift layer 19 and the base layer 21.

[0036] A gate insulating film 26 is formed on the inner wall surface of the trench 25, and a gate electrode 27 composed of doped Poly-Si or the like is formed on the gate insulating film 26. Thereby, a trench gate structure is configured. Although not particularly limited, the gate insulating film 26 is formed by thermally oxidizing the inner wall surface of the trench 25 or performing a CVD (abbreviation for chemical vapor deposition) method. And the gate insulating film 26 has a thickness of about 100 nm both on the side surface side and the bottom surface side of the trench 25.

[0037] Note that the gate insulating film 26 is also formed on the surfaces other than the inner wall surface of the trench 25. Specifically, the gate insulating film 26 is formed so as to cover a part of one surface 10a of the semiconductor substrate 10. More specifically, the gate insulating film 26 is formed so as to cover a part of the surface of the source region 22. In other words, contact holes 26a for exposing the source region 22 and the contact region 23 are formed in a portion of the gate insulating film 26 different from the portion where the gate electrode 27 is disposed.

[0038] An interlayer insulating film 28 is formed on one surface 10a of the semiconductor substrate 10 so as to cover the gate electrode 27, the gate insulating film 26, etc. The interlayer insulating film 28 is made of BPSG (abbreviation for Borophosphosilicate Glass) or the like.

[0039] Contact holes 28a for exposing the source region 22 and the contact region 23 are formed in the interlayer insulating film 28 so as to communicate with the contact holes 26a. Note that the contact holes 28a formed in the interlayer insulating film 28 are formed so as to communicate with the contact holes 26a formed in the gate insulating film 26, and function as one contact hole together with the contact holes 26a. Therefore, hereinafter, the contact holes 26a and the contact holes 28a are collectively referred to as contact holes 26b. The pattern of the contact holes 26b is arbitrary, and examples thereof include a pattern in which a plurality of square shapes are arranged, a pattern in which rectangular linear shapes are arranged, or a pattern in which linear shapes are arranged side by side. In the present embodiment, the contact holes 26b are linear along the longitudinal direction of the trench 25.

[0040] An upper electrode 29 that is electrically connected to the source region 22 and the contact region 23 through the contact holes 26b is formed on the interlayer insulating film 28. Note that in the present embodiment, the upper electrode 29 corresponds to the first electrode.

[0041] The upper electrode 29 of this embodiment is composed of an Al-Si layer or the like mainly containing Al (aluminum), and is connected to the source region 22 and the contact region 23 as follows. Specifically, a metal silicide layer 30 composed of a metal such as Ni (nickel) is formed on the portions of the source region 22 and the contact region 23 that are exposed from the contact hole 26b. This metal silicide layer 30 is for reducing the contact resistance between the source region 22 and the contact region 23 and the upper electrode 29.

[0042] And a barrier metal film 31 composed of Ti (titanium), TiN (titanium nitride), or the like is formed on the metal silicide layer 30. Note that the barrier metal film 31 is also formed on the wall surface of the contact hole 26b and the surface of the interlayer insulating film 28. This barrier metal film 31 suppresses the diffusion of Al constituting the upper electrode 29 to the semiconductor substrate 10 side or the interlayer insulating film 28 side, and suppresses the diffusion of Ni constituting the metal silicide layer 30 to the upper electrode 29 side.

[0043] And the upper electrode 29 is disposed on the barrier metal film 31, and is connected to the source region 22 and the contact region 23 via the barrier metal film 31 and the metal silicide layer 30.

[0044] A lower electrode 32 that is electrically connected to the substrate 11 is formed on the other surface 10b side of the semiconductor substrate 10. In this embodiment, the lower electrode 32 corresponds to the second electrode.

[0045] In the SiC semiconductor device of this embodiment, a MOSFET having a trench gate structure of an n-channel type inversion type is configured by such a structure. In this embodiment, the n - type, n-type, n + type corresponds to the first conductivity type, and the p-type, p + type corresponds to the second conductivity type.

[0046] And as will be described later, in such a SiC semiconductor device, when the gate voltage applied to the gate electrode 27 is equal to or higher than the threshold voltage of the insulated gate structure, a current flows between the upper electrode 29 and the lower electrode 32, resulting in an on-state. Also, in such a SiC semiconductor device, when the gate voltage applied to the gate electrode 27 is less than the threshold voltage, no current flows between the upper electrode 29 and the lower electrode 32, resulting in an off-state.

[0047] Next, the impurity concentrations of the ion implantation layers that constitute the source region 22, the contact region 23, and the first deep layer 15 in the present embodiment will be specifically described.

[0048] As described above, the source region 22 of the present embodiment is composed of an ion implantation layer and includes a noble gas element and an n-type impurity. By increasing the impurity concentration of the portion on the upper electrode 29 side (i.e., the metal silicide layer 30 side), the contact resistance with the upper electrode 29 can be reduced. Therefore, as shown in FIG. 2, the source region 22 is formed to have a concentration profile in which the impurity concentration of the portion on the upper electrode 29 side is higher than that of the portion on the side opposite to the upper electrode 29. In other words, the source region 22 is formed to have a concentration profile in which the impurity concentration of the portion on the side of surface 10a (i.e., the metal silicide layer 30) is higher in the Z-axis direction (i.e., the depth direction).

[0049] As described above, the contact region 23 is composed of an ion implantation layer and includes a noble gas element and a p-type impurity. Although not particularly shown, similar to the source region 22, the contact region 23 is formed such that the impurity concentration of the portion on the upper electrode 29 side is higher than that of the portion on the side opposite to the upper electrode 29.

[0050] Although not particularly limited, the source region 22 has an n-type impurity concentration on the upper electrode 29 side, i.e., a surface concentration of, for example, 1.0×10 21 / cm 3It is as described above. The contact region 23 has a p-type impurity concentration on the upper electrode 29 side, that is, a surface concentration of, for example, 1.0×10 21 / cm 3 or more.

[0051] As described above, the first deep layer 15 is composed of an ion implantation layer and is composed of a rare gas element and a p-type impurity. As shown in FIG. 3, the first deep layer 15 has a high-concentration region 15a having a high-concentration peak P where the impurity concentration is maximized on the interface side with the current dispersion layer 17 and the impurity concentration is such that it does not deplete in the off state. Further, the first deep layer 15 has a concentration profile having a region where the impurity concentration hardly changes along the Z-axis direction on the substrate 11 side from the high-concentration region 15a and having a low-concentration region 15b that depletes in the off state. Note that the portion of the first deep layer 15 on the substrate 11 side has a steeply large slope of change in impurity concentration and a steeply small impurity concentration, but this portion is also a region that depletes, so it becomes the low-concentration region 15b.

[0052] And, for such a first deep layer 15, it is preferable that the impurity concentration of the high-concentration peak P is increased so that a region that does not deplete is formed in the high-concentration region 15a. The high-concentration peak P has a higher impurity concentration than the current dispersion layer 17 and is, for example, 1.0×10 18 / cm 3 or more.

[0053] The above is the configuration of the SiC semiconductor device in this embodiment. Next, the operation and effects of the SiC semiconductor device will be described.

[0054] First, in the SiC semiconductor device, in the off state before a gate voltage equal to or higher than the threshold voltage is applied to the gate electrode 27, an inversion layer is not formed in the base layer 21. Therefore, even if a positive voltage, for example, 1600V is applied to the lower electrode 32, electrons do not flow from the source region 22 into the base layer 21, and the SiC semiconductor device is in an off state where no current flows between the upper electrode 29 and the lower electrode 32.

[0055] Also, when the SiC semiconductor device is in the off state, an electric field is applied between the drain and the gate, and electric field concentration may occur at the bottom of the gate insulating film 26. However, in the SiC semiconductor device, the first deep layer 15 and the JFET section 14 are provided at a position deeper than the trench 25. And the first deep layer 15 has an impurity concentration at which the high-concentration peak P is not depleted. Therefore, the depletion layer formed between the first deep layer 15 and the JFET section 14 suppresses the rise of the equipotential line due to the influence of the drain voltage, making it difficult for a high electric field to enter the gate insulating film 26. Therefore, in the present embodiment, it is possible to suppress the gate insulating film 26 from being broken.

[0056] Also, the low-concentration region 15b in the first deep layer 15 has an impurity concentration at which it is depleted. Therefore, when the SiC semiconductor device is in the off state, the portion including the low-concentration region 15b in the first deep layer 15 is also depleted. Therefore, it is possible to suppress a decrease in the breakdown voltage of the SiC semiconductor device by forming the first deep layer 15.

[0057] Then, when a gate voltage equal to or higher than the threshold voltage, for example, 20 V, is applied to the gate electrode 27, an inversion layer is formed on the surface of the base layer 21 in contact with the trench 25. As a result, a current flows between the upper electrode 29 and the lower electrode 32, and the SiC semiconductor device is turned on. In the present embodiment, since the electrons passing through the inversion layer flow through the current dispersion layer 17, the JFET section 14, and the low-concentration layer 13 to the substrate 11, it can be said that a drift layer 19 having the current dispersion layer 17, the JFET section 14, and the low-concentration layer 13 is formed.

[0058] Subsequently, a method for manufacturing the SiC semiconductor device of the present embodiment will be described with reference to FIGS. 4A to 4H. Note that FIGS. 4A to 4H are cross-sectional views with the Y-axis direction in FIG. 1 as the normal direction.

[0059] First, as shown in FIG. 4A, a constituent substrate 100 is prepared on the surface of a substrate 11, on which a buffer layer 12, a low-concentration layer 13, and a JFET section 14, all made of SiC, are formed. In other words, a constituent substrate 100 is prepared, which includes a portion of the drift layer 19 on the substrate 11 side.

[0060] Then, as shown in FIG. 4B, by performing ion implantation using a mask (not shown) on the constituent substrate 100, a first deep layer constituent layer 150 that constitutes a first deep layer 15 is formed by performing an activation process. Specifically, the first deep layer constituent layer 150 is formed by performing ion implantation multiple times while changing the acceleration energy so that the first deep layer 15 having a high-concentration region 15a and a low-concentration region 15b as shown in FIG. 3 is constituted. Further, when forming the first deep layer constituent layer 150, an inert gas element such as Ar is ion-implanted together with Al or the like as a p-type impurity. However, in this step, it is preferable to ion-implant the p-type impurity after ion-implanting the inert gas element. Note that the inert gas element may be He, Ne, Xe, Rn, or the like. Also, regarding the inert gas element implanted in the ion implantation described later, although Ar is taken as an example for explanation, it may be He, Ne, Xe, Rn, or the like.

[0061] Subsequently, as shown in FIG. 4C, a constituent layer 17a for forming a current dispersion layer 17 or the like is epitaxially grown on the JFET section 14 and the first deep layer 15 to constitute a semiconductor substrate 10.

[0062] Next, as shown in FIG. 4D, an n-type impurity is ion-implanted using a mask (not shown) on one surface 10a of the semiconductor substrate 10, and a current dispersion layer constituent layer 170 that constitutes a current dispersion layer 17 is formed by performing an activation process. Also, a p-type impurity is ion-implanted using a mask (not shown) on one surface 10a of the semiconductor substrate 10, and a second deep layer constituent layer 180 that constitutes a second deep layer 18 is formed by performing an activation process.

[0063] Subsequently, as shown in FIG. 4E, p-type impurities are ion-implanted onto one surface 10a of the semiconductor substrate 10 again using a mask (not shown), and an activation process is performed to form a base layer constituent layer 210 that constitutes the base layer 21. Also, n-type impurities are ion-implanted onto one surface 10a of the semiconductor substrate 10 using a mask (not shown), and an activation process is performed to form a source region constituent layer 220 that constitutes the source region 22. Further, p-type impurities are ion-implanted onto one surface 10a of the semiconductor substrate 10 using a mask (not shown), and an activation process is performed to form a contact region constituent layer 230 that constitutes the contact region 23.

[0064] At this time, when forming the source region constituent layer 220 and the contact region constituent layer 230, multiple ion implantations are performed while changing the acceleration energy so as to obtain a concentration profile as shown in FIG. 2 above, thereby forming the source region constituent layer 220 and the contact region constituent layer 230. Also, when forming the source region constituent layer 220, Ar as a noble gas element is ion-implanted together with the n-type impurities. Similarly, when forming the contact region constituent layer 230, Ar as a noble gas element is ion-implanted together with the p-type impurities.

[0065] Thereafter, as shown in FIG. 4F, a carbon mask (not shown) is disposed on the semiconductor substrate 10, and a heat treatment is performed at 1700 to 1900° to perform an activation process for activating each impurity. As a result, the first deep layer 15, the current dispersion layer 17, the second deep layer 18, the base layer 21, the source region 22, and the contact region 23 are formed.

[0066] At this time, in the present embodiment, Ar as a noble gas element is ion-implanted into the first deep layer constituent layer 150, the source region constituent layer 220, and the contact region constituent layer 230 together with various impurities, and the crystallinity is in a state of being disrupted. Note that the disruption of crystallinity by ion-implanting Ar here means that, compared with the case where defects are formed by ion-implanting p-type impurities or n-type impurities, since Ar has a larger atomic weight than various impurities, the disruption of crystallinity (defects) increases and becomes a stable disruption of crystallinity.

[0067] When heat treatment is performed, since the disruption of crystallinity is increased as described above, various impurities are more likely to be trapped and activated. Note that Ar is a noble gas element and is difficult to be activated, so it is difficult to be trapped when heat treatment is performed. That is, ion-implanting Ar is for increasing the activation rate of various impurities. Therefore, in the portion where the noble gas element is ion-implanted, the activation rate of various impurities can be increased. Also, in the portion where the noble gas element is ion-implanted, the activation rate of various impurities can be stabilized. In other words, in the portion where the noble gas element is ion-implanted, it can be easily made to depend on the implantation amount of Ar for the activation rate of various impurities. That is, in the portion where the noble gas element is ion-implanted, it can be easily made such that the influence of Ar becomes dominant with respect to the activation rate of various impurities. Therefore, in the present embodiment, it becomes easier to form a portion with a high impurity concentration in the first deep layer 15, the source region 22, and the contact region 23, and the variation in the impurity concentration can be suppressed.

[0068] Specifically, as shown in FIG. 5, it is confirmed that by ion-implanting Ar into the source region 22, the impurity concentration can be increased because the impurity concentration is more likely to be activated. Although not particularly shown, the same applies to the contact region 23. Further, as shown in FIG. 6, it is confirmed that by ion-implanting Ar into the first deep layer 15, the impurity concentration of the high-concentration peak P can be increased.

[0069] Note that "with Ar" in FIG. 5 indicates the result of ion-implanting Ar with the same dose amount and acceleration energy as when ion-implanting n-type impurities for forming the source region 22. Similarly, "with Ar" in FIG. 6 indicates the result of ion-implanting Ar with the same dose amount and acceleration energy as when ion-implanting p-type impurities for forming the first deep layer 15. Also, in the cases of "with Ar" and "without Ar" in FIGS. 5 and 6, the dose amounts of the respective impurities are made equal. And by ion-implanting Ar, Ar remains in the semiconductor substrate 10, but since it is a noble gas element and is difficult to activate, it hardly affects the characteristics of the semiconductor device.

[0070] Subsequently, as shown in FIG. 4G, a general semiconductor manufacturing process is performed to form a trench gate structure and to form an interlayer insulating film 28. Then, after forming a contact hole 28b, a metal film for forming a metal silicide layer 30 is disposed in the contact hole 28b. Subsequently, laser annealing or the like is performed to form the metal silicide layer 30.

[0071] Thereafter, as shown in FIG. 4H, by forming a barrier metal film 31, an upper electrode 29, and a lower electrode 32, the SiC semiconductor device is manufactured.

[0072] According to the present embodiment described above, the first deep layer 15, the source region 22, and the contact region 23 are composed of ion-implanted layers, and the ion-implanted layers are composed of containing respective impurities and a noble gas element. For this reason, the respective impurities become easy to activate, and variations in the impurity concentration can be suppressed, so that variations in the characteristics of the SiC semiconductor device can be suppressed. Also, since the respective impurities become easy to activate, the impurity concentration can be increased without increasing the dose amount.

[0073] In addition, when manufacturing a SiC semiconductor device, new defects are introduced during the manufacturing process, and the activation rate is likely to vary due to these defects. However, in this embodiment, by ion-implanting Ar, the crystallinity is deliberately disrupted, making it easier for the influence of Ar on the activation rate to become dominant. Therefore, the activation rate can be stabilized, and variations in the characteristics of the SiC semiconductor device can be suppressed.

[0074] (1) In this embodiment, the impurity concentration on the upper electrode 29 side is increased in the source region 22 and the contact region 23. Therefore, the contact resistance with the upper electrode 29 can be reduced.

[0075] (2) In this embodiment, the impurity concentration of the high-concentration peak P in the high-concentration region 15a of the first deep layer 15 is increased. Therefore, it is easier to form a region that does not deplete during the off state.

[0076] (3) In this embodiment, when forming the first deep layer constituent layer 150, the source region constituent layer 220, and the contact region constituent layer 230, a rare gas element is ion-implanted first and then each impurity is ion-implanted. Therefore, compared with the case where a rare gas element is ion-implanted after each impurity is ion-implanted, scattering of each impurity due to ion-implanting the rare gas element can be suppressed, and variations in the impurity concentration can be suppressed.

[0077] (4) In this embodiment, the semiconductor substrate 10 is made of SiC. And since the substrate 11 made of SiC has initial defects, the semiconductor substrate 10 has defects that depend on the initial defects. Therefore, by ion-implanting Ar to disrupt the crystallinity, it is easier for the influence of Ar on the activation rate to become dominant. Therefore, the activation rate can be stabilized, and variations in the characteristics of the SiC semiconductor device can be suppressed.

[0078] (5) In this embodiment, as described above, by ion-implanting Ar, the activation rate can be improved. Therefore, when performing the heat treatment in the process of FIG. 4F, compared with the case where Ar is not ion-implanted, various impurities can be sufficiently activated even at a relatively low temperature. Therefore, the temperature controllability can be improved and the quality can be stabilized.

[0079] (Other embodiments) Although the present disclosure has been described in accordance with the embodiments, it is understood that the present disclosure is not limited to the embodiments and structures. The present disclosure includes various modifications and modifications within the equivalent range. In addition, various combinations and forms, and further other combinations and forms including only one element, more than one, or less than one thereof, are within the scope and spirit of the present disclosure.

[0080] For example, in the above-described first embodiment, an n-channel type trench gate structure MOSFET with the first conductivity type being n-type and the second conductivity type being p-type was described as an example. However, this is only an example, and other semiconductor device structures, for example, a p-channel type trench gate structure MOSFET in which the conductivity type of each component is inverted with respect to the n-channel type, may also be used. Furthermore, the semiconductor device may be configured such that an IGBT having a similar structure is formed in addition to the MOSFET. In the case of an IGBT, except that the n-type substrate 11 in the first embodiment is changed to a p-type collector layer, it is the same as the vertical MOSFET described in the first embodiment. + type substrate 11 to p + type collector layer, it is the same as the vertical MOSFET described in the first embodiment.

[0081] Also, in the above-described first embodiment, an example in which the semiconductor substrate 10 is made of SiC was described. However, the semiconductor substrate 10 may be configured using a silicon substrate or other compound semiconductor substrates.

[0082] In the first embodiment described above, an example in which the first deep layer 15 extends along the X-axis direction has been explained. However, the first deep layer 15 may extend in the Y-axis direction. Further, in the first embodiment, the first deep layer 15 and the second deep layer 18 may not be formed.

[0083] Also, in the first embodiment, an example in which Ar is ion-implanted under the same conditions as each impurity has been explained. However, ion implantation may be performed under different conditions. For example, by increasing the dose amount of Ar, the activation rate can be further improved.

[0084] Furthermore, in the first embodiment, an example in which the first deep layer 15, the source region 22, and the contact region 23 are configured to contain Ar as a noble gas element has been explained. However, since the activation rate of impurities can be improved by forming an ion-implanted layer containing Ar, the base layer 21 or the like may also be configured by an ion-implanted layer containing Ar. Also, depending on the application to which the SiC semiconductor device is applied, only the first deep layer 15 may be configured to contain Ar as a noble gas element, or only the source region 22 and the contact region 23 may be configured to contain Ar as a noble gas element.

[0085] Also, in the first embodiment, an example in which the current dispersion layer 17 is formed by performing ion implantation after forming the constituent layer 17a has been explained. However, the current dispersion layer 17 may be formed by arranging the constituent layer 17a while adjusting the impurity concentration when arranging the constituent layer 17a by epitaxial growth. That is, the current dispersion layer 17 may be formed simultaneously in the process of arranging the constituent layer 17a instead of by ion implantation.

[0086] And in the first embodiment described above, the semiconductor substrate 10 may be configured by arranging the constituent layer 17a before forming the first deep layer 15, and the first deep layer 15 or the like may be formed by performing ion implantation on the semiconductor substrate 10.

Explanation of Reference Numerals

[0087] 10 Semiconductor substrate 10a One surface 10b The other surface 15 First deep layer (ion implantation layer) 22 Source region (ion implantation layer) 23 Contact region (ion implantation layer)

Claims

1. A semiconductor device in which a semiconductor element is formed, a semiconductor substrate (10) having one surface (10a) and the other surface (10b), and the semiconductor element configured to include ion implantation layers (15, 22, 23) formed on the semiconductor substrate, wherein the ion implantation layer is configured to include a noble gas element and an impurity of a first conductivity type or an impurity of a second conductivity type, having an electrode (29) disposed on one surface of the semiconductor substrate, a connection region (22, 23) connected to the electrode is formed on the one surface side of the semiconductor substrate, the connection region is composed of the ion implantation layer, and an impurity concentration of a portion on the electrode side is made higher than that of a portion on the opposite side of the electrode side, the semiconductor substrate includes a drift layer (19) of a first conductivity type, a base layer (21) of a second conductivity type formed on a surface layer portion of the drift layer, a first impurity region (22) of a first conductivity type as the connection region formed on a surface layer portion of the base layer and having a higher impurity concentration than the drift layer, a second impurity region (23) of a second conductivity type as the connection region formed on a surface layer portion of the base layer and having a higher impurity concentration than the base layer, and a high-concentration layer (11) of a first conductivity type or a second conductivity type formed on the opposite side of the base layer with the drift layer interposed therebetween and having a higher impurity concentration than the drift layer, one surface of the semiconductor substrate is composed of the first impurity region and the second impurity region, and the electrode is disposed on one surface of the semiconductor substrate and connected to the first impurity region and the second impurity region. A semiconductor device.

2. A trench gate structure having a gate insulating film (26) formed on a wall surface of a trench (25) that penetrates the base layer and the first impurity region and reaches the drift layer, and a gate electrode (27) formed on the gate insulating film, a first deep layer (15) of a second conductivity type formed below the trench in the drift layer and formed in a state separated from the trench, and a second deep layer (18) of a second conductivity type connecting the base layer and the first deep layer, wherein the first deep layer is composed of the ion implantation layer and has a configuration having a high-concentration peak (P) in which an impurity concentration is made higher on one surface side of the semiconductor substrate than that of a portion on the opposite side of the one surface side. The semiconductor device according to claim 1.

3. A semiconductor device in which a semiconductor element is formed, A semiconductor substrate (10) having one surface (10a) and the other surface (10b), and the semiconductor element configured to include ion implantation layers (15, 22, 23) formed on the semiconductor substrate, wherein the ion implantation layer is configured to include a noble gas element and an impurity of a first conductivity type or an impurity of a second conductivity type, the semiconductor substrate, has a drift layer (19) of a first conductivity type, a base layer (21) of a second conductivity type formed on a surface layer portion of the drift layer, a first impurity region (22) of a first conductivity type formed on a surface layer portion of the base layer and having a higher impurity concentration than the drift layer, a second impurity region (23) of a second conductivity type formed on a surface layer portion of the base layer and having a higher impurity concentration than the base layer, and a high-concentration layer (11) of a first conductivity type or a second conductivity type formed on the opposite side of the base layer with the drift layer interposed therebetween and having a higher impurity concentration than the drift layer, a trench gate structure having a gate insulating film (26) formed on a wall surface of a trench (25) that penetrates the base layer and the first impurity region and reaches the drift layer, and a gate electrode (27) formed on the gate insulating film, a first deep layer (15) of a second conductivity type formed below the trench in the drift layer and formed in a state separated from the trench, and a second deep layer (18) of a second conductivity type connecting the base layer and the first deep layer, wherein the first deep layer is composed of the ion implantation layer and has a high-concentration peak (P) with a higher impurity concentration on one surface side of the semiconductor substrate than a portion on the opposite side of the one surface side, a semiconductor device.

4. A semiconductor substrate (10) having one surface (10a) and the other surface (10b), and the semiconductor element configured to include ion implantation layers (15, 22, 23) formed on the semiconductor substrate, wherein the ion implantation layer is configured to include a noble gas element and an impurity of a first conductivity type or an impurity of a second conductivity type, has an electrode (29) disposed on one surface of the semiconductor substrate, a connection region (22, 23) connected to the electrode is formed on the one surface side of the semiconductor substrate, the connection region is composed of the ion implantation layer, and a portion on the electrode side has a higher impurity concentration than a portion on the opposite side of the electrode side, the semiconductor substrate, has a drift layer (19) of a first conductivity type, A base layer (21) of a second conductivity type formed on the surface layer portion of the drift layer; A first impurity region (22) of a first conductivity type, which is formed on the surface layer portion of the base layer and has a higher impurity concentration than the drift layer, and serves as the connection region; A second impurity region (23) of a second conductivity type, which is formed on the surface layer portion of the base layer and has a higher impurity concentration than the base layer, and serves as the connection region; A high-concentration layer (11) of a first conductivity type or a second conductivity type, which is formed on the side opposite to the base layer with the drift layer interposed therebetween and has a higher impurity concentration than the drift layer; and One surface of the semiconductor substrate is composed of the first impurity region and the second impurity region; A method for manufacturing a semiconductor device, wherein the electrode is disposed on one surface of the semiconductor substrate and connected to the first impurity region and the second impurity region, comprising: Ion-implanting an impurity of the first conductivity type or an impurity of the second conductivity type and the noble gas element to form constituent layers (150a, 220a, 230a); Performing an activation treatment by heat treatment to activate the impurities in the constituent layers to form the ion-implanted layer.

5. A semiconductor substrate (10) having one surface (10a) and the other surface (10b); A semiconductor element including an ion-implanted layer (15, 22, 23) formed on the semiconductor substrate; The ion-implanted layer is composed of a noble gas element and an impurity of a first conductivity type or an impurity of a second conductivity type; The semiconductor substrate includes: A drift layer (19) of a first conductivity type; A base layer (21) of a second conductivity type formed on the surface layer portion of the drift layer; A first impurity region (22) of a first conductivity type, which is formed on the surface layer portion of the base layer and has a higher impurity concentration than the drift layer; A second impurity region (23) of a second conductivity type, which is formed on the surface layer portion of the base layer and has a higher impurity concentration than the base layer; A high-concentration layer (11) of a first conductivity type or a second conductivity type, which is formed on the side opposite to the base layer with the drift layer interposed therebetween and has a higher impurity concentration than the drift layer; and A trench gate structure having a gate insulating film (26) formed on the wall surface of a trench (25) that penetrates the base layer and the first impurity region and reaches the drift layer, and a gate electrode (27) formed on the gate insulating film. A first deep layer (15) of a second conductivity type, which is below the trench in the drift layer and is formed in a state separated from the trench; A second deep layer (18) of a second conductivity type that connects the base layer and the first deep layer; and The first deep layer is composed of the ion implantation layer, and a method for manufacturing a semiconductor device having a configuration in which a high-concentration peak (P) having a higher impurity concentration than a portion on the side opposite to the one surface side is provided on one surface side of the semiconductor substrate, Ion-implanting an impurity of the first conductivity type or an impurity of the second conductivity type and the noble gas element to form a constituent layer (150a, 220a, 230a); Activating the impurities in the constituent layer by performing an activation process by heat treatment to form the ion implantation layer. A method for manufacturing a semiconductor device.

6. The method for manufacturing a semiconductor device according to claim 4 or 5, wherein in forming the constituent layer, after ion-implanting the noble gas element, the impurity of the first conductivity type or the impurity of the second conductivity type is ion-implanted.

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