Semiconductor device and module

Abstract

A capacitor 1, which is an embodiment of this semiconductor device, comprises a substrate 10, a circuit layer 20, and first resin bodies 30. The circuit layer 20 has: a first electrode layer 22 which is provided on the substrate 10 side; a second electrode layer 24 which is provided facing the first electrode layer 22; a dielectric layer 23 which is provided between the first electrode layer 22 and the second electrode layer 24 in the thickness direction T; a first external electrode 27 which is drawn out to the surface of the circuit layer 20 on the opposite side from the substrate 10; and a second external electrode 28 which is drawn out to the surface of the circuit layer 20 on the opposite side from the substrate 10, and which is provided separately from the first external electrode 27. The first resin bodies 30 are provided at four corners of the substrate 10 in a planar view from the thickness direction T. In the thickness direction T, the ends of the first resin bodies 30 on the opposite side from the substrate 10 are at higher positions than the ends of the first external electrode 27 and the second external electrode 28 on the opposite side from the substrate 10.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a module.

Background Art

[0002] As a typical capacitor element used in a semiconductor integrated circuit, for example, a MIM (Metal Insulator Metal) capacitor is known. The MIM capacitor is a capacitor having a parallel plate structure in which an insulator is sandwiched between a lower electrode and an upper electrode.

[0003] Patent Document 1 discloses an electronic component including a circuit element formed on a substrate, at least one pair of terminal electrodes connected to the circuit element and disposed opposite to at least one surface, and a support formed to protrude from the at least one pair of terminal electrodes and provided in a region that does not overlap the circuit element in a plan view of the at least one surface. Patent Document 1 describes, as an example of an electronic component, a capacitor in which a lower electrode, a dielectric layer, a first electrode, a first protective layer, a second electrode, a second protective layer, terminal electrodes, and a support are laminated in this order on a substrate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] When mounting an electronic component on an external substrate or the like using a surface mounter, a load is applied in the thickness direction of the electronic component during substrate mounting. Therefore, if an excessive load is applied to the electronic component, such a load becomes an impact force, and there may be a problem that the circuit elements formed in the electronic component are damaged. According to the electronic component described in Patent Document 1, the support protrudes more than at least one pair of terminal electrodes arranged opposite to each other. In other words, since the support is formed thicker than at least one pair of terminal electrodes arranged opposite to each other, it is said that the support can prevent mechanical destruction of the electronic component that may occur during mounting by receiving, dispersing, and relaxing the load applied from the outside.

[0006] However, in the electronic component described in Patent Document 1, since the effect of relaxing the load applied to the element surface during mounting is not sufficient, there is a risk that cracks may occur in the dielectric layer due to the load transmitted from the support.

[0007] The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor device in which the concentration of load on the dielectric layer is suppressed. Another object of the present invention is to provide a module including the above semiconductor device.

Means for Solving the Problems

[0008] The semiconductor device of the present invention includes a substrate having a first main surface and a second main surface facing each other in the thickness direction, a circuit layer provided on the first main surface of the substrate, and a first resin body. The circuit layer includes a first electrode layer provided on the substrate side, a second electrode layer provided to face the first electrode layer, a dielectric layer provided between the first electrode layer and the second electrode layer in the thickness direction, a first external electrode drawn out to the surface of the circuit layer opposite to the substrate, and a second external electrode drawn out to the surface of the circuit layer opposite to the substrate and provided spaced apart from the first external electrode. The first resin body is provided at the four corners of the substrate in a plan view from the thickness direction, and in the thickness direction, the tip of the first resin body on the side opposite to the substrate is at a position higher than the tips of the first external electrode and the second external electrode on the side opposite to the substrate.

[0009] The module of the present invention includes the semiconductor device of the present invention, a wiring board having a first land electrically connected to the first external electrode and a second land electrically connected to the second external electrode.

Advantages of the Invention

[0010] According to the present invention, it is possible to provide a semiconductor device in which the concentration of load on the dielectric layer is suppressed. Further, according to the present invention, it is possible to provide a module including the semiconductor device.

Brief Description of the Drawings

[0011]

Figure 1-1

Figure 1-2

Figure 1-3

Figure 2-1

Figure 2-2

Figure 2-3

Figure 3-1

Figure 3-2

Figure 3-3

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Figure 4-2

Figure 4-3

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Figure 5-2

Figure 5-3

Figure 5-4

Figure 5-5

Figure 5-6

Figure 5-7

Figure 5-8

Figure 5-9

Figure 5-10

Figure 5-11

Figure 6

Figure 7

Figure 8-1

Figure 8-2

Figure 8-3

Figure 9-1

Figure 9-2

Figure 9-3

Figure 10-1

Figure 10-2

Figure 10-3

Figure 11-1

Figure 11-2

Figure 11-3

Figure 12-1

Figure 12-2

Figure 12-3

Figure 13-1

Figure 13-2

Figure 13-3

Figure 14-1

Figure 14-2

Figure 14-3

Embodiments for Carrying Out the Invention

[0012] Hereinafter, the semiconductor device and the module of the present invention will be described. However, the present invention is not limited to the following configurations, and can be appropriately modified and applied without changing the gist of the present invention. In addition, a combination of two or more of the individual preferred configurations of the present invention described below is also the present invention.

[0013] Each of the embodiments shown below is an exemplification, and it goes without saying that partial substitution or combination of the configurations shown in different embodiments is possible. In and after Embodiment 2, descriptions of matters common to Embodiment 1 will be omitted, and only different points will be described. In particular, for the same operational effects due to the same configurations, they will not be sequentially mentioned for each embodiment.

[0014] In the following description, when not particularly distinguishing each embodiment, they are simply referred to as "the semiconductor device of the present invention" and "the module of the present invention". The shapes, arrangements, etc. of the semiconductor device, module, and each component of the present invention are not limited to the examples shown in the drawings.

[0015] Further, in the following, as an embodiment of the semiconductor device of the present invention, a capacitor will be described as an example. The semiconductor device of the present invention may be a capacitor itself (i.e., a capacitor element), or may be a device including a capacitor.

[0016] [Embodiment 1] The semiconductor device of the present invention includes a substrate, a circuit layer, and a first resin body. In the semiconductor device of the present invention, the first resin body is provided at the four corners of the substrate in a plan view from the thickness direction, and in the thickness direction, the tip of the first resin body on the side opposite to the substrate is at a position higher than the tips of the first external electrode and the second external electrode on the side opposite to the substrate. The semiconductor device of the present invention may further include a second resin body. In that case, the second resin body is provided between the first external electrode and the second external electrode in a plan view from the thickness direction, and in the thickness direction, the tip of the second resin body on the side opposite to the substrate is at a position higher than the tips of the first external electrode and the second external electrode on the side opposite to the substrate, and is also at a position higher than the tip of the first resin body on the side opposite to the substrate. Such an example will be described below as the capacitor of Embodiment 1 of the present invention.

[0017] FIG. 1-1 is a schematic plan view showing an example of the capacitor of Embodiment 1 of the present invention. FIG. 1-2 is a schematic side view of the capacitor shown in FIG. 1-1. FIG. 1-3 is a schematic cross-sectional view showing a portion corresponding to the line segment A1-A2 in FIG. 1-1.

[0018] In this specification, the length direction, width direction, and thickness direction of the capacitor (semiconductor device) are defined as the directions indicated by the arrows L, W, and T, respectively, as shown in FIGS. 1-1, 1-2, 1-3, etc. Here, the length direction L, width direction W, and thickness direction T are orthogonal to each other.

[0019] As shown in FIGS. 1-1, 1-2, and 1-3, the capacitor 1 includes a substrate 10, a circuit layer 20, a first resin body 30, and a second resin body 40.

[0020] The substrate 10 has a first main surface 10a and a second main surface 10b that face each other in the thickness direction T. The first main surface 10a and the second main surface 10b face each other in the thickness direction T.

[0021] Examples of the constituent material of the substrate 10 include semiconductors such as silicon (Si), silicon germanium (SiGe), and gallium arsenide (GaAs).

[0022] The electrical resistivity of the substrate 10 is preferably 10 -1 Ω·cm or more and 10 6 Ω·cm or less.

[0023] The dimension of the substrate 10 in the length direction L is preferably 200 μm or more and 600 μm or less.

[0024] The dimension of the substrate 10 in the width direction W is preferably 100 μm or more and 300 μm or less.

[0025] The dimension (thickness) of the substrate 10 in the thickness direction T is preferably 50 μm or more and 250 μm or less.

[0026] The circuit layer 20 is provided on the first main surface 10a of the substrate 10. The circuit layer 20 includes an insulating layer 21, a first electrode layer 22, a dielectric layer 23, a second electrode layer 24, a moisture-resistant protective layer 25, a resin protective layer 26, a first external electrode 27, and a second external electrode 28. In Embodiment 1, the circuit layer 20 is provided on the entire first main surface 10a of the substrate 10, but it may be provided on a part of the first main surface 10a of the substrate 10. In that case, the circuit layer 20 is preferably provided at the central position on the first main surface 10a of the substrate 10, and it is preferably provided at a position where the central axis of the substrate 10 and the central axis of the circuit layer 20 substantially coincide.

[0027] The dimension in the thickness direction T of the circuit layer 20 is preferably 5 μm or more and 70 μm or less. The dimension in the thickness direction T of the circuit layer 20 is defined as the dimension from the surface of the insulating layer 21 on the substrate 10 side to the surface of the first external electrode 27 and the second external electrode 28 that is located on the side farthest from the substrate 10 among the outermost surfaces.

[0028] The insulating layer 21 is provided on the entire first main surface 10a of the substrate 10. Although the insulating layer 21 may be provided on a part of the first main surface 10a of the substrate 10, it needs to be provided in a region that is larger than the first electrode layer 22 and overlaps the entire area of the first electrode layer 22. For example, after once forming the insulating layer on the entire first main surface 10a of the substrate 10 by oxidizing the first main surface 10a of the substrate 10 by a thermal oxidation method or forming a film by a sputtering method or a chemical vapor deposition (CVD) method, and then removing a part of the insulating layer by an etching method, the insulating layer 21 can be provided on a part of the first main surface 10a of the substrate 10.

[0029] Examples of the constituent material of the insulating layer 21 include silicon oxide (SiO, SiO 2 ), silicon nitride (SiN), aluminum oxide (Al 2 O 3 ), hafnium oxide (HfO 2 ), tantalum oxide (Ta 2 O 5 ), zirconium oxide (ZrO 2 ), etc.

[0030] The insulating layer 21 may have a single-layer structure or a multilayer structure including a plurality of layers made of the materials described above.

[0031] The dimension (thickness) in the thickness direction T of the insulating layer 21 is preferably 0.5 μm or more and 3 μm or less.

[0032] The first electrode layer 22 is provided on the substrate 10 side of the circuit layer 20, here, on the surface of the insulating layer 21 opposite to the substrate 10. Also, the first electrode layer 22 is provided up to a position separated from the end of the substrate 10. More specifically, the end of the first electrode layer 22 is located inside the end of the substrate 10. In the plan view shown in FIG. 1-1, the distance between the end of the first electrode layer 22 and the end of the substrate 10 is preferably 5 μm or more and 30 μm or less. Note that the end of the first electrode layer 22 may be provided on the surface of the insulating layer 21 up to the end of the substrate 10.

[0033] Examples of the constituent material of the first electrode layer 22 include metals such as aluminum (Al), silicon (Si), copper (Cu), silver (Ag), gold (Au), nickel (Ni), chromium (Cr), and titanium (Ti). The constituent material of the first electrode layer 22 may be an alloy containing at least one of the above-mentioned metals, and specific examples thereof include aluminum-silicon alloy (AlSi), aluminum-copper alloy (AlCu), and aluminum-silicon-copper alloy (AlSiCu).

[0034] The first electrode layer 22 may have a single-layer structure or a multilayer structure including a plurality of conductor layers made of the above-mentioned materials.

[0035] The dimension (thickness) of the first electrode layer 22 in the thickness direction T is preferably 0.3 μm or more and 10 μm or less, and more preferably 0.5 μm or more and 5 μm or less.

[0036] The dielectric layer 23 is provided between the first electrode layer 22 and the second electrode layer 24 in the thickness direction T, here, in the direction orthogonal to the first main surface 10a of the substrate 10. Also, the dielectric layer 23 is provided so as to cover the first electrode layer 22 except for the opening, and the end of the dielectric layer 23 is also provided on the surface of the insulating layer 21 from the end of the first electrode layer 22 to the end of the substrate 10.

[0037] Examples of the constituent material of the dielectric layer 23 include silicon nitride (SiN), silicon oxide (SiO, SiO 2 )), aluminum oxide (Al2 O 3 ) hafnium oxide (HfO 2 ) tantalum oxide (Ta 2 O 5 ) zirconium oxide (ZrO 2 ) and the like. Among them, the dielectric layer 23 preferably contains at least one of silicon nitride and silicon oxide.

[0038] The dimension (thickness) in the thickness direction T of the dielectric layer 23 is preferably 0.02 μm or more and 4 μm or less.

[0039] The second electrode layer 24 is provided to face the first electrode layer 22. More specifically, the second electrode layer 24 is provided on the surface of the dielectric layer 23 opposite to the substrate 10, and faces the first electrode layer 22 with the dielectric layer 23 interposed therebetween.

[0040] Examples of the constituent material of the second electrode layer 24 include metals such as aluminum (Al), silicon (Si), copper (Cu), silver (Ag), gold (Au), nickel (Ni), chromium (Cr), and titanium (Ti). The constituent material of the second electrode layer 24 may be an alloy containing at least one of the above-described metals, and specific examples thereof include aluminum-silicon alloy (AlSi), aluminum-copper alloy (AlCu), aluminum-silicon-copper alloy (AlSiCu), and the like.

[0041] The second electrode layer 24 may have a single-layer structure or a multilayer structure including a plurality of conductor layers made of the above-described materials.

[0042] The dimension (thickness) in the thickness direction T of the second electrode layer 24 is preferably 0.3 μm or more and 10 μm or less, and more preferably 0.5 μm or more and 5 μm or less.

[0043] A capacitor element is constituted by the first electrode layer 22, the dielectric layer 23, and the second electrode layer 24. More specifically, the capacitance of the capacitor element is formed in a region where the first electrode layer 22, the dielectric layer 23, and the second electrode layer 24 overlap.

[0044] The moisture-resistant protective layer 25 is provided so as to cover the dielectric layer 23 and the second electrode layer 24 except for the openings. By providing the moisture-resistant protective layer 25, the moisture resistance of the capacitor element, particularly the dielectric layer 23, is enhanced.

[0045] Examples of the constituent material of the moisture-resistant protective layer 25 include silicon nitride (SiN), silicon oxide (SiO 2 ) and the like. Each film may be provided as a single layer, but silicon nitride is preferred because it has higher moisture resistance. Further, by laminating silicon nitride and silicon oxide in this order from the lower side (the side closer to the substrate 10), while enhancing the moisture resistance inside the element with silicon nitride, the shock transmitted from the first resin body 30 through the substrate 10 during mounting can be dispersed by the silicon oxide having a small Young's modulus and a small film stress so that it does not concentrate at the end of the second electrode layer 24.

[0046] The dimension (thickness) in the thickness direction T of the moisture-resistant protective layer 25 is preferably 0.5 μm or more and 3 μm or less.

[0047] The resin protective layer 26 is provided so as to cover the first electrode layer 22 and the second electrode layer 24. Here, the resin protective layer 26 is provided on the surface of the moisture-resistant protective layer 25 opposite to the substrate 10. Further, the end of the resin protective layer 26 extends to the end of the substrate 10, and the resin protective layer 26 is provided with openings at positions overlapping the openings of the dielectric layer 23 and the moisture-resistant protective layer 25 (the openings overlapping the first electrode layer 22) and at positions overlapping the openings of the moisture-resistant protective layer 25 (the openings overlapping the second electrode layer 24), respectively. By providing the resin protective layer 26, the capacitor element, particularly the dielectric layer 23, is sufficiently protected from moisture.

[0048] Examples of the constituent material of the resin protective layer 26 include resins such as polyimide resin, polybenzoxazole resin, benzocyclobutene resin, and the resin in solder resist.

[0049] The dimension (thickness) in the thickness direction T of the resin protective layer 26 is preferably 1 μm or more and 20 μm or less.

[0050] The first external electrode 27 is drawn out on the surface of the circuit layer 20 opposite to the substrate 10 and is separated from the second external electrode 28. That is, the first external electrode 27 is located on the side of the substrate 10 opposite to the first electrode layer 22. Here, the first external electrode 27 is electrically connected to the first electrode layer 22. More specifically, the openings provided in the dielectric layer 23, the moisture-resistant protective layer 25, and the resin protective layer 26 communicate with each other along the thickness direction T and extend, and the first external electrode 27 is electrically connected to the first electrode layer 22 through the openings. Also, the first external electrode 27 is separated from the second electrode layer 24 on the plane along the length direction L and the width direction W (see FIG. 1-1), and thus is not electrically connected to the second electrode layer 24.

[0051] The first external electrode 27 may have a single-layer structure or a multilayer structure.

[0052] When the first external electrode 27 has a single-layer structure, examples of its constituent materials include gold (Au), silver (Ag), copper (Cu), palladium (Pd), nickel (Ni), titanium (Ti), aluminum (Al), alloys containing at least one of these metals, and the like.

[0053] When the first external electrode 27 has a multilayer structure, as shown in FIGS. 1-2 and 1-3, the first external electrode 27 may have, in order from the substrate 10 side, a seed layer 29a, a first plating layer 29b, and a second plating layer 29c.

[0054] Examples of the seed layer 29a of the first external electrode 27 include a laminate (Ti / Cu) of a conductor layer made of titanium (Ti) and a conductor layer made of copper (Cu).

[0055] Examples of the constituent material of the first plating layer 29b of the first external electrode 27 include nickel (Ni) and the like.

[0056] Examples of the constituent material of the second plating layer 29c of the first external electrode 27 include gold (Au), tin (Sn), and the like.

[0057] The second external electrode 28 is drawn out on the surface of the circuit layer 20 opposite to the substrate 10 and is separated from the first external electrode 27. That is, the second external electrode 28 is located on the side of the second electrode layer 24 opposite to the substrate 10. Here, the second external electrode 28 is electrically connected to the second electrode layer 24. More specifically, the openings provided in the moisture-resistant protective layer 25 and the resin protective layer 26 communicate with each other along the thickness direction T and extend, and the second external electrode 28 is electrically connected to the second electrode layer 24 through the openings. Further, the second external electrode 28 is separated from the first electrode layer 22 on the surfaces along the length direction L and the thickness direction T (see FIGS. 1-3), and thus is not electrically connected to the first electrode layer 22.

[0058] The second external electrode 28 may have a single-layer structure or a multilayer structure.

[0059] When the second external electrode 28 has a single-layer structure, examples of its constituent material include gold (Au), silver (Ag), copper (Cu), palladium (Pd), nickel (Ni), titanium (Ti), aluminum (Al), alloys containing at least one of these metals, and the like.

[0060] When the second external electrode 28 has a multilayer structure, as shown in FIGS. 1-2 and 1-3, the second external electrode 28 may have, in order from the substrate 10 side, a seed layer 29a, a first plating layer 29b, and a second plating layer 29c.

[0061] Examples of the seed layer 29a of the second external electrode 28 include a laminate (Ti / Cu) of a conductor layer made of titanium (Ti) and a conductor layer made of copper (Cu).

[0062] Examples of the constituent material of the first plating layer 29b of the second external electrode 28 include nickel (Ni) and the like.

[0063] Examples of the constituent material of the second plating layer 29c of the second external electrode 28 include gold (Au), tin (Sn), and the like.

[0064] The constituent material of the first external electrode 27 and the constituent material of the second external electrode 28 may be the same as each other or may be different from each other.

[0065] As shown in FIG. 1-1, the first resin body 30 is provided at the four corners of the substrate 10 in a plan view from the thickness direction T. More specifically, in a plan view from the thickness direction T, the distance between all locations on the uppermost surface of the first resin body 30 and the corner portion of the capacitor element (the corner portion of the substrate 10) is shorter than the shortest distance between the end portion of the second electrode layer 24 and the outer periphery of the capacitor element (the outer periphery of the substrate 10). That is, the first resin body 30 is provided within a range that does not exceed the dotted line extending from the end portion of the second electrode layer 24 in the plan view shown in FIG. 1-1. Here, the first resin body 30 is provided on the surface of the circuit layer 20 opposite to the substrate 10.

[0066] As shown in FIG. 1-2, in the thickness direction T, the tip of the first resin body 30 on the side opposite to the substrate 10 is at a position higher than the tips of the first external electrode 27 and the second external electrode 28 on the side opposite to the substrate 10. More specifically, in the thickness direction T, the tip of the first resin body 30 on the side opposite to the substrate 10 is on the side opposite to the substrate 10 with respect to the line segment connecting the tips of the first external electrode 27 and the second external electrode 28 on the side opposite to the substrate 10 (the dotted line in FIG. 1-2).

[0067] As shown in FIG. 1-1, the second resin body 40 is provided between the first external electrode 27 and the second external electrode 28 in a plan view from the thickness direction T. More specifically, in the length direction L, the second resin body 40 is provided between the normal line extending along the width direction W from the end portion of the first external electrode 27 on the second external electrode 28 side and the normal line extending along the width direction W from the end portion of the second external electrode 28 on the first external electrode 27 side. Here, the second resin body 40 is provided on the surface of the circuit layer 20 opposite to the substrate 10.

[0068] As shown in FIGS. 1-3, in the thickness direction T, the tip of the second resin body 40 on the side opposite to the substrate 10 is at a position higher than the tips of the first external electrode 27 and the second external electrode 28 on the side opposite to the substrate 10. More specifically, in the thickness direction T, the tip of the second resin body 40 on the side opposite to the substrate 10 is on the side opposite to the substrate 10 with respect to the line segment (dotted line in FIGS. 1-3) connecting the tips of the first external electrode 27 and the second external electrode 28 on the side opposite to the substrate 10.

[0069] In FIGS. 1-3, the outermost surface of the first external electrode 27 is uneven. In this case, in the thickness direction T, the portion of the outermost surface of the first external electrode 27 that is located farthest from the substrate 10 is defined as the tip of the first external electrode 27 on the side opposite to the substrate 10. The same applies to the second external electrode 28.

[0070] As shown in FIGS. 1-2, in the thickness direction T, the tip of the second resin body 40 on the side opposite to the substrate 10 is at a position higher than the tip of the first resin body 30 on the side opposite to the substrate 10.

[0071] Here, as described above, since the first electrode layer 22 is provided up to a position separated from the end of the substrate 10, the end (peripheral portion) of the circuit layer 20 is likely to descend more toward the substrate 10 side than the central portion. Although a resin protection layer 26 is provided on the end of the substrate 10 in the cross-sectional view shown in FIGS. 1-3, since the first electrode layer 22 and the second electrode layer 24 do not exist in the lower layer thereof, actually, the thickness of the resin protection layer 26 is not likely to increase. From this fact as well, the end (peripheral portion) of the circuit layer 20 is likely to descend more toward the substrate 10 side than the central portion. Therefore, in the first external electrode 27 and the second external electrode 28, the central portion side of the circuit layer 20 is likely to be at a higher position than the end portion side. On the other hand, the second resin body 40 is provided in the plan view shown in FIG. 1-1 between the first external electrode 27 and the second external electrode 28, that is, in the vicinity of the central portion rather than at the end of the circuit layer 20. Also, as described above, in the cross-sectional view shown in FIG. 1-3, the tip of the second resin body 40 on the side opposite to the substrate 10 is at a higher position than the tips of the first external electrode 27 and the second external electrode 28 on the side opposite to the substrate 10. Therefore, even in a state where the end of the circuit layer 20 descends more toward the substrate 10 side than the central portion, the second resin body 40 protrudes more than the circuit layer 20.

[0072] When the first resin body 30 protrudes more than the circuit layer 20 and the second resin body 40 protrudes more than the first resin body 30, for example, when mounting the capacitor 1 on the wiring board, the second resin body 40 contacts the wiring board side (e.g., the upper surface of the wiring board, land, solder, etc.) prior to the first resin body 30, the first external electrode 27, and the second external electrode 28. Therefore, a load is applied to the second resin body 40, and the load applied to the first resin body 30, the first external electrode 27, and the second external electrode 28 is suppressed. As a result, since the load is suppressed from being transmitted to the capacitor element via the first external electrode 27 and the second external electrode 28, breakage of the capacitor element, particularly breakage of the dielectric layer 23, is suppressed. However, when the mounting speed is increased, the variation in load becomes large, and if the second resin body 40 receives all the load alone, the stress on the dielectric layer 23 directly below the second resin body 40 may increase and cause breakage. Therefore, by making the first resin body 30 higher than the height at which the second resin body 40 is deformed by the load and lowered, the load is dispersed to the first resin body 30 before the stress that causes breakage of the dielectric layer 23 directly below the second resin body 40 is reached. Since the load applied to the first resin body 30 concentrates on the corner portions of the substrate 10 directly below the first resin body 30, breakage of the dielectric layer 23 is suppressed. Such an effect is similarly obtained when the capacitor 1 is placed on the flat plate from the circuit layer 20 side.

[0073] When the first resin body 30 is provided at positions other than the four corners of the substrate 10 in a plan view, the load during mounting is transmitted to the second electrode layer 24 via the substrate 10, and stress concentrates at the ends of the second electrode layer 24, so that the dielectric layer 23 directly below it is damaged. On the other hand, by providing the first resin body 30 limited to the four corners of the substrate 10 in a plan view, stress concentrates on the substrate 10 directly below, so that breakage of the dielectric layer 23 is suppressed. In the case of the structure in which the second electrode layer 24 is arranged closer to the left side as shown in FIGS. 1-3, by making the height of the first resin body 30 provided at the two corner portions of the substrate 10 closer to the second electrode layer 24 lower than that of the first resin body 30 provided at the two corner portions of the substrate 10 farther from the second electrode layer 24, the first resin body 30 farther from the second electrode layer 24 receives the load first, but since there is no end portion of the second electrode layer 24 where stress easily concentrates, breakage due to the load is suppressed.

[0074] As shown in FIG. 1-1, in a plan view from the thickness direction T, it is preferable that the first resin body 30 is provided at a position that does not overlap with the first electrode layer 22. Thereby, it is possible to further suppress the load from being transmitted from the first resin body 30 to the second resin body 40.

[0075] The second resin body 40 is preferably provided at a position surrounding the center of the substrate 10. As shown in FIGS. 1-1, 1-2, and 1-3, the second resin body 40 is preferably extended in a direction orthogonal to the thickness direction T and in a direction from the second external electrode 28 toward the first external electrode 27, here, in a direction intersecting the length direction L. More specifically, the second resin body 40 is preferably extended in a direction orthogonal to both the length direction L and the thickness direction T, that is, in the width direction W.

[0076] In FIGS. 1-1, 1-2, and 1-3, the second resin body 40 includes a first wall portion 40a provided on the first external electrode 27 side and a second wall portion 40b provided on the second external electrode 28 side and separated from the first wall portion 40a.

[0077] As shown in FIG. 1-1, the first wall portion 40a and the second wall portion 40b are preferably provided in parallel. In this case, for example, when mounting the capacitor 1 on the wiring board, the substrate 10 and the circuit layer 20 can be sufficiently stably held on the wiring board by the second resin body 40. In particular, in the length direction L of the substrate 10, since the first wall portion 40a is provided on one side with respect to the center thereof and the second wall portion 40b is provided on the other side, the substrate 10 and the circuit layer 20 can be more stably held on the wiring board by the second resin body 40.

[0078] In the plan view shown in FIG. 1-1, the second resin body 40 extends in a region 80 connecting the opposing ends of the first external electrode 27 and the second external electrode 28. Also, the tip of the second resin body 40 is at a position higher than the tips of the first resin body 30 and the circuit layer 20. Thus, when the capacitor 1 is mounted on the wiring board to form a module, even if so-called solder splash, i.e., the spread of solder, occurs, the path along which the solder wets and spreads becomes longer by the length of the second resin body 40. Therefore, a short circuit between the first external electrode 27 and the second external electrode 28 due to solder splash can be suppressed.

[0079] In the thickness direction T, the protruding dimension of the second resin body 40 with respect to the circuit layer 20 is preferably 50 μm or less. In the thickness direction T, the protruding dimension of the first resin body 30 with respect to the circuit layer 20 may be smaller than the protruding dimension of the second resin body 40, and preferably, the difference from the protruding dimension of the second resin body 40 is 10 μm or less.

[0080] The indentation elastic modulus of the first resin body 30 and the second resin body 40 is preferably lower than the indentation elastic modulus of the dielectric layer 23. In this case, since the flexibility of the first resin body 30 and the second resin body 40 becomes higher than the flexibility of the dielectric layer 23, it becomes easier for the first resin body 30 and the second resin body 40 to receive a load, and the load applied to the capacitor element, particularly the dielectric layer 23, is suppressed. The indentation elastic modulus of the first resin body 30 and the second resin body 40 is preferably 20 GPa or less. The indentation elastic modulus of the first resin body 30 and the indentation elastic modulus of the second resin body 40 may be the same as each other or different from each other.

[0081] The indentation elastic modulus is measured, for example, by the nanoindentation method.

[0082] The Young's modulus of the first resin body 30 and the second resin body 40 is preferably 20 GPa or less. In this case, since the flexibility of the first resin body 30 and the second resin body 40 becomes sufficiently high, it becomes easy for the first resin body 30 and the second resin body 40 to receive a load, and the load applied to the capacitor element is sufficiently suppressed. Further, the Young's modulus of the first resin body 30 and the second resin body 40 is more preferably 0.5 GPa or more and 20 GPa or less. The Young's modulus of the first resin body 30 and the Young's modulus of the second resin body 40 may be the same as each other or may be different from each other.

[0083] The Young's modulus is measured, for example, by a tensile test method.

[0084] The first resin body 30 and the second resin body 40 preferably contain at least one resin selected from the group consisting of resins in a solder resist, polyimide resins, polyimide amide resins, and epoxy resins. The resin contained in the first resin body 30 and the resin contained in the second resin body 40 may be the same as each other or may be different from each other.

[0085] The first resin body 30 and the second resin body 40 are preferably cured products of a photosensitive resin.

[0086] FIG. 2-1 is a schematic plan view showing a modification 1 of the capacitor according to Embodiment 1 of the present invention. FIG. 2-2 is a schematic side view of the capacitor shown in FIG. 2-1. FIG. 2-3 is a schematic cross-sectional view showing a portion corresponding to the line segment A1-A2 in FIG. 2-1.

[0087] Like the capacitor 1A shown in FIGS. 2-1, 2-2, and 2-3, the first resin body 30 may have a shape in which the tip is thinner than the bottom. In this case, the first resin body 30 is likely to be deformed by the load during mounting. As a result, it becomes difficult for the load to be instantaneously and locally applied at the start of contact with the wiring board side within the first resin body 30. Note that the tip of the first resin body 30 may be an acute angle, and the tip of the first resin body 30 may be pointed.

[0088] Similarly, the second resin body 40 may have a shape in which the tip is thinner than the bottom. In this case, the second resin body 40 is likely to be deformed by the load during mounting. As a result, it becomes difficult for the load to be instantaneously and locally applied at the start of contact with the wiring board side within the second resin body 40. Note that the tip of the second resin body 40 may be an acute angle, and the tip of the second resin body 40 may be pointed.

[0089] FIG. 3-1 is a schematic plan view showing a modification 2 of the capacitor according to Embodiment 1 of the present invention. FIG. 3-2 is a schematic side view of the capacitor shown in FIG. 3-1. FIG. 3-3 is a schematic cross-sectional view showing a portion corresponding to the line segment A1-A2 in FIG. 3-1.

[0090] Like the capacitor 1B shown in FIGS. 3-1, 3-2, and 3-3, the first resin body 30 may have a shape in which the tip is thinner than the bottom and the side surface on the end side of the substrate 10 stands upright with respect to the first main surface 10a of the substrate 10. In this case, the stress applied to the end of the second electrode layer 24 becomes even smaller. Note that the tip of the first resin body 30 may be an acute angle, and the tip of the first resin body 30 may be pointed.

[0091] FIG. 4-1 is a schematic plan view showing a modification 3 of the capacitor according to Embodiment 1 of the present invention. FIG. 4-2 is a schematic side view of the capacitor shown in FIG. 4-1. FIG. 4-3 is a schematic cross-sectional view showing a portion corresponding to the line segment A1-A2 in FIG. 4-1.

[0092] Like the capacitor 1C shown in FIGS. 4-1, 4-2, and 4-3, the corner of the second electrode layer 24 on the side close to the corner of the capacitor element may be cut off. Thereby, the stress applied to the corner of the second electrode layer 24 can be further reduced. Examples of the shape of cutting off the corner of the second electrode layer 24 include an arc shape, a polygon, and the like. It is preferable that the corner of the second electrode layer 24 is larger than 90° so that the distance from the corner of the capacitor element becomes longer.

[0093] The capacitor 1 shown in FIGS. 1-1, 1-2, and 1-3, which is an example of the capacitor according to Embodiment 1 of the present invention, is manufactured, for example, by the following method. FIGS. 5-1, 5-2, 5-3, 5-4, 5-5, 5-6, 5-7, 5-8, 5-9, 5-10, and 5-11 are cross-sectional schematic diagrams for explaining an example of the manufacturing method of the capacitor according to Embodiment 1 of the present invention.

[0094] <Formation of Insulating Layer> FIG. 5-1 is a cross-sectional schematic diagram for explaining an example of the process of forming an insulating layer.

[0095] As shown in FIG. 5-1, an insulating layer 21 is formed on the first main surface 10a of the substrate 10 by, for example, a thermal oxidation method, a sputtering method, or a chemical vapor deposition method.

[0096] <Formation of First Electrode Layer> FIG. 5-2 is a cross-sectional schematic diagram for explaining an example of the process of forming a first electrode layer.

[0097] A conductor layer made of the constituent material of the first electrode layer 22 is formed on the surface of the insulating layer 21 opposite to the substrate 10 by, for example, a sputtering method. Thereafter, patterning of the conductor layer is performed by combining a photolithography method and an etching method to form the first electrode layer 22 as shown in FIG. 5-2. More specifically, the first electrode layer 22 is formed up to a position separated from the end of the substrate 10.

[0098] <Formation of Dielectric Layer> FIG. 5-3 is a cross-sectional schematic diagram for explaining an example of the process of forming a dielectric layer.

[0099] A layer made of the constituent material of the dielectric layer 23 is formed so as to cover the first electrode layer 22 by, for example, a sputtering method or a chemical vapor deposition method. Thereafter, patterning of this layer is performed by combining, for example, a photolithography method and an etching method to form the dielectric layer 23 as shown in FIG. 5-3. More specifically, the dielectric layer 23 is formed such that an opening for exposing a part of the first electrode layer 22 is provided.

[0100] <Formation of the second electrode layer> FIG. 5-4 is a schematic cross-sectional view for explaining an example of the process of forming the second electrode layer.

[0101] A conductor layer made of the constituent material of the second electrode layer 24 is formed, for example, by sputtering, on the surface of the structure shown in FIG. 5-3 opposite to the substrate 10. Thereafter, patterning of the conductor layer is performed, for example, by combining photolithography and etching to form the second electrode layer 24 as shown in FIG. 5-4. More specifically, the second electrode layer 24 is formed so as to face the first electrode layer 22 with the dielectric layer 23 interposed therebetween.

[0102] <Formation of the moisture-resistant protective layer> FIG. 5-5 is a schematic cross-sectional view for explaining an example of the process of forming the moisture-resistant protective layer.

[0103] A layer made of the constituent material of the moisture-resistant protective layer 25 is formed, for example, by chemical vapor deposition, on the surface of the structure shown in FIG. 5-4 opposite to the substrate 10. Thereafter, patterning of this layer is performed, for example, by combining photolithography and etching to form the moisture-resistant protective layer 25 as shown in FIG. 5-5. More specifically, the moisture-resistant protective layer 25 is formed such that openings are provided at positions overlapping the opening of the dielectric layer 23 for exposing a part of the first electrode layer 22 and at positions for exposing a part of the second electrode layer 24.

[0104] <Formation of the resin protective layer> FIG. 5-6 is a schematic cross-sectional view for explaining an example of the process of forming the resin protective layer.

[0105] A layer made of the constituent material of the resin protection layer 26 is formed, for example, by the spin coating method, on the surface of the structure shown in FIG. 5-5 opposite to the substrate 10. Then, patterning of this layer is performed, for example, using only the photolithography method when the constituent material of the resin protection layer 26 is photosensitive, and by combining the photolithography method and the etching method when the constituent material of the resin protection layer 26 is non-photosensitive, to form a resin protection layer 26 as shown in FIG. 5-6. More specifically, openings are provided at positions overlapping the openings of the dielectric layer 23 and the moisture-resistant protection layer 25 for exposing a part of the first electrode layer 22, and at positions overlapping the openings of the moisture-resistant protection layer 25 for exposing a part of the second electrode layer 24, so as to form the resin protection layer 26.

[0106] <Formation of External Electrodes> FIG. 5-7 is a cross-sectional schematic view for explaining an example of the process of forming a seed layer. FIG. 5-8 is a cross-sectional schematic view for explaining an example of the process of forming a first plating layer and a second plating layer. FIG. 5-9 is a cross-sectional schematic view for explaining an example of the process of removing a part of the seed layer.

[0107] As shown in FIG. 5-7, a seed layer 29a is formed on the surface of the structure shown in FIG. 5-6 opposite to the substrate 10. Then, by combining the plating process and the photolithography method, a first plating layer 29b and a second plating layer 29c as shown in FIG. 5-8 are sequentially formed. After that, as shown in FIG. 5-9, a part of the seed layer 29a is removed, for example, by the etching method. Thus, a first external electrode 27 and a second external electrode 28 as shown in FIG. 5-9 are formed. More specifically, the first external electrode 27 is formed so as to be electrically connected to the first electrode layer 22 through the openings provided in the dielectric layer 23, the moisture-resistant protection layer 25, and the resin protection layer 26, respectively. Also, the second external electrode 28 is formed so as to be electrically connected to the second electrode layer 24 through the openings provided in the moisture-resistant protection layer 25 and the resin protection layer 26, respectively.

[0108] As described above, the circuit layer 20 as shown in FIGS. 5-9 is formed on the first main surface 10a of the substrate 10. The first external electrode 27 is drawn out to the surface of the circuit layer 20 opposite to the substrate 10 and is separated from the second external electrode 28. Also, the second external electrode 28 is drawn out to the surface of the circuit layer 20 opposite to the substrate 10 and is separated from the first external electrode 27.

[0109] <Formation of the first resin body and the second resin body> FIG. 5-10 is a cross-sectional schematic view for explaining an example of the process of forming a photosensitive resin film. FIG. 5-11 is a cross-sectional schematic view for explaining an example of the process of forming the first resin body and the second resin body.

[0110] As shown in FIG. 5-10, the photosensitive resin film 35 is formed on the surface of the circuit layer 20 opposite to the substrate 10. Then, by performing patterning of the photosensitive resin film 35 by photolithography, the first resin body 30 (see FIGS. 1-2) is formed on the surface of the circuit layer 20 opposite to the substrate 10.

[0111] Similarly, the photosensitive resin film 35 is formed on the surface of the circuit layer 20 opposite to the substrate 10. Then, by performing patterning of the photosensitive resin film 35 by photolithography, the second resin body 40 as shown in FIG. 5-11 is formed on the surface of the circuit layer 20 opposite to the substrate 10.

[0112] The second resin body 40 may be formed simultaneously with the first resin body 30 using the same material. By forming the first resin body 30 and the second resin body 40 simultaneously, it becomes easy to precisely control the difference in height between the first resin body 30 and the second resin body 40 in the plane. Also, the process can be shortened and the manufacturing cost can be reduced.

[0113] Thus, the capacitor 1 is manufactured.

[0114] In the above description, the case of manufacturing one capacitor 1 has been explained. However, after forming a plurality of circuit layers 20 on the first main surface 10a of the same substrate 10, the substrate 10 may be cut by dicing or the like to be separated into individual pieces, so that a plurality of capacitors 1 may be manufactured simultaneously.

[0115] The module of the present invention includes the semiconductor device of the present invention, a wiring board having a first land electrically connected to the first external electrode and a second land electrically connected to the second external electrode. Hereinafter, the module including the capacitor according to Embodiment 1 of the present invention will be described as the module according to Embodiment 1 of the present invention.

[0116] FIG. 6 is a schematic cross-sectional view showing the module according to Embodiment 1 of the present invention.

[0117] As shown in FIG. 6, the module 100 includes a capacitor 1 and a wiring board 50. More specifically, the module 100 is one in which the capacitor 1 is mounted on the wiring board 50.

[0118] The wiring board 50 includes a substrate 51, a first land 52, and a second land 53.

[0119] Various wirings are provided on the substrate 51. The various wirings on the substrate 51 are independently connected to the first land 52 and the second land 53.

[0120] The first land 52 is provided on the surface of the substrate 51 and is electrically connected to the first external electrode 27. More specifically, the first land 52 is electrically connected to the first external electrode 27 via solder 60.

[0121] Examples of the constituent material of the first land 52 include metals such as copper (Cu).

[0122] The second land 53 is provided at a position separated from the first land 52 on the surface of the substrate 51, and is electrically connected to the second external electrode 28. More specifically, the second land 53 is electrically connected to the second external electrode 28 via the solder 60.

[0123] Examples of the constituent material of the second land 53 include metals such as copper (Cu).

[0124] In the module 100, the second resin body 40 does not contact the wiring substrate 50 side (for example, the first land 52, the second land 53, the solder 60, etc.). This is considered to be due to, for example, the following mechanism.

[0125] As a first mechanism, the case where the capacitor 1 is mounted in a state where it is not displaced on the wiring substrate 50 will be described. When the capacitor 1 is mounted on the wiring substrate 50 via the solder 60, first, the second resin body 40 contacts the solder 60. Thereafter, when the reflow process is performed, although the solder 60 spreads wetly overall at each of the first land 52 and the second land 53, the solder 60 avoids the second resin body 40, and as a result, the second resin body 40 does not contact the solder 60.

[0126] As a second mechanism, the case where the capacitor 1 is mounted in a state where it is displaced on the wiring substrate 50 will be described. In this case, due to the self-alignment effect during the reflow process, as a result, the second resin body 40 does not contact the solder 60.

[0127] In the module 100, as shown in FIG. 7, a mold resin 70 may be provided between the wiring substrate 50, the first external electrode 27, and the second external electrode 28. FIG. 7 is a schematic cross-sectional view showing a state in which a mold resin is provided in the module of Embodiment 1 of the present invention.

[0128] When the first resin body 30 is provided limitedly at the four corners of the substrate 10 like the capacitor 1, when it is molded with resin after mounting, since the path through which the molding resin is filled is open, filling defects can be suppressed.

[0129] [Embodiment 2] The capacitor of Embodiment 1 of the present invention may further include a third resin body. In that case, the third resin body is provided between the first resin bodies in a plan view from the thickness direction, and in the thickness direction, the tip of the third resin body on the side opposite to the substrate is at a position higher than the tips of the first external electrode and the second external electrode on the side opposite to the substrate, and at a position lower than the tip of the first resin body on the side opposite to the substrate. Such an example will be described below as the capacitor of Embodiment 2 of the present invention.

[0130] FIG. 8-1 is a schematic plan view showing an example of the capacitor of Embodiment 2 of the present invention. FIG. 8-2 is a schematic cross-sectional view showing a portion corresponding to the line segment A1-A2 in FIG. 8-1. FIG. 8-3 is a schematic side view of the capacitor shown in FIG. 8-1.

[0131] FIG. 9-1 is a schematic plan view showing a modified example of the capacitor of Embodiment 2 of the present invention. FIG. 9-2 is a schematic cross-sectional view showing a portion corresponding to the line segment A1-A2 in FIG. 9-1. FIG. 9-3 is a schematic side view of the capacitor shown in FIG. 9-1.

[0132] In the capacitor 2 shown in FIGS. 8-1, 8-2 and 8-3 and the capacitor 2A shown in FIGS. 9-1, 9-2 and 9-3, a third resin body 41 is provided between the first resin bodies 30 in a plan view from the thickness direction T. Here, the third resin body 41 is provided at the outer peripheral portion of the substrate 10 in a plan view from the thickness direction T.

[0133] In the thickness direction T, the tip of the third resin body 41 on the side opposite to the substrate 10 is at a position higher than the tips of the first external electrode 27 and the second external electrode 28 on the side opposite to the substrate 10, and at a position lower than the tip of the first resin body 30 on the side opposite to the substrate 10.

[0134] By providing the third resin body 41, for an unexpected sudden high load during mounting, the load that cannot be fully dispersed by the first resin body 30 can be further dispersed by the third resin body 41, so that damage to the dielectric layer 23 can be suppressed.

[0135] The first resin body 30 and the third resin body 41 may be connected, but it is preferable that they are separated at the bottom because the load during mounting will not be transmitted from the first resin body 30 to the third resin body 41. The constituent material of the third resin body 41 may be the same as that of the first resin body 30. Also, the third resin body 41 may be formed simultaneously with the first resin body 30.

[0136] [Embodiment 3] In the capacitor of Embodiment 1 or Embodiment 2 of the present invention, the circuit layer may further have a third electrode layer provided facing the first electrode layer and separated from the second electrode layer. Such an example will be described below as the capacitor of Embodiment 3 of the present invention.

[0137] FIG. 10-1 is a schematic plan view showing an example of the capacitor of Embodiment 3 of the present invention. FIG. 10-2 is a schematic side view of the capacitor shown in FIG. 10-1. FIG. 10-3 is a schematic cross-sectional view showing a portion corresponding to the line segment A1-A2 in FIG. 10-1.

[0138] FIG. 11-1 is a schematic plan view showing a modified example of the capacitor of Embodiment 3 of the present invention. FIG. 11-2 is a schematic side view of the capacitor shown in FIG. 11-1. FIG. 11-3 is a schematic cross-sectional view showing a portion corresponding to the line segment A1-A2 in FIG. 11-1.

[0139] In the capacitor 3 shown in FIGS. 10-1, 10-2, and 10-3 and the capacitor 3A shown in FIGS. 11-1, 11-2, and 11-3, the circuit layer 20 further has a third electrode layer 24a.

[0140] The first external electrode 27 is drawn out on the surface of the circuit layer 20 opposite to the substrate 10 and is spaced apart from the second external electrode 28. That is, the first external electrode 27 is located on the side of the third electrode layer 24a opposite to the substrate 10. Here, the first external electrode 27 is electrically connected to the third electrode layer 24a. More specifically, the openings provided in the moisture-resistant protective layer 25 and the resin protective layer 26 communicate with each other along the thickness direction T and extend, and the first external electrode 27 is electrically connected to the third electrode layer 24a through the openings. Further, the first external electrode 27 is spaced apart from the first electrode layer 22 on the surfaces along the length direction L and the thickness direction T (see FIGS. 10-3 and 11-3), and thus is not electrically connected to the first electrode layer 22.

[0141] The third electrode layer 24a is provided to face the first electrode layer 22 and be spaced apart from the second electrode layer 24. More specifically, the third electrode layer 24a is provided on the surface of the dielectric layer 23 opposite to the substrate 10 and faces the first electrode layer 22 with the dielectric layer 23 interposed therebetween.

[0142] Examples of the constituent material of the third electrode layer 24a include metals such as aluminum (Al), silicon (Si), copper (Cu), silver (Ag), gold (Au), nickel (Ni), chromium (Cr), and titanium (Ti). The constituent material of the third electrode layer 24a may be an alloy containing at least one of the above-mentioned metals, and specific examples thereof include aluminum-silicon alloy (AlSi), aluminum-copper alloy (AlCu), aluminum-silicon-copper alloy (AlSiCu), and the like.

[0143] The third electrode layer 24a may have a single-layer structure or a multilayer structure including a plurality of conductor layers made of the above-mentioned materials.

[0144] The dimension (thickness) of the third electrode layer 24a in the thickness direction T is preferably 0.3 μm or more and 10 μm or less, and more preferably 0.5 μm or more and 5 μm or less.

[0145] A capacitor element is formed by the first electrode layer 22, the dielectric layer 23, and the third electrode layer 24a. More specifically, the capacitance of the capacitor element is formed in a region where the first electrode layer 22, the dielectric layer 23, and the third electrode layer 24a overlap.

[0146] In the configuration of the capacitor 1 shown in FIGS. 1-1, 1-2, and 1-3, a capacitor is formed on the left side, while in the configurations of the capacitor 3 shown in FIGS. 10-1, 10-2, and 10-3 and the capacitor 3A shown in FIGS. 11-1, 11-2, and 11-3, capacitors are formed on both the left and right sides. As a result, a capacitor having the same capacitance as the capacitor 1 can be formed with the thickness of the dielectric layer 23 being approximately halved. Therefore, the manufacturing cost can be reduced by the amount that the dielectric layer 23 of the capacitor with a small capacitance can be made thinner. On the other hand, when the dielectric layer 23 becomes thinner, the capacitor element is more likely to be damaged when a load is applied. However, by arranging the first resin body 30 at the four corners, damage to the capacitor element can be suppressed.

[0147] [Embodiment 4] The semiconductor device of the present invention may not include the second resin body. In that case, the thickness of the dielectric layer is preferably 0.5 μm or less, and more preferably 0.3 μm or less. Such an example will be described below as the capacitor of Embodiment 4 of the present invention.

[0148] FIG. 12-1 is a schematic plan view showing an example of the capacitor of Embodiment 4 of the present invention. FIG. 12-2 is a schematic side view of the capacitor shown in FIG. 12-1. FIG. 12-3 is a schematic cross-sectional view showing a portion corresponding to the line segment A1-A2 in FIG. 12-1.

[0149] The capacitor 4 shown in FIGS. 12-1, 12-2, and 12-3 includes the first resin body 30 but does not include the second resin body 40.

[0150] For example, when the thickness of the dielectric layer 23 is 0.5 μm or less, and more preferably 0.3 μm or less, if a load is applied to the second resin body 40 during mounting, excessive load may be applied to the dielectric layer 23 directly below the second resin body 40 through the second resin body 40, and the dielectric layer 23 may be damaged if the height of the first resin body 30 is not precisely controlled. In such a case, as shown in FIGS. 12-1, 12-2, and 12-3, by adopting a structure without the second resin body 40, the load received during mounting is applied to the first resin body 30. By providing the first resin bodies 30 only at the four corners of the substrate 10, compared to the case where the first resin bodies 30 are provided along the outer peripheral portion of the substrate 10 and the load is concentrated at the ends of the second electrode layer 24 through the substrate 10, the load is concentrated at the four corners of the substrate 10 directly below the first resin bodies 30. Therefore, the stress applied to the ends of the second electrode layer 24 is reduced, and cracks in the dielectric layer 23 can be suppressed.

[0151] Also, when being molded with resin after mounting, as shown in FIGS. 12-1, 12-2, and 12-3, if the second resin body 40 is not provided and the first resin bodies 30 are provided at the four corners of the substrate 10, compared to the case where the second resin body 40 is provided and the first resin bodies 30 are provided to cover the entire outer peripheral portion of the substrate 10, the path through which the molding resin is filled is more open, so filling defects can be suppressed.

[0152] [Embodiment 5] In the semiconductor device of the present invention, in a plan view from the thickness direction, the first resin body may be provided at a position that does not overlap with the resin protection layer. Such an example will be described below as the capacitor of Embodiment 3 of the present invention.

[0153] FIG. 13-1 is a schematic plan view showing an example of the capacitor of Embodiment 5 of the present invention. FIG. 13-2 is a schematic side view of the capacitor shown in FIG. 13-1. FIG. 13-3 is a schematic cross-sectional view showing a portion corresponding to the line segment A1-A2 in FIG. 13-1.

[0154] In the capacitor 5 shown in FIGS. 13-1, 13-2, and 13-3, in a plan view from the thickness direction T, the first resin body 30 is provided at a position that does not overlap with the resin protection layer 26.

[0155] As shown in FIG. 13-1, it is preferable that the circuit layer 20 is not formed at at least four corners of the capacitor element (at least four corners of the substrate 10). Note that the circuit layer 20 may not be formed at the outer peripheral portion of the capacitor element (the outer peripheral portion of the substrate 10).

[0156] The first resin body 30 is preferably provided directly on the substrate 10, but some layers may be present between the first resin body 30 and the substrate 10.

[0157] FIG. 14-1 is a schematic plan view showing a modified example of the capacitor according to Embodiment 5 of the present invention. FIG. 14-2 is a schematic side view of the capacitor shown in FIG. 14-1. FIG. 14-3 is a schematic cross-sectional view showing a portion corresponding to the line segment A1-A2 in FIG. 14-1.

[0158] In the capacitor 5A shown in FIGS. 14-1, 14-2, and 14-3, the first resin body 30 and the resin protection layer 26 are separated.

[0159] The first resin body 30 may be in contact with each layer of the circuit layer 20, but as shown in FIG. 14-2, it is preferably separated from the resin protection layer 26, and more preferably separated from the other circuit layers 20.

[0160] The Young's modulus of the first resin body 30 is preferably greater than the Young's modulus of the resin protection layer 26. In this case, it becomes more difficult for the load to be transmitted to the resin protection layer 26. Specifically, the first resin body 30 preferably contains a resin in the solder resist, and the resin protection layer 26 preferably contains a polyimide resin.

[0161] Even in Embodiment 5, the same effects as in Embodiment 1 can be obtained. In Embodiment 5, since the load received during mounting is less likely to be further transmitted to the resin protection layer 26, the load concentrates on the four corners of the substrate 10 directly below the first resin body 30. As a result, the stress applied to the end portion of the second electrode layer 24 is reduced, and cracks in the dielectric layer 23 can be suppressed. Further, when the first resin body 30 is separated from the resin protection layer 26, the load is less likely to be transmitted to the resin protection layer 26.

[0162] [Other Embodiments] The semiconductor device of the present invention is not limited to the above embodiments, and various applications and modifications can be made within the scope of the present invention regarding the configuration, manufacturing conditions, etc. of semiconductor devices such as capacitors.

[0163] For example, the semiconductor device of the present invention may include the first resin body and the third resin body without including the second resin body.

Description of Reference Numerals

[0164] 1, 1A, 1B, 1C, 2, 2A, 3, 3A, 4, 5, 5A Capacitor (Semiconductor Device) 10 Substrate 10a First Main Surface of Substrate 10b Second Main Surface of Substrate 20 Circuit Layer 21 Insulating Layer 22 First Electrode Layer 23 Dielectric Layer 24 Second Electrode Layer 24a Third Electrode Layer 25 Moisture-Resistant Protection Layer 26 Resin Protection Layer 27 First External Electrode 28 Second External Electrode 29a Seed Layer 29b First Plating Layer 29c Second Plating Layer 30 First Resin Body 35 Photosensitive Resin Film 40 Second Resin Body 40a First Wall Portion 40b Second Wall Portion 41 Third resin body 50 Wiring board 51 Substrate 52 First land 53 Second land 60 Solder 70 Mold resin 80 Region connecting the opposing ends of the first external electrode and the second external electrode 100 Module L Length direction T Thickness direction W Width direction

Claims

1. a substrate having a first main surface and a second main surface facing each other in the thickness direction; a circuit layer provided on the first main surface of the substrate; a first resin body; a second resin body, comprising: The circuit layer includes a first electrode layer provided on the substrate side, a second electrode layer provided to face the first electrode layer, a dielectric layer provided between the first electrode layer and the second electrode layer in the thickness direction, a first external electrode drawn out on the surface of the circuit layer opposite to the substrate, and a second external electrode drawn out on the surface of the circuit layer opposite to the substrate and provided spaced apart from the first external electrode. The first resin body is provided at four corners of the substrate in a plan view from the thickness direction. In the thickness direction, the tip of the first resin body on the side opposite to the substrate is at a position higher than the tips of the first external electrode and the second external electrode on the side opposite to the substrate. The second resin body is provided between the first external electrode and the second external electrode in a plan view from the thickness direction. In the thickness direction, the tip of the second resin body on the side opposite to the substrate is at a position higher than the tips of the first external electrode and the second external electrode on the side opposite to the substrate, and is at a position higher than the tip of the first resin body on the side opposite to the substrate. A semiconductor device.

2. A substrate having a first main surface and a second main surface facing each other in the thickness direction; a circuit layer provided on the first main surface of the substrate; a first resin body; a third resin body, comprising: The circuit layer includes a first electrode layer provided on the substrate side, a second electrode layer provided to face the first electrode layer, a dielectric layer provided between the first electrode layer and the second electrode layer in the thickness direction, a first external electrode drawn out on the surface of the circuit layer opposite to the substrate, and a second external electrode drawn out on the surface of the circuit layer opposite to the substrate and provided spaced apart from the first external electrode. The first resin body is provided at four corners of the substrate in a plan view from the thickness direction. In the thickness direction, the tip of the first resin body on the side opposite to the substrate is at a position higher than the tips of the first external electrode and the second external electrode on the side opposite to the substrate. The third resin body is provided between the first resin bodies in a plan view from the thickness direction. In the thickness direction, the tip of the third resin body on the side opposite to the substrate is at a position higher than the tips of the first external electrode and the second external electrode on the side opposite to the substrate, and is at a position lower than the tip of the first resin body on the side opposite to the substrate. A semiconductor device.

3. Further comprising a third resin body, The third resin body is provided between the first resin bodies in a plan view from the thickness direction, In the thickness direction, the tip of the third resin body on the side opposite to the substrate is at a position higher than the tips of the first external electrode and the second external electrode on the side opposite to the substrate, and is at a position lower than the tip of the first resin body on the side opposite to the substrate. The semiconductor device according to claim 1.

4. In a plan view from the thickness direction, the first resin body is provided at a position that does not overlap with the first electrode layer. The semiconductor device according to claim 1.

5. The circuit layer further has a resin protection layer that covers the first electrode layer and the second electrode layer. The semiconductor device according to claim 1.

6. In a plan view from the thickness direction, the first resin body is provided at a position that does not overlap with the resin protection layer. The semiconductor device according to claim 5.

7. The first resin body and the resin protection layer are separated from each other. The semiconductor device according to claim 6.

8. The Young's modulus of the first resin body is greater than the Young's modulus of the resin protection layer. The semiconductor device according to claim 5.

9. The first resin body contains a resin in the solder resist, The resin protection layer contains a polyimide resin. The semiconductor device according to claim 8.

10. The first external electrode is electrically connected to the first electrode layer, The second external electrode is electrically connected to the second electrode layer. The semiconductor device according to any one of claims 1 to 9.

11. The circuit layer further has a third electrode layer that faces the first electrode layer and is separated from the second electrode layer, The first external electrode is electrically connected to the third electrode layer, The second external electrode is electrically connected to the second electrode layer. The semiconductor device according to any one of claims 1 to 9.

12. A semiconductor device according to any one of claims 1 to 9, A wiring board having a first land electrically connected to the first external electrode and a second land electrically connected to the second external electrode. A module comprising:

13. The module according to claim 12, further comprising a molding resin provided between each of the wiring substrate, the first external electrode, and the second external electrode.

Images