Distributed amplifier

Abstract

To improve gain without degrading band.SOLUTION: When a bias voltage of the (n+1)th stage (n is an integer from 1 to N-1) of the N amplifier blocks 100c to 300c (N is an integer of 2 or more) is Vb_(n+1), the number of unit cells 3-1 to 3-3 in each amplifier block is Nopt, and the current flowing between the input terminal and output terminal of the unit cells 3-1 to 3-3 of each amplifier block is Iopt, the characteristic impedance of the transmission line CPW20c-1, CPW20c-2 of the n-th amplifier block, the characteristic impedances of the terminating resistors Ro1 and Ro2 of the n-th amplifier block and the transmission lines CPW10c-2 and CPW10c-3 of the (n+1)th stage amplifier block, and the terminating resistors Ri2 and Ri3 of the (n+1)th stage amplifier block are set to satisfy -Vb_(n+1) / (Iopt×Nopt).SELECTED DRAWING: Figure 8

Description

Technical Field

[0001] The present invention relates to a distributed circuit, and more particularly to a distributed amplifier.

Background Art

[0002] Broadband amplifiers are desired in various systems such as high-speed communication and high-resolution radar. As a technique for broadening the bandwidth of an amplifier, a distributed amplifier has been conventionally proposed (see Patent Document 1). FIG. 13 is a circuit diagram showing the configuration of a conventional distributed amplifier. The distributed amplifier includes an input transmission line CPW10 having an input end connected to a signal input terminal 1, an output transmission line CPW20 having a terminal connected to a signal output terminal 2, an input terminal resistor Ri1 having one end connected to the terminal of the transmission line CPW10 and the other end connected to a bias voltage Vb_1, an output terminal resistor Ro2 connecting the input end of the transmission line CPW20 and the ground, and a plurality of unit cells 3 arranged along the transmission lines CPW10 and CPW20, with an input terminal a connected to the transmission line CPW10 and an output terminal b connected to the transmission line CPW20.

[0003] The transmission line CPW10 is configured by connecting a plurality of transmission lines CPW1i, CPW1, and CPW1o in series. Similarly, the transmission line CPW20 is configured by connecting a plurality of transmission lines CPW2i, CPW2, and CPW2o in series.

[0004] As shown in FIG. 14, each unit cell 3 includes an input transistor Q30 having a base terminal connected to the transmission line CPW10 and an emitter terminal connected to a power supply voltage VEE, and an output transistor Q31 having a base terminal connected to a bias voltage Vcas1, a collector terminal connected to the transmission line CPW20, and an emitter terminal connected to the collector terminal of the input transistor Q30.

[0005] In a distributed amplifier, the parasitic capacitances of transistors Q30 and Q31 are incorporated into the input / output transmission lines CPW10 and CPW20 to achieve impedance matching. Further, by matching the propagation constants of the input / output transmission lines CPW10 and CPW20, broadband signal amplification becomes possible. In order to improve the gain of a distributed amplifier, generally, a method of increasing the number of stages (the number of parallel units of unit cell 3) as shown in FIG. 15 is adopted.

[0006] However, in a conventional distributed amplifier, there has been a problem that the bandwidth deteriorates as the number of stages increases. FIG. 16 is a diagram showing the simulation results of the S-parameter S21 of 6-stage and 12-stage distributed amplifiers. S21_6 in FIG. 16 is the S-parameter S21 of a 6-stage distributed amplifier, and S21_12 is the S-parameter S21 of a 12-stage distributed amplifier.

[0007] According to FIG. 16, it can be confirmed that the DC (direct current) gain has improved by increasing the number of stages from 6 to 12, but the bandwidth has deteriorated significantly. This bandwidth deterioration is caused by signal attenuation in the input / output transmission lines. Generally, the relationship between the bandwidth and the optimum number of stages Nopt (i.e., the maximum gain) has been clarified by Patent Document 2. Therefore, in a conventional distributed amplifier, it has been difficult to improve the gain without deteriorating the bandwidth.

Prior Art Documents

Non-Patent Documents

[0008]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0009] The present invention is made to solve the above problems, and an object thereof is to provide a distributed amplifier capable of improving gain without degrading the bandwidth.

Means for Solving the Problems

[0010] The distributed amplifier of the present invention includes N (N is an integer of 2 or more) amplifier blocks. Each amplifier block includes a first transmission line configured such that a signal is input to an input end, a second transmission line configured to output a signal from an output end, a first termination resistor having one end connected to a termination of the first transmission line, a second termination resistor having one end connected to an input end of the second transmission line, and a plurality of unit cells arranged along the first and second transmission lines, with input terminals connected to the first transmission line and output terminals connected to the second transmission line. Each amplifier block is cascade-connected such that the termination of the second transmission line is connected to the input end of the first transmission line of the subsequent amplifier block. The other end of the first termination resistor of each amplifier block is connected to a first bias voltage, the other end of the second termination resistor of each amplifier block is connected to ground, the characteristic impedance of the first transmission line of the first-stage amplifier block, the first termination resistor of the first-stage amplifier block, the characteristic impedance of the second transmission line of the last-stage amplifier block, and the value of the second termination resistor of the last-stage amplifier block are 50Ω. The first bias voltage of the (n + 1)-th stage (n is an integer from 1 to N - 1) amplifier block is Vb_(n + 1), the number of unit cells of each amplifier block is Nopt, and the current flowing between the input terminal and the output terminal of the unit cell of each amplifier blockand the optimum current at which the transistors of each unit cell operate When Iopt is used, the characteristic impedance of the second transmission line of the n-th amplifier block, the second termination resistor of the n-th amplifier block, the characteristic impedance of the first transmission line of the (n + 1)-th amplifier block, and the first termination resistor of the (n + 1)-th amplifier block are set to -Vb_(n + 1) / (Iopt × Nopt).

Advantages of the Invention

[0011] According to the present invention, the other end of the first termination resistor of each amplifier block is connected to the first bias voltage, the other end of the second termination resistor of each amplifier block is connected to the ground, the characteristic impedance of the first transmission line of the first-stage amplifier block, the first termination resistor of the first-stage amplifier block, the characteristic impedance of the second transmission line of the last-stage amplifier block, and the value of the second termination resistor of the last-stage amplifier block are set to 50Ω, and the characteristic impedance of the second transmission line of the n-th amplifier block, the second termination resistor of the n-th amplifier block, the characteristic impedance of the first transmission line of the (n + 1)-th amplifier block, and the first termination resistor of the (n + 1)-th amplifier block are set to -Vb_(n + 1) / (Iopt × Nopt). Thus, the gain can be improved without degrading the bandwidth.

Brief Description of the Drawings

[0012]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

Figure 15

Figure 16

DETAILED DESCRIPTION OF THE INVENTION

[0013] [First Embodiment] Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a circuit diagram showing the configuration of a distributed amplifier according to a first embodiment of the present invention. The distributed amplifier of this embodiment is formed by cascading an amplifier block 100 with an optimal number of stages Nopt and an amplifier block 200 with an optimal number of stages Nopt. Here, the optimal number of stages Nopt refers to the number of stages (the number of parallel unit cells) at which a desired frequency response of the amplifier block can be obtained. In the example of FIG. 1, Nopt = 6.

[0014] The amplifier block 100 includes an input transmission line CPW10_1 whose input end is connected to the signal input terminal 1, an output transmission line CPW20_1, an input terminal resistance Ri1 whose one end is connected to the end of the transmission line CPW10_1 and the other end is connected to the bias voltage Vb_1, an output terminal resistance Ro1 whose one end is connected to the input end of the transmission line CPW20_1 and the other end is connected to the ground, and a plurality of unit cells 3_1 arranged along the transmission lines CPW10_1 and CPW20_1, where the input terminal a1 is connected to the transmission line CPW10_1 and the output terminal b1 is connected to the transmission line CPW20_1. The input terminal resistance Ri1 is 50Ω. The output terminal resistance Ro1 will be described later.

[0015] The transmission line CPW10_1 is composed of a configuration in which a plurality of transmission lines CPW1i_1, CPW1_1, and CPW1o_1 are connected in series. The transmission line CPW1_1 between the unit cells and the input-side transmission line CPW1i_1 have different characteristic impedances. The reason is that in the case of the transmission line CPW1i_1, it is necessary to absorb the influence of the parasitic capacitance of the circuit in front of the signal input terminal 1 by the transmission line CPW1i_1. Similarly, the transmission lines CPW1_1 and CPW1o_1 have different characteristic impedances. The reason is that in the case of the transmission line CPW1o_1, it is necessary to absorb the influence of the parasitic capacitance of the input terminal resistance Ri1 by the transmission line CPW1o_1.

[0016] The transmission line CPW20_1 is composed of a configuration in which a plurality of transmission lines CPW2i_1, CPW2_1, and CPW12 are connected in series. The transmission line CPW2 between unit cells and the input-side transmission line CPW2i_1 have different characteristic impedances. The reason is that in the case of the transmission line CPW2i_1, it is necessary to absorb the influence of the parasitic capacitance of the output terminal resistance Ro1 by the transmission line CPW2i_1. Similarly, the transmission lines CPW2_1 and CPW12 have different characteristic impedances. The reason is that in the case of the transmission line CPW12, it is necessary to absorb the influence of the parasitic capacitance of the amplifier block 200 in the subsequent stage of the transmission line CPW20_1 by the transmission line CPW12.

[0017] The amplifier block 200 includes an input transmission line CPW10_2 whose input end is connected to the terminal of the transmission line CPW20_1 of the amplifier block 100, an output transmission line CPW20_2 whose terminal is connected to the signal output terminal 2, an input terminal resistance Ri2 whose one end is connected to the terminal of the transmission line CPW10_2 and the other end is connected to the bias voltage Vb_2, an output terminal resistance Ro2 whose one end is connected to the input end of the transmission line CPW20_2 and the other end is connected to the ground, and a plurality of unit cells 3_2 arranged along the transmission lines CPW10_2 and CPW20_2, with the input terminal a2 connected to the transmission line CPW10_2 and the output terminal b2 connected to the transmission line CPW20_2. The output terminal resistance Ro2 is 50 Ω. The input terminal resistance Ri2 will be described later.

[0018] The transmission line CPW10_2 is composed of a configuration in which a plurality of transmission lines CPW12, CPW1_2, and CPW1o_2 are connected in series. The transmission line CPW1_2 between unit cells and the input-side transmission line CPW12 have different characteristic impedances. The reason is that in the case of the transmission line CPW12, it is necessary to absorb the influence of the parasitic capacitance of the amplifier block 100 in the previous stage of the transmission line CPW10_2 by the transmission line CPW12. Similarly, the transmission lines CPW1_2 and CPW1o_2 have different characteristic impedances. The reason is that in the case of the transmission line CPW1o_2, it is necessary to absorb the influence of the parasitic capacitance of the input terminal resistance Ri2 by the transmission line CPW1o_2.

[0019] In this embodiment, the transmission line CPW20_1 for the output of the amplifier block 100 and the transmission line CPW10_2 for the input of the amplifier block 200 share the transmission line CPW12.

[0020] The transmission line CPW20_2 is composed of a configuration in which a plurality of transmission lines CPW2_2 and CPW2o_2 are connected in series. The transmission lines CPW2_2 and CPW2o_2 between the unit cells have different characteristic impedances. The reason is that in the case of the transmission line CPW2o_2, it is necessary to absorb the influence of the parasitic capacitance of the circuit etc. after the signal output terminal 2 by the transmission line CPW2o_2. The configuration of the unit cells 3_1 and 3_2 will be described in the second embodiment.

[0021] In this embodiment, by cascade-connecting the amplifier block 100 with the optimal number of stages Nopt and the amplifier block 200 with the optimal number of stages Nopt, it becomes possible to improve the gain without degrading the bandwidth.

[0022] Also, in this embodiment, the characteristic impedance Z0 of the transmission line CPW20_1 for the output of the amplifier block 100, the output terminal resistance Ro1, the characteristic impedance Z0 of the transmission line CPW10_2 for the input of the amplifier block 200, and the input terminal resistance Ri2 are greater than 50 Ω and are as follows. Z0 = Ro1 = Ri2 = -Vb_2 / (Iopt × Nopt) ···(1)

[0023] In Equation (1), Iopt is the current flowing between the input terminal and the output terminal of each unit cell 3_1 and 3_2. The bias voltages Vb_1 and Vb_2 are negative voltages.

[0024] In this embodiment, by setting the characteristic impedance Z0 of the transmission lines CPW20_1 and CPW10_2, the output terminal resistance Ro1, and the input terminal resistance Ri2 as in Equation (1), the amplifier block 100 and the amplifier block 200 can be DC-coupled, and while enabling amplification of signals from DC to high frequency, it becomes possible to further improve the gain.

[0025] [Second Embodiment] Next, a second embodiment of the present invention will be described. FIG. 2 is a circuit diagram showing the configuration of a distributed amplifier according to the second embodiment of the present invention. The distributed amplifier of this embodiment is formed by cascading an amplifier block 100a with an optimal number of stages Nopt = 6 and an amplifier block 200a with an optimal number of stages Nopt = 6.

[0026] The amplifier block 100a includes an input transmission line CPW10a_1, an output transmission line CPW20a_1, an input terminal resistance Ri1, an output terminal resistance Ro1 with one end connected to the input end of the transmission line CPW20a_1 and the other end connected to the power supply voltage VCC_1, and a plurality of unit cells 3_1 arranged along the transmission lines CPW10a_1 and CPW20a_1, with the input terminal a1 connected to the transmission line CPW10a_1 and the output terminal b1 connected to the transmission line CPW20a_1. The input terminal resistance Ri1 and the output terminal resistance Ro1 are 50 Ω.

[0027] The transmission line CPW10a_1 has the same configuration as the transmission line CPW10_1 of the first embodiment. The transmission line CPW20a_1 has a similar configuration to the transmission line CPW20_1 of the first embodiment, but the characteristic impedance Z0 is 50 Ω.

[0028] The amplifier block 200a includes an input transmission line CPW10a_2, an output transmission line CPW20a_2, an input terminal resistance Ri2 with one end connected to the end of the transmission line CPW10a_2 and the other end connected to the bias voltage Vb_2, an output terminal resistance Ro2, and a plurality of unit cells 3_2 arranged along the transmission lines CPW10a_2 and CPW20a_2, with the input terminal a2 connected to the transmission line CPW10a_2 and the output terminal b2 connected to the transmission line CPW20a_2. The output terminal resistance Ro2 and the input terminal resistance Ri2 are 50 Ω.

[0029] The transmission line CPW10a_2 has the same configuration as the transmission line CPW10_2 of the first embodiment, but the characteristic impedance Z0 is 50 Ω. The transmission line CPW20a_2 has the same configuration as the transmission line CPW20_2 of the first embodiment.

[0030] FIG. 3 is a circuit diagram showing the configuration of the unit cell 3_1 of the amplifier block 100a, and FIG. 4 is a circuit diagram showing the configuration of the unit cell 3_2 of the amplifier block 200a. As shown in FIG. 3, the unit cell 3_1 includes an input transistor Q32 having a base terminal connected to the transmission line CPW10a_1 and an emitter terminal connected to the power supply voltage VEE1, and a base terminal connected to the bias voltage Vcas1, a collector terminal connected to the transmission line CPW20a_1, and an emitter terminal connected to the collector terminal of the input transistor Q32. It is composed of an output transistor Q33.

[0031] As shown in FIG. 4, the unit cell 3_2 includes an input transistor Q34 having a base terminal connected to the transmission line CPW10a_2 and an emitter terminal connected to the power supply voltage VEE2, and a base terminal connected to the bias voltage Vcas2, a collector terminal connected to the transmission line CPW20a_2, and an emitter terminal connected to the collector terminal of the input transistor Q34. It is composed of an output transistor Q35.

[0032] The unit cell 3_1 and the unit cell 3_2 have the same circuit configuration, but the applied voltages are different. In the amplifier block 100a, VCC_1 and VEE1 are supplied as power supply voltages, and Vb_1 and Vcas1 are supplied as bias voltages. In the amplifier block 200a, ground (0V) and VEE2 are supplied as power supply voltages, and Vb_2 and Vcas2 are supplied as bias voltages. The voltages VCC_1, VEE1, Vb_1, Vcas1, VEE2, Vb_2, and Vcas2 are basically negative voltages with respect to ground.

[0033] Amplifiers used in optical communication and the like need to amplify signals from near DC to high frequencies. In this embodiment, by setting the value of the power supply voltage VCC_1 as shown in the following equation, the output common voltage of the amplifier block 100a and the input common voltage of the amplifier block 200a can be made the same voltage, enabling amplification of signals from DC to high frequencies without disturbing the operating points of the respective transistors. VCC_1 = Vb_2 + Iopt × Nopt × 50 ···(2)

[0034] As described in the first embodiment, Iopt is the current flowing between the input terminal and the output terminal of each unit cell 3_1, 3_2, and is the optimum current at which the transistors of each unit cell 3_1, 3_2 operate.

[0035] A method of inserting a DC cut capacitor between amplifier blocks without directly connecting the amplifier blocks is also conceivable. However, since the value of the capacitor that can be realized on-chip is small, it is difficult to amplify signals near DC in a configuration where a DC cut capacitor is inserted between amplifier blocks.

[0036] FIG. 5 is a diagram showing the simulation results of the S-parameters of a conventional distributed amplifier and the distributed amplifier of this embodiment. S21_6 in FIG. 5 is the S-parameter S21 of a conventional 6-stage distributed amplifier, S21_12 is the S-parameter S21 of a conventional 12-stage distributed amplifier, and S21_e is the S-parameter S21 of the distributed amplifier of this embodiment. In this embodiment, it can be confirmed that the gain can be improved without degrading the bandwidth compared to the conventional 12-stage distributed amplifier.

[0037] In this embodiment, the case where there are two amplifier blocks is shown, but three or more may be used. As an example, the configuration when there are three amplifier blocks is shown in FIG. 6. The distributed amplifier in FIG. 6 is formed by cascadingly connecting an amplifier block 100b with an optimum number of stages Nopt = 6, an amplifier block 200b with an optimum number of stages Nopt = 6, and an amplifier block 300b with an optimum number of stages Nopt = 6.

[0038] The amplifier block 100b is composed of an input transmission line CPW10b_1, an output transmission line CPW20b_1, an input terminal resistor Ri1, an output terminal resistor Ro1, and a unit cell 3_1. The configuration of the amplifier block 100b is the same as that of the amplifier block 100a.

[0039] The amplifier block 200b is composed of an input transmission line CPW10b_2, an output transmission line CPW20b_2, an input terminal resistor Ri2, an output terminal resistor Ro2, and a unit cell 3_2. The configuration of the amplifier block 200b is the same as that of the amplifier block 200a, but it is different from the configuration in Fig. 2 in that the other end of the output terminal resistor Ro2 is not grounded but connected to the power supply voltage VCC_2. The setting of the power supply voltage VCC_2 will be described later.

[0040] The amplifier block 300b is composed of an input transmission line CPW10b_3 whose input end is connected to the end of the transmission line CPW20b_2 of the amplifier block 200b, an output transmission line CPW20b_3 whose end is connected to the signal output terminal 2, an input terminal resistor Ri3 whose one end is connected to the end of the transmission line CPW10b_3 and the other end is connected to the bias voltage Vb_3, an output terminal resistor Ro3 whose one end is connected to the input end of the transmission line CPW20b_3 and the other end is connected to the ground, and a plurality of unit cells 3_3 arranged along the transmission lines CPW10b_3 and CPW20b_3, with the input terminal a3 connected to the transmission line CPW10b_3 and the output terminal b3 connected to the transmission line CPW20b_3. The output terminal resistor Ro3 and the input terminal resistor Ri3 are 50Ω.

[0041] The transmission line CPW10b_3 is composed of a configuration in which a plurality of transmission lines CPW23, CPW1_3, and CPW1o_3 are connected in series. The transmission line CPW1_3 between unit cells and the input-side transmission line CPW23 have different characteristic impedances. The reason is that in the case of the transmission line CPW23, it is necessary to absorb the influence of the parasitic capacitance of the amplifier block 200b in the previous stage of the transmission line CPW10b_3 by the transmission line CPW23. Similarly, the transmission lines CPW1_3 and CPW1o_3 have different characteristic impedances. The reason is that in the case of the transmission line CPW1o_3, it is necessary to absorb the influence of the parasitic capacitance of the input terminal resistance Ri3 by the transmission line CPW1o_3.

[0042] Note that in the configuration of FIG. 6, the transmission line CPW20b_2 for the output of the amplifier block 200b and the transmission line CPW10b_3 for the input of the amplifier block 300b share the transmission line CPW23.

[0043] The transmission line CPW20b_3 is composed of a configuration in which a plurality of transmission lines CPW2_3 and CPW2o_3 are connected in series. The transmission lines CPW2_3 and CPW2o_3 between unit cells have different characteristic impedances. The reason is that in the case of the transmission line CPW2o_3, it is necessary to absorb the influence of the parasitic capacitance of the circuit etc. in the subsequent stage of the signal output terminal 2 by the transmission line CPW2o_3.

[0044] FIG. 7 is a circuit diagram showing the configuration of the unit cell 3_3 of the amplifier block 300b. The unit cell 3_3 includes an input transistor Q36 whose base terminal is connected to the transmission line CPW10b_3 and whose emitter terminal is connected to the power supply voltage VEE3, and an output transistor Q37 whose base terminal is connected to the bias voltage Vcas3, whose collector terminal is connected to the transmission line CPW20b_3, and whose emitter terminal is connected to the collector terminal of the input transistor Q36.

[0045] VCC_1, VEE1, Vb_1, Vcas1, VCC_2, VEE2, Vb_2, Vcas2, VEE3, Vb_3, Vcas3 are negative voltages. In the configuration of FIG. 6, by setting the value of the power supply voltage VCC_2 as shown in the following equation, the output common voltage of the amplifier block 200b and the input common voltage of the amplifier block 300b can be made the same voltage, enabling amplification of signals from DC to high frequencies without disturbing the operating points of the respective transistors. VCC_2 = Vb_3 + Iopt × Nopt × 50 ···(3)

[0046] Even when there are four or more amplifier blocks, the same configuration as in this embodiment may be used. That is, when there are N (N is an integer of 2 or more) cascaded amplifier blocks, the other ends of the input terminal resistors Ri1 to RiN are connected to the bias voltages Vb_1 to Vb_N, the other ends of the output terminal resistors Ro1 to Ro(N - 1) except for the final stage are connected to the power supply voltages VCC_1 to VCC_(N - 1), the other end of the output terminal resistor RoN of the final stage is connected to the ground, and the characteristic impedance of all transmission lines and the value of the terminal resistor are set to 50Ω. Further, the power supply voltage VCC_n (n is an integer from 1 to N - 1) may be set as shown in the following equation. VCC_n = Vb_(n + 1) + Iopt × Nopt × 50 ···(4)

[0047] [Third Embodiment] Next, a third embodiment of the present invention will be described. Since this embodiment is a specific example of the first embodiment, it will be described using the reference numerals in FIG. 1. In the second embodiment, the other end of the output terminal resistor of the amplifier block except for the final stage is connected to the power supply voltage VCC. However, for ease of current capacity design of the wiring, ease of layout of the wiring, and good reflection characteristics, it is desirable to connect the other end of the output terminal resistor to the ground as shown in the first embodiment.

[0048] In this embodiment, in order to connect the other ends of the output terminal resistors Ro1 and Ro2 of each amplifier block 100 and 200 to the ground and couple the output of the amplifier block 100 and the input of the amplifier block 200 at the same DC potential, the characteristic impedance Z0 of the transmission line CPW20_1 for the output of the amplifier block 100, the output terminal resistor Ro1, the characteristic impedance Z0 of the transmission line CPW10_2 for the input of the amplifier block 200, and the input terminal resistor Ri2 are set as in Equation (1).

[0049] As an example, when Vb_2 = 3V, Iopt = 5mA, and Nopt = 6, the output terminal resistor Ro1 and the input terminal resistor Ri2 are 100Ω. By adopting the configuration of this embodiment, since the output impedance of the amplifier block 100 can be made 50Ω or more, there is also an effect that the gain of the amplifier is improved.

[0050] In the first embodiment and this embodiment, the case where there are two amplifier blocks is shown, but three or more may be used. As an example, the configuration when there are three amplifier blocks is shown in FIG. 8. The distributed amplifier in FIG. 8 is formed by cascading an amplifier block 100c with an optimal number of stages Nopt = 6, an amplifier block 200c with an optimal number of stages Nopt = 6, and an amplifier block 300c with an optimal number of stages Nopt = 6.

[0051] The amplifier block 100c is composed of an input transmission line CPW10c_1, an output transmission line CPW20c_1, an input terminal resistor Ri1, an output terminal resistor Ro1, and a unit cell 3_1. The configuration of the amplifier block 100c is the same as that of the amplifier block 100.

[0052] The amplifier block 200c is composed of an input transmission line CPW10c_2, an output transmission line CPW20c_2, an input terminal resistor Ri2, an output terminal resistor Ro2, and a unit cell 3_2. The configuration of the amplifier block 200c is the same as that of the amplifier block 200, but it is different from the first embodiment in that the value of the output terminal resistor Ro2 is greater than 50Ω.

[0053] The amplifier block 300c is composed of an input transmission line CPW10c_3, an output transmission line CPW20c_3, an input terminal resistor Ri3, an output terminal resistor Ro3, and a unit cell 3_3. The configuration of the amplifier block 300c is the same as that of the amplifier block 300b, but it is different from the second embodiment in that the value of the input terminal resistor Ri3 is greater than 50Ω.

[0054] In the configuration of Fig. 8, the characteristic impedance Z0 of the output transmission line CPW20c_2 of the amplifier block 200c, the output terminal resistor Ro2, the characteristic impedance Z0 of the input transmission line CPW10c_3 of the amplifier block 300c, and the input terminal resistor Ri3 are all greater than 50Ω and are as follows. Z0 = Ro2 = Ri3 = -Vb_3 / (Iopt × Nopt) ···(5)

[0055] Even when there are four or more amplifier blocks, the same configuration as in this embodiment may be adopted. That is, when there are N (N is an integer of 2 or more) cascaded amplifier blocks, the other ends of the input terminal resistors Ri1 to RiN are connected to the bias voltages Vb_1 to Vb_N, the other ends of the output terminal resistors Ro1 to RoN are connected to the ground, and the characteristic impedance of the input transmission line CPW10c_1 of the first stage, the input terminal resistor Ri1, the characteristic impedance of the output transmission line CPW20c_N of the last stage, and the output terminal resistor RoN are set to 50Ω.

[0056] Furthermore, the characteristic impedance Z0 of the output transmission line of the nth stage (n is an integer from 1 to N - 1) of the amplifier block excluding the last stage, the output terminal resistor Ron, the characteristic impedance Z0 of the input transmission line of the (n + 1)th stage of the amplifier block, and the input terminal resistor Ri(n + 1) may be set as follows. Z0 = Ron = Ri(n + 1) = -Vb_(n + 1) / (Iopt × Nopt) ···(6)

[0057] [Fourth Embodiment] Next, a fourth embodiment of the present invention will be described. FIG. 9 is a circuit diagram showing the configuration of a distributed amplifier according to the fourth embodiment of the present invention. The distributed amplifier of this embodiment is formed by cascading an amplifier block 100d with an optimal number of stages Nopt_1 = 6 and an amplifier block 200d with an optimal number of stages Nopt_2 = 6.

[0058] The amplifier block 100d includes an input transmission line CPW10d_1, an output transmission line CPW20d_1, an input terminal resistance Ri1, an output terminal resistance Ro1, and a plurality of unit cells 3d_1 arranged along the transmission lines CPW10d_1 and CPW20d_1, where the input terminal a1 is connected to the transmission line CPW10d_1 and the output terminal b1 is connected to the transmission line CPW20d_1.

[0059] The configuration of the amplifier block 100d is the same as that of the amplifier block 100a, except that the other end of the output terminal resistance Ro1 is connected to ground instead of the power supply voltage VCC_1, and the unit cell 3d_1 is different. The configuration of the amplifier block 200a is as described in the second embodiment.

[0060] FIG. 10 is a circuit diagram showing the configuration of the unit cell 3d_1 of the amplifier block 100d. As shown in FIG. 10, the unit cell 3d_1 includes an input transistor Q40 with its base terminal connected to the transmission line CPW10d_1 and its emitter terminal connected to the power supply voltage VEE1, and an output transistor Q41 with its base terminal connected to the bias voltage Vcas1, its collector terminal connected to the transmission line CPW20d_1, and its emitter terminal connected to the collector terminal of the input transistor Q40.

[0061] In the third embodiment, there are cases where it is difficult to design the characteristic impedance of the transmission line to be higher than 50 Ω (for example, up to about 100 Ω). In such cases, by setting the characteristic impedance of all transmission lines and the value of the terminating resistor to 50 Ω as in the second embodiment, and using transistors Q40 and Q41 in which the optimum current Iopt_1 in the unit cell 3d_1 of the amplifier block 100d is as follows, the output of the amplifier block 100d and the input of the amplifier block 200d can be coupled at the same DC potential. Iopt_1=-Vb_2 / (Nopt_1×50) ···(7)

[0062] In the first to third embodiments, amplifier blocks with the same number of stages (the number of unit cells in parallel) are used. On the other hand, in this embodiment, the number of stages Nopt_1 of the amplifier block 100d may be different from the number of stages Nopt_2 of the amplifier block 200a, where Nopt_1 is the optimum number of stages when the unit cell 3d_1 is composed of transistors with an optimum current of Ipot1.

[0063] Generally, in a bipolar transistor, there is an optimum collector current density at which the current gain cut-off frequency fT or the maximum oscillation frequency fmax is the highest (that is, the transistor operates fastest). The optimum current of a bipolar transistor with a certain emitter area (emitter length × emitter width) is defined as the optimum collector current density × emitter area. Therefore, the longer the emitter length or the larger the number of fingers, the larger the optimum current. By operating the bipolar transistors used in the circuit at the optimum current, the widest bandwidth can be achieved. Thus, when using bipolar transistors, the optimum current can be adjusted by adjusting the emitter length or the number of fingers.

[0064] Normally, the optimum current Iopt_1 of each transistor in the unit cell 3d_1 of the amplifier block 100d is larger than the optimum current Iopt_2 of each transistor in the unit cell 3_2 of the amplifier block 200a.

[0065] Therefore, the emitter length of each transistor used in amplifier block 100d is greater than the emitter length of each transistor used in amplifier block 200a. Alternatively, the number of fingers of each transistor used in amplifier block 100d is greater than the number of fingers of each transistor used in amplifier block 200a.

[0066] In this embodiment, the case where there are two amplifier blocks is shown, but three or more may be used. As an example, the configuration when there are three amplifier blocks is shown in FIG. 11. The distributed amplifier in FIG. 11 is formed by cascading amplifier block 100d with an optimal stage number Nopt_1 = 6, amplifier block 200d with an optimal stage number Nopt_2 = 6, and amplifier block 300b with an optimal stage number Nopt_3 = 6.

[0067] Amplifier block 200d is composed of an input transmission line CPW10d_2, an output transmission line CPW20d_2, an input terminal resistance Ri2, an output terminal resistance Ro2, and a plurality of unit cells 3d_2 arranged along the transmission lines CPW10d_2 and CPW20d_2, where the input terminal a2 is connected to the transmission line CPW10d_2 and the output terminal b2 is connected to the transmission line CPW20d_2.

[0068] The configuration of amplifier block 200d is the same as that of amplifier block 200b, except that the other end of the output terminal resistance Ro2 is connected to ground instead of the power supply voltage VCC_2, and the unit cell 3d_2 is different. The configuration of amplifier block 300b is as described in the second embodiment.

[0069] FIG. 12 is a circuit diagram showing the configuration of the unit cell 3d_2 of amplifier block 200d. The unit cell 3d_2 is composed of an input transistor Q42 with its base terminal connected to the transmission line CPW10d_2 and its emitter terminal connected to the power supply voltage VEE2, and an output transistor Q43 with its base terminal connected to the bias voltage Vcas2, its collector terminal connected to the transmission line CPW20d_2, and its emitter terminal connected to the collector terminal of the input transistor Q42.

[0070] By using transistors Q42 and Q43 in unit cell 3d_2 of amplifier block 200d for which the optimum current Iopt_2 is given by the following equation, the output of amplifier block 200d and the input of amplifier block 300b can be connected at the same DC potential. Iopt_2 = -Vb_3 / (Nopt_2 × 50) ···(8)

[0071] In the first to third embodiments, amplifier blocks having the same number of stages (the number of unit cells in parallel) are used. On the other hand, in this embodiment, the number of stages Nopt_2 of amplifier block 200d may be different from the number of stages Nopt_1 and Nopt_3 of amplifier blocks 100d and 300b, and is the optimum number of stages when unit cell 3d_2 is configured with transistors for which the optimum current is Ipot2.

[0072] Even when there are four or more amplifier blocks, the same configuration as in this embodiment may be used. That is, when there are N (N is an integer of 2 or more) amplifier blocks connected in cascade, the other ends of input termination resistors Ri1 to RiN are connected to bias voltages Vb_1 to Vb_N, the other ends of output termination resistors Ro1 to RoN are connected to ground, and the characteristic impedance and the value of the termination resistor of all transmission lines are set to 50Ω.

[0073] Furthermore, as the transistors used in each unit cell 3d_n of the n-th stage (n is an integer from 1 to N - 1) amplifier block excluding the final stage, transistors for which the optimum current Iopt_n is given by the following equation may be used. Iopt_n = -Vb_(n + 1) / (Nopt_n × 50) ···(9)

[0074] In the first to fourth embodiments, examples in which bipolar transistors are used in the unit cells are shown, but MOS transistors may also be used. When MOS transistors are used, in the above description, the base terminal may be replaced with the gate terminal, the collector terminal may be replaced with the drain terminal, and the emitter terminal may be replaced with the source terminal.

[0075] In addition, in the first to fourth embodiments, the case where a coplanar waveguide (CPW) is used as the transmission line is shown. However, the transmission line is not limited to CPW, and other transmission lines such as a microstrip line may be used as long as it is a transmission line.

Industrial Applicability

[0076] The present invention can be applied to a distributed amplifier that requires amplification of signals from DC to high frequency.

Explanation of Signs

[0077] 1... signal input terminal, 2... signal output terminal, 3, 3d... unit cell, 100, 100a to 100d, 200, 200a to 200d, 300b, 300c... amplifier block, CPW1, CPW1i, CPW1o, CPW2, CPW2i, CPW2o, CPW10, CPW10a to CPW10d, CPW20, CPW20a to CPW20d... transmission line, Q40 to Q43... transistor, Ri1 to Ri3, Ro1 to Ro3... resistor.

Claims

1. N amplifier blocks (N is an integer equal to or greater than 2); Each amplifier block is A first transmission line configured so that a signal is input to an input end thereof; a second transmission line configured to output a signal from an output end; a first termination resistor having one end connected to a termination of the first transmission line; a second termination resistor having one end connected to the input end of the second transmission line; a plurality of unit cells arranged along the first and second transmission lines, each unit cell having an input terminal connected to the first transmission line and an output terminal connected to the second transmission line; each amplifier block is connected in series such that an end of the second transmission line is connected to an input end of the first transmission line of the subsequent amplifier block; the other end of the first termination resistor of each amplifier block is connected to a first bias voltage, and the other end of the second termination resistor of each amplifier block is connected to ground; the characteristic impedance of the first transmission line of the first stage amplifier block, the first termination resistor of the first stage amplifier block, the second transmission line of the final stage amplifier block, and the second termination resistor of the final stage amplifier block are all 50Ω; a characteristic impedance of the second transmission line of the n-th amplifier block, the second termination resistance of the n-th amplifier block, the characteristic impedance of the first transmission line of the (n+1)-th amplifier block, and the first termination resistance of the (n+1)-th amplifier block are set to -Vb_(n+1) / (Iopt×Nopt), where Vb_(n+1) is the first bias voltage of an (n+1)-th stage (n is an integer from 1 to N-1), Nopt is the number of unit cells of each amplifier block, and Iopt is the current flowing between the input terminal and the output terminal of the unit cell of each amplifier block and at which the transistor of each unit cell operates.

2. 2. The distributed amplifier according to claim 1, Each unit cell is a first transistor having a base terminal connected to the first transmission line and an emitter terminal connected to a second power supply voltage; a second transistor having a base terminal connected to a second bias voltage, a collector terminal connected to the second transmission line, and an emitter terminal connected to the collector terminal of the first transistor.

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