Semiconductor device

Abstract

To provide a semiconductor device that can be miniaturized.SOLUTION: A semiconductor device comprises: a substrate; a first source finger 12a; a first gate finger 14a; a first drain finger 16a1; a second gate finger 14b; a second source finger 12b; a second drain finger 16a2; and a first gate wire 18b1 provided on the substrate so as to extend in a width direction, and connected with a first end of the first gate finger and not connected with the second gate finger. A width of the first gate wire in the extending direction at a first position where the first gate finger is connected with the first gate wire is smaller than that at a second position located between the first source finger and the second source finger. A second gate finger side end at the first position in the extending direction is located at a side closer to the first gate finger than the second gate finger side end at the second position in the extending direction.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device, for example, a semiconductor device having a field effect transistor.

Background Art

[0002] In a field effect transistor (FET) having a source, a gate, and a drain, it is known to arrange a plurality of unit FETs having source fingers, gate fingers, and drain fingers in the extending direction of the fingers (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In Patent Document 1, by arranging a plurality of unit FETs in the extending direction of the fingers, the gate fingers in the unit FET can be shortened. However, when the gate fingers of adjacent unit FETs in the extending direction are connected to the same gate wiring, the high-frequency characteristics may deteriorate. When one of the gate fingers of adjacent unit FETs is connected to the gate wiring and the other gate finger is not connected to the gate wiring, the interval between adjacent unit FETs cannot be reduced. For this reason, the semiconductor device becomes large-sized.

[0005] The present disclosure has been made in view of the above problems, and an object thereof is to provide a semiconductor device that can be miniaturized.

Means for Solving the Problems

[0006] One embodiment of the present disclosure includes a substrate, a first source finger provided on the substrate, a first gate finger provided on the substrate adjacent to the first source finger in the width direction and extending in the extending direction of the first source finger, a first drain finger provided on the substrate and sandwiching the first gate finger with the first source finger, a second source finger provided on the substrate in the extending direction of the first source finger and extending in the extending direction, a second gate finger provided on the substrate adjacent to the second source finger in the width direction and in the extending direction of the first gate finger and extending in the extending direction, a second drain finger provided on the substrate and sandwiching the second gate finger with the second source finger, and a first gate wiring provided on the substrate, connected to a first end of the first gate finger, not connected to the second gate finger, and extending in the width direction. The width of the first gate wiring in the extending direction at a first location where the first gate finger is connected to the first gate wiring is smaller than the width of the first gate wiring in the extending direction at a second location located between the first source finger and the second source finger. The second gate finger side end at the first location in the extending direction is located closer to the first gate finger side than the second gate finger side end at the second location in the extending direction. It is a semiconductor device.

Advantages of the Invention

[0007] According to the present disclosure, a semiconductor device that can be miniaturized can be provided.

Brief Description of the Drawings

[0008]

Figure 1

Figure 2

Figure 3

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Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

MODE FOR CARRYING OUT THE INVENTION

[0009] [Description of Embodiments of the Present Disclosure] First, the content of the embodiments of the present disclosure will be listed and described.

[0010] [Details of Embodiments of the Present Disclosure] First, the content of the embodiments of the present disclosure will be listed and described. (1) One embodiment of the present disclosure includes a substrate, a first source finger provided on the substrate, a first gate finger provided on the substrate adjacent to the first source finger in the width direction and extending in the extending direction of the first source finger, a first drain finger provided on the substrate and sandwiching the first gate finger with the first source finger, a second source finger provided on the substrate in the extending direction of the first source finger and extending in the extending direction, a second gate finger provided on the substrate in the extending direction of the first gate finger adjacent to the second source finger in the width direction and extending in the extending direction, a second drain finger provided on the substrate and sandwiching the second gate finger with the second source finger, and a first gate wiring provided on the substrate, connected to a first end of the first gate finger, not connected to the second gate finger, and extending in the width direction. The width of the first gate wiring in the extending direction at a first location where the first gate finger is connected to the first gate wiring is smaller than the width of the first gate wiring in the extending direction at a second location located between the first source finger and the second source finger. The side end of the first gate finger on the second gate finger side in the extending direction is located closer to the first gate finger side than the side end of the second gate finger on the second gate finger side in the extending direction. This can provide a semiconductor device that can be miniaturized. (2) Preferably, when viewed from the width direction, a part of the second gate finger and a part of the first gate wiring overlap. (3) Preferably, the width of the first gate wiring in the extending direction gradually increases from the first location toward the second location. (4) Preferably, it further includes a gate bus bar provided on the substrate to which the second gate finger is connected, and a second gate wiring that connects the first gate wiring and the gate bus bar and extends in the extending direction. (5) Preferably, the second gate wiring and the second gate finger sandwich the second source finger. (6) The width of the second source finger is preferably smaller than the width of the first source finger, and the width of the second gate wiring in the width direction preferably fits within the width of the first source finger. (7) It is preferable to include a via that penetrates the substrate and connects the first source finger and a metal layer provided under the substrate. (8) It is preferable to include a source wiring that connects the first source finger and the second source finger and intersects the first gate wiring without contact. (9) The substrate includes a first active region and a second active region where semiconductor layers in the substrate are activated and separated from each other, and an inactive region provided between the first active region and the second active region where the semiconductor layer is inactivated. The first source finger, the first gate finger, and the first drain finger are provided on the first active region, the second source finger, the second gate finger, and the second drain finger are provided on the second active region, and the first gate wiring is preferably provided on the inactive region. (10) A third gate finger provided on the substrate and sandwiching the first source finger with the first gate finger, a third drain finger provided on the substrate and sandwiching the third gate finger with the first source finger, a third source finger provided on the substrate, having a width smaller than the width of the first source finger, with the width in the width direction being within the width of the first source finger, provided on the same side as the second source finger with respect to the first source finger, and extending in the extending direction, a fourth gate finger provided on the substrate adjacent to the third source finger in the width direction and extending in the extending direction on the substrate in the extending direction of the third gate finger, a fourth drain finger provided on the substrate and sandwiching the fourth gate finger with the third source finger, and a third gate wiring provided on the substrate, connected to the first end of the third gate finger and not connected to the fourth gate finger and extending in the width direction, wherein the width of the third gate wiring in the extending direction at a third position where the third gate finger is connected to the third gate wiring is smaller than the width of the third gate wiring in the extending direction at a fourth position located between the first source finger and the third source finger, and it is preferable that the fourth gate finger side end at the third position in the extending direction is located closer to the third gate finger side than the fourth gate finger side end at the fourth position in the extending direction.

[0011] A specific example of a semiconductor device according to an embodiment of the present disclosure will be described below with reference to the drawings. Note that the present disclosure is not limited to these examples, and is defined by the claims, and is intended to include all modifications within the meaning and scope equivalent to the claims.

[0012] [Example 1] FIG. 1 is a plan view of a semiconductor device according to Example 1. FIGS. 2 to 5 are cross-sectional views taken along lines A-A to D-D of FIG. 1, respectively. The normal direction of the upper surface of the substrate 10 is the Z direction, the extending direction of each finger is the Y direction, and the width direction of each finger is the X direction.

[0013] As shown in FIGS. 1 to 5, the substrate 10 includes a substrate 10a and a semiconductor layer 10b provided on the substrate 10a. The region where the semiconductor layer 10b is inactivated by ion implantation or the like is the inactive region 11a, and the region that is not inactivated is the active region 11. On the substrate 10, source fingers 12a to 12c, gate fingers 14a to 14d, drain fingers 16a, 16b, gate wirings 18a, 18b1 and 18b2, a gate bus bar 22, and a drain bus bar 24 are provided.

[0014] The source fingers 12a to 12c, and the drain fingers 16a and 16b have an ohmic metal layer 40 provided on the active region 11 and a low-resistance layer 50 provided on the ohmic metal layer 40. The ohmic metal layer 40 makes an ohmic contact with the semiconductor layer 10b. The low-resistance layer 50 has a lower resistivity and is thicker than the ohmic metal layer 40. In the source fingers 12a to 12c, and the drain fingers 16a and 16b, the width of the ohmic metal layer 40 in the X direction and the Y direction may be larger than or the same as the width of the low-resistance layer 50 in the X direction and the Y direction. The source wiring 19b connects the source fingers 12a and 12b, and the source wiring 19c connects the source fingers 12a and 12c. The source wirings 19b and 19c are provided on the inactive region 11a, have the low-resistance layer 50, and do not have the ohmic metal layer 40. The portions of the drain fingers 16a and 16b on the inactive region 11a have the low-resistance layer 50 and do not have the ohmic metal layer 40.

[0015] The gate fingers 14a to 14d have a gate metal layer 45 provided on the active region 11 and do not have the low-resistance layer 50. The gate wiring 18b1 has the gate metal layer 45 provided on the inactive region 11a and does not have the low-resistance layer 50. The gate wiring 18a has the gate metal layer 45 and the low-resistance layer 50 provided on the semiconductor layer 10b. The low-resistance layer 50 has a lower resistivity and is thicker than the gate metal layer 45.

[0016] The source finger 12a extends in the Y direction and has a width W2a in the X direction and a length L2a in the Y direction. Source fingers 12b and 12c extend in the Y direction from both ends of the source finger 12a in the X direction. The source fingers 12b and 12c each have a width W2b in the X direction and a length L2b in the Y direction. A drain finger 16a extending in the Y direction is provided in the +X direction of the source fingers 12a and 12b. A drain finger 16b extending in the Y direction is provided in the -X direction of the source fingers 12a and 12c. The drain fingers 16a and 16b each have a width W6 in the X direction. Gate fingers 14a and 14b are provided between the source fingers 12a and 12b and the drain finger 16a, and gate fingers 14c and 14d are provided between the source fingers 12a and 12c and the drain finger 16b. The gate fingers 14a to 14d extend in the Y direction, and the width in the X direction corresponds to the gate length Lg.

[0017] A gate wiring 18a extending in the Y direction and having a width W8a in the X direction is provided between the source fingers 12a and 12c. Gate wirings 18b1 and 18b2 are provided between the gate fingers 14a and 14c and 14b and 14d. The gate wirings 18b1 and 18b2 have a width W8b in the Y direction and extend in the X direction, and connect the -Y direction ends of the gate fingers 14a and 14c and the +Y direction end of the gate wiring 18a respectively. The gate wirings 18b1 and 18b2 and the source wirings 19b and 19c cross each other via an insulating film 26 and are not electrically connected to each other. The -Y direction ends of the gate fingers 14b, 14d and the gate wiring 18a are connected to a gate bus bar 22. The +Y direction ends of the drain fingers 16a and 16b are connected to a drain bus bar 24. The source finger 12a is connected to a metal layer 28 provided under the substrate 10 via a via 20 penetrating the substrate 10. An insulating film 26 is provided to cover the source fingers 12a to 12c, the gate fingers 14a to 14d, the drain fingers 16a, 16b, the gate wirings 18a, 18b1 and 18b2.

[0018] The FET regions 30a and 30b are arranged in the Y direction. In the FET region 30a, the active region 11 including the source finger 12a extends in the X direction. The source finger 12a, the gate finger 14a, and the drain finger 16a form a unit FET 32a, and the source finger 12a, the gate finger 14c, and the drain finger 16b form a unit FET 32c. The gate width Wga of the unit FETs 32a and 32c corresponds to the length in the Y direction of the active region 11 including the source finger 12a. The source potential of the unit FETs 32a and 32c is supplied from the metal layer 28 to the source finger 12a via the via 20. The gate potential (and the gate signal) is supplied from the gate bus bar 22 to the gate fingers 14a and 14c via the gate wirings 18a, 18b1, and 18b2. The drain potential is supplied from the drain bus bar 24 to the drain fingers 16a and 16b. The unit FETs 32a and 32c are alternately arranged in the X direction.

[0019] In the FET region 30b, the active region 11 is provided except for the gate wiring 18a. The source finger 12b, the gate finger 14b, and the drain finger 16a form a unit FET 32b, and the source finger 12c, the gate finger 14d, and the drain finger 16b form a unit FET 32d. The gate width Wgb of the unit FETs 32b and 32d corresponds to the length in the Y direction within the active region 11 including the source fingers 12b and 12c. The source potential of the unit FETs 32b and 32d is supplied from the metal layer 28 to the source fingers 12b and 12c via the via 20 and the source finger 12a. The gate potential (and the gate signal) is supplied from the gate bus bar 22 to the gate fingers 14b and 14d. The drain potential is supplied from the drain bus bar 24 to the drain fingers 16a and 16b. The unit FETs 32b and 32d are alternately arranged in the X direction. When increasing the overall gate width of the semiconductor device, a plurality of the unit FETs 32a to 32d are arranged in the X direction.

[0020] FIG. 6 is a plan view showing an active region 11b, 11c1, 11c2, an ohmic metal layer 40, and a gate metal layer 45 in the semiconductor device according to Embodiment 1. As shown in FIG. 6, an active region 11b is provided in the FET region 30a of the substrate 10, and active regions 11c1 and 11c2 are provided in the FET region 30b. On the active region 11b, source fingers 12a, drain fingers 16a1 and 16b1 are provided by the ohmic metal layer 40, and gate fingers 14a and 14c are provided by the gate metal layer 45. On the active region 11c1, source fingers 12b and drain fingers 16a2 are formed by the ohmic metal layer 40, and a gate finger 14b is formed by the gate metal layer 45. On the active region 11c2, source fingers 12c and drain fingers 16b2 are formed by the ohmic metal layer 40, and a gate finger 14d is formed by the gate metal layer 45. The drain fingers 16a1 and 16a2 are connected by a low resistance layer 50 to form the drain finger 16a in FIG. 1. The drain fingers 16b1 and 16b2 are connected by a low resistance layer 50 to form the drain finger 16b in FIG. 1.

[0021] In the unit FET 32a, the gate finger 14a (first gate finger) is provided adjacent to the source finger 12a (first source finger) in the X direction (width direction). The drain finger 16a1 (first drain finger) and the source finger 12a sandwich the gate finger 14a. In the unit FET 32b, the source finger 12b (second source finger) is provided in the -Y direction of the source finger 12a. The gate finger 14b (second gate finger) is provided adjacent to the source finger 12b in the X direction and in the -Y direction of the gate finger 14a. The drain finger 16a2 (second drain finger) and the source finger 12b sandwich the gate finger 14b. The gate wiring 18b1 (first gate wiring) is connected to the first end (-Y side end) of the gate finger 14a and is not connected to the gate finger 14b and extends in the X direction.

[0022] In the unit FET 32c, the gate finger 14c (the third gate finger) sandwiches the source finger 12a with the gate finger 14a. The drain finger 16b1 (the third drain finger) sandwiches the gate finger 14c with the source finger 12a. In the unit FET 32d, the source finger 12c (the third source finger) is provided on the same side as the source finger 12b with respect to the source finger 12a. The gate finger 14d (the fourth gate finger) is provided in the -Y direction of the gate finger 14c adjacent to the source finger 12c in the X direction. The drain finger 16b2 (the fourth drain finger) sandwiches the gate finger 14d with the source finger 12c. The gate wiring 18b2 (the third gate wiring) is connected to the first end (-Y side end) of the gate finger 14c and is not connected to the gate finger 14d and extends in the X direction.

[0023] The gate wiring 18b1 is provided on the inactive region 11a between the active regions 11b and 11c1. The gate wiring 18b2 is provided on the inactive region 11a between the active regions 11b and 11c2. The gate wiring 18a is provided on the inactive region 11a between the active regions 11c1 and 11c2. The first ends (-Y side ends) of the gate fingers 14b, 14c and the gate wiring 18a are connected to the gate bus bar 22. The gate wiring 18b1 connects the gate finger 14a and the gate wiring 18a. The gate wiring 18b2 connects the gate finger 14c and the gate wiring 18a. The second ends (+Y side ends) of the gate fingers 14b and 14d are not connected to the gate wirings 18b1 and 18b2.

[0024] When the semiconductor device is, for example, a nitride semiconductor device, the substrate 10a is, for example, a SiC substrate, a silicon substrate, a GaN substrate, or a sapphire substrate. The semiconductor layer 10b includes nitride semiconductor layers such as, for example, a GaN layer, an AlGaN layer, and / or an InGaN layer. When the semiconductor device is, for example, a GaAs-based semiconductor device, the substrate 10a is, for example, a GaAs substrate. The semiconductor layer 10b includes arsenide semiconductor layers such as, for example, a GaAs layer, an AlGaAs layer, and / or an InGaAs layer. The ohmic metal layer 40 is a metal film, and is, for example, an adhesion film (for example, a titanium film) and an aluminum film from the side of the substrate 10. The gate metal layer 45 is a metal film, and is, for example, an adhesion film (for example, a nickel film) and a gold film from the side of the substrate 10. The low-resistance layer 50 is a metal layer, and is, for example, a barrier layer (for example, a titanium tungsten film) and a gold film. The source fingers 12a to 12c and the drain fingers 16a and 16b may not include the low-resistance layer 50. The gate wiring 18a may not include the gate metal layer 45. The gate bus bar 22 may have the gate metal layer 45 and the low-resistance layer 50, or may have the low-resistance layer 50 and not have the gate metal layer 45. The drain bus bar 24 may have the ohmic metal layer 40 and the low-resistance layer 50, or may have the low-resistance layer 50 and not have the ohmic metal layer 40. The via 20 and the metal layer 28 are, for example, an adhesion layer and a gold layer from the side of the substrate 10. The insulating film 26 is, for example, a silicon nitride film.

[0025] The width W2a of the source finger 12a in the X direction is, for example, 50 μm to 100 μm, and the length L2a in the Y direction is, for example, 100 μm to 400 μm. The width W2b of the source fingers 12b and 12c in the X direction is, for example, 5 μm to 20 μm, and the length L2b in the Y direction is, for example, 110 μm to 410 μm. The gate length Lg of the gate fingers 14a to 14d in the X direction is, for example, 0.25 μm to 2 μm. The width W6 of the drain fingers 16a and 16b in the X direction is, for example, 5 μm to 100 μm. The width W8a of the gate wiring 18a is, for example, 5 μm to 20 μm. The width W8b of the gate wirings 18b1 and 18b2 is, for example, 5 μm to 20 μm. The gate width Wga of the unit FETs 32a and 32c is, for example, 100 μm to 400 μm, and the gate width Wgb of the unit FETs 32b and 32d is, for example, 100 μm to 400 μm. The width W20 of the via 20 is, for example, 10 μm to 60 μm.

[0026] FIG. 7 is an enlarged plan view of the semiconductor device according to Example 1. As shown in FIG. 7, the width W8c in the Y direction of the gate wiring 18b1 at the first location where the gate finger 14a is connected to the gate wiring 18b1 is smaller than the width W8d in the Y direction of the gate wiring 18b1 at the second location between the source fingers 12a and 12b. The width of the gate wiring 18b1 in the Y direction linearly increases as going in the -X direction. The distance that the gate finger 14b protrudes from the active region 11c1 is L4a, the distance in the Y direction between the gate finger 14b and the gate wiring 18b1 is L8a, and the shortest distance between the gate finger 14b and the gate wiring 18b1 is L8b. The width W8c is, for example, 1 μm to 5 μm, and the width W8d is, for example, 5 μm to 20 μm. The distance L4a is, for example, 1 μm to 10 μm, and the distances L8a and L8b are, for example, 5 μm to 20 μm.

[0027] FIG. 8 is an enlarged plan view of the semiconductor device according to Comparative Example 1. As shown in FIG. 8, in Comparative Example 1, the planar shape of the gate wiring 18b1 is rectangular. The width of the gate wiring 18b1 is W8b, the distance that the gate fin 14b protrudes from the active region 11c1 is L4a, and the distance in the Y direction between the gate fin 14b and the gate wiring 18b1 is L8c.

[0028] In FIGS. 1 and 6, when a high-frequency signal is input to the gate bus bar 22, the high-frequency signal is supplied from the gate bus bar 22 to the gate fins 14b and 14d. Further, the high-frequency signal is supplied from the gate bus bar 22 to the gate fins 14a and 14c via the gate wirings 18a, 18b1, and 18b2, respectively. When the gate wirings 18b1 and 18b2 are connected to the gate fins 14b and 14d, high-frequency signals are supplied from the gate wirings 18b1 and 18b2 to the gate fins 14b and 14d, respectively. As a result, the phases of the high-frequency signals supplied from the gate bus bar 22 and the high-frequency signals supplied from the gate wirings 18b1 and 18b2 to the gate fins 14b and 14d are different. For this reason, an increase in loss or the like occurs and the high-frequency characteristics deteriorate.

[0029] In Comparative Example 1, the gate wirings 18b1 and 18b2 are not connected to the gate fingers 14b and 14d. As a result, high-frequency signals are not supplied from the gate wirings 18b1 and 18b2 to the gate fingers 14b and 14d respectively. Therefore, deterioration of high-frequency characteristics can be suppressed. Also, the first ends (-Y side ends) of the gate fingers 14b and 14d are connected to the gate bus bar 22, and the second ends (+Y side ends) are separated from the gate wirings 18b1 and 18b2. As a result, a phase difference occurs between the gate signal supplied from the gate bus bar 22 to the gate fingers 14b and 14d and the gate signal supplied from the gate wirings 18a, 18b1 and 18b2 to the gate fingers 14a and 14c. However, the gate signal is supplied to the gate fingers 14a to 14d from the same -Y direction, and signals are output from the drain fingers 16a and 16b in the +Y direction. Thereby, loss due to the phase difference can be suppressed. Therefore, the high-frequency characteristics can be improved.

[0030] The gate finger 14b protrudes from the active region 11c1 by a distance L4a. When the gate wiring 18b1 and the gate finger 14b approach each other, the high-frequency signal transmitted through the gate wiring 18b1 leaks to the gate finger 14b, resulting in deterioration of high-frequency characteristics. To suppress this, the gate wiring 18b1 and the gate finger 14b are separated by a distance L8c. The gate wiring 18b1 and the active region 11c1 are separated by a distance L4a + L8c. As a result, the substrate 10 becomes larger.

[0031] According to Example 1, as shown in FIG. 7, the width W8c of the gate wiring 18b1 in the Y direction at the first location where the gate finger 14a is connected to the gate wiring 18b1 is smaller than the width W8d of the gate wiring 18b1 in the Y direction at the second location located between the source fingers 12a and 12b. The gate finger 14b side (-Y side) end Y1 in the Y direction of the first location is located closer to the gate finger 14a side (+Y side) than the gate finger 14b side (-Y side) end Y2 in the Y direction of the second location. Thereby, even if the distances L8a and L8b between the gate wiring 18b1 and the gate finger 14b are secured to be approximately the same as the distance L8c in Comparative Example 1, the active region 11c1 can be brought closer to the gate wiring 18b1. Therefore, the area of the substrate 10 can be reduced, and the semiconductor device can be miniaturized. Further, when the areas of the substrate 10 in Comparative Example 1 and Example 1 are the same, in Example 1, the width Wgb of the active region 11c1 in the Y direction can be made larger than that in Comparative Example 1. Therefore, the output can be increased. From the viewpoint of miniaturization, the width W8c is preferably 2 / 3 or less of the width W8d, and more preferably 1 / 2 or less. From the viewpoint of reducing the resistance of the gate wiring 18b1, the width W8c is preferably 1 / 10 or more of the width W8d.

[0032] In Comparative Example 1, it is also conceivable to reduce the width W8b. However, when the width W8b is reduced, the resistance of the gate wiring 18b1 increases, and the high-frequency characteristics deteriorate. In Example 1, since the width W8d of the gate wiring 18b1 can be increased, the resistance of the gate wiring 18b1 can be reduced, and the deterioration of the high-frequency characteristics can be suppressed.

[0033] Also, when viewed from the X direction, a part of the gate finger 14b and a part of the gate wiring 18b1 overlap. That is, the +Y side end of the gate finger 14b is located between Y1 and Y2. Thereby, the active region 11c1 can be brought closer to the gate wiring 18b1. Therefore, the semiconductor device can be further miniaturized.

[0034] As shown in FIGS. 1 and 6, gate fingers 14b and 14d are connected to the gate bus bar 22. The gate wiring 18a (second gate wiring) connects the gate wirings 18b1 and 18b2 to the gate bus bar 22. In this case, when the gate finger 14b is connected to the gate wiring 18b1, the high-frequency characteristics deteriorate. Therefore, if the gate finger 14b and the gate wiring 18b1 are separated, as in Comparative Example 1, the semiconductor device becomes larger. Thus, as shown in FIG. 7, it is preferable that the width W8c of the gate wiring 18b1 is smaller than the width W8d.

[0035] As shown in FIGS. 1 and 6, the gate wiring 18a and the gate finger 14b sandwich the source finger 12b. Thereby, in a plan view, the gate wiring 18a and the source finger 12b do not overlap in the plan view. For this reason, the gate-source capacitance can be suppressed and the high-frequency characteristics can be improved.

[0036] There may be a design in which the width W2a of the source finger 12a in the X direction is widened. For example, by supplying a source potential to the source finger 12a through the via 20, the source inductance can be reduced. However, the width W2a of the source finger 12a becomes wider. On the other hand, the width W2b for supplying the source potential in the Y direction of the source fingers 12b and 12c does not have to be as wide as the width W2a. Thus, as shown in FIG. 1, the width W2b of the source finger 12b is smaller than the width W2a of the source finger 12a, and the width W8a in the X direction of the gate wiring 18a is within the width W2a of the source finger 12a. That is, when viewed from the Y direction, the gate wiring 18a, the source fingers 12b and 12c overlap the source finger 12a and do not overlap the regions other than the source finger 12a. Thereby, even if the gate wiring 18a is provided, the width of the semiconductor device in the X direction can be suppressed. Therefore, the semiconductor device can be miniaturized.

[0037] The via 20 penetrates the substrate 10 and connects the source finger 12a and the metal layer 28 provided under the substrate 10. In this way, when the via 20 is directly connected to the source finger 12a, the width W2a of the source finger 12a becomes wider. Therefore, the gate wiring 18a can be provided between the source fingers 12b and 12c.

[0038] The source wiring 19b connects the source fingers 12a and 12b and intersects the gate wiring 18b1 without contact. As a result, the source fingers 12a and 12b are electrically connected, and a high-frequency signal can be supplied from the gate wiring 18b1 to the gate finger 14a.

[0039] The semiconductor layer 10b in the substrate 10 is activated to form mutually separated active regions 11b (first active region) and 11c1 (second active region), and an inactive region 11a provided between the active regions 11b and 11c1 where the semiconductor layer 10b is inactivated is provided. The source finger 12a, the gate finger 14a, and the drain finger 16a1 are provided on the active region 11b. The source finger 12b, the gate finger 14b, and the drain finger 16a2 are provided on the active region 11c1. The gate wiring 18b1 is provided on the inactive region 11a. Thereby, the gate-source capacitance due to the gate wiring 18b1 can be reduced, and the high-frequency characteristics can be improved.

[0040] As shown in FIG. 6, also in the FETs 32c and 32d, the width of the gate wiring 18b2 in the Y direction at the third location where the gate finger 14c is connected to the gate wiring 18b2 is smaller than the width of the gate wiring 18b2 in the Y direction at the fourth location located between the source finger 12a and the source finger 12c. The gate finger 14d side (-Y side) end at the third location in the Y direction is located closer to the gate finger 14c side (+Y side) than the gate finger 14d side (-Y side) end at the fourth location in the Y direction. Thereby, the semiconductor device can be miniaturized.

[0041] [Modification Example 1 of Example 1] FIG. 9 is an enlarged plan view of a semiconductor device according to Modification 1 of Example 1. As shown in FIG. 9, among the gate wirings 18b1, the width W8c in the Y direction of the +X side portion is constant, and the width W8c in the Y direction of the -X side portion is constant. The distance in the X direction between the gate fin 14b and the gate wiring 18b1 is L8d. The same applies to the gate wiring 18b2. Other configurations are the same as those in Example 1 and the description thereof is omitted. Also in Modification 1 of Example 1, by setting the distance L8d to be approximately the same as the distance L8a, leakage of high-frequency signals from the gate wiring 18b1 to the gate fin 14b can be suppressed. Moreover, the semiconductor device can be miniaturized.

[0042] [Modification 2 of Example 1] FIG. 10 is an enlarged plan view of a semiconductor device according to Modification 2 of Example 1. As shown in FIG. 10, the width of the gate wiring 18b1 gradually increases in a curved manner as it goes from the first location where the gate fin 14a is connected to the gate wiring 18b1 in the -X direction. The -Y side edge of the gate wiring 18b1 is a substantially circular outer periphery centered on the +Y side end of the gate fin 14b. As a result, the shortest distance L8b between the gate fin 14b and the gate wiring 18b1 is substantially the same as the distances L8a and L8d. The same applies to the gate wiring 18b2. Other configurations are the same as those in Example 1 and the description thereof is omitted.

[0043] Like in Example 1 and Modification 1 thereof, the gate wiring 18b1 gradually increases in width in the Y direction as it goes from the first location to the second location. Thereby, the area of the gate wiring 18b1 can be increased and the gate resistance can be suppressed. Like in Modification 2 of Example 1, the -Y side edge of the gate wiring 18b1 is a substantially circular outer periphery centered on the +Y side end of the gate fin 14b. Thereby, the area of the gate wiring 18b1 can be further increased and the gate resistance can be further suppressed.

[0044] [Example 2] FIG. 11 is a plan view showing an active region, an ohmic metal layer, and a gate metal layer in the semiconductor device according to Embodiment 2. As shown in FIG. 11, in Embodiment 2, active regions 11c1 and 11c2 (see FIG. 6) are integrated to form an active region 11c. Source fingers 12b and 12c (see FIG. 6) are integrated to form a source finger 12bc. The width of the source finger 12bc in the X direction is substantially the same as the width of the source finger 12a in the X direction. The active region 11c extends in a strip shape in the X direction. The gate wiring 18a is formed of a low-resistance layer 50 and is provided above the source finger 12bc with an insulating film 26 interposed therebetween. Other configurations are the same as those in Embodiment 1 and the description thereof is omitted.

[0045] As in Embodiment 2, in a plan view, the gate wiring 18a may overlap the source finger 12bc. In Embodiment 2, the gate-source capacitance becomes large. Therefore, as in Embodiment 1, it is preferable that the gate wiring 18a does not overlap the source fingers 12b and 12c in a plan view.

[0046] In Embodiments 1 and 2 and their modified examples, an example in which four unit FETs are arranged in the X direction has been described. However, the number of unit FETs in the X direction may be one, or may be two, three, or five or more. Four unit FETs arranged in the X direction may be regarded as one group, and a plurality of groups may be arranged in the X direction. An example in which one via 20 is provided for one source finger 12a has been described, but a plurality of vias 20 may be provided for one source finger 12a.

[0047] It should be considered that the embodiments disclosed this time are illustrative in all respects and not restrictive. The scope of the present disclosure is shown not by the above meaning but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims are included.

Description of Reference Numerals

[0048] 10, 10a Substrate 10b Semiconductor layer 11. 11c2 active region 11a inactive region 11b active region (first active region) 11c1 active region (second active region) 12a - 12c source fingers (first - third source fingers) 12bc source finger 14a - 14d gate fingers (first - fourth gate fingers) 16a, 16b drain fingers 16a1, 16a2, 16b1, 16b2 drain fingers (first - fourth drain fingers) 18a gate wiring (second gate wiring) 18b1 gate wiring (first gate wiring) 18b2 gate wiring (third gate wiring) 19b source wiring (first source wiring) 19c source wiring (second source wiring) 20 via 22 gate bus bar 24 drain bus bar 26 insulating film 28 metal layer 30a - 30b FET region 32a - 32d unit FET 40 ohmic metal layer 45 gate metal layer 50 low - resistance layer

Claims

1. A substrate, a first source finger provided on the substrate, a first gate finger provided along the first source finger on the substrate adjacent to the first source finger in the width direction, a first drain finger provided on the substrate and sandwiching the first gate finger with the first source finger, a second source finger provided on a region of the substrate located in the extending direction in which the first source finger extends from the first source finger and extending in the extending direction, a second gate finger provided along the second source finger on a region of the substrate located in the extending direction from the first gate finger adjacent to the second source finger in the width direction, a second drain finger provided on the substrate and sandwiching the second gate finger with the second source finger, a first gate wiring provided on the substrate, connected to a first end of the first gate finger, not connected to the second gate finger, and extending in the width direction, comprising, the width of the first gate wiring in the extending direction at a first location where the first gate finger is connected to the first gate wiring is smaller than the width of the first gate wiring in the extending direction at a second location located between the first source finger and the second source finger, a semiconductor device in which a side end of the second gate finger on the second gate finger side in the extending direction is located closer to the first gate finger side than a side end of the second gate finger on the second gate finger side at the second location in the extending direction.

2. The semiconductor device according to claim 1, wherein a part of the second gate finger and a part of the first gate wiring overlap when viewed from the width direction.

3. The semiconductor device according to claim 1 or claim 2, wherein the width of the first gate wiring in the extending direction gradually increases from the first location toward the second location.

4. a gate bus bar provided on the substrate to which the second gate finger is connected, a second gate wiring connecting the first gate wiring and the gate bus bar and extending in the extending direction, The semiconductor device according to any one of claims 1 to 3, comprising.

5. The semiconductor device according to claim 4, wherein the second gate wiring and the second gate finger sandwich the second source finger.

6. The width of the second source finger is smaller than the width of the first source finger, The semiconductor device according to claim 5, wherein the width of the second gate wiring in the width direction is within the width of the first source finger.

7. The semiconductor device according to claim 6, further comprising a via that penetrates the substrate and connects the first source finger and a metal layer provided under the substrate.

8. The semiconductor device according to any one of claims 1 to 7, further comprising a source wiring that connects the first source finger and the second source finger and intersects the first gate wiring without contact.

9. The substrate includes a first active region and a second active region in which semiconductor layers in the substrate are activated and separated from each other, and an inactive region provided between the first active region and the second active region in which the semiconductor layer is inactivated. The first source finger, the first gate finger, and the first drain finger are provided on the first active region. The second source finger, the second gate finger, and the second drain finger are provided on the second active region. The semiconductor device according to any one of claims 1 to 8, wherein the first gate wiring is provided on the inactive region.

10. A third gate finger provided along the first source finger on the substrate adjacent to the width direction of the first source finger and sandwiching the first source finger with the first gate finger. A third drain finger provided on the substrate and sandwiching the third gate finger with the first source finger. A third source finger provided on the substrate, having a width smaller than the width of the first source finger, the width in the width direction being within the width of the first source finger, provided on the same side as the second source finger with respect to the first source finger, and extending in the extending direction. A fourth gate finger provided along the third source finger on a region of the substrate located in the extending direction from the third gate finger adjacent to the width direction of the third source finger. A fourth drain finger provided on the substrate and sandwiching the fourth gate finger with the third source finger. A third gate wiring provided on the substrate, connected to a first end of the third gate finger, not connected to the fourth gate finger, and extending in the width direction. Comprising. The width of the third gate wiring in the extending direction at a third location where the third gate finger is connected to the third gate wiring is smaller than the width of the third gate wiring in the extending direction at a fourth location located between the first source finger and the third source finger. The semiconductor device according to claim 8 or claim 9, wherein a fourth gate finger side end at the third location in the extending direction is located closer to the third gate finger side than a fourth gate finger side end at the fourth location in the extending direction.

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