Semiconductor device

Abstract

To provide a semiconductor device that can realize an off state without increasing power consumption.SOLUTION: A semiconductor device 100 includes a power element 110 which is in an on state when voltage is not applied to a gate, a switching field-effect transistor 102 for applying first voltage generated by a high voltage generation source 108 to the gate of the power element, and a switching field-effect transistor 103 for applying voltage that is generated by a low voltage generation source 109 lower than the first voltage and charged to a capacitive element 105 to the gate of the power element. The switching field-effect transistor 102 has small off-state current and is the enhancement type.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor device. Or a method for driving a semiconductor device. Or an electronic device including a semiconductor device. In addition, in this specification and the like, the semiconductor device generally refers to all devices that can function by utilizing semiconductor characteristics. For example, a power device, a display device having the power device, and an integrated circuit are included in the semiconductor device.

[0002] In addition, in this specification and the like, the semiconductor device generally refers to all devices that can function by utilizing semiconductor characteristics. For example, a power device, a display device having the power device, and an integrated circuit are included in the semiconductor device.

Background Art

[0003]

[0004]

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] There is an HFET (heterojunction field effect transistor) as a power device using GaN. The HFET has a structure in which an AlN layer, a GaN layer, and an AlGaN layer, which are buffer layers, are stacked on a SiC substrate, and a source electrode, a gate electrode, and a drain electrode are provided on the AlGaN layer. ​​It has. Also, due to the difference in the band gaps of the GaN layer and the AlGaN layer, a two-dimensional electron gas layer with a high concentration is formed at the interface between the GaN layer and the AlGaN layer. Since the conduction band of the two-dimensional electron gas layer has an energy level lower than the Fermi level, in the HFET, the two-dimensional electron gas layer becomes the channel, and a current flows even when no voltage is applied to the gate, resulting in a normally-on state, which causes problems as the drive circuit and protection circuit become complicated. To simply reduce the electron concentration to make the power device normally-off, the resistance of the device increases this time, so it is very difficult to achieve both normally-off and low resistance. Attempts have also been made to devise the device structure to achieve normally-off, but there are problems such as the device structure becoming complicated and the manufacturing cost increasing. and a two-dimensional electron gas layer with a high concentration is formed at the interface between the AlGaN layer. The conduction band of the two-dimensional electron gas layer has an energy level lower than the Fermi level. Therefore, in the HFET, the two-dimensional electron gas layer becomes the channel, and a current flows even when no voltage is applied to the gate, resulting in a normally-on state, which causes problems as the drive circuit and protection circuit become complicated. and a normally-on state where current flows even without applying a voltage to the gate, which has become a problem because the drive circuit and protection circuit become complicated. When simply reducing the electron concentration to make the power device normally-off, the resistance of the device increases this time, so it is very difficult to achieve both normally-off and low resistance. Attempts have also been made to devise the device structure to achieve normally-off, but there are problems such as the device structure becoming complicated and the manufacturing cost increasing. Therefore, an object of one embodiment of the present invention is to provide a semiconductor device that can realize an off state without causing an increase in power consumption.

Means for Solving the Problems

[0006] a switching field effect transistor for applying a first voltage to the gate of the power device, and a switching field effect transistor for applying a voltage lower than the first voltage to the gate of the power device, and the switching field effect transistor is a semiconductor device with a small off-current.

Means for Solving the Problems

[0007] One embodiment of the present invention includes a power device that is in an on state when no voltage is applied to the gate, a switching field effect transistor for applying a first voltage to the gate of the power device, and a switching field effect transistor for applying a voltage lower than the first voltage to the gate of the power device, and the switching field effect transistor is a semiconductor device with a small off-current. The switching field effect transistor is a semiconductor device formed of an oxide semiconductor layer in which the channel region is i-type or substantially i-type. With the switching field effect transistor, a high potential is applied to the gate of the power device. a semiconductor device formed of an oxide semiconductor layer in which the channel region is i-type or substantially i-type. By the switching field effect transistor, a high potential is applied to the gate of the power device. Alternatively, a high potential or a low potential is applied to obtain the on-state and off-state of the power device.

[0008] One embodiment of the present invention is a power MOSFET formed of an oxide semiconductor layer having a first gate and a second gate and having an n-type channel region, a field-effect transistor for switching for applying a positive voltage to the first gate and the second gate of the power MOSFET, and a field-effect transistor for switching for applying a negative voltage to the first gate and the second gate of the power MOSFET. The nodes of the first gate and the second gate of the power MOSFET are connected to the field-effect transistor for switching, and the channel region of the field-effect transistor for switching is formed of an oxide semiconductor layer that is i-type or substantially i-type. The semiconductor device is obtained. By the field-effect transistor for switching, a high potential or a low potential is applied to the first gate and the second gate of the power MOSFET to obtain the on-state and off-state of the power MOSFET. One embodiment of the present invention also includes a first field-effect transistor connected to a high-voltage power source, a second field-effect transistor connected to the first field-effect transistor, a third field-effect transistor connected to the second field-effect transistor and also connected to a low-voltage power source, a capacitive element connected to the second field-effect transistor and the third field-effect transistor, and a power MOSFET connected to the first field-effect transistor and the second field-effect transistor. The power MOSFET includes a first gate and a second gate, a first insulating layer in contact with the first gate, a second insulating layer in contact with the second gate, and the first insulating layer and the second insulating layer. and a second insulating layer in contact with the second gate, and a power MOSFET having a first insulating layer and a second insulating layer, wherein the power MOSFET has a first gate and a second gate, a first insulating layer in contact with the first gate, a second insulating layer in contact with the second gate, and the first insulating layer and the second insulating layer. A power MOSFET having a first gate and a second gate, a first insulating layer in contact with the first gate, a second insulating layer in contact with the second gate, and a first insulating layer and a second insulating layer. A power MOSFET having a first gate and a second gate, a first insulating layer in contact with the first gate, a second insulating layer in contact with the second gate, and a first insulating layer and a second insulating layer. The nodes of the first gate and the second gate of the power MOSFET are connected to the field-effect transistor for switching, and the channel region of the field-effect transistor for switching is formed of an oxide semiconductor layer that is i-type or substantially i-type. The semiconductor device is formed of an oxide semiconductor layer in which the channel region of the field-effect transistor for switching is i-type or substantially i-type. By the field-effect transistor for switching, a high potential or a low potential is applied to the first gate and the second gate of the power MOSFET to obtain the on-state and off-state of the power MOSFET. The semiconductor device is formed of an oxide semiconductor layer in which the channel region of the field-effect transistor for switching is i-type or substantially i-type. By the field-effect transistor for switching, a high potential or a low potential is applied to the first gate and the second gate of the power MOSFET to obtain the on-state and off-state of the power MOSFET. A high potential or a low potential is applied to the first gate and the second gate of the power MOSFET to obtain the on-state and off-state of the power MOSFET. A high potential or a low potential is applied to the first gate and the second gate of the power MOSFET to obtain the on-state and off-state of the power MOSFET.

[0009] One embodiment of the present invention further includes a first field-effect transistor connected to a high-voltage power source, a second field-effect transistor connected to the first field-effect transistor, a third field-effect transistor connected to the second field-effect transistor and also connected to a low-voltage power source, a capacitive element connected to the second field-effect transistor and the third field-effect transistor, and a power MOSFET connected to the first field-effect transistor and the second field-effect transistor. The power MOSFET has a first gate and a second gate, a first insulating layer in contact with the first gate, a second insulating layer in contact with the second gate, and a first insulating layer and a second insulating layer. A third field-effect transistor connected to the second field-effect transistor and also connected to a low-voltage power source, a capacitive element connected to the second field-effect transistor and the third field-effect transistor, and a power MOSFET connected to the first field-effect transistor and the second field-effect transistor. A capacitive element connected to the second field-effect transistor and the third field-effect transistor, and a power MOSFET connected to the first field-effect transistor and the second field-effect transistor. A power MOSFET connected to the first field-effect transistor and the second field-effect transistor. The power MOSFET has a first gate and a second gate, a first insulating layer in contact with the first gate, a second insulating layer in contact with the second gate, and a first insulating layer and a second insulating layer. A first insulating layer in contact with the first gate, a second insulating layer in contact with the second gate, and a first insulating layer and a second insulating layer. An oxide semiconductor layer formed therebetween, a first terminal and a second terminal serving as a source region and a drain region in contact with the oxide semiconductor layer, and the gates of the first gate and the second gate are connected to a first field effect transistor and a second field effect transistor, and the channel formation regions of the first field effect transistor to the third field effect transistor are formed of an i-type oxide semiconductor layer. The oxide semiconductor layer of the power MOSFET is an n-type semiconductor device. The carrier concentration of the oxide semiconductor layer of the power MOSFET is 1×10 cm or more and 1×1

[0010] 0 -3 , 14 cm -3 or less, preferably 1×10 0 20 cm -3 or more and 1×10 17 cm -3 or more and 1×10 20 cm -3 or less. It exists.

[0011] For the field effect transistor for switching, the carrier concentration of the oxide semiconductor layer of the first field effect transistor to the third field effect transistor is less than 5×10 cm 14 cm -3 It is less than.

[0012] The first gate or the second gate of the power MOSFET may overlap with one of the first terminal and the second terminal and may not overlap with the other. It doesn't have to overlap with the other.

Advantages of the Invention

[0013] According to one aspect of the present invention, it is possible to provide a power device that can achieve an off state without causing an increase in power consumption and a semiconductor device having the same. It can be provided.

Brief Description of the Drawings

[0014]

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Embodiments for Carrying Out the Invention

[0015] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention can be implemented in many different modes, and it will be easily understood by those skilled in the art that the form and details thereof can be variously changed without departing from the spirit and scope of the present invention. Therefore, it should not be construed as being limited to the description of the present embodiment. In the configuration of the present invention described below, the same reference numerals denote the same objects among different drawings.

[0016] In addition, in the drawings and the like of each embodiment, the size, layer thickness, or area of each component shown may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0017] Also, the terms first, second, third, up to N (N is a natural number) used in this specification are attached to avoid confusion of components, and it is noted that they are not numerically limiting.

[0018] Also, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential). Therefore, it is possible to rephrase voltage, potential, and potential difference as potential, voltage, and voltage difference, respectively.

[0019] Also, when it is explicitly described that A and B are connected, it includes the case where A and B are electrically connected, the case where A and B are functionally connected, and the case where A and B are directly connected. Here, A and B are assumed to be objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive layers, layers, etc.). Therefore, a predetermined connection relationship ​​​​For example, it is not limited to the connection relationship shown in the figure or the text, and it shall also include those other than the connection relationship shown in the figure or the text. The connection relationship other than that shown in the figure or the text is also included.

[0020] (Embodiment 1) In this embodiment, the circuit configuration and operation of a semiconductor device which is a power device will be described.

[0021] The semiconductor device shown in FIG. 1 has a power element 110 and a control circuit 100. The control circuit 10 0 has a field effect transistor 102 (also referred to as the first transistor), a field effect transistor 103 (also referred to as the second transistor), a field effect transistor 104 (also referred to as the third transistor), a capacitive element 105, an overvoltage detection circuit 106, a refresh control circuit 107, a high voltage power source 108, and a low voltage power source 109.

[0022] The control circuit 100 switches the voltage applied to the power element 110 to a high voltage generated by the high voltage power source 108 or a low voltage generated by the low voltage power source 109, and controls the amount of current flowing through the power element 110 when an overvoltage is applied between the input terminal I N and the output terminal OUT.

[0023] The gate of the field effect transistor 102 is connected to the overvoltage detection circuit 106, the first terminal is connected to the high voltage power source 108, and the second terminal is connected to the power element 110. The field effect transistor 102 controls the application of a high potential to the power element 110 connected to the second terminal.

[0024] The gate of the field effect transistor 103 is connected to the overvoltage detection circuit 106, the first terminal is connected to the second terminals of the capacitive element 105 and the field effect transistor 104, and the second terminal is connected to the power element 110.

[0025] The field effect transistor 103 controls applying the low potential charged to the capacitive element 105 from the low voltage generation source 109 to the power element 110 connected to the second terminal. The off-current described in this specification refers to the current flowing between the source and the drain, that is, between the first terminal and the second terminal, when the field effect transistor is non-conductive.

[0026] Note that the off-current described in this specification refers to the current flowing between the source and the drain, that is, between the first terminal and the second terminal, when the field effect transistor is non-conductive. The field effect transistor 104 has its gate connected to the refresh control circuit 107, its first terminal connected to the low voltage generation source 109, and its second terminal connected to the first terminals of the capacitive element 105 and the field effect transistor 103. The field effect transistor 104 controls the charging of the low potential of the capacitive element 105 connected to the second terminal.

[0027] The field effect transistor 104 has its gate connected to the refresh control circuit 107, its first terminal connected to the low voltage generation source 109, and its second terminal connected to the first terminals of the capacitive element 105 and the field effect transistor 103. The field effect transistor 104 controls the charging of the low potential of the capacitive element 105 connected to the second terminal. The channel regions of the field effect transistors 102 to 104 are formed of an i-type or substantially i-type oxide semiconductor layer. The i-type or substantially i-type oxide semiconductor layer has a carrier density of less than 5×10 cm 14 , preferably less than 1×1

[0028] The channel regions of the field effect transistors 102 to 104 are formed of an i-type or substantially i-type oxide semiconductor layer. The i-type or substantially i-type oxide semiconductor layer has a carrier density of less than 5×10 or substantially i-type oxide semiconductor layer has a carrier density of less than 5×10 cm 14 cm -3 14 , preferably less than 1×1 0 12 cm -3 14 , more preferably less than 1×10 11 cm -3 14 or less. Also, it is preferable that there are few hydrogen and oxygen defects contributing as donors, and the hydrogen concentration is preferably 1×10 cm 16 cm -3 16 or less. Note that the carrier density is obtained by Hall effect measurement. Also, lower The carrier density of the concentration is measured by CV measurement (Capacitance-Voltage-Mechanical The hydrogen concentration in the oxide semiconductor layer is obtained by the measurement of the hydrogen concentration in the oxide semiconductor layer. The measurement is performed using secondary ion mass spectrometry (SIMS). It is obtained by spectroscopic analysis.

[0029] A field-effect transistor using an i-type or substantially i-type oxide semiconductor in the channel region The resistor 102 has an off-state current of 1×10 -16 A / μm or less, even 1×10 -19 A / The size of the i-type or substantially i-type oxide semiconductor can be reduced to less than 1 μm. However, because the band gap is wide and a large amount of thermal energy is required to excite the electrons, Therefore, when a negative potential is applied to the gate electrode, In the off state, the number of holes, which are minority carriers, is essentially zero, so direct recombination occurs. Indirect recombination is unlikely to occur, and the current becomes infinitesimally small. As a result, the field effect transistor When the transistor is in a non-conducting (off) state, the oxide semiconductor layer is regarded as an insulator. On the other hand, the i-type or substantially i-type oxide semiconductor The conductor layer is a semiconductor layer formed of amorphous silicon when the field effect transistor is in a conductive state. It is expected that the current supply capacity will be higher than that of the conductor layer. The field effect transistors 102 to 104 are enhancement type transistors, and in the off state, It has a very small leakage current and a normally-off state, and has excellent switching characteristics.

[0030] The capacitor 105 is connected to the field-effect transistor 104 when the field-effect transistor 104 is intermittently turned on (ON). ) is an element for holding the low potential applied to the power element 110. The capacitive element 1 05 may be formed by a structure in which an insulating layer is sandwiched between conductors.

[0031] The overvoltage detection circuit 106 controls the conduction or non - conduction of the field - effect transistors 102 and 103 according to the voltage between the input terminal IN and the output terminal OUT. Specifically, when an overvoltage is applied between the input terminal IN and the output terminal OUT, the field - effect transistor 102 is made conductive and the field - effect transistor 103 is made non - conductive, controlling the application of the high potential from the high - voltage power source 108 to the power element 110. Also, when no overvoltage is applied between the input terminal IN and the output terminal OUT, the field - effect transistor 102 is made non - conductive and the field - effect transistor 103 is made conductive, controlling the application of the low potential charged to the capacitive element 105 from the low - voltage power source 109 to the power element 110.

[0032] The refresh control circuit 107 is a circuit that controls the conduction or non - conduction of the field - effect transistor 104 in order to control the charging of the low potential from the low - voltage power source 109 to the capacitive element 105. Specifically, it is a circuit that intermittently makes the field - effect transistor 104 conductive before the low potential held by the charging from the low - voltage power source 109 to the capacitive element 105 discharges to the power element 110, for charging the low potential.

[0033] The power element 110 uses a power element that turns on in a state where no voltage is applied to the gate. As the power element 110, a bipolar transistor, a field - effect transistor (FET (Field - Effect Tra nsistor)) using Si, SiC, GaN, or an oxide semiconductor is used. nsistor), gate turn-off thyristor, insulated gate bipolar transistor (IGBT), etc. can be used as appropriate. Also, in the case of a field effect transistor, the pa ower MOSFET (Metal Oxide Semiconductor FET), HFET, JFET (junction gate field effect transistor), etc. can be used as appropriate. The equivalent circuit of the three-terminal power element 121 is shown in Fig. 2(A). The gate of the power element 121 is connected to the field effect transistor 102 and the field effect transistor 103. Also, assuming that one of the source terminal and the drain terminal of the power element 121 is the first terminal and the other of the source terminal and the drain terminal is the second terminal, the first terminal is connected to the input terminal IN, and the second terminal is connected to the output terminal OUT.

[0034] In the present embodiment, hereinafter, as a representative example of the power element 110, as shown in Fig. 2(B), the four-terminal power MOSFET 101 will be described.

[0035] The power MOSFET 101 has four terminals, typically a first gate terminal (referred to as the first gate), a second gate terminal (referred to as the second gate), a drain terminal (also referred to as the drain), and a source terminal (also referred to as the source). The power MOSFET 101 has the first gate and the second gate arranged above and below the channel region, and a signal for controlling the switching of the power MOSFET 101 is supplied to the first gate and the second gate.

[0036] The circuit symbol of the power MOSFET 101 with the first gate 201 and the second gate 206 arranged above and below the channel region is shown in Fig. 2(C). As shown in Fig. 2(C), the power MO SFET101 The SFET 101 includes a first gate 201, a second gate 206, and a first terminal 204A and a second terminal 204B. The power MOSFET 101 has a first gate 201 and a second gate 206 to which a signal (signal G shown in FIG. 2(C)) output from a high voltage generation source 108 or a low voltage generation source 109 is input . Switching such as conduction or non-conduction between the first terminal 204A and the second terminal 204B of the power MOSFET 101 is controlled by a signal output from the high voltage generation source 108 or the low voltage generation source 109. The channel region of the power MOSFET 101 may be formed of an n-type oxide semiconductor layer

[0037] . The n-type oxide semiconductor layer may have a carrier density of 1×10 cm 16 or more and 1×10 -3 or less, preferably 1×10 20 cm -3 or more and 1×10 17 cm -3 or more and 1×10 20 cm -3 or less . In the oxide semiconductor, since hydrogen and oxygen deficiencies contribute as donors, the hydrogen concentration is preferably 1×10 16 cm -3 or more and 1×10 20 cm -3 or more

[0038] Since the power MOSFET 101 has an n-type oxide semiconductor layer in the channel region, it is possible to reduce the on-resistance as compared with a power MOSFET having an i-type oxide semiconductor layer in the channel region, and it is possible to pass a large current. However, since it has an n-type oxide semiconductor layer in the channel region, it is a depletion type, and when a voltage is applied to the gate ​It is a normally-on type in which current flows even without applying pressure. As shown in this embodiment The power MOSFET has a second gate 206 together with the first gate 201, and the first It can be turned off by applying a negative voltage to the gate 201 and the second gate 206. Therefore, the power MOSFET with low on-resistance and capable of flowing a large current can be turned off. On the other hand, it can be turned on by applying a positive voltage to the first gate 201 and the second gate 206. Also, since the power MOSFET 101 has the first gate 201 and the second gate 206, compared with a single-gate power MOS FET, by increasing the thickness of the channel region, the threshold voltage becomes more negative, and it is possible to increase the on-current.

[0039] Next, the operation of the semiconductor device shown in FIG. 2(B) will be described with reference to FIGS. 3 and 4. In the descriptions of FIGS. 3 and 4, the dotted arrows are visualized and shown to make it easier to understand the flow of signals due to the conduction or non-conduction of the power MOSFET 101 and each field-effect transistor. Also, an n-type oxide semiconductor layer is used for the channel region of the power MOSFET 101 that constitutes the semiconductor device, and it conducts due to the high potential from the high-voltage generation source 108 and becomes non-conductive due to the low potential from the low-voltage generation source 109. Note that the operation of the semiconductor device shown in FIG. 2(A) is such that in the equivalent circuits shown in FIGS. 3 and 4, the power MOSFET 101 may be replaced with the power element 121.

[0040] In FIG. 3(A), the operation when turning on the power MOSFET 101 will be described. When Under the control of the voltage detection circuit 106, the field effect transistor 102 is turned on, the field effect transistor 103 is turned off, and the field effect transistor 104 is turned off under the control of the refresh control circuit 107. By turning on the field effect transistor 102, a high potential is applied from the high voltage generation source 108 to the first gate and the second gate of the power MOSFET 101, and the power MOSFET 101 is turned on. The field effect transistor 102 is turned on, the field effect transistor 103 is turned off, and the field effect transistor 104 is turned off under the control of the refresh control circuit 107. By turning on the field effect transistor 102, a high potential is applied from the high voltage generation source 108 to the first gate and the second gate of the power MOSFET 101, and the power MOSFET 101 is turned on. By turning on the field effect transistor 102, a high potential is applied from the high voltage generation source 108 to the first gate and the second gate of the power MOSFET 101, and the power MOSFET 101 is turned on. A high potential is applied from the high voltage generation source 108 to the first gate and the second gate of the power MOSFET 101, and the power MOSFET 101 is turned on. A high potential is applied from the high voltage generation source 108 to the first gate and the second gate of the power MOSFET 101, and the power MOSFET 101 is turned on.

[0041] In FIG. 3(B), the operation when turning off the power MOSFET 101 will be described. Under the control of the overvoltage detection circuit 106, the field effect transistor 102 is turned off, the field effect transistor 103 is turned on, and the field effect transistor 104 is turned off under the control of the refresh control circuit 107. As shown in FIG. 3(B), by turning on the field effect transistor 103, the low potential charged in the capacitor element 105 from the low voltage generation source 109 is applied to the first gate and the second gate of the power MOSFET 101, and the power MOSFET 101 is turned off. Under the control of the overvoltage detection circuit 106, the field effect transistor 102 is turned off, the field effect transistor 103 is turned on, and the field effect transistor 104 is turned off under the control of the refresh control circuit 107. As shown in FIG. 3(B), by turning on the field effect transistor 103, the low potential charged in the capacitor element 105 from the low voltage generation source 109 is applied to the first gate and the second gate of the power MOSFET 101, and the power MOSFET 101 is turned off. Under the control of the overvoltage detection circuit 106, the field effect transistor 102 is turned off, the field effect transistor 103 is turned on, and the field effect transistor 104 is turned off under the control of the refresh control circuit 107. As shown in FIG. 3(B), by turning on the field effect transistor 103, the low potential charged in the capacitor element 105 from the low voltage generation source 109 is applied to the first gate and the second gate of the power MOSFET 101, and the power MOSFET 101 is turned off. Under the control of the overvoltage detection circuit 106, the field effect transistor 102 is turned off, the field effect transistor 103 is turned on, and the field effect transistor 104 is turned off under the control of the refresh control circuit 107. As shown in FIG. 3(B), by turning on the field effect transistor 103, the low potential charged in the capacitor element 105 from the low voltage generation source 109 is applied to the first gate and the second gate of the power MOSFET 101, and the power MOSFET 101 is turned off. Under the control of the overvoltage detection circuit 106, the field effect transistor 102 is turned off, the field effect transistor 103 is turned on, and the field effect transistor 104 is turned off under the control of the refresh control circuit 107. As shown in FIG. 3(B), by turning on the field effect transistor 103, the low potential charged in the capacitor element 105 from the low voltage generation source 109 is applied to the first gate and the second gate of the power MOSFET 101, and the power MOSFET 101 is turned off. Under the control of the overvoltage detection circuit 106, the field effect transistor 102 is turned off, the field effect transistor 103 is turned on, and the field effect transistor 104 is turned off under the control of the refresh control circuit 107. As shown in FIG. 3(B), by turning on the field effect transistor 103, the low potential charged in the capacitor element 105 from the low voltage generation source 109 is applied to the first gate and the second gate of the power MOSFET 101, and the power MOSFET 101 is turned off. Under the control of the overvoltage detection circuit 106, the field effect transistor 102 is turned off, the field effect transistor 103 is turned on, and the field effect transistor 104 is turned off under the control of the refresh control circuit 107. As shown in FIG. 3(B), by turning on the field effect transistor 103, the low potential charged in the capacitor element 105 from the low voltage generation source 109 is applied to the first gate and the second gate of the power MOSFET 101, and the power MOSFET 101 is turned off.

[0042] In FIG. 3(C), the operation of charging the capacitor element 105 with a low potential described in FIG. 3(B) will be described. Under the control of the overvoltage detection circuit 106, the field effect transistor 102 is turned off, the field effect transistor 103 is turned on, the field effect transistor 104 is turned on under the control of the refresh control circuit 107, and the capacitor element 105 is charged with a low potential from the low voltage generation source 109. Under the control of the overvoltage detection circuit 106, the field effect transistor 102 is turned off, the field effect transistor 103 is turned on, the field effect transistor 104 is turned on under the control of the refresh control circuit 107, and the capacitor element 105 is charged with a low potential from the low voltage generation source 109. Under the control of the overvoltage detection circuit 106, the field effect transistor 102 is turned off, the field effect transistor 103 is turned on, the field effect transistor 104 is turned on under the control of the refresh control circuit 107, and the capacitor element 105 is charged with a low potential from the low voltage generation source 109. Under the control of the overvoltage detection circuit 106, the field effect transistor 102 is turned off, the field effect transistor 103 is turned on, the field effect transistor 104 is turned on under the control of the refresh control circuit 107, and the capacitor element 105 is charged with a low potential from the low voltage generation source 109. Under the control of the overvoltage detection circuit 106, the field effect transistor 102 is turned off, the field effect transistor 103 is turned on, the field effect transistor 104 is turned on under the control of the refresh control circuit 107, and the capacitor element 105 is charged with a low potential from the low voltage generation source 109.

[0043] Note that the charging of the capacitor element 105 with a low potential described in FIG. 3(C) is performed at a constant period under the control of the refresh control circuit 107. Specifically, the charging from the low voltage generation source 109 Note that the charging of the capacitor element 105 with a low potential described in FIG. 3(C) is performed at a constant period under the control of the refresh control circuit 107. Specifically, the charging from the low voltage generation source 109 While maintaining the low potential that turns off the power MOSFET 101 with the capacitive element 105 by [reference], the semiconductor device maintains the state shown in Fig. 3(B). Then, intermittently, it changes to the state shown in Fig. 3(C), turns on the field-effect transistor 104, and charges the low potential to the capacitive element 105. For example, the operation shown in Fig. 3(C) may be performed at a rate of once per minute, taking sufficient time for charging. .

[0044] In the configuration of this embodiment as described above, although it repeats between the state of Fig. 3(A) or Fig. 3(B) and the state of Fig. 3(C), the period of maintaining the state of Fig. 3(B) becomes longer.

[0045] Here, the effects of this embodiment will be described in detail with reference to Fig. 4(A). Fig. 4(A) shows, in solid lines, the nodes connected to the first gate and the second gate of the power MOSFET 101, the field-effect transistor 103, and one end of the capacitive element 105 in the state of Fig. 3(B) described above, and shows the other connections in broken lines. When the field-effect transistor 102 and the field-effect transistor 104 are turned off, the nodes connected to the first gate and the second gate of the power MOSFET 101 become electrically floating states. As described above, since the field-effect transistor 102 and the field-effect transistor 104 are composed of an oxide semiconductor layer in which the channel region is i-type or substantially i-type, the off-current is extremely small. Therefore, the nodes connected to the first gate and the second gate of the power MOSFET 101 can maintain the low potential charged from the low-voltage generation source 109 to the capacitive element 105 for a long period of time. Constantly,

[0046] the nodes connected to the first gate and the second gate of the power MOSFET 101 are in an electrically floating state (floating state). As described above, since the field-effect transistor 102 and the field-effect transistor 104 are composed of an oxide semiconductor layer in which the channel region is i-type or substantially i-type, the off-current is extremely small. For this reason, the nodes connected to the first gate and the second gate of the power MOSFET 101 can maintain the low potential charged from the low-voltage generation source 109 to the capacitive element 105 for a long period of time. The field-effect transistor 102 and the field-effect transistor 104 are composed of an oxide semiconductor layer in which the channel region is i-type or substantially i-type, so the off-current is extremely small. Therefore, the nodes connected to the first gate and the second gate of the power MOSFET 101 can maintain the low potential charged from the low-voltage generation source 109 to the capacitive element 105 for a long period of time. the nodes connected to the first gate and the second gate of the power MOSFET 101 can maintain the low potential charged from the low-voltage generation source 109 to the capacitive element 105 for a long period of time. Instead of applying a low potential to the capacitive element, it may be applied intermittently to the capacitive element. Also, power When a low potential is applied to the first gate and the second gate of the power MOSFET 101, the power M OSFET 101 turns off. Therefore, the semiconductor device of the present embodiment can achieve the off state of the power MOSFET 101 without causing an increase in power consumption .

[0047] Also, in the semiconductor device shown in Fig. 2(C), in order to improve the potential holding characteristics of the nodes connected to the first gate and the second gate of the power MOSFET 101, as shown in Fig. 4(B) , a capacitive element 401 may be separately provided at the nodes connected to the first gate and the second gate. In the semiconductor devices shown in Figs. 2(A) and 2(B), a capacitive element 401 may be provided at the gates of the power MOSFET 101 and the power element 121 .

[0048] In the present embodiment, the contents described in each figure can be freely combined, replaced, etc. as appropriate with respect to the contents described in other embodiments .

[0049] (Embodiment 2) In the present embodiment, the structure and manufacturing method of the power MOSFET 101 shown in Embodiment 1 will be described with reference to Figs. 5 to 7 .

[0050] Fig. 5(A) shows one form of the cross-sectional configuration of the power MOSFET 101 shown in Embodiment 1 , and Fig. 5(B) shows a top view of the power MOSFET 101. The cross-sectional view along A - B in Fig. 5(B) corresponds to Fig. 5(A).

[0051] ​​​The power MOSFET 101 shown in Fig. 5(A) has a first gate 201 made of a conductive layer provided on a substrate 200, a gate insulating layer 202 provided on the first gate 201, an n-type oxide semiconductor layer 203 provided on the gate insulating layer 202, and a first terminal 204A and a second terminal 204B made of a conductive layer partially covering the oxide semiconductor layer 203. An insulating layer 205 is provided to cover the oxide semiconductor layer 203, the first terminal 204A, and the second terminal 204B, and a second gate 206 made of a conductive layer is formed to overlap a part of each of the first terminal 204A and the second terminal 204B on the insulating layer 205. The substrate 200 must have at least heat resistance enough to withstand subsequent heat treatment. When using a glass substrate as the substrate 200, it is preferable to use one with a strain point of 730 °C or higher. For the glass substrate, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. In addition, it is preferable to use a glass substrate containing more BaO than B2O3. Note that instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate can be used. In addition, crystallized glass or the like can be used. Furthermore, a structure in which an insulating layer is formed on the surface of a semiconductor substrate such as a silicon wafer or the surface of a conductive substrate made of a metal material can also be used. Although not shown in Fig. 5(A), a thermal conductive layer is provided between the substrate 200 and the first gate 201.

[0052] 2 O 3

[0053]

[0054] By forming an insulating layer with a high rate, a high heat-resistant power MOSFET 101 can be fabricated. As the insulating layer with a high thermal conductivity, there are an aluminum nitride layer, an aluminum oxynitride layer, a silicon nitride layer, etc.

[0055] The first gate 201 can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements. Also, a metal element selected from any one or more of manganese, magnesium, zirconium, and beryllium may be used. Further, the first gate 201 may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is laminated on an aluminum layer, a two-layer structure in which a titanium layer is laminated on a titanium nitride layer, a two-layer structure in which a tungsten layer is laminated on a titanium nitride layer, a two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer, a three-layer structure in which a titanium layer, an aluminum layer is laminated on the titanium layer, and a titanium layer is further formed thereon, etc. Also, a layer of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium, or a multi-combined alloy layer, or a nitride layer may be used for aluminum.

[0056] Also, the first gate 201 is indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, silicon oxide added ​​​​​​​​​​​​​​It is also possible to apply a conductive material having translucency such as indium tin oxide. Also , it is also possible to form a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal element.

[0057] The gate insulating layer 202 can be formed by a single layer or a laminate of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer. The gate insulating layer 202 is preferably formed such that the portion in contact with the oxide semiconductor layer 203 contains oxygen, and particularly preferably formed of a silicon oxide layer. By using a silicon oxide layer, oxygen can be supplied to the oxide semiconductor layer 203, and the characteristics can be improved. Moreover, the gate insulating layer 202 is hafnium silicate (HfSiO ), hafnium silicate (HfSi O

[0058] N x ) to which nitrogen is added, hafnium aluminate (HfAl ), hafnium aluminate (HfSi x O y N z ) to which nitrogen is added, or a high-k material such as hafnium oxide or yttrium oxide. By using such a high-k material, the gate leakage current can be reduced. Furthermore, it is possible to form a laminated structure of the high-k material and any one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer. The thickness of the gate insulating layer 202 can be 100 nm or more and 300 nm. ), hafnium aluminate (HfAl x O y N z ), or a high-k material such as hafnium oxide or yttrium oxide. By using such a high-k material, the gate leakage current can be reduced. Furthermore, it is possible to form a laminated structure of the high-k material and any one or more of a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer. The thickness of the gate insulating layer 202 can be 100 nm or more and 300 nm. The oxide semiconductor layer 203 that is n-type is a quaternary metal oxide such as an In-Sn-Ga-Zn- O-based metal oxide, a ternary metal oxide such as an In-Ga-Zn-O-based metal oxide, In- The oxide semiconductor layer 203 that is n-type is a quaternary metal oxide such as an In-Sn-Ga-Zn- O-based metal oxide, a ternary metal oxide such as an In-Ga-Zn-O-based metal oxide, In-

[0059] O-based metal oxide, a ternary metal oxide such as an In-Ga-Zn-O-based metal oxide, In- O-based metal oxide, a ternary metal oxide such as an In-Ga-Zn-O-based metal oxide, In- Sn-Zn-O-based metal oxides, In-Al-Zn-O-based metal oxides, Sn-Ga-Zn- O-based metal oxides, Al-Ga-Zn-O-based metal oxides, Sn-Al-Zn-O-based metal oxide and, as binary metal oxides, In-Zn-O-based metal oxides, Sn-Zn-O-based metal oxide and, Al-Zn-O-based metal oxides, Zn-Mg-O-based metal oxides, Sn-Mg-O-based metal oxides, In-Mg-O-based metal oxides, etc. can be used. Here, the n-component metal oxide is composed of n types of metal oxides. Note that, as an impurity, the oxide semiconductor layer may contain 1%, preferably 0.1%, of an element other than the metal oxide as the main component.

[0060] Also, the n-type oxide semiconductor layer 203 is a ternary metal oxide, and a metal oxide represented by InM X Zn Y O Z (Y = 0.5 to 5) may be used. Here, M is one or more elements selected from Group 13 elements such as gallium (Ga), aluminum (Al), and boron (B), or a plurality of types of elements. Note that the contents of In, M, Zn, and O are arbitrary, including the case where the content of M is zero (i.e., x = 0). On the other hand, the contents of In and Zn are not zero . That is, the above notations include In-Ga-Zn-O-based metal oxides and In-Zn-O-based metal oxide semiconductors, etc.

[0061] Also, the metal oxide forming the n-type oxide semiconductor layer 203 has an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more.

[0062] The n-type oxide semiconductor layer 203 has an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a single crystal ​An oxide semiconductor having a crystal structure can be appropriately used. Also, an oxide semiconductor having a crystal with the c-axis substantially parallel in the direction perpendicular to the surface can be used.

[0063] The n-type oxide semiconductor layer 203 has a carrier density of 1×10 16 cm -3 or more and 1×10 20 cm -3 or less, preferably 1×10 17 cm -3 or more and 1×10 20 cm -3 or less. In the oxide semiconductor, since hydrogen and oxygen deficiencies contribute as donors, the hydrogen concentration is 1×10 1×10 16 cm -3 or more and 1×10 20 cm -3 or less, which is preferable.

[0064] Also, the thickness of the n-type oxide semiconductor layer 203 is such that when a negative voltage is applied to the first gate and the second gate, the depletion layer spreads into the channel region and the power MOSFET 101 can be turned off. When the carrier density is 1×10 16 cm -3 or more and 1× 10 20 cm -3 or less, the dielectric constant is 15, the band gap is 3.15, the effective density of states in the conduction band is Nc = 2.8×10 density is Nc = 2.8×10 19 cm -3 , the effective density of states in the valence band is Nv = 1.04×10 19 cm -3 , and when there is a gate on one side of the oxide semiconductor layer, the maximum depletion layer width is 7 nm or more and 677 nm or less. Since the power MOSFET shown in FIG. 5(A) has the first gate 201 and the second gate 206, the thickness of the n-type oxide semiconductor layer 203 is It can be 14 nm or more and 1354 nm or less. Also, when the carrier density is 1×10 17 cm -3 or more and 1×10 20 cm -3 or less, the maximum depletion layer width is 7 nm or more and 218 nm or less. In this case, the thickness of the n-type oxide semiconductor layer 203 can be 14 nm or more and 436 n m or less.

[0065] The first terminal 204A and the second terminal 204B can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy containing the above-described metal element as a component, or an alloy combining the above-described metal elements. It is also possible to use one or more metal elements selected from manganese, magnesium, zirconium, and beryllium. Further, the first terminal 204A and the second terminal 204 B may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum layer containing silicon, a two-layer structure in which a titanium layer is laminated on an aluminum layer, a two-layer structure in which a titanium layer is laminated on a titanium nitride layer, a two-layer structure in which a tungsten layer is laminated on a titanium nitride layer, a two-layer structure in which a tungsten layer is laminated on a tantalum nitride layer, a three-layer structure in which a titanium layer and an aluminum layer are laminated on the titanium layer, and then a titanium layer is formed thereon. There are also, for example, a layer of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium in aluminum, or an alloy layer or a nitride layer in which a plurality are combined. It may also be used.

[0066] Further, the first terminal 204A and the second terminal 204B are indium tin oxide, tungsten oxide Indium oxide containing stannum, indium zinc oxide containing tungsten oxide, titanium Indium oxide containing tantalum, indium tin oxide containing titanium oxide, indium zinc Oxide, and other conductive materials having translucency such as indium tin oxide added with silicon oxide can also be applied. In addition, it is also possible to form a laminate structure with the above-mentioned conductive material having translucency and the above-mentioned metal element.

[0067] The insulating layer 205 can appropriately use the materials shown in the gate insulating layer 202.

[0068] The second gate 206 can appropriately use the materials shown in the first gate 201.

[0069] Since the power MOSFET 101 shown in FIG. 5 has an n-type oxide semiconductor layer in the channel region, it is possible to reduce the on-resistance and allow a large current to flow. However, since it has an n-type oxide semiconductor layer in the channel region, it is of the depletion type and is in the normally-on state where current flows even when no voltage is applied to the gate. The power MOSFET shown in this embodiment has a second gate 206 together with the first gate 201, and can be turned off by applying a negative voltage to the first gate 201 and the second gate 206. Therefore, it is possible to realize the off state of a power MOSFET having a low on-resistance and capable of flowing a large current. On the other hand, it is possible to turn on by applying a positive voltage to the first gate 201 and the second gate 206. Also, since the power MOSFET 101 has the first gate 201 and the second gate 206, compared with a single-gate power MOSFET, the thickness of the channel region can be increased. ​​is possible and capable of passing a large current.

[0070] Also, as shown in FIG. 5(B), by connecting the power MOSFETs 101 in parallel, the channel width W of the transistor can be designed to be increased. Therefore, a power device capable of passing a large current can be fabricated.

[0071] Next, FIG. 6 shows a cross-sectional configuration of a power MOSFET different from that in FIG. 5. The power MOSFET 101A shown in FIG. 6(A) is characterized in that the second gate 206A overlaps with one of the first terminal 204A and the second terminal 204B and does not overlap with the other.

[0072] The power MOSFET 101A shown in FIG. 6(A) has a first gate 201 made of a conductive layer provided on a substrate 200, a gate insulating layer 202 provided on the first gate 201, an n-type oxide semiconductor layer 203 provided on the gate insulating layer 202, a first terminal 204A and a second terminal 204B made of a conductive layer provided so as to partially cover the oxide semiconductor layer 203, and an insulating layer 205 provided so as to cover the oxide semiconductor layer 203, the first terminal 204A, and the second terminal 204B. Also, on the insulating layer 205, a second gate 206A made of a conductive layer that overlaps with one of the first terminal 204A and the second terminal 204B and does not overlap with the other is formed. That is, an oxide semiconductor layer 203 forms a region 208 that does not overlap with the second gate 206A, the first terminal 204A, and the second terminal 204B. The second gate 206A can be formed using the same materials and manufacturing method as the second gate 206 shown in FIG. 5.

[0073] The second gate 206A can be formed using the same materials and manufacturing method as the second gate 206 shown in FIG. 5.

[0074] ​​​​ The power MOSFET 101B shown in Fig. 6(B) has a first gate 201A made of a conductive layer provided on a substrate 200, a gate insulating layer 202 provided on the first gate 201A, an n-type oxide semiconductor layer 203 provided on the gate insulating layer 202, a first terminal 204A and a second terminal 204B made of a conductive layer provided so as to partially cover the oxide semiconductor layer 203, and an insulating layer 205 provided so as to cover the oxide semiconductor layer 203, the first terminal 204A, and the second terminal 204B. Also, on the insulating layer 205, a second gate 206A made of a conductive layer is formed so as to overlap one of the first terminal 204A and the second terminal 204B and not overlap the other. That is, an offset region 209 is formed in which the oxide semiconductor layer 203 does not overlap with the first gate 201A, the second gate 206A, the first terminal 204A, and the second terminal 204B. The first gate 201A can be formed using the same material and manufacturing method as the first gate 201 shown in Fig. 5. Since the power MOSFETs 101A and 101B shown in Fig. 6 have an n-type oxide semiconductor layer 203 in the channel region, it is possible to reduce the on-resistance and allow a large current to flow. However, since they have an n-type oxide semiconductor layer in the channel region, they are of the depletion type and are in a normally-on state where current flows even when no voltage is applied to the gate. The power MOSFET shown in this embodiment has a second gate 206A together with the first gate 201 or 201A.

[0075]

[0076] ​​​​​​​​​​​​​​​By applying a negative voltage to the 201 or 201A and the second gate 206A, it can be turned off. It is possible to turn it on by applying a positive voltage to the first gate 201 or 201A and the second gate 206A. Therefore, an off state of a power MOSFET with low on-resistance and capable of flowing a large current can be realized. Also, since it has the first gate 201 or 201A and the second gate 206A, it is possible to increase the thickness of the channel region compared to a power MOSFET with a single gate, and it is possible to flow a large current. Furthermore, in the power MOSFET 101B shown in FIG. 6(B), in an n-type oxide semiconductor, an offset region 209 not covered by the first gate 201A, the second gate 2 06A, the first terminal 204A, and the second terminal 204B is provided. Therefore, compared to the power MOSFET 101 shown in FIG. 5(A), the drain breakdown voltage can be increased, and a high voltage can be applied to the first terminal 204A or the second terminal 204B. Here, a method for manufacturing the power MOSFET 101 shown in FIG. 5 will be described with reference to FIG. 7. As shown in FIG. 7(A), the first gate 201 is formed on the substrate 200. Next, a gate insulating layer 202 is formed on the first gate 201. The first gate 201 can be manufactured by using a printing method, an inkjet method, etc., to reduce the number of processes. Alternatively, after forming a conductive layer by sputtering, CVD, evaporation, etc., the conductive layer is etched using a resist formed by a photolithography process as a mask. The first gate 201 can be manufactured by using a printing method, an inkjet method, etc., to reduce the number of processes. Alternatively, after forming a conductive layer by sputtering, CVD, evaporation, etc., the conductive layer is etched using a resist formed by a photolithography process as a mask. Here, a method for manufacturing the power MOSFET 101 shown in FIG. 5 will be described with reference to FIG. 7.

[0077] Here, a method for manufacturing the power MOSFET 101 shown in FIG. 5 will be described with reference to FIG. 7. Here, a method for manufacturing the power MOSFET 101 shown in FIG. 5 will be described with reference to FIG. 7.

[0078] As shown in FIG. 7(A), the first gate 201 is formed on the substrate 200. Next, a gate insulating layer 202 is formed on the first gate 201.

[0079] The first gate 201 can be manufactured by using a printing method, an inkjet method, etc., to reduce the number of processes. Alternatively, after forming a conductive layer by sputtering, CVD, evaporation, etc., the conductive layer is etched using a resist formed by a photolithography process as a mask. The first gate 201 can be manufactured by using a printing method, an inkjet method, etc., to reduce the number of processes. Alternatively, after forming a conductive layer by sputtering, CVD, evaporation, etc., the conductive layer is etched using a resist formed by a photolithography process as a mask. formed, and then the conductive layer is etched using the resist formed by the photolithography process as a mask. Etching can form the first gate 201. Note that for the first gate 201 if the end part has a tapered shape, the coverage rates of the insulating layer, semiconductor layer, and conductive layer to be formed later can be increased, which is preferable. Also, an insulating layer with high thermal conductivity is formed between the substrate 200 and the first gate 201 by a sputtering method, CVD method, coating method, printing method, etc. This is preferable.

[0080] The gate insulating layer 202 can be formed by a sputtering method, CVD method, printing method, coating method, etc. Alternatively, a high-quality gate insulating layer 202 with high density and high dielectric breakdown voltage can be formed by high-density plasma CVD using microwaves (for example, frequency 2.45 GHz). By closely contacting the oxide semiconductor layer and the high-quality gate insulating layer, the interface states can be reduced and the interface characteristics can be improved. Also, the gate insulating layer 2 02 obtained by high-density plasma CVD can be formed with a certain thickness, so it has excellent step coverage. Also, the gate insulating layer 202 obtained by high-density plasma CVD can have its thickness precisely controlled.

[0081] Next, as shown in FIG. 7(B), an n-type oxide semiconductor layer 20 3 is formed on the gate insulating layer 202. The n-type oxide semiconductor layer 203 can be fabricated using a printing method, inkjet method, etc. to reduce the number of processes. Alternatively, on the gate insulating layer 202, an n-type oxide semiconductor layer is formed by a sputtering method, CVD method, coating method, pulsed laser deposition method, etc., and then the resist formed by a photolithography process is used as a mask to etch the above oxide semiconductor layer to form an island-shaped n-type oxide semiconductor layer 203. This can be done. ​

[0082] The carrier density of the oxide semiconductor layer depends on the hydrogen concentration of the source gas and the target, the oxygen concentration, the material to be formed, and its composition under the film formation conditions. By increasing the hydrogen concentration of the oxide semiconductor layer or by reducing the oxygen concentration of the oxide semiconductor layer to include oxygen deficiency, it is possible to incorporate hydrogen or oxygen deficiency contributing as donors into the oxide semiconductor layer. Therefore, an n-type oxide semiconductor layer can be formed.

[0083] Note that after forming the oxide semiconductor layer 203, heat treatment may be performed to obtain an oxide semiconductor layer with a microcrystalline structure, a polycrystalline structure, or a single crystal structure. Alternatively, it may be an oxide semiconductor layer having a crystal structure with a c-axis substantially parallel in a direction perpendicular to the surface.

[0084] Next, as shown in FIG. 7(C), a first terminal 204A and a second terminal 204B that function as a source electrode and a drain electrode are formed. The first terminal 204A and the second terminal 204B can be manufactured by using a printing method, an inkjet method, etc., to reduce the number of steps. Alternatively, after forming a conductive layer on the gate insulating layer 202 and the oxide semiconductor layer 203 by a sputtering method, a CVD method, an evaporation method, etc., the conductive layer is etched using a resist formed by a photolithography process as a mask to form the first terminal 204A and the second terminal 204B.

[0085] Next, as shown in FIG. 7(D), an insulating layer 205 is formed on the gate insulating layer 202, the oxide semiconductor layer 203, the first terminal 204A, and the second terminal 204B. The insulating layer 205 can be formed in the same manner as the gate insulating layer 202. Next, a second gate ​​​​​​​ Form 206. The second gate 206 can be formed in the same manner as the first gate. .

[0086] Through the above steps, a power MOSFET 101 having an n-type oxide semiconductor layer in the channel region and being of the depletion type can be fabricated. In the above fabrication process , by changing the layout of the second gate, a power MOSFET 1 01A shown in FIG. 6(A) or a power MOSFET 101B shown in FIG. 6(B) can be fabricated.

[0087] (Embodiment 3) In this embodiment, the structure of a power MOSFET that can be used instead of the power MOSFET 101 shown in Embodiment 1 and Embodiment 2 will be described with reference to FIGS. 8 and 9.

[0088] The power MOSFETs shown in FIGS. 8 and 9 are different from the power MOSFET shown in FIG. 6 in that there is no gate between the substrate 200 and the oxide semiconductor layer 213.

[0089] The power MOSFET 111A shown in FIG. 8 has an n-type oxide semiconductor layer 2 13 provided on the substrate 200, and a first terminal 204A made of a conductive layer partially covering the oxide semiconductor layer 213 , a second terminal 204B provided, and a gate insulating layer 212 provided covering the oxide semiconductor layer 213, the first terminal 204A, and the second terminal 204B. On the gate insulating layer 212, a gate 2 11 made of a conductive layer overlapping a part of one of the first terminal 204A and the second terminal 204B is provided. That is, the oxide semiconductor layer 213 forms a region 208 that does not overlap with the gate 211, the first terminal 204A, and the second terminal 204B. ​

[0090] Note that, similar to the power MOSFET 101 shown in the second embodiment, by forming an insulating layer with high thermal conductivity between the substrate 200 and the oxide semiconductor layer 213, a power MOSFET 111A with high heat resistance can be manufactured. Also, the first terminal 204A and the second terminal 204B may be provided between the substrate 200 and the oxide semiconductor layer 213. Further, similar to FIG. 5(A), a gate 211 formed of a conductive layer that does not have the region 208 and overlaps a part of each of the first terminal 204A and the second terminal 204B may be provided. Note that, similar to the power MOSFET 101 shown in the second embodiment, by forming an insulating layer with high thermal conductivity between the substrate 200 and the oxide semiconductor layer 213, a power MOSFET 111A with high heat resistance can be manufactured. Also, the first terminal 204A and the second terminal 204B may be provided between the substrate 200 and the oxide semiconductor layer 213. Further, similar to FIG. 5(A), a gate 211 formed of a conductive layer that does not have the region 208 and overlaps a part of each of the first terminal 204A and the second terminal 204B may be provided. Note that, similar to the power MOSFET 101 shown in the second embodiment, by forming an insulating layer with high thermal conductivity between the substrate 200 and the oxide semiconductor layer 213, a power MOSFET 111A with high heat resistance can be manufactured. Also, the first terminal 204A and the second terminal 204B may be provided between the substrate 200 and the oxide semiconductor layer 213. Further, similar to FIG. 5(A), a gate 211 formed of a conductive layer that does not have the region 208 and overlaps a part of each of the first terminal 204A and the second terminal 204B may be provided. Note that, similar to the power MOSFET 101 shown in the second embodiment, by forming an insulating layer with high thermal conductivity between the substrate 200 and the oxide semiconductor layer 213, a power MOSFET 111A with high heat resistance can be manufactured. Also, the first terminal 204A and the second terminal 204B may be provided between the substrate 200 and the oxide semiconductor layer 213. Further, similar to FIG. 5(A), a gate 211 formed of a conductive layer that does not have the region 208 and overlaps a part of each of the first terminal 204A and the second terminal 204B may be provided. Note that, similar to the power MOSFET 101 shown in the second embodiment, by forming an insulating layer with high thermal conductivity between the substrate 200 and the oxide semiconductor layer 213, a power MOSFET 111A with high heat resistance can be manufactured. Also, the first terminal 204A and the second terminal 204B may be provided between the substrate 200 and the oxide semiconductor layer 213. Further, similar to FIG. 5(A), a gate 211 formed of a conductive layer that does not have the region 208 and overlaps a part of each of the first terminal 204A and the second terminal 204B may be provided. Note that, similar to the power MOSFET 101 shown in the second embodiment, by forming an insulating layer with high thermal conductivity between the substrate 200 and the oxide semiconductor layer 213, a power MOSFET 111A with high heat resistance can be manufactured. Also, the first terminal 204A and the second terminal 204B may be provided between the substrate 200 and the oxide semiconductor layer 213. Further, similar to FIG. 5(A), a gate 211 formed of a conductive layer that does not have the region 208 and overlaps a part of each of the first terminal 204A and the second terminal 204B may be provided.

[0091] The power MOSFET 111B shown in FIG. 9(A) has a first terminal 204A formed of a conductive layer provided on the substrate 200, an n-type oxide semiconductor layer 213 provided to cover the first terminal 204A formed of a conductive layer, a second terminal 204B formed of a conductive layer provided to partially cover the oxide semiconductor layer 213, a gate insulating layer 212 provided to cover the oxide semiconductor layer 213 and the second terminal 204B, and a gate 211 formed of a conductive layer, a wiring 214 connected to the first terminal 204A, and a wiring 215 connected to the second terminal 204B provided on the gate insulating layer 212. The power MOSFET 111B shown in FIG. 9(A) has a first terminal 204A formed of a conductive layer provided on the substrate 200, an n-type oxide semiconductor layer 213 provided to cover the first terminal 204A formed of a conductive layer, a second terminal 204B formed of a conductive layer provided to partially cover the oxide semiconductor layer 213, a gate insulating layer 212 provided to cover the oxide semiconductor layer 213 and the second terminal 204B, and a gate 211 formed of a conductive layer, a wiring 214 connected to the first terminal 204A, and a wiring 215 connected to the second terminal 204B provided on the gate insulating layer 212. The power MOSFET 111B shown in FIG. 9(A) has a first terminal 204A formed of a conductive layer provided on the substrate 200, an n-type oxide semiconductor layer 213 provided to cover the first terminal 204A formed of a conductive layer, a second terminal 204B formed of a conductive layer provided to partially cover the oxide semiconductor layer 213, a gate insulating layer 212 provided to cover the oxide semiconductor layer 213 and the second terminal 204B, and a gate 211 formed of a conductive layer, a wiring 214 connected to the first terminal 204A, and a wiring 215 connected to the second terminal 204B provided on the gate insulating layer 212. The power MOSFET 111B shown in FIG. 9(A) has a first terminal 204A formed of a conductive layer provided on the substrate 200, an n-type oxide semiconductor layer 213 provided to cover the first terminal 204A formed of a conductive layer, a second terminal 204B formed of a conductive layer provided to partially cover the oxide semiconductor layer 213, a gate insulating layer 212 provided to cover the oxide semiconductor layer 213 and the second terminal 204B, and a gate 211 formed of a conductive layer, a wiring 214 connected to the first terminal 204A, and a wiring 215 connected to the second terminal 204B provided on the gate insulating layer 212. The power MOSFET 111B shown in FIG. 9(A) has a first terminal 204A formed of a conductive layer provided on the substrate 200, an n-type oxide semiconductor layer 213 provided to cover the first terminal 204A formed of a conductive layer, a second terminal 204B formed of a conductive layer provided to partially cover the oxide semiconductor layer 213, a gate insulating layer 212 provided to cover the oxide semiconductor layer 213 and the second terminal 204B, and a gate 211 formed of a conductive layer, a wiring 214 connected to the first terminal 204A, and a wiring 215 connected to the second terminal 204B provided on the gate insulating layer 212. The power MOSFET 111B shown in FIG. 9(A) has a first terminal 204A formed of a conductive layer provided on the substrate 200, an n-type oxide semiconductor layer 213 provided to cover the first terminal 204A formed of a conductive layer, a second terminal 204B formed of a conductive layer provided to partially cover the oxide semiconductor layer 213, a gate insulating layer 212 provided to cover the oxide semiconductor layer 213 and the second terminal 204B, and a gate 211 formed of a conductive layer, a wiring 214 connected to the first terminal 204A, and a wiring 215 connected to the second terminal 204B provided on the gate insulating layer 212. The power MOSFET 111B shown in FIG. 9(A) has a first terminal 204A formed of a conductive layer provided on the substrate 200, an n-type oxide semiconductor layer 213 provided to cover the first terminal 204A formed of a conductive layer, a second terminal 204B formed of a conductive layer provided to partially cover the oxide semiconductor layer 213, a gate insulating layer 212 provided to cover the oxide semiconductor layer 213 and the second terminal 204B, and a gate 211 formed of a conductive layer, a wiring 214 connected to the first terminal 204A, and a wiring 215 connected to the second terminal 204B provided on the gate insulating layer 212.

[0092] FIG. 9(B) is a top view of the power MOSFET 111B shown in FIG. 9(A). The cross-sectional view taken along line A-B in FIG. 9(B) corresponds to FIG. 9(A). As shown in FIG. 9(B), the gate 211 is disposed around the second terminal 204B and the wiring 215 connected to the second terminal 204B. Also, the first terminal 204A and the wiring 214 connected to the first terminal 204A are disposed around the gate 211. FIG. 9(B) is a top view of the power MOSFET 111B shown in FIG. 9(A). The cross-sectional view taken along line A-B in FIG. 9(B) corresponds to FIG. 9(A). As shown in FIG. 9(B), the gate 211 is disposed around the second terminal 204B and the wiring 215 connected to the second terminal 204B. Also, the first terminal 204A and the wiring 214 connected to the first terminal 204A are disposed around the gate 211. FIG. 9(B) is a top view of the power MOSFET 111B shown in FIG. 9(A). The cross-sectional view taken along line A-B in FIG. 9(B) corresponds to FIG. 9(A). As shown in FIG. 9(B), the gate 211 is disposed around the second terminal 204B and the wiring 215 connected to the second terminal 204B. Also, the first terminal 204A and the wiring 214 connected to the first terminal 204A are disposed around the gate 211. FIG. 9(B) is a top view of the power MOSFET 111B shown in FIG. 9(A). The cross-sectional view taken along line A-B in FIG. 9(B) corresponds to FIG. 9(A). As shown in FIG. 9(B), the gate 211 is disposed around the second terminal 204B and the wiring 215 connected to the second terminal 204B. Also, the first terminal 204A and the wiring 214 connected to the first terminal 204A are disposed around the gate 211. FIG. 9(B) is a top view of the power MOSFET 111B shown in FIG. 9(A). The cross-sectional view taken along line A-B in FIG. 9(B) corresponds to FIG. 9(A). As shown in FIG. 9(B), the gate 211 is disposed around the second terminal 204B and the wiring 215 connected to the second terminal 204B. Also, the first terminal 204A and the wiring 214 connected to the first terminal 204A are disposed around the gate 211.

[0093] That is, the first terminal 204A and the second terminal 204B do not overlap. The gate 211 is provided in a region including a region that does not overlap with the first terminal 204A and the second terminal 204B. The gate 211 is provided in a region including a region that does not overlap with the first terminal 204A and the second terminal 204B. Also, a part (end portion) of the gate 211 may overlap with one or both of the first terminal 204A and the second terminal 204B.

[0094] Note that, similar to the power MOSFET 101 shown in Embodiment 2, by forming an insulating layer having a high thermal conductivity between the substrate 200, the first terminal 204A, and the oxide semiconductor layer 213, a power MOSFET 111B having high heat resistance can be manufactured. The oxide semiconductor layer 213 shown in FIGS. 8 and 9 can be formed using the same material as the oxide semiconductor layer 203 shown in Embodiment 2. Note that the power MOSFET 11 1A shown in FIG. 8 and the power MOSFET 111B shown in FIG. 9 have the gate 211 formed only on one surface side of the oxide semiconductor layer 21

[0095] 3. Therefore, the thickness of the oxide semiconductor layer 213 is such that when a negative voltage is applied to the gate 211, the depletion layer spreads into the channel region and the power MOSF ET 111B can be turned off. In this embodiment, since the number of gates is half that of the power MOSFET 101 shown in Embodiment 2, when the carrier density is 1×10 1A shown in FIG. 8 and the power MOSFET 111B shown in FIG. 9 have the gate 211 formed only on one surface side of the oxide semiconductor layer 21 3. For this reason, the thickness of the oxide semiconductor layer 213 is such that when a negative voltage is applied to the gate 211, the depletion layer spreads into the channel region and the power MOSF ET 111B can be turned off. In this embodiment, since the number of gates is half that of the power MOSFET 101 shown in Embodiment 2, when the carrier density is 1×10 ET 111B can be turned off. In this embodiment, since the number of gates is half that of the power MOSFET 101 shown in Embodiment 2, when the carrier density is 1×10 1A shown in FIG. 8 and the power MOSFET 111B shown in FIG. 9 have the gate 211 formed only on one surface side of the oxide semiconductor layer 21 16 cm -3 or more and 1×10 20 cm -3 or less, the maximum depletion layer width is 7 nm or more and 677 n m or less. Therefore, the thickness of the n-type oxide semiconductor layer 213 can be set to 7 nm or more and 677 n m or less. Also, when the carrier density is 1×10 17 cm -3 or more and 1×10 2 0 cm -3 In the following case, the maximum depletion layer width is 7 nm or more and 218 nm or less. In this case, the thickness of the n-type oxide semiconductor layer 213 can be 7 nm or more and 218 nm or less .

[0096] Note that, for the manufacturing method of the power MOSFETs shown in FIGS. 8 and 9, the manufacturing method of the power MOSFET shown in Embodiment 2 can be appropriately used in accordance with the configurations shown in FIGS. 8 and 9. .

[0097] Since the power MOSFETs shown in FIGS. 8 and 9 have an n-type oxide semiconductor layer in the channel region, it is possible to reduce the on-resistance and to pass a large current. However, since they have an n-type oxide semiconductor layer in the channel region, they are of the depletion type and are in the normally-on state in which current flows even when no voltage is applied to the gate. The power MOSFETs shown in this embodiment can be turned off by applying a negative voltage to the gate 211, and can be turned on by applying a positive voltage to the gate 211. Therefore, it is possible to realize an off state of the power MOSFET having a low on-resistance and capable of passing a large current.

[0098] (Embodiment 4) In this embodiment, the structures and manufacturing methods of the field effect transistors 102 to 104 shown in Embodiment 1 will be described with reference to FIGS. 10 and 11. Since the field effect transistors 102 to 104 may have the same structure, the field effect transistor 102 will be described here as a representative example.

[0099] The field effect transistor 102 shown in FIG. 10 has a gate 251 made of a conductive layer on a substrate 250 is provided, a gate insulating layer 252 is provided on the gate 251, and on the gate insulating layer 252 an i-type or substantially i-type oxide semiconductor layer 253 is provided. A first terminal 254A and a second terminal 254B made of a conductive layer are provided so as to partially cover the oxide semiconductor layer 2 53, and an insulating layer 255 is formed so as to cover the oxide semiconductor layer 253, the first terminal 254A, and the second terminal 254B. The substrate 250 can be appropriately the substrate 200 shown in Embodiment 2.

[0100] The substrate 250 can be appropriately the substrate 200 shown in Embodiment 2.

[0101] For the gate 251, the materials shown in the first gate 201 shown in Embodiment 2 can be appropriately used.

[0102] For the gate insulating layer 252, the materials shown in the gate insulating layer 202 shown in Embodiment 2 can be appropriately used. The thickness of the gate insulating layer 252 can be 50 nm or more and 500 nm or less. By increasing the thickness of the gate insulating layer 252, the gate leakage current can be reduced.

[0103] For the oxide semiconductor layer 253, the metal oxides shown in the oxide semiconductor layer 203 shown in Embodiment 2 can be used. In addition, an oxide semiconductor having an amorphous structure, a polycrystalline structure, or a single crystal structure can be appropriately used. In addition, an oxide semiconductor having a crystal structure in which the c-axis is substantially parallel in the direction perpendicular to the surface can be used. However, since the oxide semiconductor layer 253 is i-type or substantially i-type, the carrier density is 5×10 crystal structure of the oxide semiconductor having a crystal structure in which the c-axis is substantially parallel in the direction perpendicular to the surface can be used. However, since the oxide semiconductor layer 253 is i-type or is substantially i-type, the carrier density is 5×10 14 cm -3 less than, preferably is 1×10 12 cm​​​​-3 less than, more preferably 1×10 11 cm -3 or less. Also, it is preferable that there are few hydrogen and oxygen defects contributing as donors, and the hydrogen concentration is 1×10 16 cm -3 or less is preferable.

[0104] Purified by thoroughly removing hydrogen, reducing oxygen defects and satisfying the stoichiometric ratio The field effect transistor 102 using the oxide semiconductor layer that has been i - type or substantially i - type in the channel region can have an off - current of 1×10 -16 A or less. That is , in the non - conductive state of the field - effect transistor, the oxide semiconductor layer can be regarded as an insulator and circuit design can be carried out. On the other hand, the oxide semiconductor layer 253 in the conductive state is expected to have a higher current supply capacity than the semiconductor layer formed of amorphous silicon . Therefore, the field - effect transistor 102 is an enhancement type and becomes a normally - off state with extremely small leakage current in the off state, having excellent switching characteristics.

[0105] The first terminal 254A and the second terminal 254B can appropriately use the materials shown in the first terminal 204A and the second terminal 204B shown in Embodiment 2.

[0106] The insulating layer 255 is preferably formed of an insulating oxide layer. Representative examples of the insulating oxide layer include a silicon oxide layer, a silicon oxynitride layer, or an aluminum oxide layer. Note that the insulating layer 205 may have a laminated structure of an insulating oxide layer and an insulating nitride layer. Representative examples of the insulating nitride layer include a silicon nitride layer, a silicon oxynitride layer, or an aluminum nitride layer. Insulating layer 2 At 55, by forming a region in contact with the oxide semiconductor layer 253 with an insulating oxide layer, oxygen deficiency in the oxide semiconductor layer can be reduced and the stoichiometric ratio can be satisfied.

[0107] Note that the field effect transistor 102 can take various forms and is not limited to a specific configuration. For example, a multi-gate structure with two or more gates can be applied. Also, a structure can be adopted in which gate electrodes are disposed above and below the channel region. By adopting a configuration in which gates are disposed above and below the channel region, a configuration in which two field effect transistors are connected in parallel can also be achieved.

[0108] Here, a method for manufacturing the field effect transistor 102 shown in FIG. 10 will be described with reference to FIG. 11.

[0109] As shown in FIG. 11(A), a gate 251 is formed on a substrate 250. Next, a gate insulating layer 252 is formed on the gate 251.

[0110] The gate 251 can be appropriately formed by using the method for manufacturing the first gate 201 shown in Embodiment 2. Also, the gate insulating layer 252 can be appropriately formed by using the method for manufacturing the gate insulating layer 202 shown in Embodiment 2. Since an i-type or substantially i-type oxide semiconductor layer is extremely sensitive to interface states and interface charges, by forming the gate insulating layer 252 by high-density plasma CVD using microwaves, interface states can be reduced and interface characteristics can be improved.

[0111] Note that when forming the gate insulating layer 252, by heating the substrate 200, the gate insulating layer ​​​​​​​​​​​Hydrogen, water, hydroxyl groups, hydrides, etc. contained in 252 can be reduced.

[0112] In addition, in order to reduce hydrogen, water, hydroxyl groups, hydrides, etc. contained in the gate insulating layer 252, When forming the gate insulating layer 252 by sputtering, it is preferable to form the gate insulating layer 252 while removing hydrogen, water , hydroxyl groups or hydrides, etc. remaining in the processing chamber. . In order to remove hydrogen, water, hydroxyl groups, hydrides, etc. remaining in the processing chamber, it is preferable to use an adsorption type vacuum pump. Representative examples of adsorption type vacuum pumps are cryopumps, ion pumps, and titanium sublimation pumps. Also, as an exhaust means, a turbo pump with a cold trap added can be used.

[0113] Also, by setting the purity of the sputtering gas used when forming the gate insulating layer 252 to 6N (9 9.9999%) or more, preferably 7N (99.99999%) or more, (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less), hydrogen, water, hydroxyl groups, hydrides, etc. contained in the gate insulating layer 252 can be reduced.

[0114] Next, as shown in FIG. 11(B), an oxide semiconductor layer 253A is formed on the gate insulating layer 202. The oxide semiconductor layer 253A can be formed using a printing method, an inkjet method, or the like. Or, an oxide semiconductor layer is formed on the gate insulating layer 252 by a sputtering method, a CVD method, a coating method, a pulsed laser deposition method, etc., and the above oxide semiconductor layer is etched using the resist formed by a photolithography process as a mask to form an island-shaped oxide semiconductor layer 253A. layer 253A.

[0115] The carrier density of the oxide semiconductor layer depends on the hydrogen concentration of the source gas and the target, the oxygen concentration, the material to be formed and its composition, the heat treatment conditions, etc. of the film formation conditions. By reducing the hydrogen concentration of the oxide semiconductor layer or increasing the oxygen concentration of the oxide semiconductor layer to reduce oxygen deficiency, the oxide semiconductor layer becomes an i-type or substantially an i-type. In the present embodiment, since the treatment for making the oxide semiconductor layer i-type or substantially i-type is performed later, the oxide semiconductor layer 253A may be i-type or n-type.

[0116] When the oxide semiconductor layer is formed by sputtering, by heating the substrate, impurities such as hydrogen, water, hydroxyl groups, and hydrides contained in the oxide semiconductor layer can be reduced. In addition, crystal growth can be promoted in the first heat treatment.

[0117] When the oxide semiconductor layer is formed by sputtering, when the relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more, more preferably 99.9% or more, the impurity concentration in the oxide semiconductor layer can be reduced, and a transistor with high electrical characteristics and reliability can be obtained.

[0118] In addition, by performing a preheating treatment before forming the oxide semiconductor layer, hydrogen, water, hydroxyl groups, hydrides, etc. remaining on the inner wall of the sputtering apparatus, the target surface, and the target material can be removed, so that impurities such as hydrogen, water, hydroxyl groups, and hydrides contained in the oxide semiconductor layer can be reduced.

[0119] Similar to the gate insulating layer 252, before, during, or After formation, it is preferable to use an adsorption-type vacuum pump to remove hydrogen, water, hydroxyl groups, hydrides, etc. remaining in the sputtering apparatus. As a result, since hydrogen, water, hydroxyl groups, hydrides, etc. are exhausted, the concentrations of hydrogen, water, hydroxyl groups, hydrides, etc. contained in the oxide semiconductor layer can be reduced. Next, a first heat treatment is performed to remove impurities such as hydrogen, water, hydroxyl groups, and hydrides contained in the oxide semiconductor layer 253A. That is, at least one of dehydration and dehydrogenation can be performed. In addition, oxygen vacancies in the oxide semiconductor layer 253A are also formed in the first heat treatment. By the first heat treatment, the oxide semiconductor layer from which impurities such as hydrogen, water, hydroxyl groups, and hydrides have been removed is shown as the oxide semiconductor layer 253B in FIG. 11(C). The temperature of the first heat treatment is 400°C or higher and 750°C or lower, preferably 400°C or higher and less than the distortion point of the substrate. The heat treatment apparatus used for the first heat treatment is not particularly limited as the heat treatment apparatus, and it may be equipped with an apparatus that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace, an RTA (Rapid Thermal Anneal) apparatus such as a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA apparatus is an apparatus that performs heat treatment using high-temperature gas.

[0120]

[0121] ​

[0122] In the first heat treatment, it is preferable that nitrogen or a noble gas such as helium, neon, or argon does not contain hydrogen, water, hydroxyl groups, hydrides, or the like. Alternatively, the purity of the nitrogen or noble gas such as helium, neon, or argon introduced into the heat treatment apparatus is 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher (that is, the impurity concentration is 1 ppm or lower, preferably 0.1 ppm or lower).

[0123] In the first heat treatment, the inside of the furnace may be set to a nitrogen atmosphere during heating and the inside of the furnace may be switched to an oxygen atmosphere during cooling. After dehydration or dehydrogenation is performed in a nitrogen atmosphere, the atmosphere is switched to an oxygen atmosphere to supply oxygen to the inside of the oxide semiconductor layer, reduce the hydrogen concentration, and supply oxygen to the oxygen deficiency of the oxide semiconductor layer in which an oxygen deficiency is formed, and it is possible to form a type-i or substantially type-i oxide semiconductor layer.

[0124] Depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer 253A may crystallize and become an oxide semiconductor layer having crystals. For example, it may become an oxide semiconductor layer having crystals with a crystallization rate of 90% or higher, or 80% or higher.

[0125] Depending on the first heating conditions or the material of the oxide semiconductor layer, a crystal structure having crystals with the c-axis substantially parallel in the direction perpendicular to the surface may be formed in the surface layer portion of the amorphous oxide semiconductor layer, and it may become an oxide semiconductor layer.

[0126] Note that the first heat treatment may be performed after forming the first terminal and the second terminal on the oxide semiconductor layer. This may be done.

[0127] Here, the substrate is introduced into an electric furnace, and heat treatment is performed at 450 °C for 1 hour in an inert gas atmosphere such as nitrogen or a rare gas.

[0128] Next, as shown in FIG. 11(C), the first terminal 254A and the second terminal 254B that function as the source electrode and the drain electrode are formed. The first terminal 254A and the second terminal 254B can be formed in the same manner as the first terminal 204A and the second terminal 204B shown in Embodiment 2.

[0129] The first terminal 254A and the second terminal 254B can be formed in the same manner as the first terminal 204A and the second terminal 204B shown in Embodiment 2.

[0130] Next, as shown in FIG. 11(D), an insulating layer 255 is formed over the gate insulating layer 252, the oxide semiconductor layer 253B, the first terminal 254A, and the second terminal 254B. The insulating layer 255 can be formed by a sputtering method, a CVD method, a printing method, a coating method, or the like. Note that when a silicon oxide layer is formed as the insulating layer 255 by a sputtering method, oxygen can be supplied to oxygen vacancies contained in the oxide semiconductor layer 253A generated by the first heat treatment from the silicon oxide layer, oxygen vacancies contributing as donors can be reduced, and a stoichiometric ratio can be satisfied. As a result, an i-type or substantially i-type oxide semiconductor layer 253 can be formed. As a result, an i-type or substantially i-type oxide semiconductor layer 253 can be formed. As a result, an i-type or substantially i-type oxide semiconductor layer 253 can be formed. As a result, an i-type or substantially i-type oxide semiconductor layer 253 can be formed.

[0131] Next, a second heat treatment (preferably 200 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. The second heat treatment is performed on the insulating It may be performed after forming a protective insulating layer or a planarizing insulating layer on the edge layer 255. In this heat treatment more, it is possible to supply oxygen to the oxygen deficiency contained in the oxide semiconductor layer generated by the first heat treatment from the insulating oxide layer of the insulating layer 255, and reduce the oxygen deficiency contributing as a donor so that a composition satisfying the stoichiometric ratio can be obtained. As a result, an oxide semiconductor layer 253 that is more i-typed or substantially i-typed can be formed.

[0132] In this embodiment, a second heat treatment is performed at 250° C. for 1 hour in a nitrogen atmosphere.

[0133] Furthermore, a heat treatment at 100° C. or higher and 200° C. or lower may be performed for 1 hour or more and 30 hours or less in the air. By this heat treatment, the reliability of the field effect transistor can be enhanced.

[0134] By the above steps, a field effect transistor 102 having an i-typed or substantially i-typed oxide semiconductor layer in the channel region, an extremely small off-current, and being of an enhancement type can be manufactured.

[0135] (Embodiment 5) FIG. 12 shows one form of a semiconductor device using the power element shown in Embodiments 1 to 3 as a protection element. When an overvoltage is input to the power supply terminal, the protection element functions so that a current flows through the power element as the protection element and an overcurrent does not flow through the circuit to be protected. The circuit to be protected includes all circuits with low breakdown voltage that are destroyed by the application of an overvoltage. In this embodiment, as an example of the power element, a 4-terminal power MOSFET shown in Embodiments 1 and 2 will be described.

[0136] FIG. 12 is a semiconductor device having a power MOSFET 501, a control circuit 502, a circuit 503 to be protected, an input terminal 504, and an output terminal 505. The control circuit 502 detects an overvoltage applied to the input terminal 5 04 or the output terminal 505, and controls the operation of the power MOS FET 501 serving as a protection element.

[0137] FIG. 13 shows details of the control circuit 502. The control circuit 502 includes an overvoltage detection circuit 511, an inverter 512, a positive power supply 513, switch transistors 514, 515, 5 16, a capacitive element 517, a negative voltage generation circuit 518, an oscillation circuit 519, a frequency division circuit 520, a delay circuit 521, and an AND circuit 522. The positive power supply 513 corresponds to the high voltage power supply source 108 shown in Embodiment 1. The switch transistors 514, 515, 516 respectively correspond to the field effect transistors 102, 103, 104 shown in Embodiment 1. The capacitive element 517 corresponds to the capacitive element 105 shown in Embodiment 1. Also, the negative voltage generation circuit 518 corresponds to the low voltage power supply source 109 shown in Embodiment 1. The oscillation circuit 519, the frequency division circuit 520, the delay circuit 521, and the AND circuit 522 correspond to the refresh control circuit 107 shown in Embodiment 1. Note that the control circuit 502 is not limited to this configuration.

[0138] Next, the operations of the control circuit 502 and the power MOSFET 501 shown in FIG. 13 will be described. The overvoltage detection circuit 511 is a circuit that operates when an overvoltage that greatly exceeds the normal power supply voltage is input to the input terminal 50 4, and in this embodiment, it has a function of outputting a high -level pulse when an overvoltage is input.

[0139] ​The output terminal of the overvoltage detection circuit 511 is connected to the gate terminal of the switch transistor 514 and the input terminal of the inverter 512. The output terminal of the inverter 512 is connected to the gate terminal of the switch transistor 515. Thus, when an overvoltage is input, the switch transistor 514 turns on, and the gate terminal of the power MOSFET 501 is connected to the positive power supply 513, causing the power MOSFET 501 to turn on. As a result, current flows from the input terminal 504 to the output terminal 505, preventing an overcurrent from flowing through the protected circuit 503 shown in FIG. 12. When no overvoltage is applied, the output of the overvoltage detection circuit 511 is low, the switch transistor 514 is off, and the switch transistor 515 is on. The negative voltage generation circuit 518 is composed of a charge pump circuit or the like shown in FIG. 17 and generates a negative voltage. Since the protection circuit is not a circuit that operates frequently, it is not appropriate in terms of power consumption to constantly pass a large current.

[0140] Therefore, it is effective in reducing power consumption to charge the capacitor element 517 with a small current capacity. Therefore, power consumption can be reduced by intermittently charging the capacitor element 517 from the negative voltage generation circuit 518 via the switch transistor 516. The oscillation signal obtained by the oscillation circuit 519 is divided by the division circuit 520, and the divided signal is supplied to the gate terminal of the switch transistor 516.

[0141] That is, one of the output terminals of the division circuit 520 is connected to the first input terminal of the AND circuit 522. Also, one of the output terminals of the division circuit 520... ... ... ...

[0142] ... ... ... The other output terminal is connected to the second input terminal of the AND circuit 522 via the delay circuit 521. In this way, a pulse width corresponding to the delay time of the delay circuit 521 can be obtained, and a pulse similar to the output of the frequency divider circuit 5 20 can be obtained. By using this pulse, the gate terminal of the switch transistor 516 can be controlled.

[0143] The oscillation circuit 519 can use a general oscillation circuit, such as a ring oscillator, etc., but its type is not limited. Also, the frequency divider circuit 520 can use flip-flops. The delay circuit 521 can use a circuit using an inverter, a CR delay circuit, etc., but is not particularly limited. Also, other methods can be used to form the pulse.

[0144] In this way, a negative voltage is held in the capacitive element 517, and when no overvoltage is applied, a negative voltage is applied to the power MOSFET 501 via the switch transistor 515. While a negative voltage is applied to the gate terminal of the power MOSFET 501, the power MOS FET 501 turns off and no current flows.

[0145] FIG. 14 shows a semiconductor device in which a power MOSFET is connected in series with a circuit to be protected. Different from FIG. 1 2, when an overvoltage is applied to the input terminal, the power MOSFET 601 turns on to prevent an overvoltage from being applied to the circuit 603 to be protected.

[0146] The semiconductor device shown in FIG. 14 includes a power MOSFET 601, a control circuit 602, a circuit 603 to be protected, an input terminal 604, and an output terminal 605. The control circuit 602 is connected to the input terminal Detects an overvoltage applied to the output terminal 604 or 605 and controls the power MOSFET601 that serves as a protection element.

[0147] The details of the control circuit 602 are shown in FIG. 15. The control circuit 602 includes an overvoltage detection circuit 611, an inverter 612, a positive power supply 613, switch transistors 614, 615, 616, a capacitive element 6 17, a negative voltage generation circuit 618, an oscillation circuit 619, a frequency division circuit 620, a delay circuit 621, and an AND circuit 622. The positive power supply 613 corresponds to the high voltage generation source 1 08 shown in the first embodiment. The switch transistors 614, 615, and 616 respectively correspond to the field effect transistors 103, 102, and 104 shown in the first embodiment. The capacitive element 617 corresponds to the capacitive element 105 shown in the first embodiment. The negative voltage generation circuit 618 corresponds to the low voltage generation source 109 shown in the first embodiment. The oscillation circuit 619, the frequency division circuit 620, the delay circuit 621, and the AND circuit 622 correspond to the refresh control circuit 107 shown in the first embodiment. Note that the control circuit 602 is not limited to this configuration.

[0148] Next, the operations of the control circuit 602 and the power MOSFET 601 shown in FIG. 15 will be described. The overvoltage detection circuit 611 is a circuit that operates when an overvoltage that greatly exceeds the normal power supply voltage is input to the input terminal 60 4. In this embodiment, it has a function of outputting a high -level pulse when an overvoltage is input.

[0149] The output terminal of the overvoltage detection circuit 611 is connected to the gate terminal of the switch transistor 615 and the inverter 612. The output terminal of the inverter 612 is connected to the switch transistor 614 ​is connected to the gate terminal. Thus, when an overvoltage is input to the input terminal 604, the switch transistor 615 turns on, and the gate terminal of the power MOSFET 601 is connected to the negative voltage generation circuit 618 and turns off. As a result, the input terminal 604 and the circuit to be protected 603 are disconnected, preventing an overcurrent from flowing through the circuit to be protected 603. The negative voltage generation circuit 618 is composed of a charge

[0150] pump circuit or the like shown in FIG. 17 and generates a negative voltage. When no overvoltage is applied, the output of the overvoltage detection circuit 611 is low, the switch transistor 615 is off, the switch transistor 614 is on, and the gate terminal of the power MOSFET 601 is connected to the capacitor element 617. Since a positive voltage is held in the

[0151] capacitor element 617 from the positive power supply as described later, the power MOSFET 601 turns on. Since the protection circuit is not a circuit that operates frequently, it is not appropriate in terms of power consumption to constantly pass a large current. Therefore, it is effective in reducing power consumption to charge the capacitor element 617 with a small current capacity.

[0152] The oscillation signal obtained by the oscillation circuit 619 is divided by the division circuit 620, and the divided signal is supplied to the gate terminal of the switch transistor 616. That is, one of the output terminals of the division circuit 620 is connected to the first input terminal of the AND circuit 622. Also, the other of the output terminals of the division 。In this way, a pulse width corresponding to the delay time of the delay circuit 621 is obtained, and a pulse having the same period as the output of the frequency division circuit 620 can be obtained. By using this pulse, the gate terminal of the switch transistor 616 can be controlled.

[0153] The oscillation circuit 619 can use a general oscillation circuit such as a ring oscillator, etc., but its type is not limited. Also, the frequency division circuit 620 can use a flip-flop . The delay circuit 621 can use a circuit using an inverter, a circuit using a CR delay circuit, etc , but is not particularly limited. Also, other methods can be used for forming the pulse .

[0154] In this way, a positive voltage is held in the capacitive element 617, and when no overvoltage is applied, a positive voltage is applied to the power MOSFET 601 via the switch transistor 614 . While a positive voltage is applied to the gate terminal of the power MOSFET 601, the power MOS FET 601 turns on, and the input terminal 604 and the protected circuit 603 shown in FIG. 14 are connected .

[0155] FIG. 16 shows a configuration example of the overvoltage detection circuits 511 and 611. FIG. 16 includes a diode chain in which transistors 70 1 to 705 are diode-connected, and transistors 707, resistor 70 6, and inverter 708. When the number of stages of the diode chain is n stages, and the threshold voltage of the transistor is Vth, then n is set so that the normal operating voltage < nVth, and when an overvoltage is applied, transistors 701 to 705 turn on, and a current flows through the diode chain. When transistor 705 turns on, the transistor 707 is also turned on, and a high level is output from the output of the inverter 708.

[0156] In this embodiment, a normally-on power MOSFET using an oxide semiconductor layer having a large bandgap in the channel region is used as a protection element to prevent destruction of the semiconductor device due to application of an overvoltage.

[0157] (Embodiment 6) In this embodiment, the use of the power device described in the above embodiment will be described. The semiconductor device, which is the power device described in the above embodiment, can be used as a protection circuit for a battery of an electronic device such as a display capable of displaying an image of a computer or the like, or a protection circuit for a battery provided in vehicles (such as bicycles) driven by the power of an electromagnetic cooker or a fixed power supply.

[0158] With reference to FIG. 18, an example of an application example of a semiconductor device that is a power device and functions as a protection circuit will be described.

[0159] FIG. 18(A) shows an electromagnetic cooker 1000 as an application example including a semiconductor device that functions as a protection circuit. The electromagnetic cooker 1000 heats a cooker or the like by utilizing electromagnetic induction generated by passing a current through a coil unit 1001. The electromagnetic cooker 1000 also includes a battery 1002 for supplying a current to be passed through the coil unit 1001, a semiconductor device 1003 that functions as a protection circuit, and a solar cell 1004 for charging the battery 1002. In FIG. 18(A), a solar cell 1004 is shown as a means for charging the battery 1002, but a configuration for charging by other means may also be used. The semiconductor that functions as a protection circuit The conductor device 1003 can reduce the application of overvoltage to the battery 1002 and achieve low power consumption when the protection circuit is not operating. It can achieve low power consumption when not in operation.

[0160] FIG. 18(B) shows an electric bicycle 1010 as an application example equipped with a semiconductor device functioning as a protection circuit. The electric bicycle 1010 obtains power by passing an electric current through the motor unit 1011. Also, the electric bicycle 1010 has a battery 1012 for supplying the electric current flowing through the motor unit 1011, and a semiconductor device 1013 functioning as a protection circuit. In FIG. 18(B), although not particularly shown as a means for charging the battery 1012, a configuration in which a separate generator or the like is provided for charging may be used. The semiconductor device 1013 functioning as a protection circuit can reduce the application of overvoltage to the battery 1012 during charging and can achieve low power consumption when the function of the protection circuit is not operating. In FIG. 18(B), a pedal is shown, but it may not be provided. In FIG. 18(B), although not particularly shown as a means for charging the battery 1012, a configuration in which a separate generator or the like is provided for charging may be used. The semiconductor device 1013 functioning as a protection circuit can reduce the application of overvoltage to the battery 1012 during charging and can achieve low power consumption when the function of the protection circuit is not operating. In FIG. 18(B), a pedal is shown, but it may not be provided. In FIG. 18(B), although not particularly shown as a means for charging the battery 1012, a configuration in which a separate generator or the like is provided for charging may be used. The semiconductor device 1013 functioning as a protection circuit can reduce the application of overvoltage to the battery 1012 during charging and can achieve low power consumption when the function of the protection circuit is not operating. In FIG. 18(B), a pedal is shown, but it may not be provided. The semiconductor device 1013 functioning as a protection circuit can reduce the application of overvoltage to the battery 1012 during charging and can achieve low power consumption when the function of the protection circuit is not operating. In FIG. 18(B), a pedal is shown, but it may not be provided. In FIG. 18(B), a pedal is shown, but it may not be provided.

[0161] FIG. 18(C) shows an electric vehicle 1020 as an application example equipped with a semiconductor device functioning as a protection circuit. The electric vehicle 1020 obtains power by passing an electric current through the motor unit 1021. Also, the electric vehicle 1020 has a battery 1022 for supplying the electric current flowing through the motor unit 1021, and a semiconductor device 1023 functioning as a protection circuit. In FIG. 18(C), although not particularly shown as a means for charging the battery 1022, a configuration in which a separate generator or the like is provided for charging may be used. The semiconductor device 1023 functioning as a protection circuit can reduce the application of overvoltage to the battery 1022 during charging and can achieve low power consumption when the function of the protection circuit is not operating. In FIG. 18(C), although not particularly shown as a means for charging the battery 1022, a configuration in which a separate generator or the like is provided for charging may be used. The semiconductor device 1023 functioning as a protection circuit can reduce the application of overvoltage to the battery 1022 during charging and can achieve low power consumption when the function of the protection circuit is not operating. In FIG. 18(C), although not particularly shown as a means for charging the battery 1022, a configuration in which a separate generator or the like is provided for charging may be used. The semiconductor device 1023 functioning as a protection circuit can reduce the application of overvoltage to the battery 1022 during charging and can achieve low power consumption when the function of the protection circuit is not operating. The semiconductor device 1023 functioning as a protection circuit can reduce the application of overvoltage to the battery 1022 during charging and can achieve low power consumption when the function of the protection circuit is not operating. When the function of the protection circuit is not operating, power consumption can be reduced.

[0162] In addition, in this embodiment, the content described in each figure can be freely combined, replaced, etc. as appropriate with the content described in another embodiment. It can be freely combined, replaced, etc. as appropriate with the content described in another embodiment.

Claims

1. an oxide semiconductor layer; A first conductive layer to a fourth conductive layer, the oxide semiconductor layer has a region located above the first conductive layer, the second conductive layer has a region located above the oxide semiconductor layer, the third conductive layer has a region located above the oxide semiconductor layer, the fourth conductive layer has a region located above the oxide semiconductor layer, the first conductive layer is electrically connected to the oxide semiconductor layer; the second conductive layer has a region in contact with the first conductive layer, the third conductive layer is electrically connected to the oxide semiconductor layer; the third conductive layer has a region in contact with an upper surface of the first insulating layer, the first insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; the fourth conductive layer has a function as a gate electrode; the fourth conductive layer has a region overlapping with the first conductive layer with a channel formation region of the oxide semiconductor layer interposed therebetween, In a plan view, the third conductive layer does not overlap with the first conductive layer, an insulating surface is in contact with a lower surface of the oxide semiconductor layer, the lower surface being in contact with the third conductive layer in a plan view; Semiconductor device.

2. an oxide semiconductor layer; A first conductive layer to a fourth conductive layer, the oxide semiconductor layer has a region located above the first conductive layer, the second conductive layer has a region located above the oxide semiconductor layer, the third conductive layer has a region located above the oxide semiconductor layer, the fourth conductive layer has a region located above the oxide semiconductor layer, the first conductive layer is electrically connected to the oxide semiconductor layer; the second conductive layer has a region in contact with the first conductive layer and a region in contact with the oxide semiconductor layer, the third conductive layer is electrically connected to the oxide semiconductor layer; the third conductive layer has a region in contact with an upper surface of the first insulating layer, the first insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; the fourth conductive layer has a function as a gate electrode; the fourth conductive layer has a region overlapping with the first conductive layer with a channel formation region of the oxide semiconductor layer interposed therebetween, In a plan view, the third conductive layer does not overlap with the first conductive layer, an insulating surface is in contact with a lower surface of the oxide semiconductor layer, the lower surface being in contact with the third conductive layer in a plan view; Semiconductor device.

3. an oxide semiconductor layer; A first conductive layer to a fourth conductive layer, the oxide semiconductor layer has a region located above the first conductive layer, the second conductive layer has a region located above the oxide semiconductor layer, the third conductive layer has a region located above the oxide semiconductor layer, the fourth conductive layer has a region located above the oxide semiconductor layer, the first conductive layer is electrically connected to the oxide semiconductor layer; the second conductive layer has a region in contact with the first conductive layer, the third conductive layer is electrically connected to the oxide semiconductor layer; the third conductive layer has a region in contact with an upper surface of the first insulating layer, the first insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; the fourth conductive layer has a function as a gate electrode; the fourth conductive layer has a region overlapping with the first conductive layer with a channel formation region of the oxide semiconductor layer interposed therebetween, the second conductive layer, the third conductive layer, and the fourth conductive layer are spaced apart from one another in a plan view; In a plan view, the third conductive layer does not overlap with the first conductive layer, an insulating surface is in contact with a lower surface of the oxide semiconductor layer, the lower surface being in contact with the third conductive layer in a plan view; Semiconductor device.

4. an oxide semiconductor layer; A first conductive layer to a fourth conductive layer, the oxide semiconductor layer has a region located above the first conductive layer, the second conductive layer has a region located above the oxide semiconductor layer, the third conductive layer has a region located above the oxide semiconductor layer, the fourth conductive layer has a region located above the oxide semiconductor layer, the first conductive layer is electrically connected to the oxide semiconductor layer; the second conductive layer has a region in contact with the first conductive layer and a region in contact with the oxide semiconductor layer, the third conductive layer is electrically connected to the oxide semiconductor layer; the third conductive layer has a region in contact with an upper surface of the first insulating layer, the first insulating layer having a region in contact with an upper surface of the oxide semiconductor layer; the fourth conductive layer has a function as a gate electrode; the fourth conductive layer has a region overlapping with the first conductive layer with a channel formation region of the oxide semiconductor layer interposed therebetween, the second conductive layer, the third conductive layer, and the fourth conductive layer are spaced apart from one another in a plan view; In a plan view, the third conductive layer does not overlap with the first conductive layer, an insulating surface is in contact with a lower surface of the oxide semiconductor layer, the lower surface being in contact with the third conductive layer in a plan view; Semiconductor device.

5. In any one of claims 1 to 4, the oxide semiconductor layer contains In, Ga, and Zn; Semiconductor device.

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