Semiconductor device, semiconductor module, and manufacturing method

Abstract

In one embodiment, the semiconductor device (1) comprises: a semiconductor chip (2) configured for a voltage of at least 0.6 kV and having upper contact regions (21) on a chip top surface (20); a first electrical wiring layer (3) in electrical contact with the upper contact region (21), the first electrical wiring layer (3) having first contact regions (31) electrically assigned to the upper contact region (21); and a second electrical wiring layer (4) located on a side of the first electrical wiring layer (3) remote from the upper contact region (21) and having second contact regions (42) electrically assigned to the upper contact region (31), the second contact regions (42) being configured as external contact regions, at least one of the second contact regions (42) having a different shape than the assigned one of the upper contact regions (21) when viewed in a top view of the chip top surface (20).

Description

Technical Field

[0001] A semiconductor device and a semiconductor module including such a semiconductor device are provided. A method for manufacturing such a semiconductor device is also provided.

Background Art

[0002] European Patent Application Publication No. 2 988 328 mentions a power semiconductor module.

[0003] German Patent Application Publication No. 10 2014 218 240 discloses a power device integrated in a printed circuit board.

[0004] German Patent Application Publication No. 10 2015 115999, US Patent Application Publication No. 2010 / 0078789, US Patent No. 8 975 732, German Utility Model No. 20 2011 110547, and European Patent Application Publication No. 3 534 394 mention electrical devices.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved is to provide a semiconductor device that can be used at a relatively high voltage.

Means for Solving the Problems

[0006] This object is achieved, inter alia, by a semiconductor device, a semiconductor module, and a method as defined in the independent claims. Exemplary further developments form the subject matter of the dependent claims.

[0007] For example, the semiconductor device includes at least one intermediate electrical wiring layer in an insulator, and the at least one intermediate electrical wiring layer is located between a chip upper contact region of a semiconductor chip and a second contact region for external contact of the semiconductor device.

[0008] With at least one intermediate electrical wiring layer, the shape of the second contact region can be designed independently of the shape of the upper chip contact region. Furthermore, the distance between the upper chip contact region and the outer surface of the semiconductor device can be increased. Thus, a high voltage can be provided to the semiconductor device, and the second contact region can be designed in various ways for electrical connection of the semiconductor device.

[0009] In at least one embodiment, the semiconductor device is · a semiconductor chip configured for a voltage of at least 0.6 kV and having an upper contact region on the chip top surface, · a first electrical wiring layer in electrical contact with the upper contact region having a first contact region electrically assigned to the upper contact region, · a second electrical wiring layer located on the side far from the upper contact region of the first electrical wiring layer and having a second contact region electrically assigned to the upper contact region, the second contact region being configured as an external contact region and at least one of the second contact regions has a different shape from the assigned one of the upper contact regions when viewed in a top view of the chip top surface.

[0010] For example, at least one semiconductor chip is selected from the following group, namely metal-oxide-semiconductor field-effect transistor (MOSFET), metal-insulator-semiconductor field-effect transistor (MISFET), insulated-gate bipolar transistor (IGBT), bipolar junction transistor (BJT), thyristor, gate turn-off thyristor (GTO), gate commutated thyristor (GCT), junction gate field-effect transistor (JFET), and diode. When there are multiple semiconductor chips, all the semiconductor chips may be of the same type, or different types of semiconductor chips may exist.

[0011] For example, the semiconductor device is a power device that converts direct current from a battery into alternating current for an electric motor, also in vehicles such as hybrid vehicles or plug-in electric vehicles, or in railways such as commuter trains.

[0012] For example, the semiconductor chip, and thus the semiconductor device, is configured to match a maximum voltage of at least 0.6 kV, or at least 1.2 kV, or at least 1.6 kV. Alternatively, or in addition, the semiconductor chip, and thus the semiconductor device, is configured to match a maximum current of at least 1 A, or at least 20 A, or at least 50 A, and the maximum current may be up to 1000 A or up to 200 A.

[0013] For example, the first electrical wiring layer is an electrical wiring layer adjacent to the upper surface of the chip. One or more electrical insulating layers are present between the upper surface of the chip and the first electrical wiring layer. Through this insulating layer, an electrical through contact contacts the upper contact region of the semiconductor chip with the first contact region. The first contact region may be a structured metallization layer applied on at least one electrical insulating layer.

[0014] Similarly, at least one electrical insulating layer is present between the first electrical wiring layer and the second electrical wiring layer, and the electrical through contact extends through at least one electrical insulating layer. The second electrical wiring layer is the uppermost electrical wiring layer applied to the outer surface of the semiconductor device. For example, the second electrical wiring layer may be an additional structured metallization layer applied on the uppermost electrical insulating layer. Therefore, the second electrical wiring layer is the electrical wiring layer farthest from the upper surface of the chip. The second contact region can contact the semiconductor device to the outside, for example, to a circuit board.

[0015] For example, at least one or a part or all of the second contact region has a different shape from the upper contact region assigned to each of the upper contact regions when viewed in a top view of the upper surface of the chip. It is also possible that at least one or a part or all of the second contact region has a different shape from the first contact region assigned to each of the first contact regions.

[0016] According to at least one embodiment, the semiconductor device further includes one or more third electrical wiring layers. At least one third electrical wiring layer is located between the first electrical wiring layer and the second electrical wiring layer. Further, at least one third electrical wiring layer is electrically connected to each of the first electrical wiring layer and the second electrical wiring layer by electrical through contacts extending through particularly adjacent additional insulating layers. At least one third electrical wiring layer includes, for example, a third contact region formed by at least one additional structured metallization layer.

[0017] According to at least one embodiment, starting from the upper surface of the chip, there is an arrangement of the upper contact region of the semiconductor chip - an insulating layer having an electrical through contact - the first contact region of the first electrical wiring layer - an insulating layer having an electrical through contact - the second contact region of the second electrical wiring layer. When there are N third electrical wiring layers, there is an arrangement of the upper contact region of the semiconductor chip - an insulating layer having an electrical through contact - the first contact region of the first electrical wiring layer - N times (an insulating layer having an electrical through contact - the third contact region of the third electrical wiring layer) - an insulating layer having an electrical through contact - the second contact region of the second electrical wiring layer, where N is a natural number of 1 or more. In particular, N = 1 or N = 2 or N = 3. For example, 1 ≤ N ≤ 20, 1 ≤ N ≤ 5, 2 ≤ N ≤ 5 apply.

[0018] For example, there is exactly one electrical insulating layer between each electrical wiring layer and between the upper contact region and the first electrical wiring layer.

[0019] According to at least one embodiment, starting from the upper contact region or the first contact region and heading towards the second contact region, the shape of the respectively assigned contact region becomes more similar to the second contact region, for example, from the third electrical wiring layer to the third electrical wiring layer and finally towards the second contact region. Therefore, the shape of the intermediate electrical wiring layer can be gradually changed to approximate the second contact region.

[0020] According to at least one embodiment, the number of upper contact regions is the same as the number of contact regions in each electrical wiring layer. In other words, from the chip to the second contact region, the number of contact regions does not change. For example, starting from the upper contact region to the second contact region, there can be a one-to-one assignment of contact regions from electrical wiring layer to electrical wiring layer. For example, the contact region of one wiring layer is electrically connected to the contact region of the adjacent wiring layer by one or more electrical through contacts in any case. The same applies to the upper contact region and the first contact region.

[0021] According to at least one embodiment, the thickness of the insulating layer between wiring layers and between the upper contact region and the first wiring layer is in each case at most 200 μm or at most 120 μm. Instead of this, or in addition, the thickness is at least 10 μm or at least 50 μm or at least 80 μm.

[0022] According to at least one embodiment, at least one or some or each of the wiring layers includes one, two, or more than three contact regions.

[0023] It is possible to assign the contact regions of different wiring layers to one another according to their sizes. For example, the largest upper contact region is assigned to the largest first contact region, the largest second contact region, and the largest third contact region (if present), the smallest upper contact region is assigned to the smallest first contact region, the smallest second contact region, and the smallest third contact region (if present), and so on. These assignments may be one-to-one assignments.

[0024] For example, the smallest upper contact region and the smallest second contact region are gate contacts. "Small" and "large" refer, for example, to the area content of the respective contact regions, that is, for example, the size of the region to which the respective metallization is applied.

[0025] According to at least one embodiment, when viewed in a top view of the upper surface of the chip, at least one of the second contact regions overlaps any one of the upper contact regions for up to 20% or up to 10% or up to 5% of the size of the respective second contact region. That is, each second contact region and the assigned upper contact region do not largely overlap when viewed in the top view. This can apply to exactly one of the second contact regions, or some of the second contact regions, or all of the second contact regions.

[0026] According to at least one embodiment, when viewed in a top view of the chip top surface, at least one of the second contact regions is located completely outside of each upper contact region. That is, each second contact region and the assigned upper contact region are separated and thus do not overlap at all when viewed in a top view. This can apply to exactly one of the second contact regions, or some of the second contact regions, or all of the second contact regions.

[0027] According to at least one embodiment, a first second contact region of the second contact regions extends partially or completely around a second second contact region of the second contact regions when viewed in a top view of the chip top surface. Thus, when viewed in a top view, the second second contact region of the second contact regions can be completely surrounded by the first second contact region of the second contact regions.

[0028] According to at least one embodiment, a first second contact region of the second contact regions extends coaxially around a second second contact region of the second contact regions. Thus, each second contact region is arranged in a rotationally symmetric and / or point-symmetric manner when viewed in a top view. Such a coaxial design can achieve low parasitic inductance, as well as improvement of shielding and suppression of stray capacitance.

[0029] The fact that the first and second second contact regions in the second contact region are coaxially arranged means, for example, that the first upper contact region and the second upper contact region in the upper contact region are of a point-symmetric shape and have the same point-symmetric center. Instead of this, or in addition to this, this may mean that the first second contact region and the second second contact region in the second contact region have the same basic shape, such as a rectangle or a square or a hexagon or an octagon or a circle, when viewed in a top view, and these basic shapes are oriented in the same way, for example, have corresponding corners on the same straight line passing through a common point-symmetric center. It is possible to map the lines around the first and second second contact regions in the second contact region to each other by uniform expansion.

[0030] For example, the first second contact region in the second contact region may be a frame around the second second contact region in the second contact region and may be a source or emitter external contact pad. For example, the first second contact region in the second contact region is the largest second contact region in the second contact region. Therefore, the second second contact region in the second contact region may be the smallest external contact pad and may be a gate contact pad.

[0031] Therefore, different external electrical contact regions of the semiconductor device can be realized by the first second contact region and the second second contact region in the second contact region.

[0032] According to at least one embodiment, the upper contact region assigned to the second second contact region in the second contact region is located at the edge of the chip top surface when viewed in a top view of the chip top surface. Therefore, while the upper contact regions are arranged in an asymmetric manner, the second contact regions may be arranged in a point-symmetric manner.

[0033] According to at least one embodiment, when viewed in a top view of the chip top surface, the third second contact region among the second contact regions is L-shaped, the fourth second contact region among the second contact regions is rectangular, and is located, for example, within a notch of the third second contact region among the second contact regions at a corner of the second wiring layer.

[0034] According to at least one embodiment, the upper contact region assigned to the fourth second contact region among the second contact regions is located at the central portion of an edge such as the longitudinal edge of the chip top surface.

[0035] According to at least one embodiment, when viewed in a top view of the chip top surface, the fifth second contact region and the sixth second contact region among the second contact regions are rectangles extending parallel to each other.

[0036] According to at least one embodiment, also when viewed in a top view of the chip top surface, the upper contact region assigned to the fifth second contact region among the second contact regions is U-shaped and is located adjacent to all of the four edges of the chip top surface, and the upper contact region assigned to the sixth second contact region among the second contact regions is located outside the sixth second contact region among the second contact regions.

[0037] According to at least one embodiment, the upper contact regions are arranged in a symmetric manner. For example, when viewed in a top view of the chip top surface, there is one or two mirror symmetry axes with respect to the upper contact regions. As an alternative, the upper contact regions may be arranged in an asymmetric manner, that is, without having mirror symmetry or point symmetry in particular.

[0038] According to at least one embodiment, the semiconductor device is a chip scale package. This may mean that the overall size of the semiconductor device is 130% or less or 120% or less of the size of the chip top surface as seen in the top view of the chip top surface. Alternatively, or in addition, this may mean that the semiconductor device comprises exactly one semiconductor chip.

[0039] According to at least one embodiment, the total size of all the second contact regions combined is larger than the total size of the upper contact region or the size of the chip top surface. Thus, by having at least one intermediate wiring layer, fan-out and / or expansion from the upper contact region to the second contact regions can be achieved.

[0040] According to at least one embodiment, the thickness of the electrical wiring layer and / or the upper contact region is in each case at least 1 μm or at least 20 μm or at least 40 μm. Alternatively, the thickness is at most 200 μm or at most 100 μm. It is possible to make the upper contact region thinner than the first and third contact regions and the second contact region thicker than the first and third contact regions.

[0041] According to at least one embodiment, the diameter of the electrical through contact is in each case 20 μm or more and 200 μm or less. For example, this diameter is about 0.1 mm.

[0042] A semiconductor module is further provided. The semiconductor module comprises a semiconductor device as shown in relation to at least one of the above-described embodiments. Thus, the features of the semiconductor module are also disclosed for the semiconductor device and vice versa.

[0043] In at least one embodiment, the semiconductor module comprises one or more semiconductor devices and an electrical carrier. The second contact region is connected to at least one of the electrical contact surface or the thermal contact surface of the electrical carrier.

[0044] A method for manufacturing a semiconductor device is further provided. By this method, a semiconductor device as shown in relation to at least one of the above-described embodiments is produced. Thus, the features of the semiconductor device are also disclosed for the method, and vice versa.

[0045] In at least one embodiment, the method is for manufacturing a semiconductor device. The method comprises the following steps, namely · providing a semiconductor chip configured for a voltage of at least 0.6 kV and having an upper contact region on the chip top surface, · applying a dielectric material for a first insulating layer on the upper contact region, · forming a first electrical through contact through the first insulating layer and forming a first electrical wiring layer having a first contact region electrically assigned to the upper contact region on the first insulating layer, · optionally, applying at least one dielectric material for at least one third insulating layer on the first electrical wiring layer, forming a third electrical through contact through the at least one third insulating layer, and forming at least one third electrical wiring layer having a third contact region electrically assigned to the first contact region on the at least one third insulating layer, · applying a dielectric material for a second insulating layer on the first electrical wiring layer or on the uppermost third electrical wiring layer (if present), and · forming a second electrical through contact through the second insulating layer and forming a second electrical wiring layer having a second contact region electrically assigned to the upper contact region and configured as an external contact region of the semiconductor device on the second insulating layer including, for example, in the order described above, At least one of the second contact regions has a different shape from one of the assigned upper contact regions as seen in a top view of the chip top surface.

[0046] In at least one embodiment, the method is for manufacturing a semiconductor device. The method includes the following steps, namely · providing a semiconductor chip configured for a voltage of at least 0.6 kV and having an upper contact region on the chip top surface, · applying an insulating layer, as well as a first electrical wiring layer, a second electrical wiring layer, and at least one third electrical wiring layer on the semiconductor chip including, for example, in the order described above, · the first electrical wiring layer is in electrical contact with the upper contact region and has a first contact region electrically assigned to the upper contact region, · the second electrical wiring layer is located on the side far from the upper contact region of the first electrical wiring layer and has a second contact region electrically assigned to the upper contact region, and the second contact region is configured as an external contact region, · at least one third electrical wiring layer is located between the first electrical wiring layer and the second electrical wiring layer, is electrically connected to the first electrical wiring layer and the second electrical wiring layer, and has a third contact region, · the semiconductor chip is a power metal-insulator field-effect transistor (MISFET) or a power insulated-gate bipolar transistor (IGBT), · the first, second, and third wiring layers are each separated from one another by one of the insulating layers made of a dielectric material in each case, · at least one of the second contact regions has a different shape from one of the assigned upper contact regions as seen in a top view of the chip top surface, · The first second contact region of the second contact regions, which has a shape different from one of the assigned ones in the upper contact region, extends completely around the second second contact region of the second contact regions, which has a shape different from one of the assigned ones in the upper contact region, as seen in the top view of the chip top surface.

[0047] According to the semiconductor device and semiconductor module described in this specification, it is not necessary for the shape of the upper contact region and the shape of the external electrical contact regions such as the second contact region to correspond. Therefore, while it becomes possible to design the upper contact region to be optimal for the characteristics of the semiconductor chip, the second contact region as well as the intermediate contact region can be designed quite independently according to specific requirements of the background of the application such as the available physical space. Therefore, geometric considerations, such as electrical considerations regarding voltage, current, and insulation, as well as thermal considerations such as heat conduction and heat exchange, can be taken into account simultaneously. For example, by the coaxial design of the second contact region, low parasitic inductance, as well as improvement of shielding, improvement of suppression of stray capacitance, and / or reduction of stray inductance can be achieved. Therefore, by making at least one of the second contact regions have a different shape compared to one of the assigned ones in the upper contact region, optimizations in various aspects that are impossible when there is no intermediate first electrical wiring layer and probably no third electrical wiring layer either can be achieved.

[0048] The semiconductor devices, semiconductor modules, and methods described in this specification will be described in more detail below by way of exemplary embodiments with reference to the drawings. The same elements in the individual figures are denoted by the same reference numerals. However, the relationships between the elements are not shown to scale; rather, the individual elements may be shown exaggerated for the sake of understanding.

[0049] Brief Description of the Drawings

Brief Description of the Drawings

[0050]

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DETAILED DESCRIPTION OF THE INVENTION

[0051] In FIGS. 1 and 2, an improved semiconductor device 9 is shown. The improved semiconductor device 9 includes a semiconductor chip 2 embedded in an insulator 6. On the chip top surface 20, the semiconductor chip 2 includes an upper contact region 21. In the lateral direction, i.e., the direction parallel to the chip top surface 20, the semiconductor chip 2 is embedded in the insulating embedded portion 60 of the insulator 6.

[0052] Starting from the upper contact region 21, a first electrical via contact 71 extends through the first insulating layer 61 of the insulator 6. By the via contact 71, the upper contact region 21 is electrically connected to the first contact region 31 of the first electrical wiring layer 3 located on the main body top surface 66 of the insulator 6. As an alternative, the semiconductor chip 2 can be applied on a substrate 8, and the side surface of the substrate 8 can be in contact with the insulator 6.

[0053] Chip-scale packaging (abbreviated as CSP) has originated from the manufacturing of conventional printed circuit boards (PCBs) and has originally been conceived mainly for the integration (also called system in package (SiP)) of small and heterogeneous microelectronic components and / or optical components for consumer electronic devices. However, a package such as that shown in FIG. 1 is not suitable for high voltages exceeding, for example, 0.6 kV.

[0054] Chip scale packaging can offer various advantages over TO packages, QFN packages, and other surface mount packages, such as improved heat removal, elimination of wire bonding, and fewer parasitics, and can provide an alternative route for the assembly of power modules, such as assembly without a clean room. Another important advantage of such an embedded solution is the design freedom to fan out the contact area, also called bond pads, and integrate multilayer signal paths of any shape and complexity as needed. This enables the realization of low-inductance interconnections, the integration of sensors and controllers with a large number of I / O channels, and the realization of a super-small package that does not require wire bonding, which also results in a flat layout and / or geometric shape that is beneficial for a double-sided cooling design. Finally, the development of such technologies may impact the current semiconductor power module value chain, i.e., chip manufacturers may adopt this technology, making the current state of the art in power module design and assembly unsustainable.

[0055] One obvious advantage of CSP is that it can fan out chip pad contacts. However, in a one-metal pre-package, as shown in Figure 1, the fan-out layout is restricted by the layout of the chip contact pads, i.e., the layout of the upper contact region 21. For example, the CSP upper metallization must overlap with the chip contact pads. Therefore, the layout of the CSP upper metallization cannot be arbitrary (it is desirable for the layout of the CSP upper metallization to be arbitrary so that there is sufficient flexibility in the placement of CSP components during the design of power modules). Furthermore, for example, the expansion of gate contact pads usually comes at the expense of a reduction in the drain / emitter contact area and thus a reduction in the current capacity of the semiconductor chip.

[0056] To overcome these limitations, the semiconductor device 1 described herein, as shown in FIGS. 3 and 4, includes at least one intermediate wiring layer located between the upper contact region 21 and the uppermost second electrical wiring layer 4. In this way, a CSP component with an arbitrary layout of upper metallization is produced using a multilayer package. This can be done by means of a plurality of embedding and stacking steps. Such a solution achieves the desired fan-out without reducing the effective area of the semiconductor chip 2 and thus without reducing the current capacity.

[0057] In high-voltage applications, the thickness of the encapsulant and each insulating layer in the case of a multilayer structure must be appropriately designed to withstand the blocking voltage. Such requirements can be relaxed when the internal and upper metal pads do not cross the terminal regions of the chip and the component is further encapsulated.

[0058] In this way, a semiconductor device 1 is provided that includes a semiconductor chip 2 configured for a voltage of at least 0.6 kV. The semiconductor chip 2 has an upper contact region 21 on the chip upper surface 20, and a plurality of electrical vias 71, 72, 73 are electrically connected to the upper contact region 21. The semiconductor chip 2 and the electrical vias 71, 72, 73 are embedded in an electrically insulating insulator 6, and the electrical vias 71, 72, 73 extend through the insulator 6 in a direction away from the chip upper surface 20. At least one intermediate wiring 3, 5 is present on the side of the upper contact region 21 away from the semiconductor chip 2 and makes electrical contact with the electrical vias 71, 72, 73.

[0059] The wiring layers 3, 4, 5 are designed to avoid short circuits between upper contact regions, also called chip terminals such as gate-source-drain.

[0060] According to FIGS. 3 and 4, a first insulating layer 61 is present over the upper contact region 21, and a first electrical wiring layer 3 is applied over the first insulating layer 61. A second insulating layer 62 follows the first electrical wiring layer 3, and a second electrical wiring layer 4 having a second electrical contact region 42 is applied over the second insulating layer 62. It is possible that the second contact region 42 of the second electrical wiring layer 4 is the only contact region of the main body upper surface 66 exposed from the insulator 6. However, as an option, the semiconductor chip 2 can be electrically contacted to a substrate 8 which is, for example, a copper-based lead frame. Therefore, the portion exposed from the insulator 6 may be only the substrate 8 and the second contact region 42.

[0061] FIG. 3 shows a cross-sectional view along the dashed-dotted line of FIG. 4. According to FIGS. 3 and 4, the smaller one of the rectangular second contact regions 42 is connected to the smaller upper contact region 21 of the upper contact regions 21, but does not overlap with this upper contact region 21 when viewed in a top view. This is made possible by the first electrical wiring layer 3 arranged in the insulator 6 providing a current path parallel to the chip upper surface 20. Therefore, the shape of the second contact region 42 is largely independent of the shape of the upper contact region 21.

[0062] For example, the semiconductor chip 2 is a corresponding power MOSFET or power IGBT configured for a current of 10 A or more and / or 100 A or less. Instead of or in addition to this, the semiconductor chip 2, and thus the semiconductor device 1, is configured for a voltage of at least 1.2 kV or at least 1.5 kV.

[0063] As an option, the larger one of the upper contact regions 21 is shaped like └┘ or U when viewed from the top view. The smaller one of the upper contact regions 21 is located between the legs of └┘ or U. The arrangement of the upper contact regions 21 can have, for example, at least one axis of mirror symmetry. In FIG. 4, the upper contact region 21 is symbolized as the hatched region, and the semiconductor chip 2 is also schematically shown for ease of understanding, but the intermediate wiring layer 3 is not shown in FIG. 4.

[0064] For example, the chip upper surface 20 has a size of at least 5 mm × 5 mm and / or a maximum of 15 mm × 15 mm. Instead of this, or in addition, the thickness of the semiconductor chip 2 perpendicular to the chip upper surface 20 is at least 100 μm and / or a maximum of 1 mm, for example 300 μm to 500 μm.

[0065] For example, the electrical vias 71, 72, 73 are metallized holes or metal blocks. For each of the contact regions 21, 31, 42, 53, depending on how each of the contact regions 21, 31, 42, 53 is configured according to size and current, there can be just one or a plurality of electrical vias 71, 72, 73. When the vias 71, 72, 73 are metallized holes, the diameter of the vias 71, 72, 73 is, for example, 50 μm to 200 μm. When the vias 71, 72, 73 are metal blocks, the vias 71, 72, 73 can have a larger lateral spread. Such a metal block can be joined to the corresponding contact regions 21, 31, 42, 53 by sintering or soldering.

[0066] The height of the vias 71, 72, 73 can correspond to the height of the associated insulating layers 61, 62, 63, 65. For example, the vias 71, 72, 73 are made of copper or a copper alloy.

[0067] The semiconductor devices of FIGS. 3 and 4 include two upper contact regions 21, and thus each of the electrical wiring layers 3, 4 includes two contact regions 31, 42. Alternatively, there may be only one upper contact region 21, and thus each of the electrical wiring layers 3, 4 may have only one contact region 31, 42, or there may be at least three upper contact regions 21, and thus each of the electrical wiring layers 3, 4 has at least three contact regions 31, 42. Further, although it is not strictly essential, it is preferable that the number of upper contact regions 21 is the same as the number of contact regions 31, 42 in each of the electrical wiring layers 3, 4. In addition to the electrical contact regions 21, 31, 42, optionally, there may be thermal contact regions (not shown) to improve cooling, and these thermal contact regions do not need to have an electrical function. These aspects are applicable to all other embodiments in any combination.

[0068] In other respects, the same content as FIGS. 1 and 2 is applicable to FIGS. 3 and 4, and vice versa.

[0069] FIG. 5 shows another embodiment of the semiconductor device 1, similar to FIG. 4. According to FIG. 5, the second contact regions 42 are arranged in a coaxial manner. Thus, the first second contact region among the second contact regions 42 completely surrounds the second second contact region among the second contact regions 42 when viewed in a top view of the chip top surface 20. Thereby, the first second contact region and the second second contact region among the second contact regions 42 belong to the second electrical wiring layer 4 and can be arranged in a common plane as external electrical contact pads. In addition to those shown, further second contact regions 42 of the second electrical wiring layer 4 can exist as external electrical contact pads.

[0070] For example, the upper contact region 21 assigned to the second second contact region among the second contact regions 42 is located at the edge of the upper surface 20 of the chip, and the overlap of these contact regions 21 and 42 may be only slightly. The upper contact region 21 assigned to the first second contact region among the second contact regions 42 may also be └┘ or U-shaped when viewed in the top view of the upper surface 20 of the chip.

[0071] When viewed in the top view, there may be two or four axes of mirror symmetry with respect to the shape of the second contact region 42. For example, the track width of the outer first second contact region among the second contact regions 42 can correspond to at least 10% and / or at most 40% of the maximum edge length of the upper surface 20 of the chip. The edge length of the inner second second contact region 42 among the second contact regions 42 is, for example, at least 20% and / or at most 60% of the maximum edge length of the upper surface 20 of the chip.

[0072] In other respects, the same content as in FIGS. 1 to 4 is also applicable to FIG. 5, and vice versa. According to FIG. 6, when viewed in the top view of the upper surface 20 of the chip, the larger third second contact region among the second contact regions 42 is L-shaped, and the smaller fourth second contact region among the second contact regions 42 is rectangular or square and is located within the notch of the third second contact region among the second contact regions 42. For example, the fourth second contact region among the second contact regions 42 is located at the corner of the second electrical wiring layer 4.

[0073] For example, the upper contact region 21 is formed in the same manner as in FIGS. 4 and 5. Therefore, the smaller fourth second contact region among the second contact regions 42 may not overlap with the smaller assigned upper contact region among the upper contact regions 21. In addition to that shown in FIG. 6, it is also possible that the smaller one of the upper contact regions 21 is partially or completely covered by the third second contact region among the second contact regions 42.

[0074] In other respects, the same content as FIGS. 1 to 5 is also applicable to FIG. 6, and vice versa. According to FIG. 7, when viewed in the top view of the chip top surface 20, the fifth and sixth second contact regions among the second contact regions 42 may be rectangular and extend parallel to each other. These second contact regions 42 can have different sizes. For example, the upper contact region 21 is shaped in the same manner as FIGS. 4 to 6.

[0075] Therefore, also when viewed in the top view of the chip top surface 20, the larger upper contact region 21 assigned to the fifth second contact region among the second contact regions 42 may be └┘ or U-shaped and can be located adjacent to all four edges of the chip top surface 20. The upper contact region 21 assigned to the sixth second contact region among the second contact regions 42 is located outside the sixth second contact region among the second contact regions 42. Therefore, the sixth second contact region among the second contact regions 42 and the assigned upper contact region 21 do not overlap or overlap only slightly.

[0076] Similar to all other embodiments, the total size of all the second contact regions 42 combined can be made larger than the size of the chip top surface 20.

[0077] In other respects, the same content as FIGS. 1 to 6 is also applicable to FIG. 7, and vice versa. FIG. 8 shows that the central second second contact region of the second contact region 42 is the largest second contact region of the second contact region 42. The second second contact region of the second contact region 42 is, for example, an emitter pad or a source pad. Correspondingly, the surrounding first second contact region of the second contact region 42 may have a smaller area content as a whole and may be a gate contact pad. For example, the track width of the outer first second contact region of the second contact region 42 can correspond to at least 2% and / or at most 15% of the maximum edge length of the upper surface 20 of the chip. The edge length of the inner second second contact region of the second contact region 42 is, for example, at least 60% and / or at most 95% of the maximum edge length of the upper surface 20 of the chip.

[0078] For example, the upper contact region 21 is formed in the same shape as FIGS. 4 to 8. The second second contact region of the second contact region 42 may be square in top view.

[0079] In other respects, the same content as FIGS. 1 to 7 is also applicable to FIG. 8, and vice versa. According to FIG. 9, the inner second second contact region of the second contact region 42 is relatively small, for example, at most 10% or 5% of the overall size of the semiconductor device 1 in top view. Therefore, the surrounding first second contact region of the second contact region 42 can cover substantially the entire upper surface 66 of the body. For example, the inner second second contact region of the second contact region 42 is a gate contact pad. In this coaxial design, by placing the gate contact pad in the center, the outer layer contact region 42, which is, for example, an emitter or source contact pad, can be maximized and the parasitic inductance can be reduced. The same can be applied to all the intermediate wiring layers 3 and 5.

[0080] Looking at the above figure, it is possible that the second second contact region of the second contact region 42 does not overlap with the assigned upper contact region 21.

[0081] In other respects, the same content as in FIG. 8 is also applicable to FIG. 9, and vice versa. In the embodiment of FIG. 10, it is shown that all the first contact regions 31 of the first electrical wiring layer 3 are located in a common plane above the first insulating layer 61. Further, as an option, an additional insulating layer 65 exists around the first contact region 31 in the lateral direction. Thus, the additional insulating layer 65 is located between the first insulating layer 61 and the second insulating layer 62.

[0082] According to FIG. 10, the substrate 8 is not embedded in the insulator 6, but the insulator 6 may not be present on the side surface of the substrate 8. The substrate 8 is connected to the semiconductor chip by connection means 81 such as solder. The substrate 8 is, for example, a heat sink or a lead frame. Such a configuration can also exist in all other embodiments. Note that, for the sake of simplicity of the drawing, only one of the contact regions 31, 42 is explicitly shown in FIG. 10.

[0083] In contrast to the content shown in FIG. 10, according to FIG. 11, the first contact regions 31 assigned to different upper contact regions 21 are not located in one plane, but rather are offset in a direction perpendicular to the upper surface 20 of the chip. Thus, two additional insulating layers 65, each assigned to one of the first contact regions 31, can overlap and exist. As an additional option, an additional insulating layer 65 assigned to the connection means 81 can also exist.

[0084] In other respects, the same content as in FIGS. 1 - 9 is also applicable to FIGS. 10 and 11, and vice versa.

[0085] FIG. 12 shows that the semiconductor device 1 includes two or more intermediate layers, that is, in addition to the first electrical wiring layer 3, there is at least one third electrical wiring layer 5 located between the first electrical wiring layer 3 and the second electrical wiring layer 4. In the example of FIG. 12, there are two third electrical wiring layers 5 overlapping each other, but it is also possible that there is only one third electrical wiring layer 3 or at least three third electrical wiring layers 5.

[0086] In FIG. 12, the intermediate wiring layers 3 and 4 are configured in the same manner as in FIG. 10, and thus all the contact regions 31 and 53 of the specific wiring layers 3 and 4 are located in a common plane. However, the configuration according to FIG. 11 is also possible so that the contact regions 31 and 53 in one of the first and third wiring layers 3 and 4 can be displaced in a direction perpendicular to the upper surface 20 of the chip.

[0087] Such at least one third electrical wiring layer 5 can also exist in all other embodiments.

[0088] Furthermore, as an option, the intermediate electrical wiring layers 3 and 5 can have different patterns of contact regions 31 and 53. Therefore, starting from the upper contact region 21, the respectively assigned contact regions 31 and 53 are formed in a shape similar to the respectively assigned second contact region 42 as they approach the second contact region 42 associated with the respectively assigned contact regions 31 and 53.

[0089] It is possible to make the metallization of the intermediate wiring layers 3 and 5 thinner than that of the uppermost second electrical wiring layer 4. For example, while the thickness of the first and / or third contact regions 31, 53 is 30 μm to 70 μm, the thickness of the second contact region 42 is 80 μm to 200 μm. The same is possible in all other embodiments.

[0090] In other respects, the same content as FIGS. 1 to 11 is applicable to FIG. 12, and vice versa.

[0091] In FIGS. 13 to 16, another embodiment of the semiconductor device 1 is shown in cross-section. In this case, the semiconductor device 1 includes one third electrical wiring layer 5. Similar to the embodiment of FIG. 12, the intermediate layers 3 and 5 have different shapes so as to achieve a more gradual change in the shape of the upper contact region 21 toward the shape of the second contact region 42.

[0092] Therefore, referring to FIG. 13, the upper contact region 21 can be made, for example, in the shape as shown in FIGS. 5 to 7. Next, referring to FIG. 14, compared with FIG. 13, the smaller one of the first contact regions 31 of the first electrical wiring layer 3 extends toward the center of the semiconductor device 1.

[0093] Next, referring to FIG. 15, compared with FIG. 14, the smaller one of the third contact regions 53 is shifted to the center, and the larger one of the third contact regions 53 surrounds the smaller one of the third contact regions 53. However, the smaller one of the third contact regions 53 is still disposed off-center. Finally, referring to FIG. 16, the smaller one of the third contact regions 53 is surrounded in a symmetric manner by the larger one of the third contact regions 53.

[0094] Such a gradual change in the shape of the contact region toward the shape of the second contact region 42 can also exist in all other exemplary embodiments.

[0095] In other respects, the same content as FIGS. 1 to 12 is also applicable to FIGS. 13 to 16, and vice versa.

[0096] FIG. 17 shows a semiconductor module 10. The semiconductor module 10 includes one or more semiconductor devices 1 as shown in any one of FIGS. 1 to 16, for example. The semiconductor module 10 further includes an electrical carrier 11 such as a circuit board. The electrical carrier 11 has a contact surface 12 to which the second contact region 42 is attached, for example, by soldering or sintering.

[0097] The contact surface 12 and the assigned second contact region 42 may be of the same size (see the central semiconductor device in the semiconductor device 1), or the contact surface 12 may be larger or smaller than the assigned second contact region 42 (see the left and right semiconductor devices in the semiconductor device 1, respectively).

[0098] As a further option, the semiconductor module 10 includes a cooler 13. The cooler 13 can be attached to the substrate 8 of at least one semiconductor device 1. Thereby, heat sinks can be provided on both main surfaces of at least one semiconductor device 1, cooling is improved, and it becomes possible to handle a larger current.

[0099] Finally, referring to FIG. 18, a method for manufacturing a semiconductor device is schematically shown.

[0100] In a first method step S1, a semiconductor chip 1 having an upper contact region 42 is provided. In this step, for example, an optional insulating buried portion 60 may already be present.

[0101] Next, in method step S2, a first insulating layer 31 is provided and a first electrical through-contact 71 is generated.

[0102] In method step S3, a first electrical wiring layer 3 is formed. The first contact regions 31 may all be in the same plane (see FIG. 10), or the first contact regions 31 may be formed successively by using a further insulating layer 65 (see FIG. 11). The thickness of the further insulating layer 65 corresponds, for example, to the thickness of the associated first contact region 31.

[0103] In method step S4, a second insulating layer 62 is provided and a second electrical through-contact 72 is formed. If a further insulating layer 65 is present, the second electrical through-contact 72 may also extend through the further insulating layer 65.

[0104] Next, in method step S5, the second contact region 42 is formed, for example, by plating.

[0105] As an option, method steps S6 and S7 that are executed between method step S3 and method step S4 can exist. In method step S6, a third insulating layer 63 is formed and a third electrical via contact 73 is provided. In method step S7, a third electrical wiring layer 5 is provided. For method steps S6 and S7, depending on the number of third electrical wiring layers 5, various numbers of repetitions are possible.

[0106] Therefore, the CSP semiconductor device 1 is manufactured, for example, by the following series of steps, namely i) a step of bonding a semiconductor chip onto a substrate 8 such as a copper lead frame, for example, by sintering; ii) a step of embedding the semiconductor chip 1 and optionally also the substrate 8 by laminating copper foil and / or prepreg, cutting the prepreg, or performing epoxy compression molding as an alternative process; iii) a step of forming electrical via contacts, for example, by via drilling; iv) a step of generating respective electrical wiring layers by electroplating and structuring of copper and is manufactured thereby.

[0107] The thickness of the prepreg foil is thought to define the maximum voltage that the CSP can withstand. Standard materials are FR4 and epoxy, which have a breakdown electric field of about 2 kV per 100 μm. For a proper embedding of the semiconductor device 1 with 1.2 kV, including a safety margin, typically an insulating layer 61, 62, 63, 65 with a thickness of 100 μm is required between the semiconductor chip 1 and the upper layer of the source or gate potential. However, technical limitations, namely the stacking and perforation of thick insulating layers or multilayer insulating layers, and conformal plating for such deep via structures, have hindered the development of CSPs to high voltages, for example, exceeding 0.6 kV. According to the multilayer structure of the semiconductor device 1 presented herein, higher voltages can be achieved, for example, by increasing the thickness of the insulating layer.

[0108] The components shown in the figures follow in the order specified, preferably one on top of the other, directly or indirectly, unless otherwise indicated. Layers not in contact in the figures are preferably spaced apart from each other. When lines are drawn parallel to each other, the corresponding surfaces are preferably oriented parallel to each other. Similarly, unless otherwise indicated, the relative positions of the components drawn are accurately reproduced in the figures.

[0109] The invention described herein is not limited by the description based on the embodiments. Rather, the invention includes any novel feature and, in particular, any combination of features, including any combination of the features in the claims, even if such feature or combination itself is not explicitly shown in the claims or exemplary embodiments.

[0110] This patent application claims the priority of European Patent Application No. 2215 2939.9, the disclosure of which is incorporated herein by reference.

Explanation of Reference Signs

[0111] Reference Sign 1 Semiconductor Device 2 Semiconductor Chip Upper surface of 20 chips 21 Upper contact area 3 First electrical wiring layer 31 First contact area 4 Second electrical wiring layer 42 Second contact area 5 Third electrical wiring layer 53 Third contact area 6 Insulator 60 Insulating buried part 61 First insulating layer 62 Second insulating layer 63 Third insulating layer 65 Further insulating layer 66 Upper surface of the body 71 First electrical through contact 72 Second electrical through contact 73 Third electrical through contact 8 Substrate 81 Connection means 9 Improved semiconductor device 10 Semiconductor module 11 Electrical carrier 12 Contact surface 13 Cooler S. Method step

Claims

1. ・ A semiconductor chip (2) configured for a voltage of at least 0.6 kV and having an upper contact region (21) on the upper surface (20) of the chip, ・ A first electrical wiring layer (3) in electrical contact with the upper contact region (21) having a first contact region (31) electrically assigned to the upper contact region (21), ・ A second electrical wiring layer (4) located on the side of the first electrical wiring layer (3) far from the upper contact region (21) and having a second contact region (42) electrically assigned to the upper contact region (21), wherein the second contact region (42) is configured as an external contact region, ・ At least one third electrical wiring layer (5) located between the first electrical wiring layer (3) and the second electrical wiring layer (4), electrically connected to the first electrical wiring layer (3) and the second electrical wiring layer (4), and having a third contact region (53), comprising: ・ The semiconductor device (1) is a chip - size package, ・ The semiconductor chip (2) is a power metal - insulator field - effect transistor (MISFET) or a power insulated - gate bipolar transistor (IGBT), ・ The first electrical wiring layer (3), the second electrical wiring layer (4), and the third electrical wiring layer (5) are each separated from one another by insulating layers (61, 62, 63) made of a dielectric material, and electrical vias (71, 72, 73) are formed through the insulating layers (61, 62, 63), ・ A semiconductor device (1) in which a first second contact region of the second contact region (42), which has a different shape from one of the electrically assigned ones of the upper contact region (21), extends completely around a second second contact region of the second contact region (42), which has a different shape from one of the electrically assigned ones of the upper contact region (21), in a coaxial aspect when viewed in a top view of the upper surface (20) of the chip, and the first second contact region and the second second contact region of the second contact region (42) are arranged rotationally symmetrically and / or point - symmetrically.

2. Each located between the first electrical wiring layer (3) and the second electrical wiring layer (4), and at least two of the third electrical wiring layers (5) electrically connected to the first electrical wiring layer (3) and the second electrical wiring layer (4) comprising The semiconductor device (1) according to claim 1, wherein, starting from the first contact region (31) and towards the second contact region (42), the shape of each assigned third contact region (53) becomes similar to that from the upper contact region (21) to the second contact region (42) by the second contact region (42).

3. The semiconductor device (1) according to claim 1 or 2, wherein the thickness of the insulating layers (61, 62, 63) is 100 μm or less in each case.

4. In the top view of the chip top surface (20), the overall size of the semiconductor device (1) is 130% or less of the size of the chip top surface (20), whereby the semiconductor device (1) accurately comprises one semiconductor chip (2), The semiconductor device (1) according to claim 1 or 2, wherein the overall size of all the second contact regions (42) combined is larger than the size of the chip top surface (20).

5. - The thicknesses of the first electrical wiring layer (3), the second electrical wiring layer (4), and the third electrical wiring layer (5) are 20 μm or more and 200 μm or less in each case, - The electrical through contacts (71, 72, 73) extend through each of the insulating layers (61, 62, 63), and the electrical through contacts (71, 72, 73) electrically connect adjacent electrical wiring layers among the first electrical wiring layer (3), the second electrical wiring layer (4), and the third electrical wiring layer (5), - The diameter of the electrical through contacts (71, 72, 73) is 20 μm or more and 200 μm or less in each case, At least the semiconductor device (1) according to claim 3.

6. - At least one semiconductor device (1) according to claim 1 or 2, - An electric carrier (11) comprising The semiconductor module (10), wherein the second contact region (42) is connected to the electrical contact surface (12) of the electric carrier (11).

7. A method for manufacturing the semiconductor device (1) according to claim 1 or 2, - Prepare a semiconductor chip (2) configured for a voltage of at least 0.6 kV and having an upper contact region (21) on the upper surface (20) of the chip. - Apply an insulating layer (61, 62, 63), a first electrical wiring layer (3), a second electrical wiring layer (4), and at least one third electrical wiring layer (5) on the semiconductor chip (2). including - The semiconductor device (1) is a chip scale package. - The first electrical wiring layer (3) is in electrical contact with the upper contact region (21) having a first contact region (31) electrically assigned to the upper contact region (21). - The second electrical wiring layer (4) is located on the side far from the upper contact region (21) of the first electrical wiring layer (3) and has a second contact region (42) electrically assigned to the upper contact region (21). The second contact region (42) is configured as an external contact region. - The at least one third electrical wiring layer (5) is located between the first electrical wiring layer (3) and the second electrical wiring layer (4), is electrically connected to the first electrical wiring layer (3) and the second electrical wiring layer (4), and has a third contact region (53). - The semiconductor chip (2) is a power metal-insulator field-effect transistor (MISFET) or a power insulated gate bipolar transistor (IGBT). - The first electrical wiring layer (3), the second electrical wiring layer (4), and the third electrical wiring layer (5) are each separated from each other by one of the insulating layers (61, 62, 63) made of a dielectric material, and electrical vias (71, 72, 73) are formed through the insulating layers (61, 62, 63). A method in which a first second contact region of the second contact region (42), which has a shape different from that of the one electrically assigned among the upper contact regions (21), extends completely around a second second contact region of the second contact region (42), which has a shape different from that of the one electrically assigned among the upper contact regions (21), as seen in a top view of the chip top surface (20), and the first second contact region and the second second contact region of the second contact region (42) are arranged rotationally symmetrically and / or point symmetrically.

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