Semiconductor Circuit and Power Supply Device

Abstract

To prevent oscillation while improving PSR characteristics.SOLUTION: A semiconductor circuit includes: a first transistor connected between a first node to which an input voltage is input and a second node from which an output voltage is output; a cascode connection circuit including a plurality of second transistors cascode-connected between the first node and a third node set to a first voltage; a first capacitor connected between the second node and a fourth node of one second transistor of the plurality of second transistors; and a second capacitor connected between the first node and the fourth node, wherein a fifth node of the one second transistor is connected to a gate of the first transistor.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] A first embodiment of the present invention relates to a semiconductor circuit and a power supply device. [Background technology]

[0002] LDO (Low Drop Out) regulators are known to be able to suppress fluctuations in output voltage even when the input voltage or load current fluctuates. One of the characteristics of LDO regulators is the power supply rejection (PSR) characteristic. The PSR characteristic is the AC gain characteristic of the output voltage relative to the input voltage, and it is desirable for the PSR to be as small as possible.

[0003] Parasitic capacitance is added to the gate of the pass transistor installed in the final stage of an LDO regulator, which can degrade the PSR characteristics. The PSR characteristics can be improved by peaking the AC gain of the pass transistor's gate signal relative to the input voltage in the frequency band where the PSR characteristics degrade. However, this can shift the power supply conductance of the pass transistor to the negative side, which can cause the LDO regulator's output signal to oscillate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Patent No. 4838760 [Patent Document 2] Patent No. 5092009 Summary of the Invention [Problem to be solved by the invention]

[0005] Therefore, the embodiments of the present invention provide a semiconductor circuit and a power supply device that can improve the PSR characteristics. [Means for solving the problem]

[0006] In order to solve the above problem, according to a first embodiment of the present invention, there is provided a power supply circuit including: a first transistor connected between a first node to which an input voltage is input and a second node to which an output voltage is output; a cascode-connected circuit having a plurality of second transistors cascode-connected between the first node and a third node set to a first voltage; a first capacitor connected between the second node and a fourth node of one of the plurality of second transistors; a second capacitor connected between the first node and a fourth node, A semiconductor circuit is provided, wherein a fifth node of the one second transistor is connected to a gate of the first transistor. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a circuit diagram of a power supply device according to a first embodiment. [Figure 2] FIG. 10 is a circuit diagram of a power supply device according to a comparative example that does not have an AC path. [Figure 3] FIG. 3 is a graph showing the PSR characteristics of the power supply device of FIG. 2; [Figure 4] FIG. 2 is a graph showing the PSR characteristics of the power supply device of FIG. 1; [Figure 5] FIG. 10 is a circuit diagram of a power supply device according to a second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of a semiconductor circuit and a power supply device will be described with reference to the drawings. The following description will focus on the main components of the semiconductor circuit and the power supply device, but the semiconductor circuit and the power supply device may include components and functions that are not shown or described. The following description does not exclude components and functions that are not shown or described.

[0009] (First embodiment) Figure 1 is a circuit diagram of a power supply device 1 according to a first embodiment. The power supply device 1 in Figure 1 can be realized as a semiconductor circuit 10 formed on a semiconductor substrate. This semiconductor circuit 10 can also be packaged together with other semiconductor circuits formed on the same semiconductor substrate to form a semiconductor device.

[0010] The power supply device 1 includes a first transistor Q1, a cascode-connected circuit 2, a first capacitor C1, a second capacitor C2, a first node n1, a second node n2, and a third node n3. The power supply device 1 is also called an LDO regulator and is capable of outputting an output voltage Vout at a voltage level close to an input voltage VCCH. A load circuit 3 is connectable to the second node n2.

[0011] An input voltage VCCH is input to the first node n1. The input voltage VCCH is, for example, the power supply voltage of the power supply device 1. Hereinafter, the first node n1 may be referred to as the input voltage node n1. The second node n2 outputs the output voltage Vout of the power supply device 1. Hereinafter, the second node n2 may be referred to as the output voltage node n2.

[0012] A reference voltage is input to the third node n3. The reference voltage corresponds to a reference potential when the power supply device 1 operates, and is, for example, a ground voltage (0 V). Hereinafter, the third node n3 may be referred to as a ground voltage node n3.

[0013] The input voltage VCCH, the output voltage Vout, and the reference voltage may have any voltage levels. The power supply device 1 according to this embodiment can suppress fluctuations in the output voltage Vout and prevent oscillation of the output voltage Vout even if the input voltage VCCH or the load current flowing through the load circuit 3 fluctuates.

[0014] The first transistor Q1 is connected between an input voltage node n1 and an output voltage node n2. Hereinafter, the first transistor Q1 may be referred to as a pass transistor Q1. The pass transistor Q1 is a PMOS transistor. The source of the pass transistor Q1 is connected to the input voltage node n1, and the drain is connected to the output voltage node n2. The gate voltage of the pass transistor Q1 is controlled, for example, in accordance with the potential difference between a voltage correlated to the output voltage Vout of the power supply device 1 and a control voltage Vctl. The voltage correlated to the output voltage Vout is, for example, a divided voltage of the output voltage Vout.

[0015] The cascode connection circuit 2 has a plurality of second transistors Q2 cascode-connected between the input voltage node n1 and the ground voltage node n3. The plurality of second transistors Q2 may include transistors of a first conductivity type and transistors of a second conductivity type. In the example of FIG. 1, the cascode connection circuit 2 has a PMOS transistor Q2a, an NMOS transistor Q2b, and an NMOS transistor Q2c cascode-connected in this order between the input voltage node n1 and the ground voltage node n3. In this specification, the transistors Q2a, Q2b, and Q2c in the cascode connection circuit 2 may be collectively referred to as the second transistor Q2.

[0016] The number of connected stages of the second transistor Q2 in the cascode connection circuit 2 is arbitrary. The cascode connection circuit 2 in Fig. 1 has one PMOS transistor Q2a and two NMOS transistors Q2b and Q2c, but it may have two or more PMOS transistors Q2 and three or more NMOS transistors Q2.

[0017] The source of PMOS transistor Q2a in cascode circuit 2 is connected to input voltage node n1, and its drain is connected to the drain of NMOS transistor Q2b and the gate of pass transistor Q1. The source of NMOS transistor Q2b is connected to the drain of NMOS transistor Q2c. The source of NMOS transistor Q2c is connected to the ground node.

[0018] In this way, the drains of the transistors Q2a and Q2b of different conductivity types in the cascode connection circuit 2 are connected to the gate of the pass transistor Q1.

[0019] The first capacitor C1 is connected between the output voltage node n2 and a fourth node n4 of one second transistor Q2 (Q2b) of the plurality of second transistors Q2. More specifically, in the example of FIG. 1, the first capacitor C1 is connected between the output voltage node n2 and the source of the NMOS transistor Q2b, and the fourth node n4 is the source of the transistor Q2b. One end of the first capacitor C1 is connected to the output voltage node n2, and the other end is connected to the connection node between the source of the transistor Q2b and the drain of the transistor Q2c. In other words, the fourth node n4 is also the node to which the other end of the first capacitor C1 is connected.

[0020] The first capacitor C1 is called a Miller compensation capacitance. By providing the first capacitor C1, it is possible to obtain the effect of adding a capacitance to the gate of the pass transistor Q1 that is the capacitance of the first capacitor C1 multiplied by the gain. This effectively deteriorates the frequency characteristics of the power supply device 1, thereby preventing oscillation. However, as will be described later, the first capacitor C1 alone may not be enough to prevent oscillation, and therefore the power supply device 1 according to this embodiment also takes measures to prevent oscillation other than the first capacitor C1.

[0021] The gain multiplication refers to the gain multiplication of the common-source amplifier Q1. Hereinafter, the first capacitor C1 may be referred to as a Miller compensation capacitance C1.

[0022] The second capacitor C2 is connected between the fourth node n4 of the second transistor Q2 (Q2b) and the input voltage node n1. More specifically, in the example of FIG. 1, the second capacitor C2 is connected between the source of the NMOS transistor Q2b and the input voltage node n1. The fifth node n5 of the second transistor Q2 (Q2b) is connected to the gate of the first transistor Q1. The fifth node n5 is the drain of the transistor Q2b.

[0023] The path connecting both ends of the second capacitor C2 is called an AC path. By providing such an AC path, as will be described later, the power supply conductance of the pass transistor Q1 does not shift to the negative side, improving the PSR characteristics and preventing oscillation of the output voltage Vout of the power supply device 1. Hereinafter, the second capacitor C2 may be referred to as the AC path capacitance C2.

[0024] In the power supply device 1 according to this embodiment, the AC pass capacitance C2 is set so that the power supply conductance of the pass transistor Q1 does not shift to the negative side, thereby preventing oscillation of the output voltage Vout of the power supply device 1, as will be described later.

[0025] The second output node of the second transistor Q2 (Q2b) is connected to the gate of the pass transistor Q1. More specifically, in the example of Figure 1, the drain of the NMOS transistor Q2b is connected to the gate of the pass transistor Q1, and the second output node is the drain of the transistor Q2b.

[0026] In this way, the other end of the Miller compensation capacitance C1 is connected to the source of the second transistor Q2 (Q2b) among the multiple second transistors Q2 in the cascode connection circuit 2, the second transistor Q2 having a drain connected to the gate of the pass transistor Q1.

[0027] In addition, the power supply device 1 of FIG. 1 also includes a voltage divider circuit 4 and a differential amplifier circuit 5. The voltage divider circuit 4 is connected between the output voltage node n2 and the ground voltage node n3, and generates a divided voltage by dividing the output voltage Vout of the power supply device 1. The voltage divider circuit 4 generates a divided voltage according to the resistance ratio of two resistors R1 and R2. Note that the voltage divider circuit 4 may also generate a divided voltage according to the ratio of the number of stages of an impedance element other than a resistor, for example, a plurality of cascaded diodes. In this way, the specific configuration of the voltage divider circuit 4 is arbitrary.

[0028] The differential amplifier circuit 5 and the second transistor Q2 (Q2b) supply a voltage corresponding to the potential difference between the divided voltage and the control voltage Vctl to the gate of the pass transistor Q1. The control voltage Vctl is supplied, for example, from outside the power supply device 1. By controlling the voltage level of the control voltage Vctl, the voltage level of the output voltage Vout of the power supply device 1 can be controlled. Because the differential amplifier circuit 5 and the second transistor Q2 (Q2b) perform negative feedback control so that the divided voltage matches the control voltage Vctl, the differential amplifier circuit 5 is also called an error amplifier.

[0029] In the power supply device 1, for example, when the load current flowing through the load circuit 3 decreases, the drain voltage of the pass transistor Q1 increases, and the divided voltage output from the voltage divider circuit 4 also increases. As a result, the output voltage of the differential amplifier circuit 5 decreases, and the source-drain current of the PMOS transistor Q2a in the cascode-connected circuit 2 increases. Therefore, the gate voltage of the pass transistor Q1 connected to the source of the PMOS transistor Q2a increases, the source-drain current of the pass transistor Q1 decreases, and the increase in the output voltage Vout is suppressed.

[0030] Furthermore, in the power supply device 1, for example, when the input voltage VCCH drops, the pass transistor Q1 operates in an off direction, and the source-drain current of the pass transistor Q1 decreases. This causes the output voltage Vout output from the output voltage node n2 to drop. Therefore, the divided voltage output from the voltage divider circuit 4 also drops, and the output voltage of the differential amplifier circuit 5 increases. Therefore, the PMOS transistor Q2a in the cascode connection circuit 2 operates in an off direction, and the drain voltage of the PMOS transistor Q2a and the gate voltage of the pass transistor Q1 decrease. Therefore, the pass transistor Q1 operates in an on direction, the source-drain current of the pass transistor Q1 increases, and the output voltage Vout output from the output voltage node n2 increases.

[0031] By the above operation, even if the load current or the input voltage VCCH fluctuates, the output voltage Vout output from the output voltage node n2 is controlled to be constant.

[0032] As described above, parasitic capacitance Cp is added to the gate of pass transistor Q1 in power supply device 1. This parasitic capacitance Cp creates an AC-like current path, degrading the PSR characteristics of power supply device 1. More specifically, the degree of degradation of the PSR characteristics of power supply device 1 varies depending on the magnitude of parasitic capacitance Cp. Here, degradation of the PSR characteristics means, for example, an increase in the PSR value, and improvement of the PSR characteristics means, for example, a decrease in the PCR value.

[0033] Furthermore, the AC gain VGP0 / VCCH, which is the ratio of the gate voltage VGP0 of the pass transistor Q1 to the input voltage VCCH, changes depending on the magnitude of the parasitic capacitance Cp. If this AC gain VGP0 / VCCH is given a peak and its bandwidth is widened, the PSR characteristics improve, but the power supply conductance of the power supply 1 decreases, and there is a risk of negative power supply conductance occurring. Negative power supply conductance can cause oscillations in the input voltage VCCH at input voltage node n1 and the output voltage Vout at output voltage node n2, so it is necessary to avoid negative power supply conductance.

[0034] Therefore, in the power supply device 1 of the first embodiment, an AC path is provided by the AC path capacitance C2 between the input voltage node n1 and the source of the NMOS transistor Q2b, thereby improving the PSR characteristics and eliminating the negative power supply conductance.

[0035] 2 is a circuit diagram of a power supply device 100 according to a comparative example that does not have an AC path formed by AC path capacitance C2. The power supply device 100 of the comparative example has a circuit configuration in which the AC path capacitance C2 is omitted from the power supply device 1 of the first embodiment.

[0036] FIG. 3 is a diagram showing the PSR characteristics of a power supply device 100 of a comparative example, specifically, a schematic diagram of the PSR frequency characteristics. The horizontal axis of FIG. 3 represents frequency [Hz], and the vertical axis represents PSR [dB]. FIG. 3 shows three curves W1 to W3 representing the PSR characteristics when the parasitic capacitance Cp of the gate of the pass transistor Q1 is changed in three ways. FIG. 3 also shows the dependency of the PSR characteristics on the gate parasitic capacitance Cp. The values ​​of the parasitic capacitance Cp are as follows: curve W1 < curve W2 < curve W3. As the parasitic capacitance Cp increases, the PSR characteristic curve shifts to a larger value, as shown in FIG. 3. Curves W1 to W3 in FIG. 3 indicate that the PSR characteristics deteriorate more as the parasitic capacitance Cp increases. As mentioned above, a smaller PSR is desirable.

[0037] Giving AC gain VGP0 / VCCH a peak improves the PSR characteristics, but it also shifts the power supply conductance to the negative side, which may cause oscillation.

[0038] In contrast, the power supply device 1 of the first embodiment provides an AC path using AC path capacitance C2. The capacitance value of AC path capacitance C2 is optimized, which improves the PSR characteristics without shifting the power supply conductance to the negative side.

[0039] FIG. 4 is a diagram showing the PSR characteristics of the power supply device 1 according to the first embodiment, specifically, a schematic diagram of the PSR frequency characteristics. The horizontal axis of FIG. 4 represents frequency [Hz], and the vertical axis represents PSR [dB]. FIG. 4 illustrates three curves W11 to W13 representing the PSR characteristics when the capacitance of the AC path capacitance C2 is changed in three ways. FIG. 4 also illustrates the dependency of the PSR characteristics on the AC path capacitance C2. The capacitance values ​​of the AC path capacitance C2 are as follows: curve W11 < curve W12 < curve W13. As shown in FIG. 4, as the capacitance value of the AC path capacitance C2 increases, the PSR characteristic curve shifts to a smaller value. Curves W11 to W13 in FIG. 4 indicate that as the capacitance value of the AC path capacitance C2 increases, degradation of the PSR characteristics decreases.

[0040] Note that Figure 4 shows an example in which the larger the capacitance value of AC path capacitance C2, the less degradation of the PSR characteristics there is, but increasing the capacitance value of AC path capacitance C2 does not necessarily suppress degradation of the PSR characteristics. There is a capacitance value of AC path capacitance C2 at which the PSR characteristics value is minimum, and if the capacitance value of AC path capacitance C2 is increased beyond that capacitance value, the PSR characteristics will deteriorate.

[0041] In the power supply device 1 of the first embodiment, by selecting an appropriate capacitance value for the AC path capacitance C2, it is possible to improve the PSR characteristics without causing a peak in the AC gain VGP0 / VCCH.

[0042] In this way, in the power supply device 1 of the first embodiment, the AC pass capacitance C2 is connected between the connection node between the Miller compensation capacitance C1 and the cascode connection circuit 2 and the input voltage node n1, and the capacitance value of the AC pass capacitance C2 is optimized. This prevents the power supply conductance of the pass transistor Q1 from shifting to the negative side, improving the PSR characteristics. Therefore, there is no risk of oscillation of the output voltage Vout output from the power supply device 1 of the first embodiment, and the PSR characteristics can be improved.

[0043] (Second embodiment) Although the power supply device 1 in FIG. 1 has a differential amplifier circuit 5 separate from the cascode-connected circuit 2, a cascode-type differential amplifier circuit 6 in which the cascode-connected circuit 2 and the differential amplifier circuit 5 are integrated may be provided.

[0044] Figure 5 is a circuit diagram of a power supply device 1a according to a second embodiment. The power supply device 1a in Figure 5 can be realized as a semiconductor circuit 10a formed on a semiconductor substrate. The power supply device 1a includes a pass transistor Q1 (first transistor Q1), a voltage divider circuit 4, a cascode differential amplifier circuit 6, a first capacitor C1 (Miller compensation capacitance C1), and a second capacitor C2 (AC pass capacitance C2).

[0045] 5 includes a transistor Q3 that functions as a current source, transistors Q4a and Q4b that form part of a current mirror circuit, cascode-connected transistors Q5a, Q5b, and Q5c, and cascode-connected transistors Q6a, Q6b, and Q6c. The transistors Q4a, Q4b, Q5a, and Q6a are, for example, PMOS transistors, and the transistors Q3, Q5b, Q5c, Q6b, and Q6c are, for example, NMOS transistors.

[0046] The sources of transistors Q4a and Q4b are connected to input voltage node n1. Transistors Q5a, Q5b, and Q5c are cascode-connected between the drain of transistor Q4a and the drain of transistor Q3. Transistors Q6a, Q6b, and Q6c are cascode-connected between the drain of transistor Q4b and the drain of transistor Q3.

[0047] Hereinafter, the transistors Q5a, Q5b, and Q5c may be referred to as a first cascode connection portion 7, and the transistors Q6a, Q6b, and Q6c may be referred to as a second cascode connection portion 8.

[0048] The gates of transistors Q4a and Q4b are connected to each other, and the gates of transistors Q4a and Q4b are connected to the drains of transistors Q6a and Q6b. Therefore, transistors Q4a, Q4b, Q5a, Q5b, Q5c, Q6a, Q6b, and Q6c form a current mirror circuit. Part of the current mirror circuit and the first cascode connection section 7 correspond to the cascode connection circuit 2 in Figure 1.

[0049] The gate of transistor Q6c is supplied with the divided voltage output from voltage divider circuit 4. The gate of transistor Q5c is supplied with control voltage Vctl. By controlling the voltage level of control voltage Vctl, the voltage level of output voltage Vout of power supply device 1a can be controlled.

[0050] One end of the mirror compensation capacitance C1 is connected to the output node (output voltage node n2) of the power supply device 1a, and the other end is connected to the connection node between the source of transistor Q5b and the drain of transistor Q5c. It is known that providing the mirror compensation capacitance C1 can provide good PSR characteristics, and it is widely used in LDO regulators. This embodiment is characterized by the addition of an AC pass capacitance C2 in addition to the mirror compensation capacitance C1.

[0051] As in FIG. 1, the AC pass capacitance C2 is connected between the input voltage node n1 and the other end of the Miller compensation capacitance C1.

[0052] The cascode differential amplifier circuit 6 has four cascode-connected transistors Q4a, Q5a, Q5b, and Q5c and four cascode-connected transistors Q4b, Q6a, Q6b, and Q6c between the input voltage node n1 and the drain of the transistor Q3, but the number of cascode-connected transistor stages is arbitrary.

[0053] The other end of the Miller compensation capacitance C1 and the other end of the AC pass capacitance C2 are connected to the source of a transistor Q5b, which has a drain connected to the gate of the pass transistor Q1 in the first cascode connection section 7. The connection node between the drain of the transistor Q5a and the drain of the transistor Q5b (fifth node n5) is connected to the gate of the transistor Q1.

[0054] In the power supply device 1a of the second embodiment, by connecting the AC pass capacitance C2 between the other end of the Miller compensation capacitance C1 and the input voltage node n1, the PSR characteristics can be improved while preventing the power supply conductance of the pass transistor Q1 from shifting to the negative side, and the risk of oscillation of the output voltage Vout of the power supply device 1a is eliminated. According to the power supply device 1a of the second embodiment, in addition to improving the PSR characteristics by providing the Miller compensation capacitance C1 in the cascode differential amplifier circuit 6, the PSR characteristics can be further improved by providing the AC pass capacitance C2, and there is no need to add an active element.

[0055] The semiconductor circuits 10, 10a and power supply devices 1, 1a according to the first and second embodiments can be used, for example, as power supply circuits for various semiconductor chips. Various circuits within the semiconductor chip can be driven by the output voltage Vout output from the semiconductor circuit 10, 10a according to the first or second embodiment. The load current flowing through the load circuit 3 varies depending on the operating state of the semiconductor chip. Furthermore, the voltage level of the input voltage VCCH (e.g., power supply voltage) of the semiconductor circuit 10, 10a varies depending on environmental conditions, etc. Even if such fluctuations in the load current or input voltage VCCH occur, by providing an AC path capacitance C2 within the semiconductor circuit 10, 10a and optimizing its capacitance value, it is possible to improve the PSR characteristics and prevent oscillation of the output voltage Vout.

[0056] The embodiments of the present invention can be summarized as follows. [Appendix 1] a first transistor connected between a first node to which an input voltage is input and a second node to which an output voltage is output; a cascode-connected circuit having a plurality of second transistors cascode-connected between the first node and a third node set to a first voltage; a first capacitor connected between the second node and a fourth node of one of the plurality of second transistors; a second capacitor connected between the first node and a fourth node, A semiconductor circuit, wherein a fifth node of the first second transistor is connected to a gate of the first transistor. [Appendix 2] 2. The semiconductor circuit according to claim 1, wherein the capacitance value of the second capacitor is set so that the power supply conductance of the first transistor does not shift to the negative side. [Appendix 3] 3. The semiconductor circuit according to claim 1, wherein the gate voltage of the first transistor is controlled according to a potential difference between a voltage correlated to the output voltage of the second node and a second voltage lower than the input voltage and higher than the first voltage. [Appendix 4] a gate of another second transistor in the cascode connection circuit that is connected closer to the first node than the first second transistor is supplied with a voltage corresponding to a potential difference between the second voltage and a voltage that correlates with the output voltage of the second node. [Appendix 5] a differential amplifier circuit including the cascode-connected circuit; a voltage divider circuit connected between the second node and the third node, which divides the output voltage to generate a divided voltage; the differential amplifier circuit outputs a voltage corresponding to a potential difference between the divided voltage and the second voltage; 4. The semiconductor circuit according to claim 3, wherein a gate voltage of the first transistor is controlled in accordance with an output voltage of the differential amplifier circuit. [Appendix 6] 6. The semiconductor circuit according to claim 5, wherein the differential amplifier circuit supplies a voltage corresponding to a potential difference between the divided voltage and the second voltage to a gate of the other second transistor. [Appendix 7] The differential amplifier circuit a current source having a third transistor; a current mirror circuit having two fourth transistors whose gates are connected to each other; a first cascode connection section having a plurality of fifth transistors cascode-connected between one of the fourth transistor and the third transistor; a second cascode connection section having a plurality of sixth transistors cascode-connected between the other of the fourth transistors and the third transistor; 6. The semiconductor circuit according to claim 5, wherein the cascode connection circuit includes the first cascode connection portion and a part of the current mirror circuit. [Appendix 8] 8. The semiconductor circuit according to claim 1, wherein the plurality of second transistors of the cascode-connected circuit include a transistor of a first conductivity type and a transistor of a second conductivity type. [Appendix 9] 9. The semiconductor circuit of claim 8, wherein a node at which a drain of the first conductivity type transistor and a drain of the second conductivity type transistor are connected among the plurality of second transistors is connected to a gate of the first transistor. [Appendix 10] a first node to which an input voltage is input; a second node at which an output voltage is output; a third node set to the first voltage; a first transistor connected between the first node and the second node; a cascode connection circuit having a plurality of second transistors cascode-connected between the first node and the third node; a first capacitor connected between the second node and a fourth node of one of the plurality of second transistors; a second capacitor connected between the fourth node and the first node; a fifth node of the first second transistor connected to a gate of the first transistor;

[0057] The aspects of the present disclosure are not limited to the individual embodiments described above, but include various modifications that may be conceived by those skilled in the art, and the effects of the present disclosure are not limited to the above-described contents. In other words, various additions, modifications, and partial deletions are possible within the scope of the conceptual idea and spirit of the present disclosure, which is derived from the contents defined in the claims and their equivalents. [Explanation of symbols]

[0058] 1, 1a Power supply device, 2 Cascode connection circuit, 3 Load circuit, 4 Voltage divider circuit, 5 Differential amplifier circuit, 6 Cascode type differential amplifier circuit, 7 First cascode connection part, 8 Second cascode connection part, 10, 10a Semiconductor circuit, 100 Power supply device

Claims

1. a first transistor connected between a first node to which an input voltage is input and a second node to which an output voltage is output; a cascode-connected circuit having a plurality of second transistors cascode-connected between the first node and a third node set to a first voltage; a first capacitor connected between the second node and a fourth node of one of the plurality of second transistors; a second capacitor connected between the first node and a fourth node, A semiconductor circuit, wherein a fifth node of the one second transistor is connected to a gate of the first transistor.

2. 2. The semiconductor circuit according to claim 1, wherein the gate voltage of the first transistor is controlled in accordance with a potential difference between a voltage correlated to the output voltage of the second node and a second voltage lower than the input voltage and higher than the first voltage.

3. 3. The semiconductor circuit according to claim 2, wherein a voltage corresponding to a potential difference between a voltage correlated to an output voltage of the second node and the second voltage is supplied to a gate of another second transistor connected to the first node side of the first second transistor in the cascode connection circuit.

4. a differential amplifier circuit including the cascode-connected circuit; a voltage divider circuit connected between the second node and the third node, which divides the output voltage to generate a divided voltage; the differential amplifier circuit outputs a voltage corresponding to a potential difference between the divided voltage and the second voltage; 3. The semiconductor circuit according to claim 2, wherein the gate voltage of said first transistor is controlled in accordance with the output voltage of said differential amplifier circuit.

5. 5. The semiconductor circuit according to claim 4, wherein said differential amplifier circuit supplies a voltage corresponding to a potential difference between said divided voltage and said second voltage to the gate of another of said second transistors.

6. The differential amplifier circuit a current source having a third transistor; a current mirror circuit having two fourth transistors whose gates are connected to each other; a first cascode connection section having a plurality of fifth transistors cascode-connected between one of the fourth transistor and the third transistor; a second cascode connection section having a plurality of sixth transistors cascode-connected between the other of the fourth transistors and the third transistor; 5. The semiconductor circuit according to claim 4, wherein the cascode connection circuit includes the first cascode connection portion and a part of the current mirror circuit.

7. 7. The semiconductor circuit according to claim 1, wherein the plurality of second transistors of the cascode-connected circuit include a transistor of a first conductivity type and a transistor of a second conductivity type.

8. 8. The semiconductor circuit according to claim 7, wherein a node at which a drain of the transistor of the first conductivity type and a drain of the transistor of the second conductivity type are connected among the plurality of second transistors is connected to a gate of the first transistor.

9. a first node to which an input voltage is input; a second node at which an output voltage is output; a third node set to a first voltage; a first transistor connected between the first node and the second node; a cascode connection circuit having a plurality of second transistors cascode-connected between the first node and the third node; a first capacitor connected between the second node and a fourth node of one of the plurality of second transistors; a second capacitor connected between the first node and the fourth node, A power supply device, wherein a fifth node of the first second transistor is connected to a gate of the first transistor.

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