Main amplification circuit and high-frequency power amplifier

Abstract

To achieve low noise, high power efficiency, high linearity, high integration degree, and low cost at the same time.SOLUTION: The present invention provides a main amplification circuit and a high-frequency power amplifier. Two P-type transistor amplifier modules and two N-type transistor amplifier modules are provided. The amplifier module has a cascode structure formed by stacking K transistors. Of a first P-type transistor amplifier module and a first N-type amplifier module, a gate of a main amplifier transistor is connected to a non-inverted input terminal. Connection nodes of the first P-type transistor amplifier module and the first N-type amplifier module are connected to an inverted output terminal. Of a second P-type transistor amplifier module and a second N-type amplifier module, a gate of a main amplifier transistor is connected to the non-inverted input terminal. Connection nodes of the second P-type transistor amplifier module and the second N-type amplifier module are connected to the inverted output terminal.SELECTED DRAWING: Figure 4

Description

[Technical field]

[0001] The present invention relates to the field of integrated circuit design, and in particular to main amplifier circuits and high frequency power amplifiers. [Background technology]

[0002] As 5G and 6G communication technologies develop, more and more signal frequency bands must coexist, and the integration density of the corresponding semiconductor chips is also increasing. However, too many integrated modules will cause many problems, such as chip heat dissipation, reliability, lifespan, cost, etc. It is clear that the only way to effectively solve these problems based on current semiconductor processes is to increase the efficiency, performance (linearity), and integration density of the integrated modules as much as possible.

[0003] A high-frequency power amplifier (power amplifier) ​​is an important module in a high-frequency chip, and its power consumption accounts for about half (40-50%) of the entire power consumption of the high-frequency chip. As shown in Figure 1, the main function of the power amplifier 2 is to amplify the high-frequency signal supplied by the frequency converter 1 and drive the antenna 4 via the balun 3 to emit a wireless signal into space. An ideal power amplifier amplifies the signal at the input terminal without distortion with minimal on-chip power loss and transmits it to the antenna, so improving the power efficiency, linearity, integration, etc. of the power amplifier is essential for development. In addition, the signal transmission distance and the magnitude of the power are related, and it is also an important element of development to pursue the largest possible power amplifier output power, assuming linearity is satisfied.

[0004] FIG. 2 shows an integrated high frequency power amplifier 2, which is composed of two amplifier stages. The first stage is a preamplifier 2a, whose main function is to perform basic amplification of the signal and to isolate the power amplifier input terminal from the main amplifier 2c. The second stage is the main amplifier 2c, which mainly realizes the amplification and boosting of the signal, so that the main amplifier 2c determines the efficiency, linearity and output power of the whole power amplifier. A matching circuit 2b is further provided between the preamplifier 2a and the main amplifier 2c, which is used to realize impedance matching. The structure of the general preamplifier 2a is similar to or identical to that of the main amplifier 2c. In the main amplifier 2c, the transistors M1 and M2 form a differential pair to form a main amplifying transistor. In order to obtain high output power, the power supply voltage Vdd of the main amplifier 2c must generally be much higher than the rated operating voltage of the basic transistors M1 and M2 (transistors that exceed the rated operating voltage are easily burned out). For example, in a 22 nm CMOS process, the rated operating voltage of the basic transistors is less than 1.2 V, but in order to obtain an output power of about 1 W, the power supply voltage Vdd must be at least greater than 3.2 V. Therefore, in order to ensure the safety of the transistors, the transistors M3 and M4 are further overlapped on the upper surface of the transistors M1 and M2 to share the voltage drop of the transistors M1 and M2. Since the voltage that the transistors M3 and M4 must receive exceeds 1.2 V, it is no longer possible to select basic transistors for the transistors M3 and M4, and large-sized high-voltage transistors must be selected and used, but this selection inevitably limits the maximum power efficiency that the power amplifier can obtain.

[0005] Regardless of whether it is the transistors M1 and M2 or the transistors M3 and M4, they all have strong large signal nonlinearity characteristics, so it is necessary to add the transistors M5 and M6 to compensate for some of the nonlinearity, but the addition of the transistors M5 and M6 will undoubtedly increase the capacitive load between the two stages, and even reduce the power efficiency. The transistors M5 and M6 can only compensate for the nonlinearity of the capacitance in the transistors M1 and M2, and other nonlinearities are partially canceled by the push-pull characteristics of the differential pair M3 and M4. Therefore, a significant part of the nonlinearity is transmitted to the load RL, and the linearity of the power amplifier 2 is insufficient. In addition, as shown in Figure 3, the signal distortion increases the time that the non-zero current ID and the non-zero voltage Vout at the output terminal of the main amplifier 2c appear simultaneously, which causes additional power consumption, and further limits the power efficiency of the entire power amplifier.

[0006] In addition, with the increase of output power, under the condition of output impedance mismatch, the transistors M3 and M4 will be subjected to higher voltage, which will cause the risk of damaging the transistors M3 and M4, which will require the introduction of a standing wave ratio (VSWR) protection circuit (not shown in the drawing) due to output mismatch, which will undoubtedly further increase the cost of the circuit.

[0007] To summarize the above, the high-frequency power amplifier 2 in FIG. 2 has the following problems. (1) The high-voltage transistors M3 and M4 limit the power efficiency that the power amplifier can obtain. The transistors M3 and M4 not only have a small mutual conductance gain (compared to the basic transistors M1 and M2), but also have a larger parasitic capacitance parameter themselves, which consumes more power. (2) The compensation of the large-signal nonlinearity characteristics is not sufficient, and the added compensation circuit (transistor) itself also consumes power, so not only is it not possible to obtain a higher power efficiency, but it is also difficult to further improve the linearity. (3) The mutual conductance gain of transistors in a general CMOS process is universally low, so the driving force to the load is not strong enough when only a simple differential push-pull is used for amplification. This increases the overlap area of ​​the non-zero voltage and non-zero current at the output, which further limits the power efficiency of the power amplifier. (4) The voltage that the transistors M3 and M4 must receive can reach a maximum of twice the power supply voltage Vdd, but it is clear that it is impossible to further increase the power supply voltage Vdd in the prior art. (5) Since a standing wave ratio protection circuit needs to be added due to output mismatch, the circuit cost is increased. Therefore, how to improve the power efficiency, linearity, integration level, and output power of a power amplifier while reducing the cost is one of the problems that needs to be solved urgently by those skilled in the art.

[0008] It should be noted that the above technical background introduction is intended to facilitate a clear and complete description of the technical solutions of the present application, and is merely described for the convenience of those skilled in the art, and it cannot be assumed that the above technical solutions are known to those skilled in the art merely because they are described in the background section of the present application. Summary of the Invention [Problem to be solved by the invention]

[0009] In view of the above-mentioned drawbacks of the conventional technology, an object of the present invention is to provide a main amplifier circuit and a radio frequency power amplifier for solving the problem that, in the conventional technology, a radio frequency power amplifier cannot simultaneously achieve high power efficiency, high performance, high integration, high output power, and low cost.

[0010] To achieve the above and other related objectives, the present invention provides a main amplifier circuit for use in a high frequency power amplifier, the main amplifier circuit including at least two P-type transistor amplifier modules and two N-type transistor amplifier modules, the P-type transistor amplifier modules including a cascode structure formed by stacking K PMOS transistors, the N-type transistor amplifier modules including a cascode structure formed by stacking K NMOS transistors, K being a natural number greater than or equal to 3 and less than or equal to 5.

[0011] The first P-type transistor amplification module and the first N-type transistor amplification module are sequentially connected in series between a power supply voltage and ground, the gates of the main amplification transistors of the first P-type transistor amplification module and the first N-type transistor amplification module are connected to the non-inverting input terminal of the main amplification circuit, and the connection node between the first P-type transistor amplification module and the first N-type transistor amplification module is connected to the inverting output terminal of the main amplification circuit.

[0012] The second P-type transistor amplification module and the second N-type transistor amplification module are sequentially connected in series between a power supply voltage and ground, the gates of the main amplification transistors of the second P-type transistor amplification module and the second N-type transistor amplification module are connected to the inverting input terminal of the main amplification circuit, and the connection node between the second P-type transistor amplification module and the second N-type transistor amplification module is connected to the non-inverting output terminal of the main amplification circuit.

[0013] The gate of each transistor in the P-type transistor amplifying module and the N-type transistor amplifying module is connected to a corresponding bias voltage.

[0014] Optionally, the bias voltages of the main amplifying transistors in the P-type transistor amplifying module and the N-type transistor amplifying module are generated by the same bias current.

[0015] Optionally, in each P-type transistor amplifier module and each N-type transistor amplifier module, the gate of the transistor adjacent to the output terminal of the main amplifier circuit is connected to an RC module, and each RC module includes a first resistor and a first capacitor. The first resistor is connected between the gate and drain of the transistor adjacent to the output terminal of the main amplifier circuit, and one end of the first capacitor is connected to the gate of the transistor adjacent to the output terminal of the main amplifier circuit. The other end of each first capacitor connected to the P-type transistor amplifier module is connected to a power supply voltage, and the other end of each first capacitor connected to the N-type transistor amplifier module is grounded.

[0016] Optionally, the gate of the intermediate stage transistor of each P-type transistor amplification module and each N-type transistor amplification module receives a corresponding bias voltage and is respectively connected to a gate capacitor, the other end of the gate capacitor connected to the P-type transistor amplification module is connected to a power supply voltage, and the other end of the gate capacitor connected to the N-type transistor amplification module is grounded.

[0017] More preferentially, K is set to three.

[0018] More preferably, the power supply voltage is between 3V and 3.5V.

[0019] More selectively, the gate of each main amplifying transistor is further connected to a corresponding input terminal of the main amplifying circuit via a respective input capacitor.

[0020] In order to achieve the above and other related objects, the present invention further provides a high frequency power amplifier, which includes at least a preamplifier circuit, a first impedance matching circuit, a second impedance matching circuit and the above-mentioned main amplifier circuit.

[0021] The input terminal of the preamplifier circuit receives a high frequency input signal and performs a preliminary amplification on the high frequency input signal to compensate for distortion of the main amplifier circuit.

[0022] The first impedance matching circuit is connected between the output terminal of the preamplifier circuit and the input terminal of the main amplifier circuit, and is used to realize impedance matching between the preamplifier circuit and the main amplifier circuit.

[0023] The main amplifier circuit amplifies the output signal of the first impedance matching circuit.

[0024] The second impedance matching circuit is connected to the output terminal of the main amplifier circuit, and is used to realize impedance matching between the main amplifier circuit and the output side.

[0025] Optionally, the preamplifier circuit includes a first PMOS differential amplifier module and a first NMOS differential amplifier module.

[0026] The source of the first NMOS differential amplification module is connected to a power supply voltage, the differential input terminal is respectively connected to the non-inverting input terminal and the inverting input terminal of the pre-amplification circuit, and the differential output terminal is respectively connected to the inverting output terminal and the non-inverting output terminal of the pre-amplification circuit.

[0027] The source of the first NMOS differential amplifier module is grounded, the differential input terminal is respectively connected to the non-inverting input terminal and the inverting input terminal of the pre-amplifier circuit, and the differential output terminal is respectively connected to the inverting output terminal and the non-inverting output terminal of the pre-amplifier circuit.

[0028] The gates of the input stage transistors in the first PMOS differential amplifier module are connected to the same bias voltage, and the gates of the input stage transistors in the first NMOS differential amplifier module are connected to the same bias voltage.

[0029] Optionally, the gates of the input stage transistors of the first PMOS differential amplifier module and the first NMOS differential amplifier module are further connected to corresponding input terminals of the preamplifier circuit via an input capacitor, respectively.

[0030] Optionally, the preamplifier circuit includes a first cascode module and a second cascode module, the input terminal of the first cascode module is connected to the non-inverting input terminal of the preamplifier circuit, the output terminal of the first cascode module is connected to the inverting output terminal of the preamplifier circuit, the input terminal of the second cascode module is connected to the inverting input terminal of the preamplifier circuit, and the output terminal of the second cascode module is connected to the non-inverting output terminal of the preamplifier circuit.

[0031] Optionally, the high frequency power amplifier further includes an input buffer circuit, a third impedance matching circuit and a fourth impedance matching circuit.

[0032] The third impedance matching circuit is connected between the high frequency input signal and the input terminal of the input buffer circuit, and is used to realize impedance matching between the input side and the input buffer circuit.

[0033] The fourth impedance matching circuit is connected between the output terminal of the input buffer circuit and the input terminal of the preamplifier circuit, and is used to realize impedance matching between the input buffer circuit and the preamplifier circuit.

[0034] Further optionally, the input buffer circuit includes a current source, a second PMOS differential amplifier module, and a second NMOS differential amplifier module.

[0035] One end of the current source is connected to a power supply voltage, and the other end is connected to the source of the second PMOS differential amplifier module.

[0036] The second PMOS differential amplifier module has differential input terminals respectively connected to the non-inverting input terminal and the inverting input terminal of the input buffer circuit, and differential output terminals respectively connected to the inverting output terminal and the non-inverting output terminal of the input buffer circuit.

[0037] The source of the second NMOS differential amplifier module is grounded, the differential input terminal is respectively connected to the non-inverting input terminal and the inverting input terminal of the input buffer circuit, and the differential output terminal is respectively connected to the inverting output terminal and the non-inverting output terminal of the input buffer circuit.

[0038] A resistor is provided between the gate and drain of each transistor in the second PMOS differential amplifier module and the second NMOS differential amplifier module, and the input terminals of the second PMOS differential amplifier module and the second NMOS differential amplifier module are connected to the corresponding input terminals of the input buffer circuit through an input capacitor.

[0039] Optionally, a ground capacitor is further connected to the connection node between the second PMOS differential amplifier module and the current source.

[0040] Further optionally, each impedance matching circuit is an inductive transformer. Effect of the Invention

[0041] As described above, the main amplifier circuit and the high frequency power amplifier according to the present invention have the following beneficial effects.

[0042] (1) The main amplifier circuit and the high frequency power amplifier in the present invention adopt a dual push-pull power amplifier architecture consisting of a PMOS structure and an NMOS structure in which multiple transistors are stacked, and the dual push-pull is used to reduce the overlap time of non-zero voltage and non-zero current at the output port, thereby effectively improving power efficiency.

[0043] (2) The main amplifier circuit and the high frequency power amplifier of the present invention use an RC filter structure and the principle of capacitor voltage division to achieve equal distribution of the high power supply voltage among the three superimposed basic transistors.

[0044] (3) In the main amplifier circuit and the high frequency power amplifier of the present invention, the PMOS main amplifier transistor and the NMOS main amplifier transistor share the same bias DC current, thereby improving the power efficiency.

[0045] (4) The basic NMOS main amplifying transistor and the basic PMOS main amplifying transistor connected in parallel in the main amplifier circuit and the radio frequency power amplifier of the present invention have a characteristic that the nonlinear capacitance of the transistors is automatically compensated for, improving power efficiency without the need for additional elements.

[0046] (5) In the main amplifier circuit and the radio frequency power amplifier of the present invention, in a back-to-back connection of a PMOS structure in which a plurality of transistors are stacked and an NMOS structure in which a plurality of transistors are stacked, the nonlinear mutual conductance gain in the PMOS transistor and the nonlinear mutual conductance gain in the NMOS transistor can be mutually cancelled or partially cancelled, thereby effectively improving linearity.

[0047] (6) In the main amplifier circuit and high frequency power amplifier of the present invention, when a PMOS structure in which a plurality of transistors are stacked and an NMOS structure in which a plurality of transistors are stacked are connected back to back, the node voltages of all the basic transistors in the main amplifier circuit do not exceed the power supply voltage of the main amplifier circuit under any circumstances, and there is no need to add an additional voltage standing wave ratio protection circuit, resulting in lower costs. [Brief description of the drawings]

[0048] [Figure 1] FIG. 1 is a schematic diagram showing the operating principle of a conventional high-frequency power amplifier. [Diagram 2] FIG. 2 is a schematic diagram showing the structure of a conventional high-frequency power amplifier. [Diagram 3] FIG. 3 is a schematic diagram of the principle by which loss is caused by signal distortion in the prior art. [Figure 4] FIG. 4 is a schematic diagram showing the structure of a main amplifier circuit in the present invention. [Diagram 5] FIG. 5 is a diagram showing a voltage curve of an output terminal of an output inductor when an output mismatch occurs in the present invention. [Figure 6] FIG. 6 is a diagram showing an output voltage curve of the main amplifier circuit when there is output mismatch in the present invention. [Figure 7] FIG. 7 is a schematic diagram showing the structure of a high-frequency power amplifier according to the present invention. [Figure 8] FIG. 8 is a schematic diagram showing the structure of a preamplifier circuit according to the present invention. [Figure 9] FIG. 9 is a schematic diagram of another structure of the preamplifier circuit in the present invention. [Figure 10] FIG. 10 is a schematic diagram of another structure of a high-frequency power amplifier according to the present invention. [Figure 11] FIG. 11 is a schematic diagram showing the structure of an input buffer circuit according to the present invention. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0049] Hereinafter, the implementation of the present invention will be described through specific specific embodiments, but those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. In addition, the present invention can be implemented or applied by other different specific implementation means. Various supplements or modifications may be made to the details in this specification based on different perspectives and applications without departing from the spirit of the present invention.

[0050] Please refer to Figures 4 to 11. It should be noted that the drawings provided in this embodiment are merely for the purpose of roughly explaining the basic idea of ​​the present invention. The drawings show only assemblies related to the present invention, but are not based on the number, shape and size of the assemblies when actually implemented. The form, quantity and ratio of each assembly when actually implemented may be changed arbitrarily, and the layout and form of the assemblies may be more complicated.

[0051] EMBODIMENT 1 As shown in FIG. 4, this embodiment provides a main amplifier circuit 21, which is applied to a high frequency power amplifier 2. The main amplifier circuit 21 includes two P-type transistor amplifier modules and two N-type transistor amplifier modules, which are respectively referred to as a first P-type transistor amplifier module 211, a second P-type transistor amplifier module 212, a first N-type transistor amplifier module 213 and a second N-type transistor amplifier module 214. The first P-type transistor amplifier module 211 and the first N-type transistor amplifier module 213 are sequentially connected in series between a power supply voltage Vddda and ground, the gates of the main amplifier transistors of the first P-type transistor amplifier module 211 and the first N-type transistor amplifier module 213 are connected to the non-inverting input terminal in+ of the main amplifier circuit 21, and the connection node between the first P-type transistor amplifier module 211 and the first N-type transistor amplifier module 213 is connected to the inverting output terminal out- of the main amplifier circuit 21. The second P-type transistor amplification module 212 and the second N-type transistor amplification module 214 are sequentially connected in series between the power supply voltage Vddda and ground, the gates of the main amplification transistors of the second P-type transistor amplification module 212 and the second N-type transistor amplification module 214 are connected to the inverting input terminal in- of the main amplification circuit 21, and the connection node between the second P-type transistor amplification module 212 and the second N-type transistor amplification module 214 is connected to the non-inverting output terminal out+ of the main amplification circuit 21.

[0052] Specifically, the first P-type transistor amplifier module 211 and the second P-type transistor amplifier module 212 form a P-type transistor differential pair, and the first N-type transistor amplifier module 213 and the second N-type transistor amplifier module 214 form an N-type transistor differential pair, forming a differential push-pull. The two differential pairs are connected back-to-back together to form another push-pull superimposed on the differential pair base (the solid and dotted arrows in FIG. 4 indicate two conduction paths by different input signals). When the first P-type transistor amplifier module 211 and the second N-type transistor amplifier module 214 are conductive, the second P-type transistor amplifier module 212 and the first N-type transistor amplifier module 213 are turned off, and when the second P-type transistor amplifier module 212 and the first N-type transistor amplifier module 213 are conductive, the first P-type transistor amplifier module 211 and the second N-type transistor amplifier module 214 are turned off, thereby achieving a dual push-pull effect for the load RL. In the dual push-pull, the transient period in the signal waveform at the output terminal is inevitably shortened, so that the overlap time of the non-zero voltage and the non-zero current at the output terminal is effectively reduced, and the power efficiency is effectively improved.

[0053] More specifically, in terms of the input signal, the main amplification transistors of the first P-type transistor amplification module 211 and the first N-type transistor amplification module 213 are parallel-connected transistors with the same input signal (non-inverted input signal of the main amplification circuit 21), and the main amplification transistors of the second P-type transistor amplification module 212 and the second N-type transistor amplification module 214 are parallel-connected transistors with the same input signal (inverted input signal of the main amplification circuit 21), and the parallel-connected PMOS transistors and NMOS transistors simultaneously and automatically have the function of compensating for nonlinear capacitance. Therefore, the main amplification circuit 21 of the present invention does not need to compensate for nonlinearity caused by nonlinear capacitance by adding transistors M5 and M6 separately as in the method of FIG. 2, and the parasitic effect of transistors M5 and M6 is also eliminated. There is no doubt that the main amplification circuit 21 of the present invention will obtain higher power efficiency under the condition that the same linearity is maintained. In addition, the nonlinearity in the main amplifier circuit is not only caused by the nonlinear capacitance of the input terminal of the transistor, but also by the nonlinear mutual conductance gain of the transistor itself, and the method of Fig. 2 compensates for the nonlinear capacitance by the transistors M5 and M6, but is useless for the nonlinear mutual conductance gain. The back-to-back connection of the PMOS transistor and the NMOS transistor in the present invention can exactly cancel the nonlinear mutual conductance of the PMOS transistor and the nonlinear mutual conductance of the NMOS transistor. As shown in FIG. 4, under the same circumstances, the nonlinearity of the mutual conductance in the PMOS transistors MP1, MP2, MP3 (or MP4, MP5, MP6) and the nonlinearity of the mutual conductance in the NMOS transistors MN1, MN2, MN3 (or MN4, MN5, MN6) flow directly from the power supply to the ground terminal via MP1, MP2, MP3, MN3, MN2, MN1 (or MP4, MP5, MP6, MN6, MN5, MN4) in sequence, and therefore do not appear in the load RL, thereby effectively improving the linearity.

[0054] As shown in FIG. 4, the P-type transistor amplification module includes a cascode structure formed by stacking K PMOS transistors, and the N-type transistor amplification module includes a cascode structure formed by stacking K NMOS transistors, where K is a natural number greater than or equal to 3 and less than or equal to 5.

[0055] Specifically, in this embodiment, K is 3. In actual use, the number of transistors in the P-type transistor amplification module and the N-type transistor amplification module can be set as necessary, not limited to this embodiment. In this embodiment, the first P-type transistor amplification module 211 includes a first PMOS transistor MP1, a second PMOS transistor MP2, and a third PMOS transistor MP3. The source of the first PMOS transistor MP1 is connected to the power supply voltage Vddda, the gate is connected to the non-inverting input terminal in+ of the main amplification circuit 21, the drain is connected to the source of the second PMOS transistor MP2, the drain of the second PMOS transistor MP2 is connected to the source of the third PMOS transistor MP3, the drain of the third PMOS transistor MP3 is connected to the inverting output terminal out- of the main amplification circuit 21, and the gates of the first PMOS transistor MP1, the second PMOS transistor MP2, and the third PMOS transistor MP3 are connected to the corresponding bias voltages. At this time, the first P-type transistor amplification module 211 forms a cascode structure, and the first PMOS transistor MP1 is the main amplification transistor of the input stage. For the same reason, the second P-type transistor amplification module 212 includes a fourth PMOS transistor MP4, a fifth PMOS transistor MP5 and a sixth PMOS transistor MP6. The gate of the fourth PMOS transistor MP4 is connected to the inverting input terminal in- of the main amplification circuit 21, and the drain of the sixth PMOS transistor MP6 is connected to the non-inverting output terminal out+ of the main amplification circuit 21. The connection relationship between the PMOS transistors is the same as that of the first P-type transistor amplification module 211, and will not be described in detail here.

[0056] Specifically, in this embodiment, the first N-type transistor amplification module 213 includes a first NMOS transistor MN1, a second NMOS transistor MN2 and a third NMOS transistor MN3. The source of the first NMOS transistor MN1 is grounded, the gate is connected to the non-inverting input terminal in+ of the main amplifier circuit 21, the drain is connected to the source of the second NMOS transistor MN2, the drain of the second NMOS transistor MN2 is connected to the source of the third NMOS transistor MN3, the drain of the third NMOS transistor MN3 is connected to the inverting output terminal out- of the main amplifier circuit 21, and the gates of the first NMOS transistor MN1, the second NMOS transistor MN2 and the third NMOS transistor MN3 are connected to corresponding bias voltages. At this time, the first N-type transistor amplification module 213 forms a cascode structure, and the first NMOS transistor MN1 is the main amplifier transistor of the input stage. For the same reason, the second NMOS transistor amplification module 214 includes a fourth NMOS transistor MN4, a fifth NMOS transistor MN5 and a sixth NMOS transistor MN6. The gate of the fourth NMOS transistor MN4 is connected to the inverting input terminal in- of the main amplifier circuit 21, and the drain of the sixth NMOS transistor MN6 is connected to the non-inverting output terminal out+ of the main amplifier circuit 21. The connections between the NMOS transistors are the same as those of the first N-type transistor amplifier module 213, and will not be described in detail here.

[0057] It should be noted that in this embodiment, an output power of about 1 watt is achieved by setting the power supply voltage Vddda to 3 V to 3.5 V. The power supply voltage Vddda includes, but is not limited to, 3.3 V, and when actually used, the value of the power supply voltage can be set as necessary, without being limited to this embodiment.

[0058] It should be noted that in this embodiment, each transistor is a basic transistor, and compared with the method using high-voltage transistors in FIG. 2, not only the parasitic parameters are smaller but also the mutual conductance gain is larger, so that the power efficiency can be further improved. In addition, in this embodiment, the back-to-back connection of the PMOS transistor in which three transistors are stacked and the NMOS transistor in which three transistors are stacked means that the voltage of the node formed by connecting all the basic transistors of the main amplifier circuit 21 does not exceed the power supply voltage Vddda of the main amplifier circuit 21 under any circumstances. As shown in FIG. 5, the voltage peak of the output terminal of the output inductor (the main amplifier circuit 21 is connected to the load RL via the output inductor) during output mismatch (RL: 1 to 500 ohms) exceeds 17V when RL=500 ohms, but as shown in FIG. 6, the maximum peak of the output voltage of the main amplifier circuit 21 during output mismatch (RL: 1 to 500 ohms) is less than 4V (RL=1 ohm), and the output power when the impedance causes a fatal mismatch is small. Therefore, in this embodiment, there is no need to add any voltage standing wave ratio protection circuit, which can effectively reduce the cost of the chip.

[0059] As shown in FIG. 4, the gate of each transistor in the P-type transistor amplifying module and the N-type transistor amplifying module is connected to a corresponding bias voltage.

[0060] Specifically, as an example, the gate of the first PMOS transistor MP1 is connected to the first bias voltage Vbp1 through the second resistor R2, the gate of the fourth PMOS transistor MP4 is connected to the first bias voltage Vbp1 through the third resistor R3 (same resistance value as the second resistor R2), the gates of the second PMOS transistor MP2 and the fifth PMOS transistor MP5 are connected to the second bias voltage Vbp2, and the gates of the third PMOS transistor MP3 and the sixth PMOS transistor MP6 are connected to the third bias voltage. The gate of the first NMOS transistor MN1 is connected to the fourth bias voltage Vbn1 through the fourth resistor R4, the gate of the fourth NMOS transistor MN4 is connected to the fourth bias voltage Vbn1 through the fifth resistor R5 (same resistance value as the fourth resistor R4), the gates of the second NMOS transistor MN2 and the fifth NMOS transistor MN5 are connected to the fifth bias voltage Vbn2, and the gates of the third NMOS transistor MN3 and the sixth NMOS transistor MN6 are connected to the sixth bias voltage. Each bias voltage is provided by an external bias generating circuit (not shown in the drawing).

[0061] It should be noted that in this embodiment, the bias voltages of corresponding transistors in the first P-type transistor amplification module 211 and the second P-type transistor amplification module 212 are the same, and the bias voltages of corresponding transistors in the first N-type transistor amplification module 213 and the second N-type transistor amplification module 214 are the same. In actual use, the bias voltage of each transistor can be set as needed, regardless of this embodiment.

[0062] Specifically, as another example, the gates of the first PMOS transistor MP1, the second PMOS transistor MP2, the fourth PMOS transistor MP4, the fifth PMOS transistor MP5, the first NMOS transistor MN1, the second NMOS transistor MN2, the fourth NMOS transistor MN4 and the fifth NMOS transistor MN5 all receive an external bias voltage (same as the above example). The gate of the third PMOS transistor MP3 is connected to the first RC module 215, and is provided with a self-bias by the first RC module 215. The first RC module 215 includes a first resistor R1 and a first capacitor C1, the first resistor R1 is connected between the gate and drain of the third PMOS transistor MP3, one end of the first capacitor C1 is connected to the gate of the third PMOS transistor MP3, and the other end is connected to the power supply voltage Vddda. The gate of the sixth PMOS transistor MP6 is connected to the second RC module 216, and the device, structure and parameters of the second RC module 216 are all the same as those of the first RC module 215, and will not be described in detail here. The gate of the third NMOS transistor MN3 is connected to the third RC module 217, and the third RC module 217 and the first RC module 215 have basically the same structure, and will not be described in detail here. The difference is that in the third RC module 217, one end of the first capacitor C1 is connected to the gate of the third NMOS transistor MN3, and the other end is grounded. The gate of the sixth NMOS transistor MN6 is connected to the fourth RC module 218, and the device, structure and parameters of the fourth RC module 218 are the same as those of the third RC module 217, and will not be described in detail here.

[0063] It should be noted that in this embodiment, the device parameters of the first RC module 215 and the second RC module 216 are the same, and the device parameters of the third RC module 217 and the fourth RC module 218 are the same. In actual use, the present embodiment is not limited to this embodiment, and appropriate parameters can be set as needed.

[0064] As shown in Fig. 4, in one implementation of the present invention, the bias voltages of the main amplifier transistors in the P-type transistor amplifier module and the N-type transistor amplifier module are generated by the same bias current. That is, the same bias current is mirrored by a master-slave type replica circuit consisting of a mirror current source to obtain the first bias voltage Vbp1 and the fourth bias voltage Vbn1, which are applied to the corresponding gates via the corresponding resistors R2, R3, R4 and R5, respectively. The P-type main power amplifier transistor and the N-type main power amplifier transistor in the present invention share the same DC bias current, and in the situation where the DC bias current is the same, the transconductance gain of the main amplifier transistor in the present invention is twice that of the main amplifier transistor in Fig. 2 (assuming that the N-type transistor and the P-type transistor are the same). Therefore, the main amplifier circuit 21 in the present invention has higher power efficiency.

[0065] As shown in Fig. 4, as one implementation of the present invention, the gate of the intermediate stage transistor of each P-type transistor amplification module and each N-type transistor amplification module is respectively connected to one gate capacitor. The intermediate stage transistor refers to a transistor interposed between the main amplification transistor and the transistor close to the output terminal of the main amplification circuit 21 in each amplification module. In this embodiment, the gate of the second PMOS transistor MP2 is connected to the first gate capacitor C2, the gate of the fifth PMOS transistor MP5 is connected to the second gate capacitor C3, the other ends of the first gate capacitor C2 and the second gate capacitor C3 are connected to the power supply voltage Vddda, the gate of the second NMOS transistor MN2 is connected to the third gate capacitor C4, the gate of the fifth NMOS transistor MN5 is connected to the fourth gate capacitor C5, and the other ends of the third gate capacitor C4 and the fourth gate capacitor C5 are grounded.

[0066] In this embodiment, each RC module is for ensuring that the divided voltage of the transistors (the third PMOS transistor MP3, the sixth PMOS transistor MP6, the third NMOS transistor MN3, and the sixth NMOS transistor MN6) adjacent to the output terminal of the main amplifier circuit 21 does not exceed the rated voltage (for example, about 1.2V), and each gate capacitor (the first gate capacitor C2, the second gate capacitor C3, the third gate capacitor C4, and the fourth gate capacitor C5) can distribute the remaining power supply voltage approximately equally to the intermediate stage transistors (the second PMOS transistor MP2, the fifth PMOS transistor MP5, the second NMOS transistor MN2, and the fifth NMOS transistor MN5) and the main amplifier transistors (the first PMOS transistor MP1, the fourth PMOS transistor MP4, the first NMOS transistor MN1, and the fourth NMOS transistor MN4). In this way, the power supply voltage of 3.3V can be basically distributed equally to the three overlapping transistors, thereby ensuring that all the transistors operate safely.

[0067] As shown in FIG. 4, as one implementation of the present invention, the gate of each main amplifier transistor is further connected to the corresponding input terminal of the main amplifier circuit 21 via one input capacitor. The gates of the first PMOS transistor MP1 and the first NMOS transistor MN1 are connected to the non-inverting input terminal in+ of the main amplifier circuit 21 via the first input capacitor C6 and the third input capacitor C8, respectively, and the gates of the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 are connected to the inverting input terminal in- of the main amplifier circuit 21 via the second input capacitor C7 and the fourth input capacitor C9, respectively. Each input capacitor is used to insulate the input of the main amplifier circuit 21 from the direct current of the previous stage output terminal (at this time, the input of the main amplifier circuit 21 and the previous stage output terminal, which have the same polarity, are connected in correspondence). Not limited to this embodiment, when the input of the main amplifier circuit 21 and the previous stage output terminal are connected in a cross manner (at this time, the input of the main amplifier circuit 21 and the previous stage output terminal, which have the opposite polarity, are connected in correspondence), each input capacitor can be omitted.

[0068] Comparing the main amplifier circuit 21 in this embodiment with the main amplifier 2c in FIG. 2, the present invention simultaneously achieves low noise, high power efficiency, high linearity, high integration and low cost, and the power efficiency increases to over 60%.

[0069] EMBODIMENT 2 This embodiment provides a main amplifier circuit 21. The difference from the first embodiment is that K is 4 or 5.

[0070] Specifically, each amplification module includes four or five transistors, which corresponds to the three-transistor stacked structure in embodiment 1. The four-transistor or five-transistor stacked structure is based on the three-transistor stacked structure and adds a corresponding number of intermediate stage transistors, where each transistor is a basic transistor.

[0071] The main amplifier circuit 21 in this embodiment has the advantages of high linearity, high integration, high power efficiency and low cost. It should be noted that the four or five transistor stacked structure has more transistor tubes, which causes more gate voltage bias problems and is more likely to cause parasitic oscillation, making it more difficult for the main amplifier circuit 21 to maintain normal amplification function. At the same time, the headroom voltage of each transistor tube is reduced, which reduces the mutual conductance gain of each transistor tube and also affects the power efficiency of the main amplifier circuit.

[0072] The other structures and principles are the same as those of the first embodiment, and will not be described in detail here.

[0073] EMBODIMENT 3 7, this embodiment provides a high frequency power amplifier 2. The high frequency power amplifier 2 includes a main amplifier circuit 21, a preamplifier circuit 22, a first impedance matching circuit 23 and a second impedance matching circuit 24, and has a two-stage amplification structure.

[0074] As shown in FIG. 7, the input terminal of the preamplifier circuit 22 receives a high frequency input signal IN, and performs a basic amplification on the high frequency input signal IN to compensate for distortion of the main amplifier circuit 21.

[0075] Specifically, as one embodiment of the present invention, the preamplifier circuit 22 includes a first PMOS differential amplifier module 221 and a first NMOS differential amplifier module 222, and the source of the first PMOS differential amplifier module 221 is connected to a power supply voltage Vdd (the power supply voltage of the preamplifier circuit 22 may be the same as or different from the power supply voltage of the main amplifier circuit 21, and is not limited to this embodiment and is set based on actual needs). The differential input terminals are respectively connected to the non-inverting input terminal in+ and the inverting input terminal in- of the preamplifier circuit 22, and the differential output terminals are respectively connected to the inverting output terminal out- and the non-inverting output terminal out+ of the preamplifier circuit 22. As shown in FIG. 8, the first PMOS differential amplifier module 221 includes a seventh PMOS transistor MP7 and an eighth PMOS transistor MP8, forming a differential pair transistor. The gates of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are respectively connected to a seventh bias voltage Vbp3 via a sixth resistor R6 and a seventh resistor R7. The source of the first NMOS differential amplifier module 222 is grounded, the differential input terminal is respectively connected to the non-inverting input terminal in+ and the inverting input terminal in- of the preamplifier circuit 22, and the differential output terminal is respectively connected to the inverting output terminal out- and the non-inverting output terminal out+ of the preamplifier circuit 22. As shown in FIG. 8, the first NMOS differential amplifier module 222 includes a seventh NMOS transistor MN7 and an eighth NMOS transistor MN8, which constitute a differential pair transistor. The gates of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are respectively connected to the eighth bias voltage Vbn3 via an eighth resistor R8 and a ninth resistor R9. In this example, the seventh bias voltage Vbp3 and the eighth bias voltage Vbn3 are obtained by mirroring the same bias current by a master-slave type replica circuit consisting of a mirror current source. Furthermore, in this embodiment, the gates of the seventh PMOS transistor MP7 and the eighth PMOS transistor MP8 are connected to corresponding input terminals via a fifth input capacitor C10 and a sixth input capacitor C11, respectively, and the gates of the seventh NMOS transistor MN7 and the eighth NMOS transistor MN8 are further connected to corresponding input terminals via a seventh input capacitor C12 and an eighth input capacitor C13, respectively.

[0076] Specifically, as another embodiment of the present invention, as shown in Figure 9, the preamplifier circuit 22 includes a first cascode module 223 and a second cascode module 224, the input terminal of the first cascode module 223 is connected to the non-inverting input terminal in+ of the preamplifier circuit 22, the output terminal is connected to the inverting output terminal out- of the preamplifier circuit 22, the input terminal of the second cascode module 224 is connected to the inverting input terminal in- of the preamplifier circuit 22, and the output terminal is connected to the non-inverting output terminal out+ of the preamplifier circuit 22. As an example, the first cascode module 223 and the second cascode module 224 are realized using NMOS transistors, and the first cascode module 223 includes a ninth NMOS transistor MN9 and a tenth NMOS transistor MN10, the ninth NMOS transistor MN9 is a main amplifying transistor, the source of which is grounded, the gate of which is connected to the input signal, the drain of which is connected to the source of the tenth NMOS transistor MN10, the gate of the tenth NMOS transistor MN10 is connected to the ninth bias voltage Vbn4, and the drain of which is connected to the output terminal. For the same reason, the second cascode module 224 includes an eleventh NMOS transistor MN11 and a twelfth NMOS transistor MN12, the eleventh NMOS transistor MN11 is a main amplifying transistor, its source is grounded, its gate is connected to the input signal, its drain is connected to the source of the twelfth NMOS transistor MN12, the gate of the twelfth NMOS transistor MN12 is connected to the ninth bias voltage Vbn4, and its drain is connected to the output terminal. In this example, the output terminal of the preamplifier circuit 22 is connected to the power supply voltage Vdd through the coil of the first impedance matching circuit 23. As another example, the first cascode module 223 and the second cascode module 224 are realized using PMOS transistors, and the circuit structure is adjusted accordingly, which will not be described in detail here.

[0077] It should be noted that the preamplifier circuit 22 does not require a high power supply voltage, and it is not necessary to use the method of superimposing PMOS and NMOS transistors shown in FIG. 8 to perform preamplification, so the preamplifier circuit structure of FIG. 8 can achieve better isolation between the input and output (of the preamplifier circuit 22), and has a large mutual conductance gain, but the output amplitude is small. In addition, the preamplifier circuit structure of FIG. 9 is realized using a differential pair of basic MOS transistors, and does not use the method of superimposing PMOS and NMOS transistors, so it has a large output amplitude, but the mutual conductance gain is relatively small. In actual use, a suitable circuit structure can be selected according to needs, and it goes without saying that the preamplifier circuit is not limited to the methods listed in this embodiment, and any circuit structure that can realize preamplification of high-frequency signals is applicable to the present invention.

[0078] As shown in FIG. 7, the first impedance matching circuit 23 is connected between the output terminal of the preamplifier circuit 22 and the input terminal of the main amplifier circuit 21, and is used to realize impedance matching between the preamplifier circuit 22 and the main amplifier circuit 21.

[0079] Specifically, in this embodiment, the first impedance matching circuit 23 is realized using an inductive transformer. Both ends of a first coil of the inductive transformer are connected to the output terminals of the preamplifier circuit 22, and both ends of a second coil are connected to the input terminals of the main amplifier circuit 21.

[0080] As shown in FIG. 7, the main amplifier circuit 21 amplifies the output signal of the first impedance matching circuit .

[0081] Specifically, the main amplifier circuit 21 adopts the main amplifier circuit structure of embodiment 1 or embodiment 2. For the specific structure and principle, please refer to the above text, and will not be described in detail here.

[0082] As shown in FIG. 7, the second impedance matching circuit 24 is connected to the output terminal of the main amplifier circuit 21 and is used to achieve impedance matching between the main amplifier circuit 21 and the output side.

[0083] Specifically, in this embodiment, the second impedance matching circuit 24 is realized by using an inductive transformer. The output side includes, but is not limited to, a load, which will not be described in detail here. In Fig. 4, the transformer provided at the output terminal of the main amplifier circuit 21 is the second impedance matching circuit 24, and the transformer is shown in Fig. 4 to facilitate understanding of the operating principle of the main amplifier circuit 21.

[0084] It should be noted that, in actual use, the present invention is not limited to this embodiment, and any circuit structure capable of realizing impedance matching can be applied to the present invention.

[0085] EMBODIMENT 4 10, this embodiment provides a radio frequency power amplifier 2. The difference from embodiment 3 is that the radio frequency power amplifier 2 further includes an input buffer circuit 25, a third impedance matching circuit 26, and a fourth impedance matching circuit 27 before the preamplifier circuit 22, thereby realizing a three-stage amplification structure.

[0086] As shown in FIG. 10, the third impedance matching circuit 26 is connected between the high-frequency input signal IN and the input terminal of the input buffer circuit 25 , and is used to realize impedance matching between the input side and the input buffer circuit 25 .

[0087] Specifically, in this embodiment, the third impedance matching circuit 26 is realized by using an inductive transformer. The input side includes, but is not limited to, a front-stage frequency converter and a compensation circuit, which will not be described in detail here.

[0088] As shown in FIG. 10, input buffer circuit 25 provides isolation while at the same time providing corresponding gain.

[0089] Specifically, in this embodiment, the input buffer circuit 25 includes a current source Ib, a second PMOS differential amplifier module 251, and a second NMOS differential amplifier module 252. One end of the current source Ib is connected to a power supply voltage Vdd (which may or may not be equal to the power supply voltage of the main amplifier circuit 21 and / or the preamplifier circuit 22), and the other end is connected to the source of the second PMOS differential amplifier module 251. As an example, one current source Ib is provided for each of the two paths from the power supply to the ground, and the same current source can be shared in actual use. The differential input terminals of the second PMOS differential amplifier module 251 are respectively connected to the non-inverting input terminal in+ and the inverting input terminal in- of the input buffer circuit 25, and the differential output terminals are respectively connected to the inverting output terminal out- and the non-inverting output terminal out+ of the input buffer circuit 25. As shown in FIG. 11, the second PMOS differential amplifier module 251 includes a ninth PMOS transistor MP9 and a tenth PMOS transistor MP10, forming a differential pair transistor. The source of the second NMOS differential amplification module 252 is grounded, the differential input terminal is respectively connected to the non-inverting input terminal in+ and the inverting input terminal in- of the input buffer circuit 25, and the differential output terminal is respectively connected to the inverting output terminal out- and the non-inverting output terminal out+ of the input buffer circuit 25. As shown in Fig. 11, the second NMOS differential amplification module 252 includes a thirteenth NMOS transistor MN13 and a fourteenth NMOS transistor MN14, which form a differential pair transistor. In the second PMOS differential amplification module 251 and the second NMOS differential amplification module 252, a resistor is provided between the gate and drain of each transistor.As shown in FIG. 11, the ninth PMOS transistor MP9 and the thirteenth NMOS transistor MN13 share a tenth resistor R10, one end of which is connected to the gates of the ninth PMOS transistor MP9 and the thirteenth NMOS transistor MN13 and the other end of which is connected to the inverting output terminal out- of the input buffer circuit 25. The tenth PMOS transistor MP10 and the fourteenth NMOS transistor MN14 share an eleventh resistor R11, one end of which is connected to the gates of the tenth PMOS transistor MP10 and the fourteenth NMOS transistor MN14 and the other end of which is connected to the inverting output terminal out- of the input buffer circuit 25. A ninth input capacitor C14 is connected in series between the second PMOS differential amplifier module 251 and the second NMOS differential amplifier module 252 and the non-inverting input terminal in+ of the input buffer circuit 25, and a tenth input capacitor C15 is connected in series between the second PMOS differential amplifier module 251 and the second NMOS differential amplifier module 252 and the inverting input terminal in- of the input buffer circuit 25. In this embodiment, a ground capacitor is further connected to the connection node between the second PMOS differential amplifier module 251 and the current source Ib. As an example, the connection node between the two current sources and the second PMOS differential amplifier module 251 is connected to a first ground capacitor C16 and a second ground capacitor C17, respectively.

[0090] It should be noted that in this embodiment, the input buffer circuit 25 is a transconductance buffer. The current source Ib supplies a constant current bias to the input buffer circuit 25, thereby reducing the influence on the previous stage. The tenth resistor R10 and the eleventh resistor R11 are used to supply a DC voltage bias to isolate the input and output. In actual use, the present invention is not limited to this embodiment, and any circuit structure that can realize an isolation buffer can be applied to the present invention.

[0091] As shown in FIG. 10, the fourth impedance matching circuit 27 is connected between the output terminal of the input buffer circuit 25 and the input terminal of the preamplifier circuit 22, and is used to realize impedance matching between the input buffer circuit 25 and the preamplifier circuit 22.

[0092] Specifically, in this embodiment, the third impedance matching circuit 26 is realized using an inductive transformer.

[0093] The other structures and principles are the same as those of the third embodiment, and will not be described in detail here.

[0094] Conventional wireless communication technologies require high efficiency and high linearity of RF power amplifiers without exception, especially in the middle output power range of about 10 dB back-off, few typical conventional integrated power amplifiers can achieve power efficiency of more than 15% in the back-off output power range, while the RF power amplifier 2 of the present invention achieves a corresponding power efficiency of nearly 30%. The present invention further improves the linearity of the RF power amplifier by further compensating for the nonlinearity of the transistors through a new architecture, effectively improving the linearity by more than 10 dB compared with the similar power amplifier. The present invention uses a shared DC bias current to provide the same gain with smaller size transistors, all the transistors used are basic transistors rather than high voltage transistors, and the voltage standing wave ratio protection circuit can be omitted, so that the present invention can obtain the obvious advantage of low cost.

[0095] To sum up, the present invention provides a main amplifier circuit and a high frequency power amplifier, comprising two P-type transistor amplifier modules and two N-type transistor amplifier modules, the P-type transistor amplifier module comprises a cascode structure formed by stacking K PMOS transistors, the N-type transistor amplifier module comprises a cascode structure formed by stacking K NMOS transistors, K being a natural number greater than or equal to 3 and less than or equal to 5. The first P-type transistor amplifier module and the first N-type transistor amplifier module are sequentially connected in series between a power supply voltage and ground, the gates of the main amplifier transistors of the first P-type transistor amplifier module and the first N-type transistor amplifier module are connected to the non-inverting input terminal of the main amplifier circuit, and the connection node between the first P-type transistor amplifier module and the first N-type transistor amplifier module is connected to the inverting output terminal of the main amplifier circuit. The second P-type transistor amplification module and the second N-type transistor amplification module are sequentially connected in series between the power supply voltage and the ground, the gates of the main amplification transistors of the second P-type transistor amplification module and the second N-type transistor amplification module are connected to the inverting input terminal of the main amplification circuit, and the connection node between the second P-type transistor amplification module and the second N-type transistor amplification module is connected to the non-inverting output terminal of the main amplification circuit. The gates of each transistor in the P-type transistor amplification module and the N-type transistor amplification module are connected to the corresponding bias voltage. The main amplification circuit and the high frequency power amplifier in the present invention adopt a dual push-pull power amplifier architecture consisting of a PMOS structure and an NMOS structure stacked with multiple transistors, and use the dual push-pull to reduce the overlap time of non-zero voltage and non-zero current at the output port, thereby effectively improving the power efficiency. By using the RC filter structure and the principle of capacitive voltage division, the high power supply voltage is evenly distributed among the three basic transistors that are superimposed, and the PMOS main amplification transistor and the NMOS main amplification transistor share the same bias DC current, thereby improving the power efficiency.The parallel-connected basic NMOS main amplifier transistor and the basic PMOS main amplifier transistor have the property of automatically compensating for the nonlinear capacitance of the transistor, and improve the power efficiency without the need for additional elements. The back-to-back connection of the PMOS structure with multiple stacked transistors and the NMOS structure with multiple stacked transistors can cancel or partially cancel the nonlinear transconductance gain of the PMOS transistor and the nonlinear transconductance gain of the NMOS transistor, effectively improving the linearity, and ensuring that the node voltages of all basic transistors in the main amplifier circuit will not exceed the power supply voltage of the main amplifier circuit under any circumstances, eliminating the need for additional voltage standing wave ratio protection circuits, and lowering the cost. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has high industrial applicability.

[0096] The above-described embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Those skilled in the art may make supplements or modifications to the above-described embodiments without departing from the spirit and scope of the present invention. Therefore, any equivalent supplements or modifications that a person skilled in the art completes without departing from the spirit and technical ideas disclosed in the present invention are still included in the scope of the claims of the present invention. [Explanation of symbols]

[0097] 1 Frequency converter 2. Radio Frequency Power Amplifier 2a preamplifier 2b matching circuit 2c Main amplifier 3. Balun 4 Antennas 21 Main amplifier circuit 22 Preamplifier Circuit 23 First impedance matching circuit 24 Second impedance matching circuit 25 Input buffer circuit 26 Third impedance matching circuit 27 Fourth impedance matching circuit 211 First P-type transistor amplifier module 212 Second P-type transistor amplifier module 213 First N-type transistor amplifier module 214 Second N-type transistor amplifier module 215~218 1st~4th RC Modules 221 First PMOS differential amplifier module 222 First NMOS differential amplifier module 223 First Cascode Module 224 Second Cascode Module 251 Second PMOS differential amplifier module 252 Second NMOS differential amplifier module

Claims

1. A main amplifier circuit applied to a high frequency power amplifier, comprising: the main amplifier circuit includes at least two P-type transistor amplifier modules and two N-type transistor amplifier modules, the P-type transistor amplifier module includes a cascode structure configured by stacking K PMOS transistors, the N-type transistor amplifier module includes a cascode structure configured by stacking K NMOS transistors, K is a natural number greater than or equal to 3 and less than or equal to 5; a first P-type transistor amplification module and a first N-type transistor amplification module are sequentially connected in series between a power supply voltage and a ground, the gates of the main amplification transistors of the first P-type transistor amplification module and the first N-type transistor amplification module are connected to a non-inverting input terminal of the main amplification circuit, and a connection node between the first P-type transistor amplification module and the first N-type transistor amplification module is connected to an inverting output terminal of the main amplification circuit; a second P-type transistor amplification module and a second N-type transistor amplification module are sequentially connected in series between a power supply voltage and a ground, the gates of the main amplification transistors of the second P-type transistor amplification module and the second N-type transistor amplification module are connected to an inverting input terminal of the main amplification circuit, and a connection node between the second P-type transistor amplification module and the second N-type transistor amplification module is connected to a non-inverting output terminal of the main amplification circuit; A main amplifier circuit, characterized in that the gates of the transistors in the P-type transistor amplifier module and the N-type transistor amplifier module are connected to corresponding bias voltages.

2. 2. The main amplifier circuit according to claim 1, wherein the bias voltages of the main amplifier transistors in the P-type transistor amplifier module and the N-type transistor amplifier module are generated by the same bias current.

3. 2. The main amplifier circuit according to claim 1, wherein in each P-type transistor amplifier module and each N-type transistor amplifier module, a gate of a transistor adjacent to an output terminal of the main amplifier circuit is connected to an RC module, each RC module includes a first resistor and a first capacitor, the first resistor is connected between a gate and a drain of a transistor adjacent to the output terminal of the main amplifier circuit, one end of the first capacitor is connected to a gate of a transistor adjacent to the output terminal of the main amplifier circuit, the other end of each first capacitor connected to the P-type transistor amplifier module is connected to a power supply voltage, and the other end of each first capacitor connected to the N-type transistor amplifier module is grounded.

4. 2. The main amplifier circuit according to claim 1, wherein the gates of the intermediate stage transistors of each P-type transistor amplifier module and each N-type transistor amplifier module receive a corresponding bias voltage and are respectively connected to one gate capacitor, the other end of the gate capacitor connected to the P-type transistor amplifier module is connected to a power supply voltage, and the other end of the gate capacitor connected to the N-type transistor amplifier module is grounded.

5. 5. The main amplifier circuit according to claim 1, wherein K is set to 3.

6. 6. The main amplifier circuit according to claim 5, wherein the power supply voltage is 3V to 3.5V.

7. 2. The main amplifier circuit according to claim 1, wherein the gate of each main amplifier transistor is further connected to a corresponding input terminal of the main amplifier circuit via an input capacitor.

8. 1. A radio frequency power amplifier comprising: A preamplifier circuit, a first impedance matching circuit, a second impedance matching circuit, and a main amplifier circuit according to any one of claims 1 to 4, The input terminal of the preamplifier circuit receives a high frequency input signal, and performs a preliminary amplification on the high frequency input signal to compensate for distortion of the main amplifier circuit; the first impedance matching circuit is connected between the output terminal of the preamplifier circuit and the input terminal of the main amplifier circuit, and is used to realize impedance matching between the preamplifier circuit and the main amplifier circuit; the main amplifier circuit amplifies the output signal of the first impedance matching circuit; 2. A high frequency power amplifier, comprising: a first impedance matching circuit connected to an output terminal of the first amplifier circuit and adapted to realize impedance matching between the first amplifier circuit and an output side of the first amplifier circuit;

9. The preamplifier circuit includes a first PMOS differential amplifier module and a first NMOS differential amplifier module; The source of the first PMOS differential amplifier module is connected to a power supply voltage, the differential input terminal is respectively connected to the non-inverting input terminal and the inverting input terminal of the preamplifier circuit, and the differential output terminal is respectively connected to the inverting output terminal and the non-inverting output terminal of the preamplifier circuit; The source of the first NMOS differential amplifier module is grounded, the differential input terminal is respectively connected to the non-inverting input terminal and the inverting input terminal of the preamplifier circuit, and the differential output terminal is respectively connected to the inverting output terminal and the non-inverting output terminal of the preamplifier circuit; 9. The high frequency power amplifier according to claim 8, wherein the gates of the input stage transistors of the first PMOS differential amplification module are connected to the same bias voltage, and the gates of the input stage transistors of the first NMOS differential amplification module are connected to the same bias voltage.

10. 10. The high frequency power amplifier according to claim 9, wherein the gates of the input stage transistors of the first PMOS differential amplifier module and the first NMOS differential amplifier module are further connected to the corresponding input terminals of the preamplifier circuit through an input capacitor, respectively.

11. 9. The high frequency power amplifier according to claim 8, wherein the preamplifier circuit includes a first cascode module and a second cascode module, an input terminal of the first cascode module is connected to a non-inverting input terminal of the preamplifier circuit, an output terminal of the first cascode module is connected to an inverting output terminal of the preamplifier circuit, an input terminal of the second cascode module is connected to an inverting input terminal of the preamplifier circuit, and an output terminal of the second cascode module is connected to the non-inverting output terminal of the preamplifier circuit.

12. the high frequency power amplifier further includes an input buffer circuit, a third impedance matching circuit and a fourth impedance matching circuit; the third impedance matching circuit is connected between the high frequency input signal and the input terminal of the input buffer circuit, and is used to realize impedance matching between the input side and the input buffer circuit; 9. The high frequency power amplifier according to claim 8, wherein the fourth impedance matching circuit is connected between an output terminal of the input buffer circuit and an input terminal of the preamplifier circuit, and is used to realize impedance matching between the input buffer circuit and the preamplifier circuit.

13. the input buffer circuit includes a current source, a second PMOS differential amplifier module and a second NMOS differential amplifier module; One end of the current source is connected to a power supply voltage, and the other end is connected to the source of the second PMOS differential amplifier module; The second PMOS differential amplifier module has differential input terminals respectively connected to the non-inverting input terminal and the inverting input terminal of the input buffer circuit, and a differential output terminal respectively connected to the inverting output terminal and the non-inverting output terminal of the input buffer circuit; The source of the second NMOS differential amplifier module is grounded, the differential input terminal is respectively connected to the non-inverting input terminal and the inverting input terminal of the input buffer circuit, and the differential output terminal is respectively connected to the inverting output terminal and the non-inverting output terminal of the input buffer circuit; 13. The high frequency power amplifier according to claim 12, wherein a resistor is provided between the gate and drain of each transistor in the second PMOS differential amplifier module and the second NMOS differential amplifier module, and input terminals of the second PMOS differential amplifier module and the second NMOS differential amplifier module are connected to corresponding input terminals of the input buffer circuit via an input capacitor.

14. 14. The high frequency power amplifier according to claim 13, further comprising a ground capacitor connected to a connection node between the second PMOS differential amplifier module and the current source.

15. 9. A high frequency power amplifier according to claim 8, wherein each impedance matching circuit is an inductive transformer.

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