Semiconductor device and method of manufacturing the same

Abstract

To provide a semiconductor device capable of improving reliability.SOLUTION: A semiconductor device 10a comprises a first semiconductor chip 15a, a first joining material 16a arranged on the first semiconductor chip 15a and having conductivity, and a metal plate 19a joined to the first semiconductor chip 15a by the first joining material 16a. When viewed from a thickness direction of the metal plate 19a, the metal plate 19a includes a first region 21a joined to the first semiconductor chip 15a and a second region 22a arranged adjacent to the first region 21a in a first direction, which is a direction in which current flows in the metal plate 19a from the first semiconductor chip 15a. In a second direction perpendicular to the first direction, a width of the second region 22a is smaller than a width of the first region 21a.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method of manufacturing the semiconductor device.

Background Art

[0002] A semiconductor device in which semiconductor elements are arranged on a substrate is known (see, for example, Patent Document 1). The semiconductor device disclosed in Patent Document 1 is a power module and includes a first circuit including a first switching element and a second circuit including a second switching element. The first switching element is electrically connected to a diode element by a first connection metal member.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In the semiconductor device disclosed in Patent Document 1, a switching element and a diode element are electrically connected by a plate-shaped metal member. Here, in the manufacturing process of the semiconductor device, if the electrical connection state of semiconductor elements such as a switching element and a diode element is insufficient, it will hinder the efficient flow of current, and as a result, the reliability of the semiconductor device cannot be improved.

[0005] Therefore, one of the objects is to provide a semiconductor device capable of improving reliability.

Means for Solving the Problems

[0006] A semiconductor device according to the present disclosure includes a first semiconductor chip, a first bonding material disposed on the first semiconductor chip and having conductivity, and a metal plate bonded to the first semiconductor chip by the first bonding material. The metal plate includes a first region bonded to the first semiconductor chip and a second region disposed adjacent to the first region in a first direction which is the direction of current flowing through the metal plate from the first semiconductor chip, as viewed in the thickness direction of the metal plate. In a second direction perpendicular to the first direction, the width of the second region is smaller than the width of the first region.

Advantages of the Invention

[0007] According to the above semiconductor device, reliability can be improved.

Brief Description of the Drawings

[0008]

Figure 1

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Figure 10

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Figure 13

Embodiments for Carrying Out the Invention

[0009] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. The semiconductor device according to the present disclosure includes a first semiconductor chip, a first bonding material disposed on the first semiconductor chip and having conductivity, and a metal plate bonded to the first semiconductor chip by the first bonding material. The metal plate includes a first region bonded to the first semiconductor chip when viewed in the thickness direction of the metal plate, and a second region disposed adjacent to the first region in a first direction which is the direction of current flowing through the metal plate from the first semiconductor chip. In a second direction perpendicular to the first direction, the width of the second region is smaller than the width of the first region.

[0010] The semiconductor chip included in the semiconductor device is electrically connected to other members by wires or the like. Here, in the electrical connection between the semiconductor chip and other members, it is more preferable to use a metal plate having a large cross-sectional area because the amount of heat generated when a large current flows can be reduced. Here, when bonding the semiconductor chip and the metal plate, there may be a case where the semiconductor chip and the metal plate are bonded by reflow using a bonding material that melts by heat such as solder. In such a case, even if the semiconductor chip is placed at an appropriate position before the bonding material melts, the semiconductor chip may move due to the melting of the bonding material, and the semiconductor chip may be displaced from the appropriate position and bonded.

[0011] According to the semiconductor device of the present disclosure, a metal plate including a first region and a second region narrower than the first region is included. Therefore, when joining the first region and the first semiconductor chip, the position of the first semiconductor chip can be regulated by using the second region with a smaller width of the metal plate during reflow. Regarding the form of using the second region, for example, a jig having ribs is fitted into the second region with a smaller width of the metal plate, and the ribs are used to suppress the movement of the first semiconductor chip. By doing so, it is possible to suppress the displacement of the position where the first semiconductor chip is joined during reflow. Therefore, it becomes easy to join the first semiconductor chip at an appropriate position. As a result, a highly reliable semiconductor device can be obtained.

[0012] Further, the semiconductor device according to the present disclosure includes a first semiconductor chip, a first bonding material disposed on the first semiconductor chip and having conductivity, and a metal plate joined to the first semiconductor chip by the first bonding material. The metal plate includes, when viewed in the thickness direction of the metal plate, a first region joined to the first semiconductor chip, a second region disposed adjacent to the first region in a first direction which is the direction of the current flowing through the metal plate from the first semiconductor chip, and a third region disposed on the opposite side of the first region in the first direction adjacent to the second region. In a second direction perpendicular to the first direction, the width of the second region is smaller than the width of the first region. In the second direction, the width of the third region is larger than the width of the second region.

[0013] According to such a semiconductor device, it includes a metal plate including a first region and a second region narrower than the first region. Therefore, when joining the first region and the first semiconductor chip, the position of the semiconductor chip can be regulated by using the second region with a smaller width of the metal plate during reflow. By doing so, it is possible to suppress the displacement of the position where the semiconductor chip is joined during reflow. Therefore, it becomes easy to join the semiconductor chip at an appropriate position. Also, a third region having a width larger than the width of the second region can be electrically connected to other members included in the semiconductor device to allow current to flow. Since the width of the third region is larger than the width of the second region, a wide contact area can be ensured and current can be efficiently flowed. As a result, a highly reliable semiconductor device can be obtained.

[0014] In the above semiconductor device, the metal plate may include a depression formed by the first region, the second region, and the third region when viewed in the thickness direction of the metal plate. By doing so, by using this depression and fitting a rib-shaped member into the depression, the movement of the first semiconductor chip during reflow can be regulated. Therefore, the possibility that the position of the first semiconductor chip is displaced and joined can be greatly reduced.

[0015] The above semiconductor device may further include a circuit pattern arranged in the thickness direction of the metal plate and a second bonding material arranged on the circuit pattern and having conductivity. The first semiconductor chip may be joined to the circuit pattern by the second bonding material. By doing so, the second bonding material can appropriately join the circuit pattern and the first semiconductor chip.

[0016] The above semiconductor device may further include a circuit pattern arranged in the thickness direction of the metal plate and a third bonding material arranged on the circuit pattern and having conductivity. The metal plate may be joined to the circuit pattern by the third bonding material. By doing so, the third bonding material can appropriately join the circuit pattern and the metal plate.

[0017] In the semiconductor device described above, the metal plate may be joined to the circuit pattern in the third region. By doing so, the flow of current between the first semiconductor chip and the circuit pattern flowing through the first region, the second region, and the third region can be smoothed.

[0018] The semiconductor device may further include a second semiconductor chip and a fourth bonding material disposed on the second semiconductor chip and having conductivity. The metal plate may further include a fourth region joined to the second semiconductor chip when viewed in the thickness direction of the metal plate. By doing so, the flow of current between the first semiconductor chip and the second semiconductor chip flowing through the first region, the second region, and the fourth region can be smoothed.

[0019] In the semiconductor device described above, at least one of the first bonding material, the second bonding material, the third bonding material, and the fourth bonding material may be solder. By doing so, productivity can be improved and the bonding of each member, such as the bonding between the first semiconductor chip and the metal plate, can be surely performed.

[0020] In the semiconductor device described above, at least one of the first bonding material, the second bonding material, the third bonding material, and the fourth bonding material may be a sintered material. By doing so, strong bonding of each member, such as strong bonding between the first semiconductor chip and the metal plate, can be performed.

[0021] In the semiconductor device described above, when viewed in the thickness direction of the metal plate, the length of the first semiconductor chip in the first direction may be equal to or greater than the length of the first region. By doing so, in the manufacturing process of the semiconductor device, the end face of the first semiconductor chip can be more surely brought into contact with the member disposed on the side portion of the second region, and the possibility that the position of the first semiconductor chip is displaced and joined can be greatly reduced.

[0022] In the semiconductor device described above, the first semiconductor chip may be a transistor chip. The first region may be provided at a position avoiding the gate electrode pad of the first semiconductor chip when viewed in the thickness direction of the metal plate. By doing so, the gate electrode pad is not covered by the first region, and electrical connection between the gate electrode pad and the gate terminal or the like can be easily performed.

[0023] In the semiconductor device described above, the first semiconductor chip may include a semiconductor layer made of SiC or GaN. By including a semiconductor layer made of SiC or GaN in the first semiconductor chip, the first semiconductor chip can be used as a wide bandgap semiconductor chip. A wide bandgap semiconductor chip refers to a semiconductor chip having a larger bandgap than a semiconductor chip made of Si.

[0024] In the method for manufacturing a semiconductor device according to the present disclosure, the semiconductor device includes a first semiconductor chip, a first bonding material disposed on the first semiconductor chip and having conductivity, and a metal plate bonded to the first semiconductor chip by the first bonding material. The metal plate includes a first region bonded to the first semiconductor chip and a second region disposed adjacent to the first region in a first direction which is the direction of current flowing from the first semiconductor chip into the metal plate when viewed in the thickness direction of the metal plate. In a second direction perpendicular to the first direction, the width of the second region is smaller than the width of the first region. The method for manufacturing a semiconductor device includes a step of preparing an alignment jig including a frame body having an inner wall surface constituting a through hole and ribs provided on the inner wall surface, and a step of using the alignment jig to stack the first semiconductor chip and the first region so as to sandwich the first bonding material in the through hole, and arranging the first semiconductor chip, the first bonding material, and the metal plate by fitting a portion having a small width of the second region into the ribs.

[0025] According to such a method for manufacturing a semiconductor device, displacement of the position of the first semiconductor chip can be suppressed by the ribs when the first semiconductor chip and the metal plate are bonded by the first bonding material. Therefore, a highly reliable semiconductor chip can be obtained more surely.

[0026] In the method for manufacturing the semiconductor device described above, after the step of arranging the first semiconductor chip, the first bonding material, and the metal plate, a step of heating to a temperature equal to or higher than the melting temperature of the first bonding material may be further included. By doing so, bonding by the first bonding material can be performed more reliably.

[0027] Further, in the method for manufacturing a semiconductor device according to the present disclosure, the semiconductor device includes a first semiconductor chip, a first bonding material disposed on the first semiconductor chip and having conductivity, a metal plate bonded to the first semiconductor chip by the first bonding material, a circuit pattern disposed in the thickness direction of the metal plate, and a second bonding material disposed on the circuit pattern and having conductivity. The metal plate includes a first region bonded to the first semiconductor chip when viewed in the thickness direction of the metal plate, and a second region disposed adjacent to the first region in a first direction which is the direction of the current flowing from the first semiconductor chip into the metal plate. In a second direction perpendicular to the first direction, the width of the second region is smaller than the width of the first region. The first semiconductor chip is bonded to the circuit pattern by the second bonding material. The method for manufacturing a semiconductor device includes a step of previously bonding the first region and the first semiconductor chip with the first bonding material, a step of preparing an alignment jig including a frame body having an inner wall surface constituting a through hole and ribs provided on the inner wall surface, a step of disposing the alignment jig on the circuit pattern, laminating the circuit pattern and the first semiconductor chip so as to sandwich the second bonding material in the through hole, and a step of disposing the first semiconductor chip, the first bonding material, the second bonding material, and the metal plate by fitting a portion having a small width of the second region into the ribs.

[0028] According to such a method for manufacturing a semiconductor device, when bonding the first semiconductor chip and the circuit pattern with the second bonding material, displacement of the position of the first semiconductor chip can be suppressed by the ribs. Therefore, a highly reliable semiconductor chip can be obtained more surely.

[0029] In the method for manufacturing the semiconductor device, after the step of arranging the first semiconductor chip, the first bonding material, the second bonding material, and the metal plate, a step of heating to a temperature equal to or higher than the melting temperature of the second bonding material may be further included. By doing so, bonding can be performed more reliably with the second bonding material.

[0030] [Details of Embodiments of the Present Disclosure] Next, embodiments of the semiconductor device of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals and their descriptions will not be repeated.

[0031] (Embodiment 1) The configuration of the semiconductor device in Embodiment 1 of the present disclosure will be described. FIG. 1 is a schematic perspective view of the semiconductor device in Embodiment 1. FIG. 2 is a schematic side view of the semiconductor device shown in FIG. 1. FIG. 3 is a schematic plan view showing a part of the semiconductor device shown in FIG. 1 enlarged. FIG. 4 is an enlarged view of the part shown in region IV in FIG. 3. FIG. 5 is a schematic plan view showing the configuration of a circuit pattern, which will be described later, in the semiconductor device shown in FIG. 1.

[0032] Referring to FIGS. 1, 2, 3, 4, and 5, the semiconductor device 10a in Embodiment 1 includes a plate-shaped base plate 11a as a base portion, a substrate 12a, a circuit pattern 14, a first semiconductor chip 15a, a first bonding material 16a, a second bonding material 16b, a third bonding material 16c, and a metal plate 19a. For ease of understanding, the thicknesses of the circuit pattern 14, the first bonding material 16a, etc. are exaggerated and shown thick. Further, the semiconductor device 10a further includes a frame surrounding the substrate 12a, a resin sealing material for sealing the space on the substrate 12a, terminals (bus bars) for ensuring electrical connection with the outside of the semiconductor device 10a, etc., but illustration and description of these are omitted.

[0033] In this embodiment, the base plate 11a is rectangular in shape such that, when viewed in the thickness direction (Z direction), the length in the X direction is longer than the length in the Y direction. The base plate 11a has insulating properties. The base plate 11a is made of, for example, ceramic. The base plate 11a includes a first surface 11b located on one side in the thickness direction and a second surface 11c located on the other side in the thickness direction.

[0034] On the first surface 11b of the base plate 11a, a substrate 12a is disposed. In this embodiment, the substrate 12a is rectangular in shape such that, when viewed in the thickness direction (Z direction), the length in the X direction is longer than the length in the Y direction. The substrate 12a includes a first surface 12b located on one side in the thickness direction and a second surface 12c located on the other side in the thickness direction. The second surface 12c of the substrate 12a is joined to the first surface 11b of the base plate 11a.

[0035] On the first surface 12b of the substrate 12a, a circuit pattern 14 is disposed. The circuit pattern 14 is a conductive member, specifically composed of, for example, a copper plate. The circuit pattern 14 includes a first circuit board 13a, a second circuit board 13b, a third circuit board 13c, and a fourth circuit board 13d. The first circuit board 13a, the second circuit board 13b, the third circuit board 13c, and the fourth circuit board 13d are arranged at intervals from each other. Note that the arrangement of the first circuit board 13a and the like included in the circuit pattern 14 is schematically shown. Also, the illustration of members electrically connected to the first circuit board 13a included in the circuit pattern 14 and wires connected to the third circuit board 13c are omitted. Further, the illustration of other circuit boards included in the circuit pattern 14 is also omitted from the viewpoint of facilitating understanding.

[0036] The first semiconductor chip 15a is a wide-bandgap semiconductor chip. Specifically, the first semiconductor chip 15a includes a semiconductor layer made of SiC (silicon carbide). The first semiconductor chip 15a is plate-shaped. The first semiconductor chip 15a is rectangular when viewed in the thickness direction. In this embodiment, the first semiconductor chip 15a is a diode chip. The first semiconductor chip 15a includes a cathode electrode pad 17a disposed on one side in the thickness direction (Z direction) and an anode electrode pad 18a disposed on the other side in the thickness direction. That is, the first semiconductor chip 15a is a diode chip through which current flows in the longitudinal direction (Z direction) which is the thickness direction. Alternatively, the first semiconductor chip 15a may be an SBD (Schottky barrier diode) made of SiC.

[0037] The first semiconductor chip 15a is mounted on the second circuit board 13b. The first semiconductor chip 15a is arranged such that the cathode electrode pad 17a faces the second circuit board 13b. The second circuit board 13b and the first semiconductor chip 15a are joined by a conductive second bonding material 16b made of solder or the like. That is, the second bonding material 16b is interposed between the first semiconductor chip 15a and the second circuit board 13b. The first semiconductor chip 15a is arranged such that the end face 27a is located on the side of the first circuit board 13a. The cathode electrode pad 17a of the first semiconductor chip 15a is electrically connected to the second circuit board 13b of the circuit pattern 14.

[0038] In this embodiment, the metal plate 19a is used to electrically connect the circuit pattern 14 and the first semiconductor chip 15a. Specifically, the metal plate 19a is a copper clip. That is, the metal plate 19a is made of copper.

[0039] The metal plate 19a includes a first region 21a, a second region 22a, and a third region 23a when viewed in the thickness direction (Z direction) of the metal plate 19a. In FIGS. 3 and 4, the boundaries between the first region 21a and the second region 22a and between the second region 22a and the third region 23a are each indicated by a dashed line. The first region 21a and the second region 22a are arranged adjacent to each other. The second region 22a and the third region 23a are arranged adjacent to each other. Each of the first region 21a, the second region 22a, and the third region 23a is rectangular when viewed in the thickness direction. Note that a thick portion 24a is formed in a part of the third region 23a. The thickness of the thick portion 24a corresponds to the sum of the thickness of the first bonding material 16a and the thickness of the first semiconductor chip 15a. The thickness of the portion of the third region 23a where the thick portion 24a is formed is thicker than the thickness of the first region 21a by the thickness of the first bonding material 16a and the thickness of the first semiconductor chip 15a. When viewed in the thickness direction of the metal plate 19a, the length of the first semiconductor chip 15a in the first direction is equal to or greater than the length of the first region 21a. In the present embodiment, particularly referring to FIG. 4, on the second region 22a side, the length of the first semiconductor chip 15a in the first direction is longer than the first region 21a by a length D 1 only.

[0040] The metal plate 19a is joined to the first semiconductor chip 15a by a conductive first bonding material 16a made of solder or the like. Specifically, the first region 21a of the metal plate 19a and the anode electrode pad 18a of the first semiconductor chip 15a are joined by the first bonding material 16a. That is, the first bonding material 16a is interposed between the first region 21a of the metal plate 19a and the first semiconductor chip 15a. The metal plate 19a and the anode electrode pad 18a of the first semiconductor chip 15a are electrically connected.

[0041] The metal plate 19a is joined to the circuit pattern 14 by a conductive third joining material 16c composed of solder or the like. Specifically, the third region 23a of the metal plate 19a and the first circuit board 13a of the circuit pattern 14 are joined by the third joining material 16c. That is, the third joining material 16c is interposed between the third region 23a of the metal plate 19a and the first circuit board 13a. The metal plate 19a and the first circuit board 13a of the circuit pattern 14 are electrically connected.

[0042] During the operation of the semiconductor device 10a, a current flows from the first semiconductor chip 15a, which is a diode chip, into the metal plate 19a. The direction in which the current flows in the metal plate 19a is the X direction, which is the first direction. The second region 22a is arranged adjacent to the first region 21a in the first direction. Also, the third region 23a is arranged adjacent to the second region 22a in the first direction.

[0043] Here, in the second direction (Y direction) perpendicular to the first direction of the metal plate 19a, the width W of the second region 22a 2 is smaller than the width W of the first region 21a 1 Also, in the second direction, the width W of the third region 23a 3 is larger than the width W of the second region 22a 2 In the present embodiment, the width W of the first region 21a 1 and the width W of the third region 23a 3That is, they are the same. With such a configuration of the first region 21a, the second region 22a, and the third region 23a, recesses 25a and 26a are formed. The metal plate 19a includes the recesses 25a and 26a formed by the first region 21a, the second region 22a, and the third region 23a when viewed in the thickness direction (Z direction) of the metal plate 19a. The recesses 25a and 26a have a shape in which both end faces of the metal plate 19a in the second direction are notched in the region where the second region 22a is disposed. The recess 25a is composed of a first side wall surface 31a provided in the first region 21a, a second side wall surface 32a provided in the second region 22a, and a third side wall surface 33a provided in the third region 23a. The recess 26a is composed of a first side wall surface 34a provided in the first region 21a, a second side wall surface 35a provided in the second region 22a, and a third side wall surface 36a provided in the third region 23a. When viewed in the thickness direction of the metal plate 19a, the first side wall surfaces 31a and 34a and the third side wall surfaces 33a and 36a each extend along the second direction. When viewed in the thickness direction of the metal plate 19a, the second side wall surfaces 32a and 35a each extend along the first direction.

[0044] Next, a method for manufacturing the semiconductor device 10a having the above-described configuration will be described. FIG. 6 is a flowchart showing typical steps of a method for manufacturing a semiconductor device according to Embodiment 1 shown in FIG. 1. Referring to FIG. 6, in the method for manufacturing the semiconductor device 10a according to Embodiment 1, first, as step (S10), a base plate, a substrate, and an alignment jig preparation step are performed. In this step (S10), first, a substrate 12a having a circuit pattern 14 formed thereon as shown in FIG. 5 described above is bonded onto the base plate 11a. Also, an alignment jig in which through holes and ribs described later are formed is prepared. The configuration of the alignment jig will be described in detail later. Further, an outer jig used for attaching the alignment jig is also prepared. Although illustration of the outer jig is omitted, the outer jig has a fitting hole for fitting the alignment jig and is attached so as to cover the entire base plate 11a and used.

[0045] Next, as step (S20), a first semiconductor chip and a first bonding material placement step are performed. In this step (S20), a second bonding material and a third bonding material placement step are also performed together. FIG. 7 is a schematic perspective view showing a state in which a first semiconductor chip and a first bonding material are placed, and a metal plate is further placed. FIG. 8 is a schematic perspective view showing an enlarged part of the semiconductor device shown in FIG. 7. In FIG. 8, the illustration of the alignment jig described later is omitted, and the outer shape of the alignment jig is shown by a two-dot chain line. In the present embodiment, plate solder is used as the first bonding material 16a, the second bonding material 16b, and the third bonding material 16c. Also, from the viewpoint of facilitating understanding, in the first direction, the end face of the first bonding material 16a, the second bonding material 16b, and the end face 27a of the first semiconductor chip 15a are aligned and shown.

[0046] Referring to FIGS. 7 and 8 together, in this step (S20), first, an alignment jig 41a is placed. In this case, the outer jig is attached so as to cover the entire base plate 11a, and the alignment jig is placed by fitting it into the fitting hole. Here, the configuration of the alignment jig 41a will be described. The alignment jig 41a is made of carbon and includes a frame body 42a having an inner wall surface 45a that constitutes a through hole, and a pair of ribs 43a, 44a provided on the inner wall surface 45a. The inner wall surface 45a of the frame body 42a is formed along the outer shape of the metal plate 19a. The pair of ribs 43a, 44a are opposed to each other and are provided so as to protrude inward. The positions where the ribs 43a, 44a are provided are positions corresponding to the depressions 25a, 26a formed in the metal plate 19a when the metal plate 19a is accommodated in the frame body 42a.

[0047] Then, the alignment jig 41a is disposed on the first circuit board 13a and the second circuit board 13b of the circuit pattern 14. The alignment jig 41a is disposed such that the penetrating direction of the through hole is the thickness direction of the substrate 12a. At this time, the alignment jig 41a is disposed across the first circuit board 13a and the second circuit board 13b. Also, when viewed in the thickness direction of the substrate 12a, the ribs 43a, 44a are disposed so as to be positioned between the first circuit board 13a and the second circuit board 13b.

[0048] Thereafter, within the space surrounded by the frame body 42a of the alignment jig 41a, the second bonding material 16b is disposed on the second circuit board 13b. FIG. 9 is a schematic plan view showing an enlarged state in which the second bonding material 16b is disposed. Then, the first semiconductor chip 15a is disposed on the second bonding material 16b. Here, when the first semiconductor chip 15a is disposed, the cathode electrode pad 17a of the first semiconductor chip 15a is disposed so as to be in contact with the second bonding material 16b. Here, the alignment jig 41a is provided with ribs 43a, 44a. Therefore, even if the first semiconductor chip 15a attempts to move in the X direction, when viewed in the thickness direction of the substrate 12a, the end face 27a of the rectangular first semiconductor chip 15a contacts the side wall surfaces constituting the ribs 43a, 44a, and the movement of the first semiconductor chip 15a in the X direction is restricted.

[0049] Thereafter, the first bonding material 16a is disposed on the first semiconductor chip 15a. In this case, the first bonding material 16a is disposed on the anode electrode pad 18a of the first semiconductor chip 15a.

[0050] Also, within the space surrounded by the frame body 42a of the alignment jig 41a, the third bonding material 16c is disposed on the fourth circuit board 13d. FIG. 10 is a schematic plan view showing an enlarged state in which the third bonding material 16c is disposed.

[0051] Next, as step (S30), a metal plate placement step is performed. In this step (S30), the metal plate 19a is placed within the space surrounded by the frame 42a of the alignment jig 41a. At this time, the metal plate 19a is placed in such a manner that the depressions 25a and 26a are fitted into the ribs 43a and 44a. The state in which the metal plate 19a is placed is the state shown in FIGS. 7 and 8. That is, the method for manufacturing the semiconductor device 10a uses an alignment jig 41a including a frame 42a having an inner wall surface 45a constituting a through hole and ribs 43a and 44a provided on the inner wall surface 45a, and stacks the first semiconductor chip 15a and the first region 21a so as to sandwich the first bonding material 16a within the through hole, and places the first semiconductor chip 15a, the first bonding material 16a, and the metal plate 19a in such a manner that a portion of the second region 22a having a small width is fitted into the ribs 43a and 44a.

[0052] Next, as step (S40), a heating step is performed. In this step (S40), the whole is heated with the alignment jig 41a placed. The conditions of the heating step depend on the characteristics of the solder or sintered material which are the members to be joined. For example, when using an Sn (tin)-Ag (silver)-Cu (copper) based solder, heating is performed at a temperature of 100°C or higher and 300°C or lower for 1 minute or longer and 60 minutes or shorter. By heating, the first bonding material 16a, the second bonding material 16b, and the third bonding material 16c each composed of solder are once melted and then the respective members are joined. Here, since the alignment jig 41a is provided with the ribs 43a and 44a, even when the first bonding material 16a and the second bonding material 16b are melted in the heating step, the first semiconductor chip 15a is caught by the ribs 43a and 44a, and movement of the first semiconductor chip 15a in the X direction can be suppressed.

[0053] Next, as step (S50), an alignment jig removal step is performed. In this step (S50), after the respective members are joined by the first bonding material 16a, the second bonding material 16b, and the third bonding material 16c, the alignment jig 41a is removed from above the substrate 12a. The removed state becomes the state shown in FIG. 1.

[0054] Thereafter, for the semiconductor device 10a in the state shown in FIG. 1 obtained, attachment of terminals (bus bars), attachment of a case, sealing with a sealing material, etc. are carried out to obtain the final semiconductor device 10a.

[0055] According to the semiconductor device 10a of the present disclosure, it includes a metal plate 19a including a first region 21a and a second region 22a having a width smaller than that of the first region 21a. Therefore, when joining the first region 21a and the first semiconductor chip 15a, the position of the first semiconductor chip 15a can be regulated by using the second region 22a with a small width of the metal plate 19a during reflow. By doing so, it is possible to suppress the position of the first semiconductor chip 15a from shifting during reflow. Thus, it becomes easy to join the first semiconductor chip 15a at an appropriate position. Also, a third region 23a having a width larger than the width of the second region 22a can be electrically connected to other members included in the semiconductor device 10a to allow current to flow. Since the width of the third region 23a is larger than the width of the second region 22a, a wide contact area can be ensured and current can flow efficiently. As a result, a highly reliable semiconductor device 10a can be obtained.

[0056] In the present embodiment, the metal plate 19a includes a third region 23a that is adjacent to the second region 22a and is arranged on the opposite side of the first region 21a in the first direction. In the second direction, the width of the third region 23a is larger than the width of the second region 22a. Therefore, a third region 23a having a width larger than the width of the second region 22a can be electrically connected to the circuit pattern 14 included in the semiconductor device 10a to allow current to flow. Since the width of the third region 23a is larger than the width of the second region 22a, a wide contact area can be ensured and current can flow efficiently. Thus, a more reliable semiconductor device 10a can be obtained.

[0057] In this embodiment, the metal plate 19a includes depressions 25a and 26a formed by a first region 21a, a second region 22a, and a third region 23a when viewed in the thickness direction of the metal plate 19a. Therefore, by utilizing this depression, ribs 43a and 44a can be fitted into the depressions 25a and 26a to restrict the movement of the first semiconductor chip 15a during reflow. Accordingly, the possibility that the first semiconductor chip 15a is misaligned and joined can be greatly reduced.

[0058] In this embodiment, the first semiconductor chip 15a is joined to the circuit pattern 14 by the second bonding material 16b. Therefore, the circuit pattern 14 and the first semiconductor chip 15a can be properly joined by the second bonding material 16b.

[0059] In this embodiment, the metal plate 19a is joined to the circuit pattern 14 by the third bonding material 16c. Therefore, the circuit pattern 14 and the metal plate 19a can be properly joined by the third bonding material 16c.

[0060] In this embodiment, the metal plate 19a is joined to the circuit pattern 14 in the third region 23a. Therefore, the flow of current between the first semiconductor chip 15a and the circuit pattern 14 flowing through the first region 21a, the second region 22a, and the third region 23a can be smoothed.

[0061] In this embodiment, the length of the first semiconductor chip 15a in the first direction is equal to or greater than the length of the first region 21a. Therefore, in the manufacturing process of the semiconductor device 10a, the end face 27a of the first semiconductor chip 15a can be more reliably brought into contact with the member disposed on the side portion of the second region 22a, and the possibility that the first semiconductor chip 15a is misaligned and joined can be greatly reduced.

[0062] In this embodiment, the first bonding material 16a is solder. Therefore, productivity can be improved, and the first semiconductor chip 15a and the metal plate 19a can be reliably bonded. Also, in this case, the second bonding material 16b and the third bonding material 16c are also solder. Therefore, the metal plate 19a, the first semiconductor chip 15a, and the circuit pattern 14 can be bonded in a single process, and productivity can be improved.

[0063] Also, in the method of manufacturing the semiconductor device described above, after the step of arranging the first semiconductor chip, the first bonding material, and the metal plate, a step of heating to a temperature equal to or higher than the melting temperature of the first bonding material is included. Therefore, bonding with the first bonding material can be performed more reliably.

[0064] (Embodiment 2) Next, Embodiment 2, which is another embodiment, will be described. FIG. 11 is a schematic plan view showing a part of the semiconductor device in Embodiment 2. The semiconductor device of Embodiment 2 is different from that of Embodiment 1 in that the first semiconductor chip is a transistor chip.

[0065] Referring to FIG. 11, the first semiconductor chip 15b included in the semiconductor device 10b of Embodiment 2 is a transistor chip. Specifically, for example, the first semiconductor chip 15b is a metal-oxide-semiconductor field-effect transistor (MOSFET). The first semiconductor chip 15b is plate-shaped. The first semiconductor chip 15b includes a drain electrode pad disposed on one side in the thickness direction (Z direction) and a source electrode pad 52b and a gate electrode pad 53b disposed on the other side in the thickness direction. That is, the first semiconductor chip 15b is a transistor chip through which current flows in the longitudinal direction (Z direction), which is the thickness direction. In the present embodiment, the source electrode pad 52b and the gate electrode pad 53b are arranged at intervals in the first direction (X direction).

[0066] The metal plate 19b in which the depressions 25b and 26b are formed includes a first region 21b, a second region 22b, and a third region 23b. The first region 21b is provided at a position avoiding the gate electrode pad 53b of the first semiconductor chip 15b when viewed in the thickness direction of the metal plate 19b. Specifically, in the metal plate 19b, the length of the first region 21b in the first direction is shorter than the length of the first region 21a in the first embodiment. The metal plate 19b and the source electrode pad 52b of the first semiconductor chip 15b are joined by a first bonding material. That is, in the first semiconductor chip 15b, the gate electrode pad 53b is not covered by the metal plate 19b and is not in contact therewith. The gate electrode pad 53b is electrically connected to a gate terminal or the like by a wire or the like (not shown).

[0067] Even by configuring in this way, when joining the first semiconductor chip 15b, the possibility that the position of the first semiconductor chip 15b shifts can be reduced. And it becomes a configuration in which the gate electrode pad 53b is not covered by the first region 21b, and the electrical connection between the gate electrode pad 53b and the gate terminal or the like can be easily performed.

[0068] (Embodiment 3) Next, Embodiment 3, which is still another embodiment, will be described. FIG. 12 is a schematic plan view showing a part of the semiconductor device in Embodiment 3. The semiconductor device of Embodiment 3 is different from that of Embodiment 2 in that the position of the gate electrode pad in the first semiconductor chip is different.

[0069] Referring to FIG. 12, the first semiconductor chip 15c included in the semiconductor device 10c of Embodiment 3 is a transistor chip. Specifically, for example, the first semiconductor chip 15c is a metal-oxide-semiconductor field-effect transistor (MOSFET). The first semiconductor chip 15c is plate-shaped. The first semiconductor chip 15c includes a drain electrode pad disposed on one side in the thickness direction (Z direction), and a source electrode pad 52c and a gate electrode pad 53c disposed on the other side in the thickness direction. That is, the first semiconductor chip 15c is a transistor chip in which current flows in the longitudinal direction (Z direction) which is the thickness direction. In the present embodiment, the source electrode pad 52c and the gate electrode pad 53c are arranged at intervals in the second direction (Y direction).

[0070] The metal plate 19c in which the depressions 25c and 26c are formed includes a first region 21c, a second region 22c, and a third region 23c. The first region 21c is provided at a position avoiding the gate electrode pad 53c of the first semiconductor chip 15c when viewed in the thickness direction of the metal plate 19c. Specifically, in the metal plate 19c, the length of the first region 21c in the second direction is shorter than the length of the first region 21c in Embodiment 1. And the metal plate 19c and the source electrode pad 52c of the first semiconductor chip 15c are joined by a first bonding material. That is, in the first semiconductor chip 15c, the gate electrode pad 53c is not covered by the metal plate 19c and is not in contact. The gate electrode pad 53c is electrically connected to a gate terminal or the like by a wire or the like (not shown).

[0071] Even with such a configuration, it is possible to reduce the risk of displacement of the position of the first semiconductor chip 15c during bonding of the first semiconductor chip 15c. And the gate electrode pad 53c is not covered by the first region 21c, and the electrical connection between the gate electrode pad 53c and the gate terminal or the like can be easily performed.

[0072] (Embodiment 4) Next, Embodiment 4, which is still another embodiment, will be described. FIG. 13 is a schematic plan view showing a part of the semiconductor device according to Embodiment 4. The semiconductor device of Embodiment 4 is different from that of Embodiment 1 in that it includes a first semiconductor chip as a diode chip and a second semiconductor chip as a transistor chip.

[0073] Referring to FIG. 13, the semiconductor device 10d according to Embodiment 4 includes a first semiconductor chip 15d as a diode chip and a second semiconductor chip 41d as a transistor chip. Specifically, the first semiconductor chip 15d is a Schottky barrier diode. Specifically, the second semiconductor chip 41d is a metal-oxide-semiconductor field-effect transistor (MOSFET). The first semiconductor chip 15d and the second semiconductor chip 41d are mounted on the same circuit board 42d of the circuit pattern.

[0074] The semiconductor device 10d includes a metal plate 19d. In the present embodiment, current flows in the Y direction within the metal plate 19d. That is, the first direction is the Y direction. The metal plate 19d includes a first region 21d, a second region 22d, a third region 23d, a fourth region 44d, and a fifth region 45d. The first region 21d, the second region 22d, the third region 23d, the fourth region 44d, and the fifth region 45d are arranged side by side in the first direction. The second semiconductor chip 41d is joined to the fourth region 44d by a fourth bonding material 16d shown by a broken line.

[0075] In a second direction (X direction) perpendicular to the first direction (Y direction), the width of the second region 22d is smaller than the width of the first region 21d. Further, the width of the second region 22d is smaller than the width of the third region 23d. The first region 21d, the second region 22d, and the third region 23d form depressions 25d and 26d. Also, a fifth region 45d is arranged adjacent to the third region 23d in the first direction, and a fourth region 44d is arranged adjacent to the fifth region 45d in the first direction. In a second direction (X direction) perpendicular to the first direction (Y direction), the width of the fifth region 45d is smaller than the width of the third region 23d. Further, the width of the fifth region 45d is smaller than the width of the fourth region 44d. The third region 23d, the fourth region 44d, and the fifth region 45d form depressions 46d and 47d. The first semiconductor chip 15d is joined to the metal plate 19d by a first bonding material using the depressions 25d and 26d. The second semiconductor chip 41d is joined to the metal plate 19d by a fourth bonding material 16d using the depressions 25d, 26d, 46d, and 47d. The fourth region 44d is joined to a circuit board 43d arranged at a distance from the circuit board 42d in the first direction.

[0076] Note that the source electrode pad of the second semiconductor chip 41d included in the semiconductor device 10d is connected to a circuit board 48d of a circuit pattern by a wire (not shown). Also, the Kelvin source terminal of the second semiconductor chip 41d included in the semiconductor device 10d is connected to a circuit board 49d of a circuit pattern by a wire (not shown).

[0077] Even with this configuration, it is possible to reduce the risk of misalignment of the positions of the first semiconductor chip 15d and the second semiconductor chip 41d during bonding of the first semiconductor chip 15d and the second semiconductor chip 41d. Also, by doing so, it is possible to smooth the flow of current between the first semiconductor chip 15d and the second semiconductor chip 41d flowing through the first region 21d, the second region 22d, and the fourth region 44d.

[0078] (Other embodiments) In the above-described embodiment, the first semiconductor chip is configured to include a semiconductor layer made of SiC. However, the present invention is not limited to this, and the first semiconductor chip may include a semiconductor layer made of GaN. That is, the first semiconductor chip may include a semiconductor layer made of SiC or GaN. Such a first semiconductor chip can be used as a wide bandgap semiconductor chip.

[0079] Also, in the above-described embodiment, the recess formed in the metal plate is provided on both sides in the second direction. However, the present invention is not limited to this, and a configuration in which the recess is provided only on one side may be adopted. Further, a configuration in which a plurality of recesses are provided at intervals in the first direction may be adopted. The shape of the recess is not limited to the shape of the above-described embodiment. For example, when viewed in the thickness direction of the metal plate, it may be arc-shaped or may include a curve. Also, when viewed in the thickness direction of the metal plate, it may have a shape in which a V-shaped notch is formed.

[0080] In the above-described embodiment, the metal plate is made of copper. However, the present invention is not limited to this, and other members, for example, copper plated with gold or Ni (nickel), may be used. Also, the thickness of the metal plate may be made uniform, and if necessary, it may be bent or processed such as bending to increase the thickness before use.

[0081] Regarding the method for manufacturing the semiconductor device, a step of previously joining the first region and the first semiconductor chip with a first bonding material, a step of preparing an alignment jig including a frame body having an inner wall surface constituting a through hole and ribs provided on the inner wall surface, a step of disposing the alignment jig on the circuit pattern, laminating the circuit pattern and the first semiconductor chip so that the second bonding material is sandwiched in the through hole, and a step of disposing the first semiconductor chip, the first bonding material, the second bonding material, and the metal plate by fitting a portion having a small width of the second region into the ribs may be included.

[0082] According to such a method for manufacturing a semiconductor device, when the first semiconductor chip and the circuit pattern are joined by the second bonding material, the rib can suppress the displacement of the position of the first semiconductor chip. Therefore, a highly reliable semiconductor chip can be obtained more surely.

[0083] Further, in the method for manufacturing a semiconductor device, after the step of arranging the first semiconductor chip, the first bonding material, the second bonding material, and the metal plate, a step of heating to a temperature equal to or higher than the melting temperature of the second bonding material may be further included. By doing so, the joining by the second bonding material can be performed more surely.

[0084] In the semiconductor device, at least one of the first bonding material, the second bonding material, the third bonding material, and the fourth bonding material may be solder. By doing so, productivity can be improved, and the joining of each member, such as the joining of the first semiconductor chip and the metal plate, can be surely performed.

[0085] In the semiconductor device, at least one of the first bonding material, the second bonding material, the third bonding material, and the fourth bonding material may be a sintered material. By doing so, a strong joining of each member, such as a strong joining of the first semiconductor chip and the metal plate, can be performed.

[0086] It should be understood that the embodiments disclosed this time are illustrative in all respects and not restrictive in any way. The scope of the present disclosure is defined not by the above description but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims be included.

Industrial Applicability

[0087] The semiconductor device and the method for manufacturing a semiconductor device of the present disclosure can be particularly advantageously applied when an improvement in reliability is required.

Explanation of Signs

[0088] Semiconductor devices 10a, 10b, 10c, 10d Base plate 11a First surface 11b, 12b Second surface 11c, 12c Substrate 12a First circuit board 13a Second circuit board 13b Third circuit board 13c Fourth circuit board 13d Circuit pattern 14 First semiconductor chips 15a, 15b, 15c, 15d First bonding material 16a Second bonding material 16b Third bonding material 16c Fourth bonding material 16d Cathode electrode pad 17a Anode electrode pad 18a Metal plates 19a, 19b, 19c, 19d First regions 21a, 21b, 21c, 21d Second regions 22a, 22b, 22c, 22d Third regions 23a, 23b, 23c, 23d Thick portion 24a Depressions 25a, 25b, 25c, 25d, 26a, 26b, 26c, 26d, 46d, 47d End face 27a First side wall surfaces 31a, 34a Second side wall surfaces 32a, 35a Third side wall surfaces 33a, 36a Alignment jig 41a Second semiconductor chip 41d Frame 42a Circuit boards 42d, 43d, 48d, 49d Ribs 43a, 44a Fourth region 44d Inner wall surface 45a Fifth region 45d Source electrode pads 52b, 52c Gate electrode pads 53b, 53c IV region D 1 Length W 1 ,W 2 ,W 3 frame

Claims

1. A first semiconductor chip, a first bonding material disposed on the first semiconductor chip and having conductivity, a metal plate bonded to the first semiconductor chip by the first bonding material, and comprising: the metal plate, a first region bonded to the first semiconductor chip as viewed in the thickness direction of the metal plate, a second region disposed adjacent to the first region in a first direction which is the direction of current flowing from the first semiconductor chip into the metal plate, a third region disposed on the opposite side of the first region in the first direction adjacent to the second region, and including: in a second direction perpendicular to the first direction, the width of the second region is smaller than the width of the first region, in the second direction, the width of the third region is larger than the width of the second region, a thick portion is provided in the third region, in the thickness direction of the metal plate, the thickness of the region where the thick portion is provided in the third region is thicker than the thickness of the first region, a second semiconductor chip, a fourth bonding material disposed on the second semiconductor chip and having conductivity, and further comprising: the metal plate further includes a fourth region bonded to the second semiconductor chip as viewed in the thickness direction of the metal plate, a semiconductor device.

2. The semiconductor device according to claim 1, wherein the thickness of the thick portion corresponds to the sum of the thickness of the first bonding material and the thickness of the first semiconductor chip.

3. The semiconductor device according to claim 1 or claim 2, wherein the metal plate includes a depression formed by the first region, the second region, and the third region as viewed in the thickness direction of the metal plate.

4. Further comprising a circuit pattern disposed in the thickness direction of the metal plate, the semiconductor device according to any one of claims 1 to 3, wherein the metal plate is bonded to the circuit pattern in the third region.

5. a circuit pattern disposed in the thickness direction of the metal plate, a second bonding material disposed on the circuit pattern and having conductivity, and further comprising: the semiconductor device according to any one of claims 1 to 4, wherein the first semiconductor chip is bonded to the circuit pattern by the second bonding material.

6. a circuit pattern disposed in the thickness direction of the metal plate, a third bonding material disposed on the circuit pattern and having conductivity, and further comprising: The semiconductor device according to any one of claims 1 to 5, wherein the metal plate is joined to the circuit pattern by the third joining material.

7. The semiconductor device according to any one of claims 1 to 6, wherein, when viewed in the thickness direction of the metal plate, the length of the first semiconductor chip in the first direction is equal to or greater than the length of the first region.

8. The first semiconductor chip is a transistor chip, The semiconductor device according to any one of claims 1 to 7, wherein the first region is provided at a position avoiding the gate electrode pad of the first semiconductor chip when viewed in the thickness direction of the metal plate.

9. The semiconductor device according to any one of claims 1 to 8, wherein the first semiconductor chip includes a semiconductor layer made of SiC or GaN.

10. The semiconductor device according to any one of claims 1 to 9, wherein at least one of the first joining material and the fourth joining material is solder or a sintered material.

11. The semiconductor device according to claim 5, wherein the second joining material is solder or a sintered material.

12. The semiconductor device according to claim 6, wherein the third joining material is solder or a sintered material.

13. A method of manufacturing a semiconductor device, The semiconductor device includes a first semiconductor chip, a first joining material having conductivity and disposed on the first semiconductor chip, a metal plate joined to the first semiconductor chip by the first joining material, and The metal plate includes a first region joined to the first semiconductor chip when viewed in the thickness direction of the metal plate, a second region disposed adjacent to the first region in a first direction which is the direction of current flowing from the first semiconductor chip into the metal plate, a third region disposed on the opposite side of the first region in the first direction adjacent to the second region, and in a second direction perpendicular to the first direction, the width of the second region is smaller than the width of the first region, in the second direction, the width of the third region is larger than the width of the second region, a thick portion is provided in the third region, in the thickness direction of the metal plate, the thickness of the region where the thick portion is provided in the third region is thicker than the thickness of the first region, The method of manufacturing the semiconductor device includes a step of preparing an alignment jig including a frame body having an inner wall surface constituting a through hole and ribs provided on the inner wall surface, A method of manufacturing a semiconductor device, including a step of laminating the first semiconductor chip and the first region so as to sandwich the first bonding material in the through hole using the alignment jig, and arranging the first semiconductor chip, the first bonding material, and the metal plate by fitting a portion having a small width of the second region into the rib.

14. The method of manufacturing a semiconductor device according to claim 13, further including a step of heating to a temperature equal to or higher than the melting temperature of the first bonding material after the step of arranging the first semiconductor chip, the first bonding material, and the metal plate.

15. A method of manufacturing a semiconductor device, wherein the semiconductor device includes a first semiconductor chip, a first bonding material having conductivity and disposed on the first semiconductor chip, a metal plate bonded to the first semiconductor chip by the first bonding material, a circuit pattern disposed in the thickness direction of the metal plate, and a second bonding material having conductivity and disposed on the circuit pattern. The metal plate includes a first region bonded to the first semiconductor chip when viewed in the thickness direction of the metal plate, and a second region disposed adjacent to the first region in a first direction which is the direction of current flowing from the first semiconductor chip into the metal plate. In a second direction perpendicular to the first direction, the width of the second region is smaller than the width of the first region. The first semiconductor chip is bonded to the circuit pattern by the second bonding material. The method of manufacturing the semiconductor device includes a step of previously bonding the first region and the first semiconductor chip with the first bonding material, a step of preparing an alignment jig including a frame body having an inner wall surface constituting a through hole and ribs provided on the inner wall surface, a step of disposing the alignment jig on the circuit pattern, laminating the circuit pattern and the first semiconductor chip so as to sandwich the second bonding material in the through hole, and arranging the first semiconductor chip, the first bonding material, the second bonding material, and the metal plate by fitting a portion having a small width of the second region into the rib.

16. The method of manufacturing a semiconductor device according to claim 15, further including a step of heating to a temperature equal to or higher than the melting temperature of the second bonding material after the step of arranging the first semiconductor chip, the first bonding material, the second bonding material, and the metal plate.

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