Quantum computer verification apparatus and method

Abstract

This quantum computer verification device comprises: a division unit 1 that divides n qubits acted on by a quantum circuit U into m qubits and (n-m) qubits such that the number of straddling CZ gates becomes D=O(log n); a stabilizer operator calculation unit 2 that calculates a stabilizer operator ^sk for each value of k; an estimation unit 3 that obtains T2 estimated values by selecting (i, j, i', j') at random T2 times for each of the values of k and calculates estimated values of the real part of the value of the following formula; an average value calculation unit 4 that obtains, for each of the values of k, an average value of the T2 estimated values and sets the obtained average value as an estimated value of Tr[ρout^sk] for a corresponding one of the values of k; and a fidelity estimated value calculation unit 5 that obtains an average value of the estimated values of Tr[ρout^sk] corresponding to the values of k so as to be set as an estimated value Fest of the fidelity F of the quantum circuit U.

Description

Technical Field

[0001] The present invention relates to a technique for verifying the correctness of the operation of a quantum computer.

Background Art

[0002] A quantum computer of size n prepares n quantum bits represented by normalized two-dimensional complex vectors, applies arbitrary single-qubit gates and CZ gates to them, and finally measures some or all of the quantum bits in the Pauli Z basis, also called the computational basis, to obtain a calculation result.

[0003] In particular, when realizing a quantum computer in a solid quantum system such as a superconducting circuit, operations are performed on the quantum bits prepared on the chip.

[0004] Such a chip is called a quantum chip and is characterized by a graph representing which two-qubit gates can act directly between which quantum bits. Each vertex of the graph represents the position of a quantum bit, meaning that a two-qubit gate can act directly only between the quantum bits connected by an edge.

[0005] As a specific example, FIG. 6 shows a graph characterizing a 53-qubit quantum chip created by IBM (see, for example, Non-Patent Document 1). Each number 0-52 is the number of a quantum bit, meaning that, for example, a two-qubit gate can be directly applied between the 0th and 1st qubits, but not directly between the 0th and 2nd qubits.

[0006] In particular, when a graph characterizing a quantum chip containing n quantum bits can be separated into two subgraphs having Θ(n) vertices by removing a constant number of edges independent of the value of n, the quantum chip is said to be sparse.

[0007] In the case of Figure 6, as shown by the dashed lines, by removing two edges, namely the edge between vertices 21 and 28 and the edge between vertices 25 and 29, the graph can be separated into a subgraph consisting of vertices 0-27 and a subgraph consisting of vertices 28-52.

[0008] The verification of a quantum computer is carried out by repeatedly applying 1 and 2 quantum bit gates to the quantum bits on the quantum chip that has been actually created, and then generating the state ρ out However, the ideal pure state |Ψ predicted by theory t >. Specifically, the measure of closeness is the fidelity F=<Ψ t |ρ out |Ψ t >, |FF est A real number F that satisfies |≦ε with probability 1-δ or greater est The purpose of verification is to find out.

[0009] Where, ρ out is the trace whose value is 1. n ×2 n is a positive semidefinite matrix of |Ψ t >2 n A normalized complex vector of dimension, <Ψ t |is|Ψ t >, where ε, δ are real numbers satisfying 0<ε, δ<1.

[0010] The closer ε is to 0, the closer the actual fidelity is to the estimated value, meaning the higher the estimation accuracy. Also, the closer δ is to 0, the lower the probability of estimation failure, meaning the more reliable the estimation is.

[0011] Usually F est The size of the quantum device (for simplicity, let us call it B) that can be used to find ρ is required to be smaller than the size of the quantum computer we want to verify (for simplicity, let us call it A). How many ρ out If you enter a copy of est The efficiency of the verification method can be evaluated by whether or not ρ outSince a copy of [[ID=]] is prepared by operating the quantum computer A to be verified the same number of times as the required number of copies, it can be said that a verification method with a smaller required number of copies is more efficient. In particular, when the required number of samples is polynomial with respect to the size n of the quantum computer A to be verified, it is called efficient.

[0012] When the size of the quantum computer is n, on average

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[0013] First, for a natural number k satisfying 1 ≤ k ≤ 4 n let W k be the tensor product of n Pauli matrices This W k is used to

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[0014] 1. First, the value of k is randomly selected according to the following probability distribution

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[0015] 2. The quantum computer outputs ρ out m i times, and each is used with the selected ki W corresponding to the value of ki is measured on the basis of. As a result, A is obtained as the j-th measurement result ij ∈ {1, -1} (1 ≤ j ≤ m i ).

[0016] Using these,

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[0017] 3. Using {~X i} i=1 L obtained in Step 2, the average value

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[0018] The value of k is

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Prior Art Documents

Non-Patent Documents

[0019]

Non-Patent Document 1

Non-Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0020] The method proposed in Non-Patent Document 2 can be applied to the verification of any quantum chip including n qubits, but to do so, on average, at most

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[0021] An object of the present invention is to provide a quantum computer verification apparatus and method capable of verifying a quantum computer more efficiently than in the prior art.

Means for Solving the Problems

[0022] A quantum computer verification apparatus according to one aspect of the present invention includes a dividing unit that divides n qubits on which a quantum circuit U acts into m qubits and (n - m) qubits such that the number of CZ gates spanning them is D = O(log n), and the quantum circuit U can be expressed as follows using an m-qubit gate V i and an (n - m)-qubit gate W j and is expressed as follows,

Equation

[0023] The verification of a quantum computer can be performed more efficiently than before. [Brief Description of the Drawings]

[0024]

Figure 1

Figure 2

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[0025] Hereinafter, embodiments of the present invention will be described in detail. In the drawings, components having the same function are denoted by the same reference numerals, and redundant description will be omitted.

[0026] [Quantum Computer Verification Apparatus and Method] As shown in FIG. 1, the quantum computer verification apparatus includes, for example, a splitting unit 1, a stabilizer operator calculation unit 2, an estimation unit 3, an average value calculation unit 4, and a fidelity estimation value calculation unit 5.

[0027] The quantum computer verification method is realized, for example, by each component of the quantum computer verification apparatus performing the processes of steps S1 to S5 described below and shown in FIG. 2.

[0028] Note that the symbol “^” used in the text should originally be described directly above the following character, but due to text notation limitations, it is described immediately before the character. In mathematical formulas, these symbols are described in their original positions, that is, directly above the characters. For example, “ ^ X” in the text is described as follows in the mathematical formula. Mathematics The quantum computer verification apparatus and method are an apparatus and method for more efficiently verifying a quantum computer than in the past. Verification is to evaluate the closeness between the actually output quantum state and the theoretically expected correct quantum state by a quantity called fidelity.

[0029] Hereinafter, for an n - qubit state with density D, Mathematics We propose a method for estimating the fidelity by measuring fewer than n qubits in each copy. This method is applicable to general quantum computers, similar to conventional methods. In particular, this method is efficient when used for verifying quantum computers with the density of the output quantum state D = O(log n). As will be described later, this method can also be used for verifying quantum computers with D ≠ O(log n).

[0030] Define the density of a quantum state as follows. Consider a gate set composed of single-qubit gates and CZ (Controlled-Z) gates.

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[0031] Define a NISQ (Noisy Intermediate-Scale Quantum) computer as a quantum circuit of O(log n) depth on a quantum chip represented by a graph that can be divided into two subgraphs of the same number of vertices by removing a constant number of edges. Therefore, the density of the output state of a NISQ computer is D = O(log n).

[0032] For example, consider a quantum chip represented by a 1D graph as shown in Fig. 3. This graph can be divided into two subgraphs of the same number of vertices by removing the middle edge. When a quantum circuit of depth d is implemented on the quantum chip represented by this graph, the density D is at most d.

[0033] For any \(0 \lt \varepsilon, \delta \lt 1\) of hope and any \(n\)-qubit state \(|\Psi\rangle\) with density \(D = O(\log n)\) t \(\geq U|0\rangle\) n , with probability at least \(1 - \delta\), find \(|F\rangle\) est - \(\langle\Psi|\) t \(\rho|\) out \(|\Psi\rangle\) t \(|\leq \varepsilon\) satisfying \(F\) est efficiently. Here, \(\rho\) out is the output state of an actual NISQ computer, assuming this state does not change over time. Furthermore, for \(n / 2 \leq m \lt n - 1\), assume that any \((m + 1)\)-qubit gate can be realized with an error of the diamond norm \(\varepsilon / 4\) D+2 .

[0034] First, the splitting part 1 divides the \(n\) qubits on which the quantum circuit \(U\) acts into \(m\) qubits and \((n - m)\) qubits such that the number of CZ gates spanning them is \(D = O(\log n)\) (step S1). Since the density of \(|\Psi\rangle\) t is \(D = O(\log n)\), such a division can always be performed.

[0035] The divided quantum circuit \(U\) is expressed as follows.

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[0036] The stabilizer operator calculation part 2 randomly selects the value of \(k \in \{0, 1\}\) n \(T\) times, and for each \(k\), calculates the stabilizer operator \(\hat{s}\) 1 defined by the following formula (step S2). The stabilizer operator calculation part 2 randomly selects the value of \(k \in \{0, 1\}\) k e.g., uniformly randomly \(T\) n times. 1 [Number] T 1 is a predetermined positive integer. Q i,j † =V i (×)W j where k i is the i-th bit of k, and Z i is the Pauli Z gate acting on the i-th qubit, and i L ,j L is the L-th bit of i,j, and i·j=(+) L=1 D i L j L Here, (×) represents the tensor product. (+) represents the exclusive OR. † represents the complex conjugate transpose.

[0037] The estimator 3, for each k, randomly selects (i,j,i’,j’) T 2 times, and calculates the estimated value of the real part of the following formula to obtain T 2 estimated values (step S3). The estimator 3 randomly selects (i,j,i’,j’) uniformly at random for each k T 2 times. The obtained T 2 estimated values are sent to the average value calculator 4. T 2 is a predetermined positive integer. Tr represents the diagonal sum. [Number] The estimator 3 calculates the expected value of Σ L∈{0,1}^3 β(i,j,i’,j’,L) / 2 as the estimated value of the real part of the above formula (step S3).

[0038] For this purpose, the estimator 3 operates the quantum circuit of FIG. 4 T 3 times for each L. T 3 is a predetermined positive integer. H is the Hadamard gate, and X is the Pauli X gate. The square box (V i † ,V i’ † ,W j† ,W j’ † The symbol with a vertical line attached to ()) represents the one obtained by controlling the quantum gate written in the square box. Furthermore, for any L ∈ {0, 1} 3 with respect to, C L = S^(δ L1,1 δ L2,0 )H^(δ L1+L2,1 )X^(L 3 ). Z is the Pauli Z gate, and S = √Z. δ a,b is the Kronecker delta. δ a,b = 1 when a = b, and δ a,b = 0 when a ≠ b. The meter mark represents the Pauli Z measurement. o ∈ {0, 1}, b ∈ {0, 1}, z ∈ {0, 1} n represent the measurement results.

[0039] Let the part enclosed by the upper dashed line in Figure 4 be the first quantum circuit. The first quantum circuit is a quantum circuit including the m - qubit gate V i . The inputs of the first quantum circuit are |0> and the m - qubits divided by the division part 1 in ρ out .

[0040] Let the part enclosed by the lower dashed line in Figure 4 be the second quantum circuit. The second quantum circuit is a quantum circuit including the n - m - qubit gate W j . The inputs of the second quantum circuit are |0> and the n - m - qubits divided by the division part 1 in ρ out .

[0041] β(i, j, i’, j’, L) = (-1)^((1 + δ L1,0 δ L2,0 )o)α(i, j, i’). α(i, j, i’) ∈ {1, -1} is 1 only when (+) i=1 n z i k i = i·j(+)i’·j’(+)b is satisfied, and -1 otherwise.

[0042] The average value calculation unit 4, for each k, T 2Find the average value of the individual estimated values, and use the obtained average value as the estimated value of Tr[ρ out ^s k corresponding to each k (step S4). The obtained estimated values of Tr[ρ out ^s k corresponding to each k are sent to the fidelity estimator 5.

[0043] The fidelity estimator 5 finds the average value of the estimated values of Tr[ρ out ^s k corresponding to each k, and uses it as the estimated value F est of the fidelity F of the quantum circuit U (step S5). In step S2, k is selected T 1 times. Therefore, it can be said that the fidelity estimator 5 finds the average value of the T 1 estimated values of Tr[ρ out ^s k and uses it as the estimated value F est of the fidelity F of the quantum circuit U.

[0044] Figure 5 shows an overview of these operations. First, the qubits of the quantum circuit U are divided into m qubits and n - m qubits. The m qubits of the output state ρ out of the quantum circuit U and |0> are input to the first quantum circuit. The n - m qubits of the output state ρ out of the quantum circuit U and |0> are input to the second quantum circuit.

[0045] In Figure 5, the calculations performed using the measurement results of the first quantum circuit and the second quantum circuit are represented as classical post - processing.

[0046] The size of the first quantum circuit is m + 1, and the size of the second quantum circuit is n - m + 1. Since both are less than n, the size of the quantum circuit used for verification is smaller than the size of the quantum computer to be verified (in this case, a NISQ computer).

[0047] In the conventional method, the faithfulness to be estimated was utilized by writing it as the sum of the expected values of the tensor products of Pauli matrices. Therefore, the required number of copies increased exponentially with respect to the size n of the quantum computer to be verified. On the other hand, by using a decomposition method different from the conventional method, such as in the above-described embodiment, this problem is avoided.

[0048] The number of samples required for the method described in the embodiment is at most [Number] This is the case. In the case of a NISQ computer, since D = O(log n), this number becomes polynomial with respect to the number of qubits n. In particular, when D, δ, and ε are constants, even if the size of the quantum computer increases, the time required for verification does not change and is constant. That is, by the method described in the embodiment, it becomes possible to verify a NISQ computer in a shorter time than before.

[0049] The method described in the embodiment can also be applied when the quantum computer to be verified is not a NISQ computer, or in other words, when the depth is O(log n) but the quantum chip is not sparse. Even in this case, the method described in the embodiment is more efficient than the conventional method. Many of the currently created quantum chips can be represented by a planar graph with a constant maximum degree. When represented in this way, the dependence of the number of samples of the method described in the embodiment is 2^(O((√n)log n)). Although 2^(O((√n)log n)) is not a polynomial, it is smaller than the conventional number of samples O(2 n ).

[0050] [Modification Example] As described above, the embodiments of the present invention have been explained. However, the specific configuration is not limited to these embodiments, and it goes without saying that even if there are appropriate design changes and the like without departing from the gist of the present invention, they are included in the present invention.

[0051] In the embodiments, the various processes described are not only executed in time series according to the order of description, but may also be executed in parallel or individually according to the processing capabilities of the device that executes the processes, or as necessary.

Claims

1. A splitting unit that divides the n qubits on which the quantum circuit U acts into m qubits and (n - m) qubits such that the number of CZ gates spanning them is D = O(log n), The quantum circuit U can be expressed as follows using the m-qubit gate V i and the (n - m)-qubit gate W j assuming it can be represented by the following equation 【24 Points】 Q i,j † =V i (×)W j where k i is the i-th bit of k, and Z i is the Pauli Z gate acting on the i-th qubit, and i L , j L is the L-th bit of i, j, and i · j=(+) L=1 D i L j L where T 1 is a predetermined positive integer, k ∈ {0, 1} n randomly selects the value of T 1 times, and for each k, a stabilizer operator ^s defined by the following equation k is calculated by a stabilizer operator calculation unit, 【Number 25】 ρ out is the state output by the quantum circuit U. For each k, (i, j, i’, j’) is randomly selected T 2 times, and by calculating the estimated value of the real part of the value of the following formula, T 2 estimated values are obtained, and an estimation unit 【Number 26】 For each k, the said T 2 Calculate the average value of the estimated values, and use the obtained average value as the estimated value of Tr[ρ out ^s k corresponding to each k, an average value calculation unit For each k, find the average value of the estimated value of Tr[ρ out ^s k , and obtain the estimated value F est of the fidelity F of the quantum circuit U, and a fidelity estimation value calculation unit that sets it as such. A quantum computer verification device comprising the same.

2. A splitting step in which the splitting unit divides the n qubits on which the quantum circuit U acts into m qubits and (n - m) qubits such that the number of CZ gates spanning them is D = O(log n), The stabilizer operator calculation unit determines that the quantum circuit U can be expressed as follows using the m-qubit gate V i and the (n - m)-qubit gate W j and assumes that it can be represented by the following equation 【Number 27】 Q i,j † =V i (×)W j where k i is the i-th bit of k, and Z i is the Pauli Z gate acting on the i-th qubit, and i L ,j L is the L-th bit of i,j, and i·j=(+) L=1 D i L j L where T 1 is a predetermined positive integer, k ∈ {0,1} n randomly selects the value of k 1 T times, and for each k, the stabilizer operator ^s k defined by the following formula is calculated, which is the stabilizer operator calculation step, and 【Number 28】 The estimation unit estimates ρ out which is the state output by the quantum circuit U, and for each k, randomly selects T 2 times of (i, j, i', j'), and calculates the estimated value of the real part of the value of the following formula to obtain T 2 estimated values, which is an estimation step; 【No. 29】 For each k, the average value calculation unit obtains the average value of the T 2 estimated values, and sets the obtained average value as the estimated value of Tr[ρ out ^s k corresponding to each k, which is the average value calculation step, The fidelity estimation value calculation unit obtains the average value of the estimated values of Tr[ρ out ^s k corresponding to each k, and sets the estimated value F est of the fidelity F of the quantum circuit U as the estimated value of the fidelity, and A quantum computer verification method comprising the same.

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