A voltage regulator that provides immediate response to load changes

Abstract

To provide a voltage regulator.SOLUTION: A voltage regulator includes an operational amplifier, a first transistor, a second transistor, a capacitor and a current sink circuit. The operational amplifier outputs a control voltage according to an amplified differential voltage between a first input terminal and a second input terminal of the operational amplifier. The first transistor includes a control terminal receiving the control voltage, a first terminal coupled to a supply terminal, a second terminal providing an output voltage, and a bulk terminal. The second transistor includes a second terminal coupled to the bulk terminal of the first transistor, and a bulk terminal coupled to the supply terminal. The capacitor includes a first terminal coupled to the bulk terminal of the first transistor, and a second terminal receiving the output voltage. The current sink circuit generates a feedback voltage according to the output voltage and outputs the feedback voltage to the operational amplifier.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a power supply circuit, and more particularly, to a voltage regulator that provides immediate response to load changes.

Background Art

[0002] A voltage regulator is a device designed to automatically maintain a constant voltage level and has a wide range of applications in power supplies for electronic devices, computing devices, mobile devices, portable devices, household appliances, and the like. For application in wearable devices, the voltage regulator needs to consume less power to achieve a long service life and adopt a configuration with a smaller output capacitor or no capacitor to reduce manufacturing costs. One solution to achieve low power consumption is to apply lower current drivability in the voltage regulator to the output transistor. However, an output transistor with low current drivability and a small output capacitor may result in low circuit response.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Patent Document 8

Summary of the Invention

[0004] According to an embodiment of the present invention, a voltage regulator includes an operational amplifier, a first transistor, a second transistor, a first capacitor, and a current sink circuit. The operational amplifier has a first input terminal, a second input terminal, and an output terminal. The output terminal outputs a control voltage according to the amplified differential voltage between the first input terminal and the second input terminal. The first transistor has a control terminal coupled to the output terminal of the operational amplifier, a first terminal coupled to a supply terminal, a second terminal that supplies an output voltage to a load terminal, and a bulk terminal. The second transistor has a control terminal coupled to the output terminal of the operational amplifier, a first terminal coupled to the supply terminal, a second terminal coupled to the bulk terminal of the first transistor, and a bulk terminal coupled to the supply terminal. The first capacitor has a first terminal coupled to the bulk terminal of the first transistor and the second terminal of the second transistor, and a second terminal coupled to the second terminal of the first transistor. The current sink circuit is coupled to the second terminal of the first transistor, the second terminal of the first capacitor, the second input terminal of the operational amplifier, and a ground terminal.

[0005] According to another embodiment of the present invention, the voltage regulator includes an operational amplifier, a first transistor, a second transistor, a first capacitor, and a current sink circuit. The operational amplifier has a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first output terminal outputs a first control voltage according to the amplified differential voltage between the first input terminal and the second input terminal, and the second output terminal outputs a second control voltage according to the amplified differential voltage between the first input terminal and the second input terminal. The first transistor has a control terminal coupled to the first output terminal of the operational amplifier, a first terminal coupled to a supply terminal, a second terminal that supplies an output voltage to a load terminal, and a bulk terminal. The second transistor has a control terminal coupled to the first output terminal of the operational amplifier, a first terminal coupled to the supply terminal, a second terminal coupled to the bulk terminal of the first transistor, and a bulk terminal coupled to the supply terminal. The first capacitor has a first terminal coupled to the bulk terminal of the first transistor and the second terminal of the second transistor, and a second terminal coupled to the second terminal of the first transistor. The current sink circuit is coupled to the second terminal of the first transistor, the second terminal of the first capacitor, the second input terminal of the operational amplifier, the second output terminal of the operational amplifier, and a ground terminal.

[0006] These and other objects of the present invention will become apparent to those skilled in the art after reading the following detailed description of the preferred embodiments shown in the various figures and drawings.

Brief Description of the Drawings

[0007]

Figure 1

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Figure 2

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Figure 3

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Figure 4

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Figure 5

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Figure 6

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Figure 7

[0014]

Figure 8

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Figure 9

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Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0017] FIG. 1 is a schematic circuit diagram of a voltage regulator 1 according to an embodiment of the present disclosure. The voltage regulator 1 may supply an output voltage Vout to a load L and may maintain the output voltage Vout at a predetermined level regardless of the load state. The predetermined level may be substantially constant. The load L may be a processor of a computing device. The processor may operate in an active mode or a sleep mode. In the active mode, the processor may consume a high current from the voltage regulator 1, and the voltage regulator 1 may operate in a heavy load state. In the sleep mode, the processor may consume a low current from the voltage regulator 1, and the voltage regulator 1 may operate in a light load state. When switching from the light load state to the heavy load state, the load L consumes an excessive amount of current from the voltage regulator 1, resulting in a rapid drop in the output voltage Vout. Conversely, when switching from the heavy load state to the light load state, the load L consumes a reduced amount of current from the voltage regulator 1, resulting in a rapid increase in the output voltage Vout. The rapid change in the output voltage Vout may be less than 100 mV. Depending on the load magnitude, the rapid change in the output voltage Vout may be 100 mV or more. The voltage regulator 1 may immediately adjust the current flowing to the load L in response to a change in the output voltage Vout.

[0018] The voltage regulator 1 may include an operational amplifier 10, a transistor M1, a transistor M2, a capacitor Cc, and a current sink circuit 12. The operational amplifier 10 includes a first input terminal, a second input terminal, and an output terminal. The transistor M1 has a control terminal coupled to the output terminal of the operational amplifier 10, a first terminal coupled to the supply terminal, a second terminal that supplies an output voltage Vout to the load terminal of the load L, and a bulk terminal. The supply terminal may supply a substantially constant supply voltage VDD. The transistor M2 has a control terminal coupled to the output terminal of the operational amplifier 10, a first terminal coupled to the supply terminal, a second terminal coupled to the bulk terminal of the transistor M1, and a bulk terminal coupled to the supply terminal. The capacitor Cc has a first terminal coupled to the bulk terminal of the transistor M1 and the second terminal of the transistor M2, and a second terminal coupled to the second terminal of the transistor M1. The current sink circuit 12 is coupled to the second terminal of the transistor M1, the second terminal of the capacitor Cc, the second input terminal of the operational amplifier 10, and the ground terminal. The ground terminal may supply a substantially constant ground voltage VSS. The load L may include a load terminal, a resistor Rout, and a capacitor Cout. The resistor Rout has a first terminal coupled to the load terminal and a second terminal coupled to the ground terminal. The capacitor Cout has a first terminal coupled to the load terminal and a second terminal coupled to the ground terminal.

[0019] The current sink circuit 12 may have a resistor R1. The resistor R1 has a first terminal coupled to the second terminal of the transistor M1, the second terminal of the capacitor Cc, and the second input terminal of the operational amplifier 10, and a second terminal coupled to the ground terminal. The resistor R1 may provide a current sink path that draws (sinks) excess current to the ground terminal.

[0020] Transistor M1 may generate a current Im1 according to a control voltage va. The current Im1 may include a current Ic that charges a capacitor Cout and a current Iload that flows through a resistor Rout. Transistor M1 may be a P-type metal oxide semiconductor field effect transistor (MOSFET) having a threshold voltage Vthp. When the control voltage va is lower than the difference between the supply voltage VDD and the absolute value of the threshold voltage |Vthp|, transistor M1 is turned on to generate a current Im1. The magnitude of the current Im1 may be a function of the difference between the supply voltage VDD and the control voltage va. In other words, the lower the control voltage va, the larger the current Im1 supplied. When the control voltage va is higher than the difference between the supply voltage VDD and the absolute value of the threshold voltage |Vthp|, transistor M1 is turned off to stop the generation of the current Im1.

[0021] The first input terminal of the operational amplifier 10 may receive a reference voltage Vref. The reference voltage Vref may have a fixed value. The second input terminal of the operational amplifier 10 may receive a feedback voltage Vfb. The feedback voltage Vfb may be controlled to be equal to the reference voltage Vref. The output terminal of the operational amplifier 10 may output a control voltage according to the amplified differential voltage between the first input terminal and the second input terminal. The first input terminal of the operational amplifier 10 may be an inverting input terminal, and the second input terminal of the operational amplifier 10 may be a non-inverting input terminal. The feedback voltage Vfb may be positively correlated with the output voltage Vout. In an embodiment, the feedback voltage Vfb may be equal to the output voltage Vout. The operational amplifier 10 may generate a control voltage va according to the difference between the feedback voltage Vfb and the reference voltage Vref. When the output voltage Vout drops suddenly, the feedback voltage Vfb may drop accordingly. When the feedback voltage Vfb drops, the difference between the feedback voltage Vfb and the reference voltage Vref may increase (when the feedback voltage Vfb is lower than the reference voltage Vref, the result of subtracting Vref from Vfb may be negative for the operational amplifier 10), and the control voltage va may decrease. As a result of the decrease in the control voltage va, by turning on the transistor M1, the current Im1 may further increase. Therefore, a sudden drop in the output voltage Vout can be compensated, and the output voltage Vout can be maintained at a predetermined level. Conversely, when the output voltage Vout rises suddenly, the feedback voltage Vfb may increase accordingly. When the feedback voltage Vfb rises, the difference between the feedback voltage Vfb and the reference voltage Vref may increase (when the feedback voltage Vfb is higher than the reference voltage Vref, the result of subtracting Vref from Vfb may be positive for the operational amplifier 10), and the control voltage va may increase. As a result of the increase in the control voltage va, the current Im1 may further decrease by turning on the transistor M1 weakly, or the supply may be stopped to turn off the transistor M1 completely. Therefore, a sudden rise in the output voltage Vout can be compensated, and the output voltage Vout can be maintained at a predetermined level.Therefore, the generation of the control voltage va depends on the difference between the feedback voltage Vfb and the reference voltage Vref, and the convergence of the control voltage va consumes time and may slow down the response of the voltage regulator 1 to changes in the output voltage Vout.

[0022] Therefore, the transistor M2 and the capacitor Cc are incorporated to speed up the response of the voltage regulator 1 to maintain the output voltage Vout at a predetermined level when the output voltage Vout changes rapidly. The transistor M2 may be a P-type MOSFET and may function as a resistor. In the light load state, the control voltage va may increase, and thus, the transistor M2 may be turned off or slightly turned on, the resistance of the transistor M2 may increase, and the bulk voltage vb of the transistor M1 is mostly determined by the output voltage Vout. In the heavy load state, the control voltage va may decrease, and thus, the transistor M2 may be turned on, the resistance of the transistor M2 may decrease, and the bulk voltage of the transistor M1 is determined by the supply voltage VDD and the output voltage Vout. The transistor M2 and the capacitor Cc may function as a time constant circuit configured between the supply terminal, the bulk terminal of the transistor M1, and the second terminal of the transistor M1. The change in the output voltage Vout may be propagated as the bulk voltage vb at the bulk terminal of the transistor M1 through the capacitor Cc. The threshold voltage Vthp of the transistor M1 may be affected by its bulk voltage vb due to the body effect and can be expressed by Equation (1):

Equation

[0023] As shown in Equation (1), the threshold voltage Vthp is negatively correlated with the source-bulk voltage Vsb. A rapid drop in the output voltage Vout may cause a drop in the bulk voltage vb of the transistor M1 via the capacitor Cc. Therefore, the source-bulk voltage Vsb of the transistor M1 may increase, the threshold voltage Vthp of the transistor M1 may decrease, the transistor M1 increases the current Im1 while keeping the control voltage va unchanged, pulls up the output voltage Vout, and maintains the output voltage Vout at a substantially constant level. A rapid rise in the output voltage Vout may cause a rise in the bulk voltage vb of the transistor M1 via the capacitor Cc. Therefore, the source-bulk voltage Vsb of the transistor M1 may decrease, the threshold voltage Vthp of the transistor M1 may increase, the transistor M1 decreases the current Im1 while keeping the control voltage va unchanged, pulls down the output voltage Vout, and maintains the output voltage Vout at a substantially constant level.

[0024] The capacitance of the capacitor Cc can be selected without affecting the stability of the voltage regulator 1. In some embodiments, the capacitance of the capacitor Cc may be less than one-tenth of the capacitance of the capacitor Cout and can satisfy Equation (2):

Equation

[0025] FIG. 2 is a waveform of the voltage regulator 1 represented as an exemplary load change state. Lines 20 and 22 represent the waveforms of the output voltage Vout in the embodiments of the present invention and the prior art, respectively, and lines 24 and 26 represent the waveforms of the current Im1 in the embodiments of the present invention and the related art, respectively.

[0026] In the embodiment, at time t1, the load state is switched from a heavy load state to a light load state. Between time t1 and time t2, the load L draws a reduced amount of current Iload, the waveform 20 of the output voltage Vout rises from a predetermined level Vprd to an output peak level Vp1, the bulk voltage vb increases from the supply voltage VDD to a bulk peak level Vbp, the control voltage va remains at the voltage level Vl, and the waveform 24 of the current Im1 decreases from a current level Ih to a current level Il in response to the increase in the bulk voltage vb, suppressing the rise of the waveform 20 of the output voltage Vout. The supply voltage VDD may be the stable level of the bulk voltage vb. Between time t2 and time t3, the waveform 20 of the output voltage Vout drops from the output peak level Vp1, the bulk voltage vb drops from the bulk peak level Vbp, the control voltage va remains at the voltage level Vl, the waveform 24 of the current Im1 remains at the current level Il, suppressing the rise of the waveform 20 of the output voltage Vout. Between time t3 and time t4, the waveform 20 of the output voltage Vout continues to drop to a predetermined level Vprd, the bulk voltage vb continues to drop to the supply voltage VDD, the control voltage va begins to rise from the voltage level Vl toward a voltage level Vh, the waveform 24 of the current Im1 remains at the current level Il, pulling down the waveform 20 of the output voltage Vout toward the predetermined level Vprd.

[0027] In the related art, between time t1 and time t3, the waveform 22 of the output voltage Vout rises from a predetermined level Vprd to the output peak level Vp2, the control voltage va remains at the voltage level Vl, and the waveform 26 of the current Im1 remains at the current level Ih. The output peak level Vp2 of the waveform 22 can be higher than the output peak level Vp1 of the waveform 20. Between time t3 and time t5, the control voltage va rises from the voltage level Vl to the voltage level Vh, the waveform 26 of the current Im1 decreases from the current level Ih to the current level Il, and the waveform 22 of the output voltage Vout is pulled down to the predetermined level Vprd. Compared with the related art, the waveform 20 of the output voltage Vout returns to the predetermined level Vprd at time t4, and the waveform 22 of the output voltage Vout returns to the predetermined level Vprd at time t5. Therefore, the embodiment of the present invention responds to changes in the load state faster than the related art.

[0028] FIG. 3 is a waveform of the voltage regulator 1 represented as another exemplary load change state. Lines 30 and 32 represent the waveforms of the output voltage Vout in the embodiment of the present invention and the related art, respectively, and lines 34 and 36 represent the waveforms of the current Im1 in the embodiment of the present invention and the related art, respectively.

[0029] In the embodiment, at time t1, the load state is switched from a light load state to a heavy load state. Between time t1 and time t2, the load L draws an increased amount of current Iload, the waveform 30 of the output voltage Vout drops from a predetermined level Vprd to an output valley level Vvl, the bulk voltage vb decreases from the supply voltage VDD to a bulk valley level Vbv, the control voltage va remains at the voltage level Vh, and the waveform 34 of the current Im1 rises from a current level Il to a current level Ih1 in response to the decrease in the bulk voltage vb to compensate for the drop in the waveform 30 of the output voltage Vout. Between time t2 and time t3, the waveform 30 of the output voltage Vout rises from the output valley level Vv1 to a predetermined level Vprd, the bulk voltage vb rises from the bulk valley level Vbv toward the supply voltage VDD, the control voltage va remains at a predetermined voltage level Vh, the waveform 34 of the current Im1 drops from the current level Ih1 to a final level If to pull up the waveform 30 of the output voltage Vout to a predetermined level Vprd. Between time t3 and time t4, the control voltage va drops from the voltage level Vh to a voltage level Vl. Between time t4 and time t5, the control voltage va remains at the voltage level Vl, the waveform 34 of the current Im1 remains at the final level If, and the waveform 30 of the output voltage Vout remains at a predetermined level Vprd.

[0030] In the related art, between time t1 and time t3, the waveform 32 of the output voltage Vout drops from a predetermined level Vprd to the output valley level Vv2, the control voltage va remains at the voltage level Vh, and the waveform 36 of the current Im1 remains at the current level Il. The output valley level Vv2 can be lower than the output valley level Vv1. Between time t3 and time t4, the control voltage va drops from the voltage level Vh to the voltage level Vl, and the waveform 36 of the current Im1 increases from the current level Il to the current level Ih2 to pull up the waveform 32 of the output voltage Vout from the output valley level Vv2 to the predetermined level Vprd. Between time t4 and time t5, the control voltage va remains at the voltage level Vl, and the waveform 36 of the current Im1 decreases from the current level Ih2 to the final level If to pull up the waveform 32 of the output voltage Vout to the predetermined level Vprd. Compared with the related art, the waveform 30 of the output voltage Vout is returned to the predetermined level Vprd at time t3, and the waveform 32 of the output voltage Vout is returned to the predetermined level Vprd at time t5. Therefore, the embodiment of the present invention responds to changes in the load state faster.

[0031] FIG. 4 is a schematic circuit diagram of a voltage regulator 4 according to another embodiment of the present invention. The voltage regulator 4 is different from the voltage regulator 1 in that a current sink circuit 42 is used to replace the current sink circuit 12. The voltage regulator 4 operates in the same manner as the voltage regulator 1, and its description is omitted for simplicity. The current sink circuit 42 will be described in detail in the following paragraphs.

[0032] The current sink circuit 42 includes a transistor M3. The transistor M3 has a first terminal coupled to the second terminal of the transistor M1, the second terminal of the capacitor Cc, and the second input terminal of the operational amplifier 10, a second terminal coupled to the ground terminal, a control terminal receiving a fixed bias voltage Vbias, and a bulk terminal coupled to the ground terminal. The transistor M3 may be an N-type MOSFET and may function as a resistor whose resistance is controlled by the bias voltage Vbias. The transistor M3 may provide a current sink path for drawing (sinking) an excess current to the ground terminal.

[0033] Figure 5 is a schematic circuit diagram of a voltage regulator 5 according to another embodiment of the present invention. The voltage regulator 5 is different from the voltage regulator 1 in that a current sink circuit 52 is used to replace the current sink circuit 12. The voltage regulator 5 operates in the same manner as the voltage regulator 1, and its description is omitted for simplicity. The current sink circuit 52 will be described in detail in the following paragraphs.

[0034] The current sink circuit 52 may include a resistor R1 and a resistor R2 configured as a voltage divider. The resistor R2 has a first terminal coupled to the second terminal of the transistor M1 and the second terminal of the capacitor Cc, and a second terminal. The resistor R1 has a first terminal coupled to the second terminal of the resistor R2 and the second input terminal of the operational amplifier 10, and a second terminal coupled to the ground terminal. The first terminal of the resistor R1 may supply a feedback voltage Vfb to the operational amplifier 10. The feedback voltage Vfb is positively correlated with the output voltage Vout and may be lower than the output voltage Vout. In some embodiments, the resistor R1 and the resistor R2 may be implemented by transistors. The voltage regulator 5 can have a regulator gain represented by Equation (3): Vout / Vref=(Rb1+Rb2) / Rb1 Equation (3) Here, Vout is the output voltage. Vref is the reference voltage. Rb1 is the resistance of the resistor R1. Rb2 is the resistance of the resistor R2.

[0035] FIG. 6 is a circuit schematic of the operational amplifier 10 according to the embodiments shown in FIGS. 1, 4, and 5. The operational amplifier 10 may include transistors M60 to M66. The transistors M60, M61, M63, and M65 may be P-type MOSFETs, and the transistors M62, M64, and M66 may be N-type MOSFETs. The transistor M60 has a control terminal that receives a fixed bias voltage Vbias, a first terminal coupled to the supply terminal, and a second terminal. The transistor M65 has a control terminal that receives a fixed bias voltage Vbias, a first terminal coupled to the supply terminal, and a second terminal. The transistors M60 and M65 may function as current sources. The transistor M61 has a control terminal coupled to the first input terminal of the operational amplifier 10, a first terminal coupled to the second terminal of the transistor M60, and a second terminal. The transistor M63 has a control terminal coupled to the second input terminal of the operational amplifier 10, a first terminal coupled to the second terminal of the transistor M60, and a second terminal. The transistor M62 has a control terminal, a first terminal coupled to the control terminal of the transistor M62 and the second terminal of the transistor M61, and a second terminal coupled to the ground terminal. The transistor M64 has a control terminal coupled to the control terminal of the transistor M62, a first terminal coupled to the second terminal of the transistor M63, and a second terminal coupled to the ground terminal. The transistors M62 and M64 may be configured as a current mirror. The transistor M66 has a control terminal coupled to the first terminal of the transistor M64, a first terminal coupled to the second terminal of the transistor M65, and a second terminal coupled to the ground terminal.

[0036] The operational amplifier 10 may receive a reference voltage Vref at the control terminal of transistor M61, receive a feedback voltage Vfb at the control terminal of transistor M63, and output a control voltage va at the second terminal of transistor M65 and the first terminal of transistor M66. The reference voltage Vref is fixed, and as a result, the current passing through transistor M61 becomes equal to the current passing through transistor M63 in the steady state (Vref is equal to Vfb) as described above. The feedback voltage Vfb may change together with the output voltage Vout. As the feedback voltage Vfb decreases, the current passing through transistor M63 may increase correspondingly. The current mirrors of transistors M62 and M64 equalize the currents passing through transistors M62 and M64. Therefore, the extra current in the current passing through transistor M63 may be directed to the control terminal of transistor M66, increasing the voltage of the control terminal of transistor M66 and decreasing the control voltage va at the first terminal of transistor M66. As a result, the control voltage of the operational amplifier 10 may decrease because the current passing through transistor M66 increases by increasing the voltage of the control terminal of transistor M66. As the feedback voltage Vfb increases, the current passing through transistor M63 may decrease correspondingly. The current mirrors of transistors M62 and M64 equalize the currents passing through transistors M62 and M64. Therefore, the insufficient current in the current passing through transistor M63 may be directed to the control terminal of transistor M66, decreasing the voltage of the control terminal of transistor M66, and establishing the control voltage va at the first terminal of transistor M66. As a result, the control voltage va of the operational amplifier 10 may increase because the current passing through transistor M66 decreases by decreasing the voltage of the control terminal of transistor M66.

[0037] In the embodiments in FIGS. 1, 4, and 5, transistors M2 and capacitor Cc are utilized to adjust the bulk voltage vb of transistor M1 with a fast circuit response when the output voltage Vout changes rapidly, reducing the fluctuations in the output voltage due to changes in the load state.

[0038] FIG. 7 is a schematic circuit diagram of a voltage regulator 7 according to another embodiment of the present invention. The voltage regulator 7 is different from the voltage regulator 1 in that a current sink circuit 72 is used to replace the current sink circuit 12, and an operational amplifier 70 is used to replace the operational amplifier 10. The transistors M1, M2, and the capacitor Cc in the voltage regulator 7 operate in the same manner as those in the voltage regulator 1, and the description thereof is omitted for simplicity. The operational amplifier 70 and the current sink circuit 72 will be described in detail in the following paragraphs.

[0039] The operational amplifier 70 includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal. The first input terminal of the operational amplifier 70 may receive a fixed reference voltage Vref. The second input terminal of the operational amplifier 70 may receive a feedback voltage Vfb. The first input terminal of the operational amplifier 70 may be an inverting input terminal, and the second input terminal of the operational amplifier 70 may be a non-inverting input terminal. The first output terminal of the operational amplifier 70 may output a first control voltage va according to the amplified differential voltage between the first input terminal and the second input terminal, and the second output terminal of the operational amplifier 70 may output a second control voltage va2 according to the amplified differential voltage between the first input terminal and the second input terminal. The first control voltage va may be the same as or different from the second control voltage va2. The current sink circuit 72 may be coupled to the second terminal of the transistor M1, the second terminal of the capacitor Cc, the second input terminal of the operational amplifier 70, the second output terminal of the operational amplifier 70, and the ground terminal.

[0040] The current sink circuit 72 may include a transistor M4, a transistor M5, and a capacitor Cc2. The transistor M4 has a control terminal coupled to the second output terminal of the operational amplifier 70, a first terminal coupled to the second terminal of the transistor M1, a second terminal coupled to the ground terminal, and a bulk terminal. The first terminal of the transistor M4 may supply the output voltage Vout to the load terminal of the load L. The transistor M5 has a control terminal coupled to the second output terminal of the operational amplifier 70, a first terminal coupled to the bulk terminal of the transistor M4, a second terminal coupled to the ground terminal, and a bulk terminal coupled to the ground terminal. The capacitor Cc2 has a first terminal coupled to the first terminal of the transistor M4 and a second terminal coupled to the bulk terminal of the transistor M4 and the first terminal of the transistor M5. The second terminal of the transistor M1 and the first terminal of the transistor M4 supply a feedback voltage Vfb to the second input terminal of the operational amplifier 70. The transistors M1 and M2 may be P-type MOSFETs, and the transistors M4 and M5 may be N-type MOSFETs.

[0041] When the load state switches from a heavy load state to a light load state, the current sink circuit 72 may provide a current sink path that draws an excessive current to the ground terminal, suppressing a sudden increase in the output voltage Vout. Similarly, when the load state switches from a light load state to a heavy load state, the current sink circuit 72 may reduce a sudden drop in the output voltage Vout. The transistor M4 may generate a drain current Im4 according to a second control voltage va2. The drain current Im4 can satisfy Equation (4): Iload = Im1 - Ic - Im4 Equation (4) Here, Iload is the current passing through the resistor Rout. Im1 is the drain current generated by the transistor M1. Ic is the current charging the capacitor Cout. Im4 is the drain current generated by the transistor M4.

[0042] Transistor M4 has a threshold voltage Vthn. When the second control voltage va2 is higher than the difference between the threshold voltage Vthn and the ground voltage VSS, transistor M4 is turned on to generate a current Im4. The magnitude of the current Im4 may be a function of the difference between the second control voltage va2 and the ground voltage VSS. In other words, a higher second control voltage va2 supplies a larger current Im4. When the second control voltage va2 is lower than the difference between the threshold voltage Vthn and the ground voltage VSS, transistor M4 is turned off to stop the generation of the current Im4.

[0043] Transistor M5 and capacitor Cc2 are incorporated to speed up the response of the voltage regulator 7 in order to maintain the output voltage Vout at a predetermined level Vprd when the output voltage Vout changes rapidly. Transistor M5 may function as a resistor. Transistor M5 and capacitor Cc2 may function as a time constant circuit configured between the ground terminal, the bulk terminal of transistor M4, and the first terminal of transistor M4. The change in the output voltage Vout may be propagated as a bulk voltage vb2 at the bulk terminal of transistor M4 via capacitor Cc2. The threshold voltage Vthn of transistor M4 may be affected by its bulk voltage vb2 due to the body effect and can be expressed by Equation (5):

Number

[0044] The threshold voltage Vthn is positively correlated with the source-bulk voltage Vsb. A rapid increase in the output voltage Vout may cause an increase in the bulk voltage vb2 of the transistor M4 via the capacitor Cc2. Accordingly, the source-bulk voltage Vsb of the transistor M4 may decrease, the threshold voltage Vthn of the transistor M4 may decrease, the transistor M4 increases the current Im4 while keeping the second control voltage va2 unchanged, draws the excess current to the ground terminal, pulls down the output voltage Vout, and maintains the output voltage Vout at a substantially constant level. A rapid decrease in the output voltage Vout may cause a decrease in the bulk voltage vb2 of the transistor M4 via the capacitor Cc2. Accordingly, the source-bulk voltage Vsb of the transistor M4 may increase, the threshold voltage Vthn of the transistor M4 may increase, the transistor M4 decreases the current Im4 while keeping the control voltage va2 unchanged, and maintains the output voltage Vout at a substantially constant level.

[0045] FIG. 8 is a waveform of the voltage regulator 7 represented as an exemplary load change state. Lines 80 and 82 represent waveforms of the output voltage Vout in the embodiment of the present invention and the related art, respectively, lines 83 and 85 represent waveforms of the current Im1 of the transistor M1 in the embodiment of the present invention and the related art, respectively, and lines 87 and 89 represent waveforms of the current Im4 of the transistor M4 in the embodiment of the present invention and the related art, respectively.

[0046] In the embodiment, at time t1, the load state is switched from a heavy load state to a light load state. Between time t1 and time t2, the load L draws a reduced amount of current Iload, the waveform 80 of the output voltage Vout rises from a predetermined level Vprd to an output peak level Vp1, the bulk voltage vb of the transistor M1 increases from the supply voltage VDD to a bulk peak level Vbp, the bulk voltage vb2 of the transistor M4 increases from the ground voltage VSS to a bulk peak level Vp2, the first control voltage va remains at the voltage level Vl, the second control voltage va2 remains at the voltage level vl2, and the current Im1 decreases from the current level Ih to the current level Ilb1 in response to the increase in the bulk voltage of the transistor M1, and the current Im4 increases from the current level Il2 to the current level Ihp2 in response to the increase in the bulk voltage vb2 of the transistor M4, suppressing the rise of the waveform 80 of the output voltage Vout. The ground voltage VSS may be the stable level of the bulk voltage vb2 of the transistor M4. Between time t2 and time t3, the current Im1 rises from the current level Ilb1 to the current level Il, the current Im4 drops from the current level Ihp2 to the current level Ih2, the output voltage Vout drops from the output peak level Vp1, the bulk voltage vb of the transistor M1 drops from the bulk peak level Vbp to the supply voltage VDD, the bulk voltage vb2 of the transistor M4 drops from the bulk peak level Vbp2 to the ground voltage VSS, the first control voltage va remains at the voltage level Vl, the second control voltage va2 remains at the voltage level Vl2, and the waveform 80 of the output voltage Vout is pulled down to a predetermined level Vprd. Between time t3 and time t4, the first control voltage va rises from the voltage level Vl to the voltage level Vh, the second control voltage va2 rises from the voltage level Vl2 to the voltage level Vh2, the current Im1 remains at the current level Il, the current Im4 remains at the current level Ih2, and the output voltage Vout remains at the predetermined level Vprd. The voltage level Vl may be the same as or different from the voltage level Vl2. The voltage level Vh may be the same as or different from the voltage level Vh2. After time t4, the current Im1 remains at the current level Il, the current Im4 remains at the current level Ih2, and the output voltage Vout remains at the predetermined level Vprd.

[0047] In the related art, between time t1 and time t3, the waveform 82 of the output voltage Vout rises from a predetermined level Vprd to the output peak level Vp2, the waveform 85 of the current Im1 remains at the current level Ih, and the waveform 89 of the current Im4 remains at the current level Il2. The output peak level Vp2 of the waveform 82 may be higher than the output peak level Vp1 of the waveform 80. Between time t3 and time t4, the waveform 85 of the current Im1 drops from the current level Ih to the current level Il, the waveform 89 of the current Im4 rises from the current level Il2 to the current level Ih2, the first control voltage va rises from the voltage level Vl to the voltage level Vh, and the second control voltage va2 rises from the voltage level Vl2 to the voltage level Vh2 to lower the waveform 82 of the output voltage Vout to a predetermined level Vprd. Compared with the related art, the waveform 80 of the output voltage Vout is returned to the predetermined level Vprd at time t3, and the waveform 82 of the output voltage Vout is returned to the predetermined level Vprd at time t4. Therefore, the embodiment of the present invention responds to changes in the load state faster than the related art.

[0048] FIG. 9 is a waveform of the voltage regulator 7 represented as another exemplary load change state. Lines 90 and 92 represent the waveforms of the output voltage Vout in the embodiment of the present invention and the related art, respectively, lines 93 and 95 represent the waveforms of the current Im1 of the transistor M1 in the embodiment of the present invention and the related art, respectively, and lines 97 and 99 represent the waveforms of the current Im4 of the transistor M4 in the embodiment of the present invention and the related art, respectively.

[0049] In the embodiment, at time t1, the load state is switched from a light load state to a heavy load state. Between time t1 and time t2, the load L draws an increased amount of current Iload, the waveform 90 of the output voltage Vout drops from a predetermined level Vprd to an output valley level Vv1, the bulk voltage vb of the transistor M1 decreases from the supply voltage VDD to a bulk valley level Vbv, the bulk voltage vb2 of the transistor M4 decreases from the ground voltage VSS to a second bulk valley level Vbv2, the first control voltage va and the second control voltage va2 remain at voltage levels Vh and Vh2 respectively, the current Im1 rises from a current level Il to a current level Ih1 in response to the decrease in the bulk voltage vb of the transistor M1, the current Im4 drops from a current level Ih2 to a current level Ilb2 to compensate for the drop in the waveform 90 of the output voltage Vout. Between time t2 and time t3, the waveform 90 of the output voltage Vout rises from the output valley level Vv1, the bulk voltage vb of the transistor M1 rises from the bulk valley level Vbv, the bulk voltage vb2 of the transistor M4 rises from the second bulk valley level Vbv2, the first control voltage va and the second control voltage va2 remain at voltage levels Vh and Vh2 respectively, the current Im1 drops from the current level Ih1, the current Im4 rises from the current level Ilb2 to pull up the waveform 90 of the output voltage Vout towards a predetermined level Vprd. Between time t3 and time t4, the waveform 90 of the output voltage Vout rises to the predetermined level Vprd, the bulk voltage vb of the transistor M1 rises to the supply voltage VDD, the bulk voltage vb2 of the transistor M4 rises to the ground voltage VSS, the first control voltage va and the second control voltage va2 drop from voltage levels Vh and Vh2 towards voltage levels Vl and Vl2 respectively, the current Im1 drops to a current level If, the current Im4 rises to a current level Il2 to pull up the waveform 90 of the output voltage Vout to the predetermined level Vprd.

[0050] In the related art, between time t1 and time t3, for the waveform 92 of the output voltage Vout, it drops from a predetermined level Vprd to the output valley level Vv2, the waveform 95 of the current Im1 remains at the current level Il, the waveform 99 of the current Im4 remains at the current level Ih2, and the first control voltage va and the second control voltage va2 remain at the voltage levels Vh and Vh2, respectively. The output valley level Vv2 of the waveform 92 may be lower than the output valley level Vv1 of the waveform 90. Between time t3 and time t5, for the waveform 95 of the current Im1, it rises from the current level Il to the current level If, for the waveform 99 of the current Im4, it drops from the current level Ih2 to the current level Il2, the first control voltage va drops from the voltage level Vh to the voltage level Vl, the second control voltage va2 drops from the voltage level Vh2 to the voltage level Vl2, and the waveform 92 of the output voltage Vout rises from the output valley level Vv2 to a predetermined level Vprd. Compared with the related art, the waveform 90 of the output voltage Vout is returned to a predetermined level Vprd at time t4, and the waveform 92 of the output voltage Vout is returned to a predetermined level Vprd at time t5. Therefore, the embodiment of the present invention responds to changes in the load state faster than the related art.

[0051] FIG. 10 is a schematic circuit diagram of a voltage regulator 10 according to another embodiment of the present invention. The voltage regulator 10 is different from the voltage regulator 7 in that a current sink circuit 102 is used to replace the current sink circuit 72. The voltage regulator 10 operates in the same manner as the voltage regulator 7, and its description is omitted for simplicity. The current sink circuit 102 will be described in detail in the following paragraphs.

[0052] The current sink circuit 102 includes a transistor M4, a transistor M5, a capacitor Cc2, a resistor R1, and a resistor R2. The transistor M4 has a control terminal coupled to the second output terminal of the operational amplifier 70, a first terminal coupled to the second terminal of the transistor M1, a second terminal coupled to the ground terminal, and a bulk terminal. The first terminal of the transistor M4 supplies the output voltage Vout to the load terminal. The transistor M5 has a control terminal coupled to the second output terminal of the operational amplifier 70, a first terminal coupled to the bulk terminal of the transistor M4, a second terminal coupled to the ground terminal, and a bulk terminal coupled to the ground terminal. The capacitor Cc2 has a first terminal coupled to the first terminal of the transistor M4 and a second terminal coupled to the bulk terminal of the transistor M4 and the first terminal of the transistor M5. The resistor R2 has a first terminal coupled to the second terminal of the transistor M1 and the second terminal of the capacitor Cc, and a second terminal. The resistor R1 has a first terminal coupled to the second terminal of the resistor R2 and the second input terminal of the operational amplifier 70, and a second terminal coupled to the ground terminal. The first terminal of the resistor R1 may supply the feedback voltage Vfb to the operational amplifier 10. The feedback voltage Vfb is positively correlated with the output voltage Vout and may be lower than the output voltage Vout. In some embodiments, the resistor R1 and the resistor R2 may be implemented by transistors. The regulator gain of the voltage regulator 10 may be determined by Equation (3). The transistors M1 and M2 may be P-type MOSFETs, and the transistors M4 and M5 may be N-type MOSFETs.

[0053] Compared with the embodiments shown in FIGS. 1, 4, and 5, the voltage regulators 7 and 10 respond better to a sudden increase in the output voltage Vout by providing the transistor M4 in the current sink path.

[0054] FIG. 11 is a circuit schematic of an example of the operational amplifier 70 according to the embodiments shown in FIGS. 7 and 10. The operational amplifier 70 may include transistors M111 to M117. The transistors M111, M113, M114, and M116 may be P-type MOSFETs, and the transistors M112, M115, and M117 may be N-type MOSFETs.

[0055] The transistor M113 has a control terminal that receives a fixed bias voltage Vbias, a first terminal coupled to the supply terminal, and a second terminal. The transistor M111 has a control terminal, a first terminal coupled to the supply terminal, and a second terminal coupled to the control terminal of the transistor M111. The transistor M114 has a control terminal coupled to the first input terminal of the operational amplifier 70, a first terminal coupled to the second terminal of the transistor M113, and a second terminal. The transistor M116 has a control terminal coupled to the second input terminal of the operational amplifier 70, a first terminal coupled to the second terminal of the transistor M113, and a second terminal. The transistor M115 has a control terminal, a first terminal coupled to the control terminal of the transistor M115 and the second terminal of the transistor M114, and a second terminal coupled to the ground terminal. The transistor M117 has a control terminal, a first terminal coupled to the control terminal of the transistor M117 and the second terminal of the transistor M116, and a second terminal coupled to the ground terminal. The transistor M112 has a control terminal coupled to the control terminal of the transistor M115, a first terminal coupled to the second terminal of the transistor M111, and a second terminal coupled to the ground terminal.

[0056] Transistor M113 may function as a current source that receives a fixed bias voltage Vbias and generates a fixed drain current id. The drain current id of transistor M113 may be divided into a first current i1 passing through transistors M114 and M115 and a second current i2 passing through transistors M116 and M117. The operational amplifier 70 may receive a reference voltage Vref at the control terminal of transistor M114, receive a feedback voltage Vfb at the control terminal of transistor M116, output a first control voltage va at the second terminal of transistor M111, and output a second control voltage va2 at the control terminal of transistor M117. Transistors M115 and M112 may function as a current mirror. Transistor M111 may function as a current source. The sum of the first current i1 and the second current i2 is equal to the drain current id of transistor M113. When the feedback voltage Vfb decreases, the second current i2 generated by transistor M116 may decrease, resulting in an increase in the first current i1. The increase in the first current i1 may generate a decrease in the first control voltage va through transistors M115, M112, and M111, and the decrease in the second current i2 may be converted into a decrease in the second control voltage va2 through transistor M117. When the feedback voltage Vfb increases, the second current i2 generated by transistor M116 may increase, resulting in a decrease in the first current i1. The decrease in the first current i1 may generate an increase in the first control voltage va through transistors M115, M112, and M111, and the increase in the second current i2 may be converted into an increase in the second control voltage va2 through transistor M117.

[0057] The embodiments of FIGS. 7 and 10 provide a current source path and a current sink path to reduce the rise and fall of the output voltage Vout, and utilize transistors M2 and capacitor Cc to adjust the bulk voltage vb of transistor M1 in the current source path, and utilize transistors M5 and capacitor Cc2 to adjust the bulk voltage vb2 of transistor M4 in the current sink path to further speed up the circuit response and maintain the output voltage Vout at a substantially constant level.

[0058] Those skilled in the art will immediately understand that numerous modifications and changes to the apparatus and method may be made while maintaining the teachings of the present invention. Accordingly, the foregoing disclosure should be construed as being limited only by the appended claims.

Description of the Reference Numerals

[0059] 1 Voltage regulator 10 Operational amplifier 12 Current sink circuit

Claims

1. An operational amplifier having a first input terminal, a second input terminal, and an output terminal, wherein the output terminal outputs a control voltage according to an amplified differential voltage between the first input terminal and the second input terminal, and an operational amplifier; A first transistor having a control terminal coupled to the output terminal of the operational amplifier, a first terminal coupled to a supply terminal, a second terminal for supplying an output voltage to a load terminal, and a bulk terminal; A second transistor having a control terminal coupled to the output terminal of the operational amplifier, a first terminal coupled to the supply terminal, a second terminal coupled to the bulk terminal of the first transistor, and a bulk terminal coupled to the supply terminal; A first capacitor having a first terminal coupled to the bulk terminal of the first transistor and the second terminal of the second transistor, and a second terminal coupled to the second terminal of the first transistor; A current sink circuit coupled to the second terminal of the first transistor, the second terminal of the first capacitor, the second input terminal of the operational amplifier, and a ground terminal; A voltage regulator comprising the above.

2. The current sink circuit includes a resistor having a first terminal coupled to the second terminal of the first transistor, the second terminal of the first capacitor, and the second input terminal of the operational amplifier, and a second terminal coupled to the ground terminal. The voltage regulator according to claim 1.

3. The current sink circuit includes a third transistor having a first terminal coupled to the second terminal of the first transistor, the second terminal of the first capacitor, and the second input terminal of the operational amplifier, a second terminal coupled to the ground terminal, a control terminal for receiving a fixed bias voltage, and a bulk terminal. The voltage regulator according to claim 1.

4. The third transistor is an N-type metal oxide semiconductor field effect transistor (MOSFET). The voltage regulator according to claim 3.

5. The current sink circuit includes: A first resistor having a first terminal coupled to the second terminal of the first transistor and the second terminal of the first capacitor, and a second terminal; A resistor having a first terminal coupled to the second terminal of the first resistor and the second input terminal of the operational amplifier, and a second terminal coupled to the ground terminal; The voltage regulator according to claim 1, including the above.

6. The voltage regulator according to any one of claims 1 to 5, wherein the first transistor and the second transistor are P-type MOSFETs.

7. An operational amplifier having a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first output terminal outputs a first control voltage according to an amplified differential voltage between the first input terminal and the second input terminal, and the second output terminal outputs a second control voltage according to the amplified differential voltage between the first input terminal and the second input terminal; an operational amplifier A first transistor having a control terminal coupled to the first output terminal of the operational amplifier, a first terminal coupled to the supply terminal, a second terminal for supplying an output voltage to the load terminal, and a bulk terminal A second transistor having a control terminal coupled to the first output terminal of the operational amplifier, a first terminal coupled to the supply terminal, a second terminal coupled to the bulk terminal of the first transistor, and a bulk terminal coupled to the supply terminal A first capacitor having a first terminal coupled to the bulk terminal of the first transistor and the second terminal of the second transistor, and a second terminal coupled to the second terminal of the first transistor A current sink circuit coupled to the second terminal of the first transistor, the second terminal of the first capacitor, the second input terminal of the operational amplifier, the second output terminal of the operational amplifier, and the ground terminal A voltage regulator comprising:

8. The current sink circuit includes: A third transistor having a control terminal coupled to the second output terminal of the operational amplifier, a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to the ground terminal, and a bulk terminal, wherein the first terminal of the third transistor supplies the output voltage to the load terminal; a third transistor A fourth transistor having a control terminal coupled to the second output terminal of the operational amplifier, a first terminal coupled to the bulk terminal of the third transistor, a second terminal coupled to the ground terminal, and a bulk terminal coupled to the ground terminal A second capacitor having a first terminal coupled to the first terminal of the third transistor and a second terminal coupled to the bulk terminal of the third transistor and the first terminal of the fourth transistor Including The second terminal of the first transistor and the first terminal of the third transistor supply a feedback voltage to the second input terminal of the operational amplifier. The voltage regulator according to claim 7.

9. The current sink circuit A third transistor having a control terminal coupled to the second output terminal of the operational amplifier, a first terminal coupled to the second terminal of the first transistor, a second terminal coupled to a ground terminal, and a bulk terminal, wherein the first terminal of the third transistor supplies the output voltage to the load terminal; a third transistor A fourth transistor having a control terminal coupled to the second output terminal of the operational amplifier, a first terminal coupled to the bulk terminal of the third transistor, a second terminal coupled to the ground terminal, and a bulk terminal coupled to the ground terminal A second capacitor having a first terminal coupled to the first terminal of the third transistor and a second terminal coupled to the bulk terminal of the third transistor and the first terminal of the fourth transistor A first resistor having a first terminal coupled to the second terminal of the first transistor and the second terminal of the first capacitor and a second terminal A second resistor having a first terminal coupled to the second terminal of the first resistor and the second input terminal of the operational amplifier and a second terminal coupled to the ground terminal The voltage regulator according to claim 7, comprising

10. The first transistor and the second transistor are P-type MOSFETs, and the third transistor and the fourth transistor are N-type MOSFETs. The voltage regulator according to claim 8 or 9.

11. The first input terminal of the operational amplifier is an inverting input terminal, and the second input terminal of the operational amplifier is a non-inverting input terminal. The voltage regulator according to any one of claims 1 to 10.

12. The first input terminal of the operational amplifier receives a fixed reference voltage. The voltage regulator according to any one of claims 1 to 11.

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