Automatic Increment Write Count for Non-Volatile Memory

Abstract

To provide a method of tracking metadata for a nonvolatile memory device.SOLUTION: In a system 100, a memory device 110 has multiple nonvolatile (NV) memory arrays that collectively store a block of data, with each array storing a portion of the data block. A selected NV memory array stores a write count for the block of data. In response to a write command, the NV memory arrays that store data perform an internal pre-write read. The selected NV memory array that stores the write count will perform a pre-write read of the write count, increment the write count internally to the selected NV memory array, and write the incremented write count back to the selected NV memory array.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The description generally relates to non-volatile memory devices, and more specifically to tracking metadata for non-volatile memory devices.

Background Art

[0002] Non-volatile (NV) memory devices have limited write durability. NV memory refers to memory whose state is indeterminate when power to the device is cut off. Write durability refers to the number of times data can be written to the medium before reliability is lost. In addition, the medium is subject to write disturb. Write disturb is when repeated access to a target memory address causes an unintended change in the value at an adjacent victim address. State That is.

[0003] Due to potential problems related to the number of writes, the system determines how often to perform data refresh and data movement to manage cell durability and write disturb, based on the number of writes Track to do. The conventional approach to write tracking is write tracking per block. Each time data is written to a block, the system accesses the write count and increments the write count. In a system where the write count is stored in the non-volatile medium itself, access requires reading the data That before the block is written. Conventionally, the media controller Is , That reads the data And , After incrementing the data, and writes it back to the medium along with the user data And already Do . This operation reduces the effective write bandwidth of the system.

Brief Description of the Drawings

[0004] The following description includes discussions of figures with illustrations provided as examples of implementations. The drawings should be understood as examples and not as limitations. As used herein, references to one or more examples are to be understood as descriptions of specific features, structures, or characteristics included in at least one implementation of the present invention. Phrases such as "in one example" or "in an alternative example" that appear herein provide examples of implementations of the present invention and do not necessarily all refer to the same implementation. However, they are not necessarily mutually exclusive either.

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[0012] Specific details and implementations will be described below. The description includes a non-limiting description of diagrams that may illustrate some or all of the examples and other potential implementations.

DETAILED DESCRIPTION OF THE INVENTION

[0013] As described herein, the system tracks the number of writes to non-volatile (NV) memory by storing metadata in one of a plurality of NV memory arrays. In In one example, the NV memory is a memory device having a three-dimensional cross-point (3DXP) storage medium. Multiple The NV memory arrays store data blocks together. Each array stores a portion of the data blocks One section To stores, and the selected array If stores the write count of the data blocks. For The system may use the write count to determine how often to perform data refresh or data movement to manage cell durability and write disturb.

[0014] The write procedures for certain NV memory technologies take a relatively long time and consume a lot of power. To manage energy usage and write latency, in one example, the NV memory writes only the bits that are changed during the write. For The NV memory can issue an internal read operation in response to a write command. Purposefully The internal This read can be referred to as " Purposeful " or " Prefetch (pre - read) ". Through the internal Preliminary read (read before writing) read, the memory device Purposeful reads the contents of the memory cells, compares the existing data with the input data, and changes Its own the Have beenOnly bits can be written.

[0015] The selected NV memory array that stores the write count reads its content including the write count internally. Purposeful The selected NV memory array executes a read. Co to the controller Book the write count To increment automatically increments the write count internally without transmitting it to the controller. The selected NV memory array can write back the incremented write count to its bit cells. In one example, the selected NV memory array writes back the write count along with user data to other NV memory arrays. The automatic increment can eliminate the need for the controller to read and increment the write count. The involvement of the controller Should with the automatic increment can Disappear by the automatic increment For each write cycle of the NV medium, the controller By to the NV medium Generate perform At least the read cycles can be saved .

[0016] In one example, the selected NV memory array that stores the write count may include an internal write count threshold. This The NV memory array Is increments the write count When and This NV memory array compares the write count with the threshold and, if the write count has reached the write count threshold, can also send or pass an alert to the controller. Case

[0017] In one example, the selected NV memory array executes an automatic increment in response to a mode selection within the memory device. The mode generally refers to operations executed based on configuration settings, and different operations are performed in response to the same situation based on different configurations. Thus, for example, the selected NV memory array Of mode Of selection To ​Prefetch Operation Together with may be configured to perform an automatic increment, and other Multiple NV memory arrays perform an automatic increment Without simply Prefetch is configured to perform an operation. In one example, in this mode, the automatic increment hardware available in each NV memory array is enabled.

[0018] FIG. 1 is a block diagram of an example of a system having a selected memory array that stores a write count and performs an automatic increment on the write count. System 100 represents a memory system or a memory device. System 100 includes a plurality of memory devices 110 identified as devices [0:10]. Having 11 devices is an example, and it will be understood that other systems may have more or fewer devices. Each device shown may include one or more memory devices.

[0019] In one example, Multiple device 110 represents the system 100 Of separate Multiple NV memory arrays. In one example, the memory array may include 3DXP media. In one example, the memory array may include other NV storage media. In one example, each device 110 includes a plurality of arrays. In one example, each device 110 represents a separate NV memory array. In one example, each device 110 represents a separate NV memory chip or memory die. The number of devices 110 within system 100 is determined by the storage capacity of system 100, the internal architecture, and other factors. In one example, each device 110 represents a separate media die. In one example, each device 110 represents a separate media device.

[0020] In one example, system 100 represents an NV storage device, such as a storage module like an NV dual in-line memory module (DIMM). In one example, system 100 is a device such as a solid state drive (SSD), or a part of such a device. In one example, controller 120 represents a media controller for system 100. A media controller represents a control device for controlling access to a storage medium of system 100. From the perspective of the host system in which system 100 is integrated Looking at , Multiple device 110 only appears to be available storage. Controller 120 as a media controller manages a specific device 、 data address Access to , internal command And operations for executing host commands 、 adherence to timing And and other management of access to device 110. In one example, it is as follows.

[0021] System 100 indicates device [0:7] as storing data 130. Data 130 represents user data, or data created by a related host and stored in system 100. In one example, device [8:9] stores ECC132 representing error checking and correction (ECC) data for data 130. In one example, device 10 stores ECC132 and metadata (MD) 134. Thus, device 10 can store not only ECC data for use with ECC132, but also have additional metadata for management of access to device 110. In one example, additional metadata 134 includes a write count for tracking the number of writes to block 112. Block 112 can include data 130, ECC132, and MD134. From block 112, multiple Device 110 Is stores data blocks together Manage to be understood.

[0022] Channel 140 represents a communication channel between the controller 120 and the device 110. In one example, channel 140 may be referred to as a 3DXP channel. Through channel 140, the controller 120 can communicate with the device 110. Channel 140 may include a control signal line or a command signal line and a data signal line.

[0023] In one example, when the system 100 receives a write operation or a write command from a host, the controller 120 Data causes the vice 110 to execute a write command Commands or controls for processing may be generated within system 100 . The command includes an address and data to be written. The controller 120 decodes the command and identifies block 112 as the address of the data to be written. Identify In one example, the controller 120 generates ECC data for writing together with the data received from the host. In one example, devices [0:7] receive multiple bytes of data to be written to data 130, and the controller 120 provides ECC132 to devices [8:10]. In one example, the controller 120 does not provide a write count to device 10. If the metadata 134 includes information other than the write count, the controller 120 provides such metadata to device 10 Would be .

[0024] In one example, block 112 Complex can be regarded as having codewords written across a number of devices 110. Represented by data 130 In one example, device 10 Memory tracks the write count in the tadata Specialized for and is the selected device. In one example, the controller 120 identifies the location of each device 110 and selects one device for tracking metadata. The system 100 indicates device 10 as the selected array for storing the metadata 134. In one example, the controller 120 provides To configuration settings for each device 110 Make it so, in this configuration setting,Device 110 Is is enabled as a selected array for performing automatic increment of the write count. Thus, depending on the configuration settings, the automatic increment of the selected memory array can be selectively enabled or disabled.

[0025] In one example, for all code writes, or writes of code words, Multiple Device 110 first reads their Devices respective data contents. Preliminary read of As part of As an example, in one case, Device 10 reads the write count and increments the write count for write-back to Device 10 The In one example, Device 10 places the incremented write count on the data bus along with the other data to be written Ku .

[0026] Conventionally, the logic for tracking the write count would be included in Controller 120. In one example, Device 10 includes logic for tracking the write count. In one example, the logic is enabled when Device 10 is in the automatic increment mode. In one example, Controller 120 Data relates to the settings of Device 10 To the automatic increment mode to set a write count threshold (e.g., a value in a register).

[0027] In one example, the block size of Block 112 can be 64 bytes, 128 bytes, 256 bytes, or some other number of bytes for 3DXP media. NAND (not AND) flash typically has a larger block size such as 4K bytes or 2K bytes. Managing the write count of blocks can have a higher positive performance impact on systems with smaller block sizes. More

[0028] ​FIG. 2 is a block diagram of a system having a selected memory array that performs an automatic increment on write count metadata. System 200 provides an example of a system according to system 100 of FIG. 1. Storage 250 may represent an example of system 100. Controller 252 is an example of controller 120 of system 100.

[0029] System 200 includes a host 210 having a memory controller 220 coupled to a storage 250. Host 210 represents a computing platform to which storage 250 is coupled. For example, host 210 can be or include a computer or other computing device. Memory controller 220 represents a controller for managing access to a memory device 230. In one example, memory controller 220 is part of a host processor (not specifically shown) of host 210. Memory controller 220 can alternatively be considered a storage controller depending on the connection of storage 250.

[0030] In one example, the non-volatile memory of memory device 230 can be coupled to a storage bus such as a Peripheral Component Interconnect Express (PCIe) bus. In one example, the non-volatile memory of memory device 230 is non-volatile, but also byte-addressable and random-accessible, and can be coupled to a system memory bus such as a Double Data Rate (DDR) memory bus. Host 210 includes an I / O (input / output) interface 212. I / O 212 represents hardware for interfacing with storage 250. I / O 212 can include an interface to a command bus or a command and address bus as well as a data bus. In one example, the interface includes other signal lines such as signal lines for memory device 230 to send an alert to host 210.

[0031] Memory device 230 is shown to have I / O 240 representing I / O for the memory device. Controller 252, although not shown specifically, is understood to include I / O hardware and I / O firmware for receiving commands, exchanging data with host 210, and interfacing with memory device 230. I / O 240 includes command (CMD) 242 representing an interface to a command bus or a CA bus. Data 244 represents an interface to a data bus or a DQ bus. In one example, I / O 240 includes alert 246 representing an interface to one or more signal lines for the memory device 230 to send an alert to host 210. For example, when memory device 230 is a selected device for managing the write count of the memory device, alert 246 enables the selected device to send an alert in response to the write count reaching a threshold. To include Memory controller 220 includes scheduler 222 for managing the scheduling and transmission of a series of commands to storage 250. Scheduler 222 includes logic for determining the order and timing requirements of the commands. Memory controller 220 makes a decision about which commands to send in which order. By determining the order of the commands, scheduler 222 ensures compliance with the timing requirements. A group of of the memory device For In one example, host 210 receives an alert from memory device 230 indicating that a data block has reached the write threshold. In one example, in response to an alert flag, memory controller 220 may read one or more registers of memory device 230 to identify the alert. In response to the alert, in one example, memory controller 220 issues a command to trigger a refresh

[0032] operation.

[0033] In one example, A certain data block Regarding In one example, in response to an alert flag, memory controller 220 may read one or more registers of memory device 230 to identify the alert. In response to the alert, in one example, memory controller 220 issues a command to trigger a refresh Or movement to different storage locations of data (e.g., different addresses in storage), etc. operation.To Transmission Do Determine whether to do so. If the memory controller 220 determines to execute an operation in response to an alert, the scheduler 222 may schedule a command to be sent to the storage 250.

[0034] The memory controller 220 includes command logic 224 for generating a command to be sent to the memory device 230. The command may include a write command or a read command. The memory controller 220 sends a read command to a command bus, which may also be referred to as a command and address bus, and after a delay period, the memory device 230 drives data on the data bus. In one example, the command logic 224 may send a refresh command or a command to move data to a different location.

[0035] The storage 250 includes a plurality of memory devices 230. The memory device 230 includes a memory array 232 representing an array of non-volatile memory cells or storage cells. The memory cells store 1-bit of data or multiple bits for multi-level cells. In one example, the array 232 is divided as a bank of memory or other subset of memory. In one example, the memory device 230 is part of a group of memory devices where one or more memory devices are organized as a rank of memory. A rank of memory is a group of memory resources that are accessed in parallel because they share a chip select signal or an enable signal.

[0036] In one example, the array 232 includes non-volatile memory cells. Non-volatile (NV) memory maintains its state even when power is removed from the memory. Volatile memory becomes in an indeterminate state when power is removed from the memory. In one example, the NV medium of the array 232 is a 3DXP medium.

[0037] System 200 includes a controller 252 representing a media controller for storage 250 representing a memory or storage module. In one example, controller 252 receives commands and data from host 210 And , Memory and determines internal commands to be sent to the memory device Make it so that the memory device will respond to internal commands . Also, controller 252 can send certain portions of data to a specific memory device 230. Also, system 200 shows a controller 234 of memory device 230. Controller 234 represents the logic in the memory device for receiving and decoding commands and can drive the circuitry that needs to respond to the commands.

[0038] Memory device 230 Related to the operation of memory device 230 includes one or more registers or storage locations, represented by register 236, for storing configuration information or Value . In one example, register 236 includes one or more mode registers. In one example, register 236 includes configuration information for controlling the write count auto-increment mode of memory device 230.

[0039] In one example, memory device 230 includes a scratch pad 262 representing a temporary storage location that the memory device 230 uses for internal operations. In one example, memory device 230 responds to a write command by Prefetch executing an operation. Prefetch The operation can include reading the contents of an address in array 232 and comparing it with the A certain buffered copy of the data to be written Should . The write buffer, although not specifically shown, provides a And temporary buffer for data exchanged with array 232. In one example, the buffer For continues in a data path for exchanging data between array 232 and the data bus Is in terms of Connect continuing In ,The buffer Data bus To It can be considered to be in-line.

[0040] In one example, as a result of the comparison, a result that can be stored in the scratch pad 262 is generated. The scratch pad 262 represents storage for internal operations that are not sent to the controller 252. The auto-increment circuit 264 increments a value and The incremented value Write-back to the memory array Should be with user data and ECC data Connect combines Straighten represents hardware for enabling auto-increment, such as a logic circuit for performing the above and other operations. In one example, the auto-increment circuit 264 can be dynamically enabled and disabled based on the configuration of the memory device 230. That is, when the memory device 230 is configured as the selected write count array, the auto-increment circuit 264 can be enabled to perform an auto-increment operation on the write count.

[0041] FIG. 3 is a block diagram of an implementation for performing auto-increment on write count metadata. Diagram 300 represents a flow that can be implemented by a system related to the non-volatile memory system being described.

[0042] In one example, the controller represents a media controller and 3DXP represents an NV memory device. The central column represents operations performed by all 3DXP or all memory arrays or memory devices. The right column represents operations performed by the selected 3DXP device.

[0043] The controller includes a write command and The of the write command ForGenerate an address (ADDR) (block 310). In one example, in response to a write command, all 3DXP devices decode the address of the command (block 320). After sending the command, the controller sends data on the DQ bus Above after an appropriate delay (block 312). The delay is a write delay defined for the 3DXP media.

[0044] In one example, in response to To decoding Done the command, all 3DXP devices Itself retrieve the current data content of Prefetch (block 322). These The 3DXP device Prefetch compares the retrieved data with D data on the DQ bus Received on (block 324).

[0045] One of the 3DXP devices is selected as the selected 3DXP device for managing the write count Are . In one example, the selected 3DXP device is configured to enter an auto-increment mode. Such a mode can be configured, in one example, by setting a register or configuration bit. For example, the configuration field or bit can be auto-increment = 0 for non-selected 3DXP devices and auto-increment = 1 for the selected device.

[0046] In one example, the selected 3DXP device increments the write count (block 330). In one example, the selected 3DXP device compares the current write count (WR_CNT) with the incremented write count (WR_CNT + 1) (block 332). In one example, in addition to the write count, the selected 3DXP device stores ECC data or user data. Thus, the selected 3DXP device Prefetched compares the data with the DQ bus OnIt is possible to perform a comparison with data.

[0047] In one example, for a selected 3DXP device, the automatic increment write count mode is enabled. This means that the system can ignore a specific N bytes (e.g., 2 bytes or 3 bytes) of the DQ bus for write commands. Thus, for example, in one instance Multiple the 3DXP device can collectively perform a comparison of PRE_RD[15:3] and DQ_BUS[15:3]. PRE_RD[15:3] is Multiple 14 bytes of data read from the memory array of the 3DXP device (which may include data from the selected 3DXP device), and DQ_BUS[15:3] represents 14 bytes of data received from the host. The Last 3 bytes of the DQ bus can be ignored. The selected 3DXP device can perform a comparison of PRE_RD[2:0] and (PRE_RD[2:0] + 1). PRE_RD[2:0] represents write count metadata, and (PRE_RD[2:0] + 1) represents the incremented write count.

[0048] In one example, the 3DXP device writes only the data that is changed in response to a write command. In one example, for the comparison of user data, ECC data, or write count metadata For any of them the 3DXP device Data - data onto the bus Back For example, 3DXP the device Data - the comparison result of the data to the inverted Are bits Regarding comparison To write can be placed into the write buffer. In one example, the 3DXP device writes only the inverted Are bits (block 326).

[0049] In one example, the selected 3DXP device compares the incremented write count (WR_CNT+1) to a threshold count (WR_CNT_MAX) (block 334). In one example, if the threshold is reached, the 3DXP device alerts the host (block 336). In one example, the media controller sets the threshold or write count limit via a configuration register (such as a mode register). Thus, if the count reaches the threshold, the selected 3DXP device can set a flag or other alert. In response to the alert, the media controller can take appropriate action in response to the write count reaching the threshold (block 338).

[0050] FIG. 4 is a flowchart of an example of a process for automatic increment of a write count. The process 400 for automatic increment of a write count can be performed by an example of a system according to the system 100 of FIG. 1 or the system 200 of FIG. 2.

[0051] In one example, at 402, a non-volatile memory device, such as a 3DXP device, receives a configuration command from a host controller. If the NV memory device is selected to store a write count, the configuration command can configure the NV memory device to perform an automatic increment.

[0052] If the configuration command enables automatic increment at the YES branch of 404, in one example, at 406, Configuration the command configures the selected device to manage the write count. If the configuration command does not enable automatic increment at the NO branch of 404, the device is not selected to manage the write count. If the device does not manage write count metadata, in one example, at 408, The the configuration disables the automatic increment circuit on the device. That is , all devices may include an automatic increment circuit 、 one selected device Is, has an enabled function, and other devices have a disabled function.

[0053] Regardless of which configuration is set for the memory device, the memory device can be prepared to receive an access command. In response to receiving a write command at 410, or in response to the reception of the command, in one example, at 412, the memory device stores them at the address associated with the write command Memory device for the data that Prefetch it has already stored.

[0054] In the case of multiple memory devices, there is one device selected to manage the write count. Therefore, Standard for the standard operation Typical cases are , one device will have other operations for managing the write count. In one example, When auto - increment is not enabled, In the case of 414 NO branches, 416 In , the memory device The prefetched data compares with the data For receiving believed in the write command.

[0055] In one example, the memory device executes a comparison between the current data content ( Prefetch the data written) and the data to be written 。 because Memory the device only writes the deltas or bits that are inverted due to the write command. Therefore, in one example, Will be each memory device determines for each bit of the data to be written Multiple whether the Should bit is inverted. In the NO branch of 418 Bit if the bit is not inverted, in one example, at 420, the device Bit does not execute the write of the bit. Unchanged

[0056] Bit In the YES branch of 418 BitWhen the bit is inverted, in one example, at 422, Memory the device inverts the bit on the data bus. Thus, the device can place the result of the comparison on the data bus for writing to the memory array. In one example, Prefetched the data is placed on the data bus Not and is used only for comparison, In this case, what should be written the result Is , Data is placed on the data bus. Once the data on the data bus To is set, at 424, Memory the device The writes the data to the array.

[0057] For a device storing a write count, on the YES branch of 414, auto - increment is enabled. In one example, at 426, the selected device increments the write count and compares the incremented write count to a threshold. The threshold can be a threshold for indicating the risk of write disturb, Lifecycle a threshold for indicating the end of or some other threshold. In one example, The the device compares the incremented value to multiple different thresholds.

[0058] On the YES branch of 428, if one or more thresholds are reached, in one example, at 430, the device sends an alert to the host. In one example, when multiple thresholds are compared, the device can send different alerts for different thresholds. In one example, the device sends a single alert and the host queries the device Source to determine For whether the threshold has been reached. Regardless of whether the threshold has been reached, in one example, after incrementing the write count, at 432, the device can load the incremented write count for write - back to the array. For the selected device, for comparison of inverted bits, write The write count can be Prefetched considered as data 、 The incremented write count is from the DQ bus Is a substitute for the write data。The process returns to 416.

[0059] Figure 5 is a block diagram of an example of a memory subsystem in which write count automatic increment can be implemented. System 500 includes a processor and elements of a memory subsystem within a computing device. System 500 provides an example of a system according to system 100 of FIG. 1 or system 200 of FIG. 2.

[0060] In one example, system 500 includes automatic increment logic 590 within memory device 540. In one example, memory device 540 is a memory block according to any example herein. Regarding It can be selected from a plurality of memory devices of memory module 570 for managing block write counts. In one example, memory device 540 stores write count metadata in memory array 560. In one example, register 544 includes a field that is written to determine whether memory device 540 is the selected memory device for managing write counts. In one example, automatic increment logic 590 includes hardware for performing automatic increment of the write count.

[0061] The processor 510 represents the processing unit of a computing platform capable of executing an operating system (OS) and applications, and the processing unit can be generically referred to as the host or user of the memory. The OS and applications execute operations that result in memory access. The processor 510 can include one or more distinct processors. Each of the distinct processors can include a single processing unit, a multi-core processing unit, or a combination thereof. The processing unit can be a primary processor such as a CPU (central processing unit), a peripheral processor such as a GPU (graphics processing unit), or a combination thereof. Memory access can also be initiated by a device such as a network controller or a hard disk controller. Such a device can be integrated with processors within some systems, attached to the processors, or a combination thereof via a bus (e.g., PCI Express). The system 500 can be implemented as a SoC (system on chip) or implemented with stand-alone components.

[0062] In one example, a reference to a memory device may refer to a non-volatile memory device whose state is determined even when power is cut off from the device. In one example, the non-volatile memory device is a block-addressable memory device such as NAND technology or NOR technology. Thus, the memory device may also include next-generation non-volatile devices such as three-dimensional cross-point memory devices, other byte-addressable non-volatile memory devices, etc. The memory device may include a non-volatile byte-addressable medium that stores data based on the resistance state or phase of the memory cells. In one example, the memory device may use a chalcogenide phase change material (e.g., chalcogenide glass). In one example, the memory device is a multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM) or phase change memory with switch (PCM), resistive memory, nanowire memory, ferroelectric transistor random access memory (FeTRAM), magnetic resistive random access memory incorporating memristor technology (MRAM) or spin transfer torque (STT) MRAM or any combination of the above or other memories, or may include them.

[0063] Memory controller 520 represents one or more memory controller circuits or devices for system 500. Memory controller 520 represents control logic that generates memory access commands in response to execution of operations by processor 510. Memory controller 520 accesses one or more memory devices 540. Memory device 540 can be a DRAM device related to any of those mentioned above. In one example, memory devices 540 are organized and managed as different channels. Each channel couples to a bus and signal lines that couple to multiple memory devices in parallel. Each channel is operable independently. Thus, each channel is accessed and controlled independently, and timing, data transfer, command and address exchange, and other operations are separate for each channel. The coupling can refer to an electrical coupling, a communication coupling, a physical coupling, or a combination thereof. The physical coupling can include direct contact. The electrical coupling includes an interface or interconnection that enables electricity to flow between components, enables signaling between components, or enables both. The communication coupling includes a connection that enables components to exchange data, including wired or wireless.

[0064] In one example, the settings of each channel are controlled by separate mode registers or other register settings. In one example, while each memory controller 520 manages a separate memory channel, system 500 can be configured to have multiple channels managed by a single controller or multiple controllers on a single channel. In one example, memory controller 520 is part of host processor or host processor device 510, such as logic implemented on the same die or implemented in the same package space as the processor.

[0065] Memory controller 520 includes I / O interface logic 522 coupled to a memory bus such as the memory channel mentioned above. I / O interface logic 522 (and I / O interface logic 542 of memory device 540) may include pins, pads, connectors, signal lines, traces or wires, or other hardware connected to the device, or combinations thereof. I / O interface logic 522 may include a hardware interface. As shown, I / O interface logic 522 includes at least a driver / transceiver for signal lines. Generally, wires within an integrated circuit interface couple to pads, pins or connectors to interface with signal lines or traces or other wires between devices. I / O interface logic 522 may include drivers, receivers, transceivers or terminations or other circuits or combinations of circuits for exchanging signals on signal lines between devices. The exchange of signals includes at least one of transmission or reception. Although shown coupling I / O 522 from memory controller 520 to I / O 542 of memory device 540, it will be understood that in an implementation of system 500 where a group of memory devices 540 are accessed in parallel, multiple memory devices may include an I / O interface to the same interface of memory controller 520. The implementation of system 500 includes one or more memory modules 570. I / O 542 may include interface hardware of the memory module in addition to the interface hardware on the memory device itself. Other memory controllers 520 include separate interfaces to other memory devices 540.

[0066] The bus between the memory controller 520 and the memory device 540 may be implemented as a plurality of signal lines coupling the memory controller 520 to the memory device 540. The bus typically includes at least a clock (CLK) 532, a command / address (CMD) 534, and write data (DQ) and read data (DQ) 536, as well as zero or more other signal lines 538. In one example, the bus or connection between the memory controller 520 and the memory may be referred to as a memory bus. In one example, the memory bus is a multi-drop bus. The signal line for CMD may be referred to as a "C / A bus" (or ADD / CMD bus, or some other symbol designation indicating the transfer of command (C or CMD) and address (A or ADD) information), and the signal lines for write and read DQ may be referred to as a "data bus". In one example, an independent channel has a different clock signal, C / A bus, data bus, and other signal lines. Thus, the system 500 may be considered to have a plurality of "buses" in the sense that independent interface paths may be considered separate buses. In addition to the explicitly shown lines, it will be understood that the bus may include at least one of strobe signaling lines, alert lines, auxiliary lines, or other signal lines, or combinations thereof. It will also be understood that serial bus technology may be used for the connection between the memory controller 520 and the memory device 540. An example of serial bus technology is 8B10B encoding and high-speed data transmission with an embedded clock via a single differential pair of signals in each direction. In one example, CMD 534 represents a signal line shared in parallel with a plurality of memory devices. In one example, a plurality of memory devices share the encoded command signal line of CMD 534, each having a separate chip select (CS_n) signal line for selecting an individual memory device.

[0067] In an example of system 500, it will be appreciated that the bus between memory controller 520 and memory device 540 includes an auxiliary command bus CMD534 and an auxiliary bus DQ536 for transmitting write data and read data. In one example, the data bus may include bidirectional lines for read data and write / command data. In another example, the auxiliary bus DQ536 may include unidirectional write signal lines for writes from the host to the memory and for data, and may include unidirectional lines for read data from the memory to the host. Depending on the selected memory technology and system design, other signals 538 may be associated with a bus or sub-bus such as a strobe line DQ. Based on the design of system 500, or an implementation if a design supports multiple implementations, the data bus may have some bandwidth per memory device 540. For example, the data bus can support memory devices having any of an x4 interface, an x8 interface, an x16 interface or other interfaces. The W in the specification "xW" is an integer indicating the interface size or width of the interface of memory device 540, and represents the number of signal lines for exchanging data with memory controller 520. The interface size of a memory device is a control factor regarding how many memory devices can be used simultaneously per channel within system 500, or can be coupled in parallel to the same signal lines. In one example, high bandwidth memory devices, wide interface devices or stacked memory configurations or combinations thereof can enable wider interfaces such as an x128 interface, an x256 interface, an x512 interface, an x1024 interface or other data bus interface widths.

[0068] In one example, the memory device 540 and the memory controller 520 exchange data via a data bus in bursts or in a series of consecutive data transfers. A burst corresponds to the number of transfer cycles related to the bus frequency. In one example, a transfer cycle can be all clock cycles of a transfer that occur at the same clock or strobe signal edge (e.g., rising edge). In one example, all clock cycles referring to the cycles of the system clock are divided into a plurality of unit intervals (UI). Each UI is a transfer cycle. For example, double data rate transfer is triggered at both edges of the clock signal (e.g., rising and falling). A burst can continue over a configured number of UIs. This can be a configuration stored in a register or a configuration triggered on the fly. For example, a series of eight consecutive transfer periods can be considered a burst length 8 (BL8), and each memory device 540 can transfer data at each UI. Thus, an x8 memory device operating at BL8 can transfer 54 bits of data (8 data signal lines × 8 data bits transferred per line via the burst). It will be understood that this simple example is illustrative only and not limiting.

[0069] Memory device 540 represents the memory resources for system 500. In one example, each memory device 540 is a separate memory die. In one example, each memory device 540 can be an interface having multiple (e.g., two) channels per device or die. Each memory device 540 includes I / O interface logic 542 having a bandwidth determined by the device implementation (e.g., x16 or x8 or some other interface bandwidth). The I / O interface logic 542 enables the memory device to interface with the memory controller 520. The I / O interface logic 542 can include a hardware interface and can respond to the I / O 522 of the memory controller, but at the memory device end. In one example, multiple memory devices 540 are connected in parallel to the same command and data buses. In another example, multiple memory devices 540 are connected in parallel to the same command bus and to different data buses. For example, system 500 can be configured using multiple memory devices 540 coupled in parallel. Each memory device responds to commands and accesses each internal memory resource 560. In the case of a write operation, an individual memory device 540 can write a portion of the entire data word, and in the case of a read operation, an individual memory device 540 can fetch a portion of the entire data word. The remaining bits of the word are provided or received in parallel by other memory devices.

[0070] In one example, the memory device 540 is placed directly on the motherboard of the computing device or on the host system platform (e.g., the printed circuit board (PCB) on which the processor 510 is located). In one example, the memory device 540 can be organized into a memory module 570. In one example, the memory module 570 represents a dual in-line memory module (DIMM). In one example, the memory module 570 represents another organization of multiple memory devices for sharing at least a portion of the access or control circuitry. The circuitry can be a separate circuit, a separate device, or a separate substrate from the host system platform. The memory module 570 can include multiple memory devices 540 and can include support for multiple separate channels to the included memory devices disposed thereon. In another example, the memory device 540 can be incorporated into the same package as the memory controller 520 by techniques such as, for example, a multi-chip module (MCM), a package-on-package, a through-silicon via (TSV), or other techniques or combinations thereof. Similarly, in one example, multiple memory devices 540 can be incorporated into a memory module 570. They themselves can be incorporated into the same package as the memory controller 520. It will be appreciated that in these and other implementations, the memory controller 520 can be part of the host processor 510.

[0071] Each memory device 540 includes one or more memory arrays 560. The memory array 560 represents an addressable memory location or a storage location for data. Typically, the memory array 560 is managed as rows of data and is accessed through the control of word lines (rows) and bit lines (individual bits within a row). The memory array 560 can be organized as separate channels, ranks, banks, and partitions of memory. A channel can refer to an independent control path to a storage location within the memory device 540. A rank can refer to a common location (e.g., the same row address in different devices) across multiple memory devices arranged in parallel. A bank can refer to a sub-array of memory locations within the memory device 540. In one example, a bank of memory is divided into sub-banks having at least a portion of the shared circuitry (e.g., drivers, signal lines, control logic) for the sub-banks. This allows for separate addressing and access. It will be understood that channels, ranks, banks, sub-banks, bank groups, or other organizations of memory locations, and combinations of such organizations, can overlap in their application to those physical resources. For example, the same physical memory location can be accessed through a particular channel as a particular bank that may also belong to a rank. Thus, the organization of memory resources is to be understood inclusively rather than exclusively.

[0072] In one example, the memory device 540 includes one or more registers 544. The registers 544 represent one or more storage devices or storage locations that provide configurations or settings for the operation of the memory device. In one example, the registers 544 can provide storage locations in the memory device 540 for storing data accessed by the memory controller 520 as part of a control operation or a management operation. In one example, the registers 544 include one or more mode registers. In one example, the registers 544 include one or more general-purpose registers. Depending on the configuration of the locations within the registers 544, the memory device 540 can be configured to operate in different "modes". Different operations within the memory device 540 can be triggered based on the mode, by command information. Additionally, or alternatively, different operations can also be triggered from address information or other signal lines, depending on the mode, by different modes. The settings of the registers 544 can indicate a configuration of I / O settings (e.g., timing, termination, or ODT (on-die termination) 546, driver configuration, or other I / O settings).

[0073] In one example, the memory device 540 includes an ODT 546 as part of the interface hardware associated with the I / O 542. The ODT 546 can be configured as described above and can provide impedance settings applied to the interface to a specified signal line. In one example, the ODT 546 is applied to the DQ signal line. In one example, the ODT 546 is applied to the command signal line. In one example, the ODT 546 is applied to the address signal line. In one example, the ODT 546 can be applied to any combination of the foregoing. The ODT setting can be changed based on whether the memory device is the selected target of an access operation or a non-target device. The ODT 546 setting can affect the timing and reflection of signaling on the termination line. Careful control of the ODT 546 can enable faster operation with improved impedance and load matching. The ODT 546 can be applied to specific signal lines of the I / O interfaces 542, 522 (e.g., ODT for DQ lines or ODT for CA lines), but not necessarily to all signal lines.

[0074] Memory device 540 includes a controller 550 that represents control logic within the memory device for controlling internal operations within the memory device. For example, controller 550 decodes commands sent by memory controller 520 and generates internal operations to execute or satisfy the commands. Controller 550 may be referred to as an internal controller and is separate from host's memory controller 520. Controller 550 can determine which mode is selected based on register 544 and can configure the execution of operations for accessing memory resources 560 or other operations internally based on the selected mode. Controller 550 generates control signals for controlling the routing of bits within memory device 540 to provide an appropriate interface for the selected mode and send commands to appropriate memory locations or addresses. Controller 550 includes command logic 552 that can decode command encodings received on command signal lines and address signal lines. Thus, command logic 552 can be or can include a command decoder. By using command logic 552, the memory device can identify commands and generate internal operations to execute the requested commands.

[0075] Referring back to the memory controller 520, the memory controller 520 includes command (CMD) logic 524 that represents logic or circuitry for generating commands to be sent to the memory device 540. The generation of commands can refer to preparing commands before scheduling or commands queued for transmission. Generally, signaling within the memory subsystem includes address information within or associated with a command for the memory device to indicate or select one or more memory locations at which to execute the command. In response to scheduling of a transaction of the memory device 540, the memory controller 520 can issue a command via I / O 522 to cause the memory device 540 to execute the command. In one example, a controller 550 of the memory device 540 receives and decodes the command and address information received from the memory controller 520 via I / O 542. Based on the received command and address information, the controller 550 can execute the command by controlling the timing of operations of logic and circuitry within the memory device 540. The controller 550 is responsible for compliance with standards or specifications within the memory device 540, such as timing requirements and signaling requirements. The memory controller 520 can implement compliance with standards or specifications through access scheduling and control.

[0076] The memory controller 520 includes a scheduler 530 that represents logic or circuitry for generating and ordering transactions to be sent to the memory device 540. From one perspective, a main function of the memory controller 520 is to schedule memory accesses and other transactions to the memory device 540 Thing It can be said. Such scheduling is for data by the processor 510 OfTo implement the requirements and to generate the transaction itself, which may include maintaining data integrity (e.g., by using commands related to refresh). Since a transaction may include one or more commands, it may result in the transfer of commands or data or both at one or more timing cycles such as clock cycles or unit intervals. A transaction may be for access such as read or write or related commands or combinations thereof. Other transactions may include configuration, setting, memory management commands for data integrity, or other commands or combinations thereof.

[0077] Memory controller 520 typically includes logic such as a scheduler 530 to enable the selection and ordering of transactions to improve the performance of system 500. Thus, memory controller 520 can select which of the outstanding transactions should be sent to memory device 540 in which order. This is typically implemented using logic that is much more complex than a simple first-in-first-out algorithm. Memory controller 520 manages the transmission of transactions to memory device 540 and manages the timing related to the transactions. In one example, there is critical timing for a transaction. The timing can be managed by memory controller 520 and can be used in the decision of how to schedule the transaction with scheduler 530.

[0078] In one example, the memory controller 520 includes refresh (REF) logic 526. The refresh logic 526 can be used to refresh memory resources to maintain a definitive state. Volatile memory resources need to be refreshed regularly to maintain their state, while non-volatile memory resources may need to be refreshed to avoid read / write disturb. In one example, the refresh logic 526 indicates the location of the refresh and the type of refresh to be performed. The refresh logic 526 can trigger self-refresh within the memory device 540, or execute an external refresh (which may be referred to as an auto-refresh command) by sending a refresh command, or a combination thereof. In one example, the controller 550 within the memory device 540 includes refresh logic 554 for applying a refresh within the memory device 540. The refresh logic 554 generates internal operations and executes the refresh either internally or in accordance with an external refresh received from the memory controller 520.

[0079] FIG. 6 is a block diagram of an example of a computing system in which write count auto-increment can be implemented. System 600 represents a computing device according to any example herein and can be a laptop computer, a desktop computer, a tablet computer, a server, a game control system or an entertainment control system, an embedded computing device or other electronic device. System 600 provides an example of a system according to system 100 of FIG. 1 or system 200 of FIG. 2.

[0080] In one example, system 600 includes, or includes both, automatic increment logic 692 within memory subsystem 620 or automatic increment logic 694 within storage subsystem 680. In one example, one NV memory device or NV memory array of memory 630 or one NV memory device of storage 684 Selected from among multiple devices manages the block write count of a memory block according to any example herein And is obtained. In one example, the selected NV memory device or NV memory array stores write count metadata. In one example, the selected device is selected based on a configuration mode configured to manage the write count Do . In one example, automatic increment logic 692 or automatic increment logic 694 includes hardware for performing an automatic increment of the write count.

[0081] System 600 includes a processor 610. Processor 610 can include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core or other processing hardware, or combinations thereof, for providing processing or execution of instructions for system 600. Processor 610 controls the overall operation of system 600 and can be, or include, one or more programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations of such devices.

[0082] In one example, system 600 includes an interface 612 coupled to a processor 610. Interface 612 may represent a faster interface or high-throughput interface for system components that require a higher bandwidth connection, such as memory subsystem 620 or graphics interface component 640. Interface 612 may be a stand-alone component or represent an interface circuit that may be integrated into the processor die. Interface 612 may be integrated on the processor die as a circuit or integrated into the system-on-chip as a component. When present, graphics interface 640 interfaces to a graphics component for providing a visual display to a user of system 600. Graphics interface 640 may be a stand-alone component or may be integrated into the processor die or system-on-chip. In one example, graphics interface 640 can drive a high-definition (HD) display or an ultra-high-definition (UHD) display that provides output to a user. In one example, the display may include a touch screen display. In one example, graphics interface 640 generates a display based on data stored in memory 630, based on operations performed by processor 610, or based on both.

[0083] The memory subsystem 620 represents the main memory of the system 600 and provides a storage area for data values used in the execution of code or routines executed by the processor 610. The memory subsystem 620 can include one or more memory devices 630, such as read-only memory (ROM), flash memory, one or more types of random access memory (RAM) such as DRAM, 3DXP (3D cross-point) or other memory devices, or a combination of such devices. The memory 630 stores and hosts, among other things, an operating system (OS) 632 for providing a software platform for the execution of instructions within the system 600. In addition, an application 634 can be executed on the software platform of the OS 632 from the memory 630. The application 634 represents a program. The program has its own operation logic for performing one or more functions. The process 636 represents an agent or routine that provides auxiliary functions to the OS 632 or one or more applications 634 or a combination thereof. The OS 632, the application 634, and the process 636 provide software logic for providing functions for the system 600. In one example, the memory subsystem 620 includes a memory controller 622 that generates commands and issues them to the memory 630. It will be understood that the memory controller 622 can be a physical part of the processor 610 or a physical part of the interface 612. For example, the memory controller 622 can be an integrated memory controller integrated into the circuit with the processor 610, such as integrated into a processor die or a system-on-chip.

[0084] Although not specifically shown, it will be understood that system 600 may include one or more buses or bus systems between devices, such as a memory bus, a graphics bus, an interface bus, or others. A bus or other signal lines can couple components communicably or electrically to each other, or can couple components communicably and electrically. A bus can include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuits, or combinations thereof. A bus can include, for example, a system bus, a Peripheral Component Interconnect (PCI) bus, a HyperTransport architecture bus, or an Industry Standard Architecture (ISA) bus, a Small Computer System Interface (SCSI) bus, a Universal Serial Bus (USB), or one or more of other buses or combinations thereof.

[0085] In one example, system 600 includes an interface 614 that can be coupled to interface 612. Interface 614 can be an interface that is slower than interface 612. In one example, interface 614 represents an interface circuit that can include stand-alone components and integrated circuits. In one example, a plurality of user interface components or peripheral components, or both, are coupled to interface 614. Network interface 650 provides system 600 with the function of communicating with remote devices (e.g., servers or other computing devices) via one or more networks. Network interface 650 can include an Ethernet (registered trademark) adapter, a wireless interconnect component, a cellular network interconnect component, a USB (Universal Serial Bus), or other wired or wireless standard-based interface, or a proprietary interface. Network interface 650 can exchange data with remote devices. Such exchange can include transmitting data stored in memory or receiving data stored in memory.

[0086] In one example, system 600 includes one or more input / output (I / O) interfaces 660. The I / O interface 660 may include one or more interface components. Through the interface components, a user interacts with system 600 (e.g., voice, alphanumeric, tactile / touch, or other interfaces). The peripheral interface 670 may include any hardware interface not specifically described above. A peripheral generally refers to a device that is subordinately connected to system 600. A subordinate connection is a connection where system 600 provides a software platform or a hardware platform, or where an operation is executed on the platform and the user interacts using the platform.

[0087] In one example, system 600 includes a storage subsystem 680 for storing data in a non-volatile manner. In one example, in a particular system implementation, at least certain components of storage 680 may overlap with components of memory subsystem 620. Storage subsystem 680 includes a storage device 684. Storage device 684 can be or include any conventional medium for storing large amounts of data in a non-volatile manner, such as one or more magnetic disks, solid state disks, 3DXP disks, or optical-based disks, or combinations thereof. Storage 684 holds code or instructions and data 686 in a persistent state (i.e., the values are retained even if power to system 600 is shut off). Storage 684 may generally be considered a “memory,” but memory 630 is typically an execution memory or working memory for providing instructions to processor 610. Storage 684 is non-volatile, while memory 630 may include volatile memory (i.e., when power to system 600 is shut off, the data values or states become indeterminate). In one example, storage subsystem 680 includes a controller 682 for interfacing with storage 684. In one example, controller 682 can be a physical part of interface 614 or processor 610, or can include circuitry or logic for both processor 610 and interface 614.

[0088] Power supply 602 provides power to the components of system 600. More specifically, power supply 602 typically interfaces with one or more power supplies 604 within system 600 to provide power to the components of system 600. In one example, power supply 604 includes an AC-DC (alternating current - direct current) adapter for plugging into a wall outlet. Such an AC power supply can be a renewable energy (e.g., solar power generation) power supply 602. In one example, power supply 602 includes a DC power supply such as an external AC-DC converter. In one example, power supply 602 or power supply 604 includes wireless charging hardware for charging via proximity to a charging magnetic field. In one example, power supply 602 can include an internal battery or fuel cell power supply.

[0089] FIG. 7 is a block diagram of an example of a mobile device in which write count automatic increment can be implemented. System 700 represents a mobile computing device such as a computing tablet, a cellular phone or smartphone, a wearable computing device or other mobile device or an embedded computing device. Although certain ones of these components are generally shown, it will be understood that not all components of such a device are shown within system 700. System 700 provides an example of a system according to system 100 of FIG. 1 or system 200 of FIG. 2.

[0090] In one example, system 700 includes auto-increment logic 790 within memory subsystem 760. In one example, one NV memory device or NV memory array of memory 762 can be selected from among a plurality of devices for managing the block write count of a memory block according to any example herein. In one example, the selected NV memory device or NV memory array stores write count metadata. In one example, the selected device is selected based on a configuration mode configured to manage the write count. In one example, auto-increment logic 790 includes hardware for performing an auto-increment of the write count.

[0091] System 700 includes a processor 710 that executes the main processing operations of system 700. Processor 710 can include one or more physical devices such as a microprocessor, application processor, microcontroller, programmable logic device, or other processing means. The processing operations executed by processor 710 include the execution of an operating platform or operating system on which application and device functions are executed. The processing operations include operations related to I / O (input / output) with a human user or other devices, operations related to power management, operations related to the connection of system 700 to another device, or combinations thereof. The processing operations can also include operations related to voice I / O, display I / O, or other interfaces, or combinations thereof. Processor 710 can execute data stored in memory. Processor 710 can write or edit data stored in memory.

[0092] In one example, system 700 includes one or more sensors 712. The sensors 712 represent embedded sensors or interfaces to external sensors, or combinations thereof. With the sensors 712, the system 700 can monitor or detect one or more conditions of the environment or device in which the system 700 is implemented. The sensors 712 can include environmental sensors (such as temperature sensors, motion detectors, light detectors, cameras, chemical sensors (e.g., carbon monoxide sensors, carbon dioxide sensors, or other chemical sensors)), pressure sensors, accelerometers, gyroscopes, medical sensors or physiological sensors (e.g., biosensors, heart rate monitors, or other sensors for detecting physiological attributes), or other sensors, or combinations thereof. The sensors 712 can also include sensors for biometric systems, such as fingerprint recognition systems, face detection or recognition systems, or other systems for detecting or recognizing user characteristics. The sensors 712 are to be broadly understood and should not be understood as a limitation to many different types of sensors that can be implemented with the system 700. In one example, the one or more sensors 712 couple to the processor 710 via a front-end circuit integrated with the processor 710. In one example, the one or more sensors 712 couple to the processor 710 via another component of the system 700.

[0093] In one example, system 700 includes an audio subsystem 720 that represents hardware (e.g., audio hardware and audio circuitry) and software components (e.g., drivers, codecs) related to providing audio functionality to a computing device. The audio functionality can include speaker output or headphone output and microphone input. Devices for such functionality can be integrated into or connected to the system 700. In one example, a user interacts with the system 700 by providing audio commands that are received and processed by the processor 710.

[0094] The display subsystem 730 represents hardware (e.g., a display device) components and software components (e.g., a driver) that provide a visual display for a user to view. In one example, the display includes a tactile component or a touch screen element for a user to interact with the computing device. The display subsystem 730 includes a display interface 732 that includes a specific screen or hardware device used to provide a display to the user. In one example, the display interface 732 includes logic separate from the processor 710 (such as a graphics processor) to perform at least some processing related to the display. In one example, the display subsystem 730 includes a touch screen device that provides both output and input to the user. In one example, the display subsystem 730 includes a high-definition (HD) display or an ultra-high-definition (UHD) display that provides output to the user. In one example, the display subsystem includes or drives a touch screen display. In one example, the display subsystem 730 generates display information based on data stored in the memory, or based on operations executed by the processor 710, or based on both of them.

[0095] The I / O controller 740 represents hardware devices and software components related to user interaction. The I / O controller 740 can operate to manage hardware that is part of the audio subsystem 720 or the display subsystem 730 or both. Additionally, the I / O controller 740 indicates connection points for additional devices connected to the system 700. Through these connection points, a user can interact with the system. For example, devices that can be attached to the system 700 can include a microphone device, a speaker system or stereo system, a video system or other display device, a keyboard device or keypad device, buttons / switches, or other I / O devices for use with specific applications such as a card reader, or other devices.

[0096] As described above, the I / O controller 740 can interact with the audio subsystem 720 or the display subsystem 730 or both. For example, input through a microphone or other audio device can provide input or commands for one or more applications or functions of the system 700. Additionally, audio output can be provided instead of or in addition to the display output. In another example, if the display subsystem includes a touch screen, the display device can also function as an input device that is at least partially managed by the I / O controller 740. Additional buttons or switches for providing I / O functions managed by the I / O controller 740 can also be present on the system 700.

[0097] In one example, I / O controller 740 manages devices such as accelerometers, cameras, light sensors or other environmental sensors, gyroscopes, global positioning system (GPS) or other hardware or sensors 712 that may be included in system 700. Inputs can be part of direct user interaction, but can also provide environmental inputs to the system that affect its operation (such as noise filtering, adjusting the display for luminance detection, applying a flash for the camera, or other features).

[0098] In one example, system 700 includes power management 750 that manages battery power usage, battery charging, and functions related to power saving operations. Power management 750 manages power from power supply 752 that provides power to components of system 700. In one example, power supply 752 includes an AC-DC (alternating current - direct current) adapter for plugging into a wall outlet. Such an AC power source can be renewable energy (e.g., solar power, motion-based power). In one example, power supply 752 includes only DC power provided by a DC power source such as an external AC-DC converter. In one example, power supply 752 includes wireless charging hardware for charging via proximity to a charging magnetic field. In one example, power supply 752 can include an internal battery or fuel cell power source.

[0099] The memory subsystem 760 includes a memory device 762 for storing information in the system 700. The memory subsystem 760 may include a non-volatile (state does not change when power to the memory device is cut off) memory device, a volatile (state becomes uncertain when power to the memory device is cut off) memory device, or a combination thereof. The memory 760 can store not only application data, user data, music, photos, documents, or other data, but also system data (whether long-term or temporary) related to the execution of applications and functions of the system 700. In one example, the memory subsystem 760 includes a memory controller 764 (which can be considered part of the control of the system 700 and potentially part of the processor 710). The memory controller 764 includes a scheduler that generates and issues commands to control access to the memory device 762.

[0100] The connection 770 includes hardware devices (e.g., wireless connectors or wired connectors and communication hardware or a combination of wired and wireless hardware) and software components (e.g., drivers, protocol stacks) to enable the system 700 to communicate with external devices. The external devices can be other computing devices, separate devices such as wireless access points or base stations, and peripheral devices such as headsets, printers, or other devices. In one example, the system 700 exchanges data with external devices for storage in memory or for display on a display device. The data exchanged can include data stored in memory for reading, writing, or editing, or data already stored in memory.

[0101] Connection 770 may include multiple different types of connections. For generality, system 700 is shown with a cellular connection 772 and a wireless connection 774. Cellular connection 772 generally refers to a cellular network connection provided by a wireless carrier such as via GSM (registered trademark) (Global System for Mobile Communications), or a variant or derivative standard thereof, or CDMA (Code Division Multiple Access) or a variant or derivative standard thereof, TDM (Time Division Multiplexing) or a variant or derivative standard thereof, LTE (Long Term Evolution, also referred to as "4G", "5G"), or other cellular service standards. Wireless connection 774 refers to a non-cellular wireless connection and may include a personal area network (such as Bluetooth (registered trademark)), a local area network (such as WiFi (registered trademark)) or a wide area network (such as WiMAX) or other wireless communications or combinations thereof. Wireless communication refers to transferring data through the use of modulated electromagnetic radiation through a non-solid medium. Wired communication is caused by a solid communication medium.

[0102] Peripheral connection 780 includes a hardware interface and connector as well as software components (such as drivers, protocol stacks) for making peripheral connections. It will be understood that system 700 can be both a peripheral device to other computing devices ("outward" 782) and a peripheral device connected to system 700 ("inward" 784). System 700 generally has a "docking" connector for connecting to other computing devices for purposes such as managing content on system 700 (such as downloading, uploading, changing, synchronizing). In addition, the docking connector can enable system 700 to connect to certain peripheral devices that enable system 700 to control content output to, for example, an audio-visual system or other system.

[0103] In addition to the proprietary docking connector or other proprietary connection hardware, system 700 can make peripheral connections 780 via common connectors or standard-based connectors. Common types can include Universal Serial Bus (USB) connectors (which can include any of a number of different hardware interfaces), Mini DisplayPort (MDP), DisplayPort such as High-Definition Multimedia Interface (HDMI (registered trademark)) or other types.

[0104] Generally, with respect to the description herein, in one example, a non-volatile memory device comprises a plurality of non-volatile (NV) memory arrays for storing data blocks together, each array storing a portion of a data block, one of the NV memory arrays storing a write count of the data block, and a command bus interface for receiving write commands for writing data blocks to the NV memory arrays, in response to receiving a write command, the NV memory arrays perform internal read-ahead writing of the data block to the NV memory arrays, one NV memory array performs read-ahead writing of the write count, increments an internal write count of one NV memory array, and writes the incremented write count to one NV memory array.

[0105] In one example, the NV memory array has separate NV memory chips. In one example, one NV memory array further stores error checking and correction (ECC) data. In one example, the NV memory array further has a register for storing a write count configuration, one NV memory array stores a register configuration for the write count mode, and another NV memory array stores a register configuration for disabling the write count mode. In one example, the NV memory array further has auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware. In one example, the NV memory array performs a pre-read write of data to the NV memory array, compares the data in the NV memory array with the data to be written, and writes only the bits having different values due to the write command. In one example, one NV memory array stores a write threshold and passes an alert to a related controller in response to the write count reaching the write threshold.

[0106] Generally, with respect to the description herein, in one example, the system includes a controller and a non-volatile memory device, the non-volatile memory device including a plurality of non-volatile (NV) memory arrays for collectively storing data blocks, each array storing a portion of a data block, one of the NV memory arrays storing a write count of the data block, and a command bus interface for receiving a write command for writing a data block to the NV memory array, in response to receiving the write command, the NV memory array performs an internal pre-read write of the data block to the NV memory array, one NV memory array performs a pre-read write of the write count, increments an internal write count of one NV memory array, and writes the incremented write count to one NV memory array.

[0107] In one example, the NV memory array has separate NV memory chips. In one example, one NV memory array further stores error checking and correction (ECC) data. In one example, the NV memory array further has a register for storing a write count configuration, one NV memory array stores a register configuration for the write count mode, and another NV memory array stores a register configuration for disabling the write count mode. In one example, the NV memory array further has auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware. In one example, one NV memory array stores a write threshold and passes an alert to the controller in response to the write count reaching the write threshold. In one example, the system further comprises one or more of a host processor device coupled to the non-volatile memory device, a display communicatively coupled to the host processor, a network interface communicatively coupled to the host processor, or a battery that powers the system.

[0108] Generally, with respect to the description herein, in one example, a method includes storing a data block collectively across a plurality of non-volatile (NV) memory arrays, each array storing a portion of the data block, and one of the NV memory arrays storing a write count of the data block; receiving a write command for writing the data block to the NV memory array; and in response to receiving the write command, the NV memory array performs an internal read-ahead write of the data block to the NV memory array, one NV memory array performs a read-ahead write of the write count, increments an internal write count of one NV memory array, and writes the incremented write count to one NV memory array.

[0109] In one example, the NV memory array has separate NV memory chips. In one example, one NV memory array further stores error checking and correction (ECC) data. In one example, the NV memory array further has a register for storing a write count configuration, one NV memory array stores a register configuration for the write count mode, and another NV memory array stores a register configuration for disabling the write count mode. In one example, the NV memory array further has auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware. In one example, one NV memory array further stores a write threshold, and one NV memory array passes an alert to a related controller in response to the write count reaching the write threshold.

[0110] The flowcharts shown herein provide examples of a series of various processing operations. The flowcharts can represent not only operations executed by software or firmware routines, but also physical operations. The flowcharts can represent examples of the implementation of the states of a finite state machine (FSM) that can be implemented in hardware and / or software. The order of operations is shown in a particular sequence or order, but can be modified unless otherwise specified. Therefore, the diagrams shown should be understood only as examples, and the processing can be executed in a different order, and some operations can be executed in parallel. Additionally, one or more operations can be omitted. Therefore, not all implementations execute all operations.

[0111] In the context of the various operations or functions described herein, they may be described or defined as software code, instructions, configurations, and / or data. The content can be in a directly executable form (the "object" form or "executable" form), source code, or differential code (the "delta" code or "patch" code). The software content described herein can be provided via a manufactured product in which the content is stored, or via a method of transmitting data through operating a communication interface to transmit data through the communication interface. A machine-readable storage medium can cause a machine to execute the described functions or operations, and includes any mechanism that stores information in a form accessible by a machine (such as a computing device, an electronic system, etc.), such as a recordable / non-recordable medium (e.g., read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory devices, etc.). A communication interface includes any mechanism that serves as an interface to any of a hardwired, wireless, optical, etc. medium for communicating with another device, such as a memory bus interface, a processor bus interface, an Internet connection, a disk controller, etc. The communication interface can be configured by providing configuration parameters and / or transmitting signals to prepare the communication interface to provide a data signal describing the software content. The communication interface can be accessed via one or more commands or signals transmitted to the communication interface.

[0112] The various components described herein can be means for performing the described operations or functions. Each component described herein includes software, hardware, or a combination thereof. The component can be implemented as a software module, a hardware module, application-specific hardware (e.g., application-specific hardware, application-specific integrated circuit (ASIC), digital signal processor (DSP), etc.), an embedded controller, a hardwired circuit, etc.

[0113] In addition to what has been described in this specification, various modifications can be made to the disclosed and implemented aspects of the present invention without departing from their scope. Therefore, the examples and illustrations in this specification should be construed in an illustrative sense and not in a limiting sense. The scope of the present invention should be determined only by reference to the following claims. [Other possible items] [Item 1] A plurality of non-volatile (NV) memory arrays for storing data blocks collectively, each array storing a portion of the data blocks, and one of the NV memory arrays storing the write count of the data blocks, the plurality of NV memory arrays; A command bus interface for receiving a write command to write the data block to the NV memory array, in response to receiving the write command, the NV memory array performing an internal Preliminary read thereof to the NV memory array, and one of the NV memory arrays performing an Preliminary read thereof to increment the write count internally in the one NV memory array and write the incremented write count to the one NV memory array, the command bus interface; A non-volatile memory device comprising. [Item 2] The non-volatile memory device according to item 1, wherein the NV memory array has a separate NV memory chip. [Item 3] The non-volatile memory device according to item 1, wherein the one NV memory array further stores error checking and correction (ECC) data. [Item 4] The above NV memory array further has a register for storing a write count configuration, one of the above NV memory arrays stores a register configuration for the write count mode, and the other above NV memory array stores a register configuration for disabling the above write count mode. The non-volatile memory device according to item 1. [Item 5] The above NV memory array further has automatic increment hardware, and the above write count mode selectively enables or disables the above automatic increment hardware. The non-volatile memory device according to item 4. [Item 6] The above NV memory array, the above NV memory array In The above of the above data block Preliminary read Execute, compare the data in the above NV memory array with the data to be written, and write only the bits having different values due to the above write command. The non-volatile memory device according to item 1. [Item 7] One of the above NV memory arrays stores a write threshold, and in response to the write count reaching the above write threshold, passes an alert to the associated controller. The non-volatile memory device according to item 1. [Item 8] A controller, A non-volatile memory device and A system comprising, The above non-volatile memory device is A number of non-volatile (NV) memory arrays for collectively storing data blocks, each array storing a portion of the above data block, and one of the above NV memory arrays storing the write count of the above data block. A plurality of NV memory arrays, Complex A command bus interface for receiving a write command for writing the above data block to the above NV memory array. In response to receiving the above write command, the above NV memory array performs an internal of the above data block to the above NV memory array Preliminary readExecute, and one of the above NV memory arrays is for the write count of Preliminary read Execute, increment the write count inside the one NV memory array, and write the incremented write count to the one NV memory array, a command bus interface and Having, System. [Item 9] The NV memory array includes separate NV memory chips, the system according to item 8. [Item 10] The one NV memory array further stores error checking and correction (ECC) data, the system according to item 8. [Item 11] The NV memory array further has a register for storing a write count configuration, the one NV memory array stores a register configuration for the write count mode, and the other NV memory arrays store a register configuration for disabling the write count mode, the system according to item 8. [Item 12] The NV memory array further has auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware, the system according to item 11. [Item 13] The one NV memory array stores a write threshold, and in response to the write count reaching the write threshold, passes an alert to the controller, the system according to item 8. [Item 14] A host processor device coupled to the non-volatile memory device, A display communicatively coupled to the host processor, A network interface communicatively coupled to the host processor, or, A battery that powers the system The system according to item 8 further includes one or more of. [Item 15] Storing a data block in a plurality of non-volatile (NV) memory arrays, each array storing a portion of the data block, and one of the NV memory arrays storing a write count of the data block; Receiving a write command for writing the data block to the NV memory array; Comprising; In response to receiving the write command, the NV memory array performs an internal write of the data block to the NV memory array, and one of the NV memory arrays performs an operation on the write count; Purposeful preliminary read One of the NV memory arrays increments the write count and writes the incremented write count to the one NV memory array. Preliminary read Internal of the one NV memory array; In Method. Method. [Item 16] The method according to item 15, wherein the NV memory array includes separate NV memory chips. [Item 17] The method according to item 15, wherein the one NV memory array further stores error checking and correction (ECC) data. [Item 18] The method according to item 15, wherein the NV memory array further has a register for storing a write count configuration, the one NV memory array stores a register configuration for a write count mode, and the other NV memory arrays store a register configuration for disabling the write count mode. [Item 19] The method according to item 18, wherein the NV memory array further has automatic increment hardware, and the write count mode selectively enables or disables the automatic increment hardware. [Item 20] The one NV memory array further stores a write threshold, and the one NV memory array passes an alert to an associated controller in response to the write count reaching the write threshold, the method of item 15.

Claims

1. A plurality of non-volatile (NV) memory arrays for collectively storing data blocks, each of the plurality of NV memory arrays storing a part of the data block, and one of the plurality of NV memory arrays further storing a write count of the data block; a plurality of NV memory arrays, A command bus interface for receiving a write command for writing the data block to the plurality of NV memory arrays, and in response to receiving the write command, the plurality of NV memory arrays execute an internal pre-read of the data block in the plurality of NV memory arrays, and the one NV memory array executes the internal pre-read of the write count, increments the write count inside the one NV memory array, and writes the incremented write count to the one NV memory array; a command bus interface A non-volatile memory device comprising.

2. The non-volatile memory device according to claim 1, wherein the plurality of NV memory arrays have separate NV memory chips.

3. The non-volatile memory device according to claim 1 or 2, wherein the one NV memory array further stores error checking and correction (ECC) data.

4. The plurality of NV memory arrays further have a register for storing a write count configuration, the one NV memory array stores a register configuration of a write count mode, and the other plurality of NV memory arrays store a register configuration for disabling the write count mode. The non-volatile memory device according to any one of claims 1 to 3.

5. The non-volatile memory device according to claim 4, wherein the plurality of NV memory arrays further have auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware.

6. The plurality of NV memory arrays, after performing the pre-read of the data block in the plurality of NV memory arrays, compare the data read by the pre-read of the plurality of NV memory arrays with the data to be written, and write only the bits having different values due to the write command. The non-volatile memory device according to any one of claims 1 to 5.

7. The one NV memory array stores a write threshold, and in response to the write count reaching the write threshold, passes an alert to an associated controller. The non-volatile memory device according to any one of claims 1 to 6.

8. A system having a non-volatile memory, a controller, a non-volatile memory device and wherein the non-volatile memory device is a plurality of non-volatile (NV) memory arrays for collectively storing data blocks, each of the plurality of NV memory arrays stores a part of the data block, and one of the plurality of NV memory arrays further stores a write count of the data block; a plurality of NV memory arrays, a command bus interface for receiving a write command for writing the data block to the plurality of NV memory arrays, in response to receiving the write command, when the plurality of NV memory arrays perform an internal pre-read of the data block in the plurality of NV memory arrays, the one NV memory array performs the internal pre-read of the write count, increments the write count inside the one NV memory array, and writes the incremented write count to the one NV memory array. A command bus interface having a system.

9. The plurality of NV memory arrays include separate NV memory chips. The system according to claim 8.

10. The one NV memory array further stores error checking and correction (ECC) data. The system according to claim 8 or 9.

11. The plurality of NV memory arrays further includes a register for storing a write count configuration, wherein one of the NV memory arrays stores a register configuration in a write count mode, and the other plurality of NV memory arrays store a register configuration for disabling the write count mode. The system according to any one of claims 8 to 10.

12. The plurality of NV memory arrays further includes and has auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware. The system according to claim 11.

13. One of the NV memory arrays stores a write threshold, and in response to the write count reaching the write threshold, passes an alert to the controller. The system according to any one of claims 8 to 12.

14. A host processor device coupled to the non-volatile memory device, A display communicatively coupled to the host processor, A network interface communicatively coupled to the host processor, or A battery for supplying power to the system The system according to any one of claims 8 to 13, further comprising one or more of.

15. A method for storing data, comprising: Storing data blocks collectively in a plurality of non-volatile (NV) memory arrays, each of the plurality of NV memory arrays storing a part of the data block, and one of the plurality of NV memory arrays further storing a write count of the data block; Receiving a write command for writing the data block to the plurality of NV memory arrays; Comprising In response to receiving the write command, when the plurality of NV memory arrays perform an internal pre-read of the data block in the plurality of NV memory arrays, the one NV memory array performs the internal pre-read of the write count, increments the write count inside the one NV memory array, and writes the incremented write count to the one NV memory array. Method.

16. The method according to claim 15, wherein the plurality of NV memory arrays include separate NV memory chips.

17. The method according to claim 15 or 16, wherein the one NV memory array further stores error checking and correction (ECC) data.

18. The method according to any one of claims 15 to 17, wherein the plurality of NV memory arrays further include a register for storing a write count configuration, the one NV memory array stores a register configuration for the write count mode, and the other plurality of NV memory arrays store a register configuration for disabling the write count mode.

19. The method according to claim 18, wherein the plurality of NV memory arrays further include auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware.

20. The method according to any one of claims 15 to 19, wherein the one NV memory array further stores a write threshold, and the one NV memory array passes an alert to an associated controller in response to the write count reaching the write threshold.

21. An apparatus for storing data, means for collectively storing a data block in a plurality of non-volatile (NV) memory arrays, each of the plurality of NV memory arrays storing a part of the data block, and one of the plurality of NV memory arrays further storing a write count of the data block; means for receiving a write command for writing the data block to the plurality of NV memory arrays; means for, in response to receiving the write command, performing an internal pre-read of the write count in the one NV memory array, incrementing the write count inside the one NV memory array, and writing the incremented write count to the one NV memory array, in connection with performing an internal pre-read of the data block in the plurality of NV memory arrays. An apparatus comprising the above.

22. The apparatus according to claim 21, wherein the plurality of NV memory arrays include separate NV memory chips.

23. The apparatus according to claim 21 or 22, wherein the one NV memory array further includes means for storing error checking and correction (ECC) data.

24. The apparatus according to any one of claims 21 to 23, wherein the plurality of NV memory arrays further includes a register for storing a write count configuration, the one NV memory array stores a register configuration for a write count mode, and the other plurality of NV memory arrays store a register configuration for disabling the write count mode.

25. The apparatus according to claim 24, wherein the plurality of NV memory arrays further includes auto-increment hardware, and the write count mode selectively enables or disables the auto-increment hardware.

26. The apparatus according to any one of claims 21 to 23, wherein the one NV memory array further stores a write threshold, and the one NV memory array passes an alert to an associated controller in response to the write count reaching the write threshold.

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