Method for manufacturing a substrate with chips and substrate processing apparatus

Abstract

This method for manufacturing a chip-mounted substrate includes the following steps (A)-(B). (A) A stacked substrate is prepared, the stacked substrate including a plurality of chips, a first substrate to which the plurality of chips are temporarily bonded, and a second substrate bonded to the first substrate with the plurality of chips interposed therebetween. (B) The plurality of chips bonded to the first substrate and the second substrate are separated from the first substrate to be bonded to one side including a device layer of a third substrate. The first substrate from which the chips are separated includes an alignment mark used for positioning the chips and the first substrate when bonding, and for measuring a positional shift after bonding.

Description

Technical Field

[0001] The present disclosure relates to a method for manufacturing a substrate with chips and a substrate processing apparatus.

Background Art

[0002] FIG. 20 of Patent Document 1 illustrates a manufacturing process of chips on a wafer. In this manufacturing process, the singulated first memory chips are bonded one by one to a base wafer on which a plurality of second memory chips are formed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] One aspect of the present disclosure provides a technique for reusing an alignment mark used for alignment during bonding of a chip and a substrate or for measurement of misalignment after bonding.

Means for Solving the Problems

[0005] A method for manufacturing a substrate with chips according to one aspect of the present disclosure includes the following (A) to (B). (A) Prepare a laminated substrate including a plurality of chips, a first substrate to which the plurality of chips are temporarily bonded without an adhesive, and a second substrate bonded to the first substrate via the plurality of chips. (B) Separate the plurality of chips bonded to the first substrate and the second substrate from the first substrate so as to bond them to one side of a device layer of a third substrate. The first substrate separated from the chips includes an alignment mark used for alignment during bonding of the chips and the first substrate or for measurement of misalignment after bonding. The separation of the plurality of the chips and the first substrate includes forming a plurality of modified layers with a laser beam on a division surface where the first substrate is to be divided in the thickness direction, and dividing the first substrate starting from the plurality of the modified layers.

Advantages of the Invention

[0006] According to one aspect of the present disclosure, the alignment mark can be reused.

Brief Description of the Drawings

[0007]

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DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. In each drawing, the same or corresponding components are denoted by the same reference numerals, and the description thereof may be omitted.

[0009] The method for manufacturing a substrate with chips has, for example, S1 to S7 shown in FIG. 1. S1 in FIG. 1 has, for example, S11 to S14 shown in FIG. 2. Also, S6 shown in FIG. 1 has, for example, S61 to S63 shown in FIG. 3.

[0010] First, in S1 of FIG. 1, as shown in FIGS. 4 and 5, the first substrate 1 and the chips 2A and 2B are joined. In S11 of FIG. 2 included in S1 of FIG. 1, the first substrate 1 and the chips 2A and 2B are prepared.

[0011] The first substrate 1 has, for example, a silicon wafer 11, an absorption layer 12, and a bonding layer 13. Note that the absorption layer 12 may also serve as the bonding layer 13 as described later, and the first substrate 1 only needs to have the silicon wafer 11 and the absorption layer 12. Instead of the silicon wafer 11, a compound semiconductor wafer may be used. The compound semiconductor wafer is not particularly limited, but is, for example, a GaAs wafer, a SiC wafer, a GaN wafer, an InP wafer, or an AlN wafer.

[0012] The absorption layer 12 is disposed between the silicon wafer 11 and the chips 2A and 2B. As will be described in detail later, as shown in FIG. 11, the laser beam LB2 passes through the silicon wafer 11 and is absorbed by the absorption layer 12. Since the laser beam LB2 is absorbed by the absorption layer 12 and does not hit the chips 2A and 2B, breakage of the chips 2A and 2B can be suppressed. The absorption layer 12 is, for example, a silicon oxide layer, and is formed by a thermal oxidation method, a CVD (Chemical Vapor Depositon) method, or the like.

[0013] Note that the absorption layer 12 only needs to be able to absorb the laser beam LB2 to such an extent that breakage of the chips 2A and 2B can be suppressed, and may be a silicon nitride layer, a silicon carbonitride layer, or the like. The silicon nitride layer is formed by a thermal nitridation method, a CVD method, or the like. The silicon carbonitride layer is formed by a CVD method or the like.

[0014] The bonding layer 13 is disposed between the absorption layer 12 and the chips 2A and 2B and contacts the chips 2A and 2B as shown in FIG. 4. The bonding layer 13 is, for example, an insulating layer such as a silicon oxide layer. The bonding layer 13 may be made of a material different from that of the absorption layer 12 or the same material. In the latter case, the absorption layer 12 may also serve as the bonding layer 13.

[0015] The first substrate 1 includes an alignment mark 15. The alignment mark 15 is used for alignment during the bonding of the first substrate 1 with the chips 2A and 2B, or for measuring the misalignment after bonding. The alignment mark 15 may be used for both alignment and measurement of misalignment. The measurement result of the misalignment after bonding is used, for example, for alignment during the bonding of the first substrate 1 with the chips in subsequent times. Also, the measurement result of the misalignment after bonding may be used for quality control such as discrimination of defective products.

[0016] As shown in FIG. 12, the alignment mark 15 is formed between the silicon wafer 11 and the absorption layer 12, and is formed on the side opposite to the chips 2A and 2B with reference to the dividing surface D. By dividing the first substrate 1 at the dividing surface D, the silicon wafer 11 and the chips 2A and 2B can be separated. The alignment mark 15 is attached to the silicon wafer 11 separated from the chips 2A and 2B. Therefore, when the silicon wafer 11 is reused, it is not necessary to reform the alignment mark 15, and the alignment mark 15 can be reused.

[0017] The alignment mark 15 absorbs infrared rays used for imaging the alignment mark 15. The infrared camera images the alignment mark 15 by receiving the infrared rays transmitted through the silicon wafer 11. The wavelength of the infrared rays used for imaging is different from the wavelength of the laser beam LB2, and is, for example, 1000 nm to 2000 nm. The absorption rate of the infrared rays used for imaging the alignment mark 15 by the alignment mark 15 is, for example, 45% or more and 100% or less, preferably 50% or more and 100% or less, and more preferably 60% or more and 100% or less.

[0018] As shown in FIG. 11, the alignment mark 15 transmits the laser beam LB2. The laser beam LB2 passes through the silicon wafer 11 and the alignment mark 15, and forms a modified layer M in the absorption layer 12. When the absorption layer 12 absorbs the laser beam LB2, the modified layer M is formed. A plurality of modified layers M are formed on the dividing surface D. Division is performed starting from the plurality of modified layers M. The wavelength of the laser beam LB2 is, for example, 8800 nm to 11000 nm. The alignment mark 15 has a transmittance of the laser beam LB2 of, for example, 45% or more and 100% or less, preferably 50% or more and 100% or less, and more preferably 60% or more and 100% or less.

[0019] As described above, the alignment mark 15 is formed of a material that absorbs infrared rays used for imaging of the alignment mark 15 and transmits the laser beam LB2. Specifically, for example, the alignment mark 15 includes a Ge film, a SiGe film, a metal silicide film, or an AlN film. Films such as Ge films 2 differ from SiO films and metal films in that they absorb infrared rays for imaging and transmit the laser beam LB2. Incidentally, SiO 2 films transmit infrared rays for imaging and absorb the laser beam LB2. Also, metal films can absorb infrared rays for imaging but also absorb the laser beam LB2. The method for forming the alignment mark 15 will be described later.

[0020] The chip 2A has a silicon wafer 21A and a device layer 22A. The device layer 22A is formed on the surface of the silicon wafer 21A. The device layer 22A includes semiconductor elements, circuits, terminals, etc. After the formation of the device layer 22A, the silicon wafer 21A is diced into a plurality of chips 2A.

[0021] Similar to the chip 2A, the chip 2B has a silicon wafer 21B and a device layer 22B. The device layer 22B has a function different from that of the device layer 22A, and the chip 2A and the chip 2B have different thicknesses. After the formation of the device layer 22B, the silicon wafer 21B is diced into a plurality of chips 2B.

[0022] In S12 shown in FIG. 2, which is included in S1 of FIG. 1, the bonding surface 14 of the first substrate 1 is surface-modified with plasma or the like. Specifically, the Si—O bonds on the bonding surface 14 are broken to form unbonded hands of Si, enabling the hydrophilicity of the bonding surface 14. 2 The bonding surface 14 is surface-modified with plasma or the like. Specifically, the Si—O bonds on the bonding surface 14 are broken to form unbonded hands of Si, enabling the hydrophilicity of the bonding surface 14.

[0023] For example, in a reduced-pressure atmosphere, oxygen gas as a processing gas is excited to form plasma and is ionized. Oxygen ions are irradiated onto the bonding surface 14, and the bonding surface 14 is modified. The processing gas is not limited to oxygen gas and may be, for example, nitrogen gas or the like.

[0024] In the above S12, not only the bonding surface 14 of the first substrate 1 but also the bonding surfaces 24A and 24B of the chips 2A and 2B may be surface-modified. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B is surface-modified.

[0025] In S13 shown in FIG. 2, which is included in S1 of FIG. 1, the bonding surface 14 of the first substrate 1 is hydrophilized. For example, the first substrate 1 is held by a spin chuck, and pure water such as DIW (deionized water) is supplied to the bonding surface 14 of the first substrate 1 that rotates together with the spin chuck. OH groups are attached to the unbonded hands of Si on the bonding surface 14, and the bonding surface 14 is hydrophilized.

[0026] In the above S13, not only the bonding surface 14 of the first substrate 1 but also the bonding surfaces 24A and 24B of the chips 2A and 2B may be hydrophilized. At least one of the bonding surface 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B is hydrophilized.

[0027] In S14 shown in FIG. 2, which is included in S1 of FIG. 1, the chips 2A and 2B are temporarily bonded to the bonding surface 14 of the first substrate 1 one by one. The chips 2A and 2B are bonded to the first substrate 1 with the device layers 22A and 22B facing the first substrate 1.

[0028] The chip 2A, 2B and the first substrate 1 are joined by van der Waals forces (intermolecular forces) and hydrogen bonds between OH groups. Thereafter, heat treatment may be performed to increase the bonding strength. The heat treatment causes a dehydration reaction. Since the solids are directly bonded to each other without using a liquid adhesive, it is possible to prevent displacement due to deformation of the adhesive and generation of inclination due to unevenness in the thickness of the adhesive.

[0029] By the way, in Patent Document 1 described above, unlike the technology of the present disclosure, the chips 2A and 2B are permanently bonded to a third substrate 6 described later without temporarily bonding the chips 2A and 2B to the first substrate 1. Therefore, both suppression of entrapment of bubbles and foreign matters during bonding and accurate position control are required at the same time.

[0030] When the chips 2A and 2B are bonded to the third substrate 6 one by one as in Patent Document 1, in order to suppress entrapment of bubbles during bonding, the chips 2A and 2B may be deformed one by one. The bonding surfaces 24A and 24B of the chips 2A and 2B are deformed into downwardly convex curved surfaces, and are gradually bonded to the third substrate 6 from the center toward the periphery, and finally return to a flat surface.

[0031] Deforming the bonding surfaces 24A and 24B of the chips 2A and 2B into downwardly convex curved surfaces includes fixing the respective peripheries of the chips 2A and 2B and pressing down the respective centers of the chips 2A and 2B. However, since the individual sizes of the chips 2A and 2B are small, the distance between the fixing location and the pressing location is narrow. Therefore, it is difficult to deform the chips 2A and 2B one by one.

[0032] According to the present embodiment, the chips 2A and 2B are temporarily bonded to the first substrate 1 and later separated from the first substrate 1. Therefore, even if bubbles are entrapped during bonding between the chips 2A and 2B and the first substrate 1, it does not pose a problem. Therefore, in S14 described above, the bonding surfaces 24A and 24B of the chips 2A and 2B can be bonded to the bonding surface 14 of the first substrate 1 while remaining flat surfaces. Since the chips 2A and 2B are not deformed, the accuracy of position control of the chips 2A and 2B can be improved, and the chips 2A and 2B can be accurately placed at the target positions.

[0033] Also, according to the present embodiment, the chips 2A and 2B are temporarily bonded to the first substrate 1 and later separated from the first substrate 1. Therefore, even if particles are caught during the bonding of the chips 2A and 2B to the first substrate 1, it does not pose a problem. Accordingly, the bonding surfaces 14 of the first substrate 1 and the bonding surfaces 24A and 24B of the chips 2A and 2B may be dirty to such an extent that it does not hinder the bonding. The required cleanliness can be low.

[0034] Next, in S2 of FIG. 1, as shown in FIG. 6, a plurality of chips 2A and 2B are thinned and the thicknesses are made uniform. In FIG. 6, the two-dot chain line indicates the state immediately before S2, and the solid line indicates the state at the completion of S2. Among the chips 2A and 2B, the silicon wafers 21A and 21B are thinned, and the device layers 22A and 22B are not thinned. The thinning includes grinding or laser processing.

[0035] Next, in S3 of FIG. 1, as shown in FIG. 7, a bonding layer 3 is formed on the surfaces of the chips 2A and 2B. The bonding layer 3 is an insulating layer such as a silicon oxide layer, similar to the bonding layer 13 of the first substrate 1, and is formed by a CVD method or the like. The chips 2A and 2B are arranged with a space therebetween, and since the underlying surface of the bonding layer 3 has irregularities, the surface of the bonding layer 3 also has irregularities.

[0036] Next, in S4 of FIG. 1, as shown in FIGS. 8 and 9, the surface of the bonding layer 3 is planarized. Since the bonding layer 3 is a silicon oxide layer or the like and has high hardness, polishing such as CMP (Chemical Mechanical Polishing) takes time for planarization.

[0037] Therefore, first, as shown in FIG. 8, the convex portions 31 of the bonding layer 3 are irradiated with a laser beam LB1. The convex portions 31 absorb the laser beam LB1 and change their state from solid phase to gas phase and scatter, or scatter while remaining in the solid phase. Note that the laser beam LB1 may also be irradiated to the concave portions 32 of the bonding layer 3. If the irradiation intensity of the concave portions 32 is lower than the irradiation intensity of the convex portions 31, the surface of the bonding layer 3 can be planarized.

[0038] The irradiation point of the laser beam LB1 is moved by a galvanometer scanner or an XYθ stage. The galvanometer scanner moves the laser beam LB1. The XYθ stage moves the first substrate 1 in the horizontal directions (X-axis direction and Y-axis direction) and rotates it around the vertical axis. Instead of the XYθ stage, an XYZθ stage may be used.

[0039] Subsequently, as shown in FIG. 9, the surface of the bonding layer 3 is further planarized by CMP or the like. Since the convex portions 31 have been selectively removed before CMP, the undulations remaining on the surface of the bonding layer 3 after CMP can be reduced.

[0040] Next, in S5 of FIG. 1, as shown in FIG. 10, the chips 2A and 2B are bonded to the second substrate 5. The second substrate 5 contacts the planarized surface of the bonding layer 3 and is bonded to the chips 2A and 2B via the bonding layer 3.

[0041] The second substrate 5 has, for example, a silicon wafer 51 and a bonding layer 53. The bonding layer 53 is an insulating layer such as a silicon oxide layer and is formed by a CVD method or the like, similar to the bonding layer 13 of the first substrate 1.

[0042] At least one of the bonding surface 54 of the second substrate 5 and the bonding surface 34 of the bonding layer 3 may be subjected to surface modification and hydrophilic treatment before bonding. The second substrate 5 and the bonding layer 3 are bonded by van der Waals forces (intermolecular forces) and hydrogen bonds between OH groups. Since solids are directly bonded to each other without using a liquid adhesive, displacement due to deformation of the adhesive or the like can be prevented. Also, the occurrence of inclination due to uneven thickness of the adhesive or the like can be prevented.

[0043] The second substrate 5 is bonded to the first substrate 1 via the bonding layer 3 with its bonding surface 54 facing downward. That is, the substrates are bonded to each other. At this time, the bonding surface 54 of the second substrate 5 is deformed into a downwardly convex curved surface to prevent air bubbles from being trapped, and is gradually bonded from the center toward the periphery and finally returns to a flat surface.

[0044] The deformation of the second substrate 5 can be realized by fixing the periphery of the second substrate 5 and pressing down the center of the second substrate 5. When deforming the second substrate 5, compared with the case of deforming the chips 2A and 2B one by one, since the distance between the fixing position and the pressing position is wide, the deformation is easy. The reason why the deformation is easy is the bonding between the substrates.

[0045] Note that the arrangement of the second substrate 5 and the first substrate 1 may be reversed, the second substrate 5 may be disposed below the first substrate 1, and the bonding surface 54 of the second substrate 5 may face upward. In this case, the bonding surface 54 of the second substrate 5 is deformed into a convex curved surface upward to prevent the inclusion of air bubbles, is gradually bonded from the center toward the periphery, and finally returns to a flat surface.

[0046] Note that the bonding of the second substrate 5 and the first substrate 1 should be gradually performed from the center toward the periphery. First, the second substrate 5 is bent and deformed, but the first substrate 1 may be bent and deformed first. Also in this case, the substrates are bonded to each other. However, it is preferable to hold the first substrate 1 flat and hold the chips 2A and 2B flat from the viewpoint of protecting the chips 2A and 2B.

[0047] Next, in S6 of FIG. 1, as shown in FIGS. 11, 12, and 13, the chips 2A and 2B are separated from the first substrate 1. In S61 of FIG. 3 included in S6 of FIG. 1, as shown in FIG. 11, a plurality of modified layers M are formed on a dividing surface D where the first substrate 1 is to be divided in the thickness direction by a laser beam LB2. The modified layer M is formed in a dot shape and is formed, for example, at or above the condensing point.

[0048] The laser beam LB2 passes through the silicon wafer 11 of the first substrate 1 and forms the modified layer M on the absorption layer 12 of the first substrate 1. The absorption layer 12 is disposed between the silicon wafer 11 and the chips 2A and 2B and absorbs the laser beam LB2. Since the laser beam LB2 hardly hits the chips 2A and 2B, damage to the chips 2A and 2B can be suppressed.

[0049] The laser beam LB2 passes through the silicon wafer 11 and the alignment mark 15 and has a wavelength of, for example, 8800 nm to 11000 nm so as to be absorbed by the absorption layer 12. The light source of the laser beam LB2 is, for example, a CO 2 laser. The wavelength of the CO 2 laser is about 9300 nm. The laser beam LB2 is pulsed.

[0050] The formation position of the modified layer M is moved by a galvanometer scanner or an XYθ stage. The galvanometer scanner moves the laser beam LB2. The XYθ stage moves the first substrate 1 in the horizontal directions (X-axis direction and Y-axis direction) and rotates it around the vertical axis. Instead of the XYθ stage, an XYZθ stage may be used.

[0051] A plurality of modified layers M are formed at intervals in the circumferential direction and the radial direction of the first substrate 1. When the modified layer M is formed, cracks CR connecting the modified layers M to each other are also formed.

[0052] In S62 included in FIG. 1, as shown in FIG. 12, the first substrate 1 is divided starting from the modified layer M. First, the upper chuck 131 holds the first substrate 1, and the lower chuck 132 holds the second substrate 5. However, the arrangement of the first substrate 1 and the second substrate 5 may be reversed up and down, and the upper chuck 131 may hold the second substrate 5 and the lower chuck 132 may hold the first substrate 1. Next, when the upper chuck 131 rises with respect to the lower chuck 132, the crack CR spreads planar starting from the modified layer M, and the first substrate 1 is divided at the division surface D.

[0053] In the above S62, with the rise of the upper chuck 131, rotation of the upper chuck 131 around the vertical axis may be performed. The first substrate 1 can be screwed at the division surface D. Instead of the rise of the upper chuck 131, or in addition to the rise of the upper chuck 131, the lowering of the lower chuck 132 may be performed. Also, rotation of the lower chuck 132 around the vertical axis may be performed.

[0054] In S6 of FIG. 1, in S63 of FIG. 3, as shown in FIG. 13, the residue 16 of the first substrate 1 attached to the chips 2A and 2B is removed by CMP or the like. The residue 16 includes a part of the absorption layer 12 and the bonding layer 13. After the removal of the residue 16, the device layers 22A and 22B of the chips 2A and 2B are exposed again. The device layers 22A and 22B are, for example, semiconductor memories.

[0055] Next, in S7 of FIG. 1, as shown in FIG. 14, the chips 2A and 2B are bonded to one side 64 including the device layer 62 of the third substrate 6 in a state of being bonded to the second substrate 5. The third substrate 6 includes a silicon wafer 61 and a device layer 62.

[0056] The device layer 62 is formed on the surface of the silicon wafer 61. The device layer 62 includes semiconductor elements, circuits, terminals, etc., and is electrically connected to the device layers 22A and 22B of the chips 2A and 2B. The device layer 62 is, for example, a peripheral circuit (also called "peripheral") of a semiconductor memory or an input / output circuit (also called "IO") of a semiconductor memory.

[0057] At least one of the bonding surface 64 of the third substrate 6 and the bonding surfaces 24A and 24B of the chips 2A and 2B may be subjected to surface modification and hydrophilic treatment before bonding. The third substrate 6 and the chips 2A and 2B are bonded by van der Waals forces (intermolecular forces) and hydrogen bonds between OH groups. Since solids are directly bonded to each other without using a liquid adhesive, displacement due to deformation of the adhesive can be prevented. Also, generation of inclination due to uneven thickness of the adhesive can be prevented.

[0058] The third substrate 6 is bonded to the second substrate 5 via the chips 2A and 2B with its bonding surface 64 facing downward. That is, the substrates are bonded together. At this time, the bonding surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface to prevent air bubbles from being trapped, and is gradually bonded from the center toward the periphery and finally returns to a flat surface.

[0059] The deformation of the third substrate 6 can be realized by fixing the periphery of the third substrate 6 and pressing the center of the third substrate 6. When deforming the third substrate 6, compared with the case of deforming the chips 2A and 2B one by one, since the distance between the fixing position and the pressing position is large, the deformation is easy. The reason why the deformation is easy is the bonding between the substrates.

[0060] Note that the arrangement of the third substrate 6 and the second substrate 5 may be reversed, the third substrate 6 may be arranged below the second substrate 5, and the bonding surface 64 of the third substrate 6 may face upward. In this case, the bonding surface 64 of the third substrate 6 is deformed into a convex curved surface upward to prevent the entrapment of air bubbles, and is gradually bonded from the center to the periphery, and finally returns to a flat surface. Also in this case, the substrates are bonded to each other.

[0061] Note that the bonding of the third substrate 6 and the second substrate 5 should be gradually performed from the center to the periphery. First, the third substrate 6 is bent and deformed, but the second substrate 5 may be bent and deformed first. Also in this case, the substrates are bonded to each other.

[0062] By the above S7, the substrate with chips 7 is obtained. The substrate with chips 7 includes the third substrate 6 and a plurality of chips 2A and 2B. The substrate with chips 7 further includes the second substrate 5. Note that the second substrate 5 may be separated from the chips 2A and 2B, and the substrate with chips 7 may include the third substrate 6 and the chips 2A and 2B.

[0063] As described above, according to the present embodiment, in order to obtain the substrate with chips 7, instead of bonding the plurality of chips 2A and 2B one by one to one side of the third substrate 6, first, they are temporarily bonded to one side of the first substrate 1. Since the entrapment of air bubbles at this stage does not pose a problem, the bonding surfaces 24A and 24B of the chips 2A and 2B can be bonded to the bonding surface 14 of the first substrate 1 while remaining flat. Since the chips 2A and 2B do not need to be deformed forcibly, the accuracy of the position control of the chips 2A and 2B can be improved, and the chips 2A and 2B can be accurately placed at the target positions.

[0064] Subsequently, a plurality of chips 2A and 2B bonded to the first substrate 1 are bonded to the opposing surface of the first substrate 1 of the second substrate 5. Subsequently, the plurality of chips 2A and 2B bonded to the first substrate 1 and the second substrate 5 are separated from the first substrate 1. Next, the plurality of chips 2A and 2B separated from the first substrate 1 are bonded to one surface 64 including the device layer 62 of the third substrate 6 in a state of being bonded to the second substrate 5.

[0065] At this time, the bonding surface 64 of the third substrate 6 is deformed into a downwardly convex curved surface in order to prevent the entrapment of air bubbles, and is gradually bonded from the center toward the periphery, and finally returns to a flat surface. Deforming the third substrate 6 is easier than deforming the chips 2A and 2B one by one. This is because it is a bonding of substrates to each other. Therefore, compared with the case of permanently bonding the chips 2A and 2B to the third substrate 6 without going through the step of temporarily bonding the chips 2A and 2B to the first substrate 1 as in the above Patent Document 1, no air bubbles are entrapped and the positional accuracy is also good, and a substrate 7 with chips can be obtained.

[0066] Further, according to the present embodiment, the silicon wafer 11 separated from the chips 2A and 2B has alignment marks 15 attached thereto. Therefore, when reusing the silicon wafer 11, it is not necessary to reform the alignment marks 15, and the alignment marks 15 can be reused. The silicon wafer 11 separated from the chips 2A and 2B is bonded to a chip different from the chips 2A and 2B.

[0067] Next, with reference to FIGS. 15A to 15F, a method for forming a Ge film, which is an alignment mark, will be described. The forming method includes first to sixth steps. In the first step, as shown in FIG. 15A, a silicon wafer 11 is prepared.

[0068] In the second step, as shown in FIG. 15B, the surface of the silicon wafer 11 is etched to form trenches. The depth of the trenches is not particularly limited, but is, for example, 100 nm.

[0069] In the third step, as shown in FIG. 15C, SiO is formed on the surface of the silicon wafer 112 Form the film 17 and fill the trench with SiO 2 film 17. The SiO 2 film 17 is formed by CVD method using, for example, TEOS (tetraethoxysilane). The SiO 2 film thickness of the film 17 is not particularly limited, but is, for example, 100 nm.

[0070] In the fourth step, as shown in FIG. 15D, the SiO 2 film 17 is planarized by CMP or the like to expose a part of the surface of the silicon wafer 11. The remaining part of the surface of the silicon wafer 11 is covered with the SiO 2 film 17. The remaining SiO 2 film thickness of the film 17 is not particularly limited, but is, for example, 100 nm.

[0071] In the fifth step, as shown in FIG. 15E, the exposed surface of the silicon wafer 11 is etched to form a trench between the SiO 2 films 17. The depth of the trench is not particularly limited, but is, for example, 100 nm.

[0072] In the sixth step, as shown in FIG. 15F, an SiGe film 15A is epitaxially grown on the bottom surface of the trench of the silicon wafer 11, and a Ge film 15B is epitaxially grown on the SiGe film 15A. An alignment mark including the SiGe film 15A and the Ge film 15B is formed. The film thickness of the SiGe film 15A is not particularly limited, but is, for example, 20 nm. The film thickness of the Ge film 15B is not particularly limited, but is, for example, 80 nm.

[0073] Table 1 shows an example of the optical characteristics of a Ge film with a film thickness of 80 nm.

[0074]

Table 1

[0075] As shown in Table 1, the Ge film with a film thickness of 80 nm has an infrared absorption rate of 59.0% for infrared rays with a wavelength of 1000 nm and can absorb the infrared rays used for imaging. Also, the Ge film with a film thickness of 80 nm has a transmittance of 63.0% for laser light with a wavelength of 9300 nm and can transmit the laser light used for forming the modified layer.

[0076] Next, a method for forming the SiGe film, which is an alignment mark, will be described. The method for forming the SiGe film is the same as the method for forming the Ge film shown in FIGS. 15A to 15F, except that in the sixth step, after epitaxially growing the SiGe film 15A with a film thickness of 100 nm, the Ge film 15B is not epitaxially grown. An alignment mark including only the SiGe film 15A is formed. The process can be shortened compared to the case where the alignment mark includes both the SiGe film 15A and the Ge film 15B. Note that the film thickness of the SiGe film 15A is not limited to 100 nm.

[0077] FIG. 16 shows an example of the optical characteristics of the SiGe film with a film thickness of 100 nm. In FIG. 16, the solid line indicates the optical characteristics of the SiGe film, and the dashed line indicates the optical characteristics of bare silicon. The SiGe film with a film thickness of 100 nm has a transmittance of about 48% for laser light with a wavelength of 9300 nm and can transmit the laser light used for forming the modified layer.

[0078] Next, with reference to FIGS. 17A to 17G, a method for forming the metal silicide film, which is an alignment mark, will be described. The forming method includes the first to seventh steps. Since the first to fourth steps shown in FIGS. 17A to 17D are the same as the first to fourth steps shown in FIGS. 15A to 15D, the description thereof will be omitted.

[0079] In the fifth step, as shown in FIG. 17E, an Ni film 18 is formed on the surface of the silicon wafer 11. The Ni film 18 covers not only the exposed surface of the silicon wafer 11 but also the surface of the SiO 2 film 17. The film thickness of the Ni film 18 is not particularly limited, but is, for example, 20 nm.

[0080] In the sixth step, as shown in FIG. 17F, the silicon wafer 11 is heated to react the silicon wafer 11 with the Ni film 18 to form the NiSi 2 film 15C. The heating temperature of the silicon wafer 11 is not particularly limited, but is, for example, 500 °C.

[0081] In the seventh step, as shown in FIG. 17G, the Ni film 18 is removed with SPM or the like to expose the NiSi 2 film 15C. SPM is an aqueous solution containing sulfuric acid and hydrogen peroxide. The mixing ratio is, for example, 1:1:5 by mass (H 2 SO 4 :H 2 O 2 :H 2 O = 1:1:5). The time for etching the Ni film 18 with SPM is, for example, 15 minutes.

[0082] An alignment mark including the NiSi 2 film 15C is formed. Note that the metal silicide is not limited to NiSi 2 and may be, for example, TiSi 2 or CoSi. The film thickness of NiSi 2 is, for example, 20 nm to 40 nm. The film thickness of TiSi 2 is, for example, 50 nm to 80 nm. The film thickness of CoSi is, for example, 30 nm to 50 nm.

[0083] FIG. 18 shows an example of the absorption rate of a TiSi 2 film having a film thickness of 210 nm. As shown in FIG. 18, the TiSi 2 film having a film thickness of 210 nm has an infrared absorption rate of about 90% at a wavelength of 1000 nm to 2000 nm and can absorb infrared rays used for imaging. Further, the TiSi 2 film having a film thickness of 210 nm has an absorption rate of about 15% for a laser beam having a wavelength of 9300 nm and can transmit the laser beam used for forming the modified layer.

[0084] In general, the thinner the film thickness, the smaller the absorption rate and the larger the transmittance. Therefore, for TiSi having a film thickness of 50 nm to 80 nm2 The film has an absorption rate of laser light with a wavelength of 9300 nm less than about 15% and can transmit the laser light used for forming the modified layer.

[0085] Next, with reference to FIGS. 19A to 19G, a method for forming an AlN film as an alignment mark will be described. The forming method includes first to seventh steps. Since the first to fifth steps shown in FIGS. 19A to 19E are the same as the first to fifth steps shown in FIGS. 15A to 15E, the description thereof will be omitted.

[0086] In the sixth step, as shown in FIG. 19F, an AlN film 15D is formed on the surface of the silicon wafer 11, and the trench is filled with the AlN film 15D. The AlN film 15D is formed, for example, by an ALD (Atomic Layer Deopsiton) method using TMA (trimethylsilane).

[0087] Specifically, a plasma - mixed gas (a mixed gas containing Ar gas and H 2 gas and N 2 gas), Ar gas, TMA gas, and Ar gas are repeatedly supplied in this order to form an AlN film. The mixing ratio of the mixed gas is, for example, 1:6:3 (Ar:H 2 :N 2 = 1:6:3) by volume. By supplying the plasma - mixed gas, NH groups are formed on the surface of the silicon wafer 11. The NH groups react with the TMA gas to form an AlN film. The AlN film formed by this method exhibits a blue color and is hereinafter also referred to as a blue AlN film. The blue AlN film contains impurities and exhibits a blue color. The film thickness of the blue AlN film is not particularly limited, but is, for example, 100 nm.

[0088] In the seventh step, as shown in FIG. 19G, the AlN film 15D is planarized by CMP or the like to expose a part of the surface of the silicon wafer 11. The remaining part of the surface of the silicon wafer 11 is covered with the AlN film 15D. The film thickness of the remaining AlN film 15D is not particularly limited, but is, for example, 100 nm. An alignment mark including the AlN film 15D is formed.

[0089] FIG. 20 shows an example of the transmittance of a blue AlN film with a film thickness of 100 nm. The blue AlN film with a film thickness of 100 nm has a transmittance of infrared rays with a wavelength of 1000 nm of about 60% and can absorb the infrared rays used for imaging. The blue AlN film has a lower transmittance of infrared rays with a wavelength of 1000 nm than a normal AlN film and is suitable as an alignment mark.

[0090] Next, with reference to FIG. 21 and the like, the substrate processing apparatus 100 that performs S61 and S62 in FIG. 3 will be described. In FIG. 21, the X-axis direction, the Y-axis direction, and the Z-axis direction are perpendicular to each other, the X-axis direction and the Y-axis direction are horizontal directions, and the Z-axis direction is a vertical direction. The substrate processing apparatus 100 includes a loading / unloading unit 101, a transfer unit 110, a laser processing unit 120, a dividing unit 130, and a control unit 140.

[0091] The loading / unloading unit 101 has a placement unit 102 on which the cassette C is placed. The cassette C houses a plurality of stacked substrates 8 at intervals in the vertical direction. The stacked substrate 8 includes a plurality of chips 2A, 2B, a first substrate 1, and a second substrate 5. As shown in FIG. 12, the stacked substrate 8 is divided into a first divided body 81 and a second divided body 82 at a dividing surface D. Thereafter, the first divided body 81 and the second divided body 82 are separately housed in the cassette C. The first divided body 81 includes a silicon wafer 11 and can be reused as a new first substrate 1 after being carried out of the substrate processing apparatus 100. An absorption layer 12 or the like may be reformed on the surface of the silicon wafer 11 for reuse as the first substrate 1. On the other hand, the second divided body 82 includes the chips 2A, 2B and is subjected to S63 in FIG. 3 and S7 in FIG. 1 and the like after being carried out of the substrate processing apparatus 100. Note that the number of the placement units 102 and the number of the cassettes C are not limited to those shown in FIG. 21.

[0092] The conveying unit 110 is arranged adjacent to the loading / unloading unit 101, the laser processing unit 120, and the splitting unit 130, and conveys the laminated substrate 8 or the like to these units. The conveying unit 110 has a holding mechanism for holding the laminated substrate 8 or the like. The holding mechanism is capable of moving in the horizontal directions (both the X-axis direction and the Y-axis direction) and the vertical direction, and rotating about the vertical axis.

[0093] As shown in FIG. 11, the laser processing unit 120 forms a plurality of modified layers M with a laser beam LB2 on a splitting surface D where the first substrate 1 is to be split in the thickness direction. The modified layers M are formed in a dot shape, for example, formed at or above the condensing point. The laser processing unit 120 includes, for example, a stage 121 for holding the first substrate 1, and an optical system 122 for irradiating the first substrate 1 held by the stage 121 with the laser beam LB2. The stage 121 is, for example, an XYθ stage or an XYZθ stage. The optical system 122 includes, for example, a condensing lens. The condensing lens condenses the laser beam LB2 toward the first substrate 1. The optical system 122 may further include a galvanometer scanner.

[0094] As shown in FIG. 12, the splitting unit 130 splits the first substrate 1 starting from the modified layer M. The splitting unit 130 includes, for example, an upper chuck 131 and a lower chuck 132. The upper chuck 131 holds the first substrate 1, and the lower chuck 132 holds the second substrate 5. However, the arrangement of the first substrate 1 and the second substrate 5 may be reversed up and down. Next, when the upper chuck 131 rises with respect to the lower chuck 132, a crack CR spreads planar starting from the modified layer M, and the first substrate 1 is split at the splitting surface D. In other words, the laminated substrate 8 is split into a first split body 81 and a second split body 82 at the splitting surface D. Along with the rising of the upper chuck 131, rotation about the vertical axis of the upper chuck 131 may be performed. The first substrate 1 can be screwed at the splitting surface D.

[0095] The control unit 140 is, for example, a computer and includes a CPU (Central Processing Unit) 141 and a storage medium 142 such as a memory as shown in FIG. 21. A program for controlling various processes executed in the substrate processing apparatus 100 is stored in the storage medium 142. The control unit 140 controls the operation of the substrate processing apparatus 100 by causing the CPU 141 to execute the program stored in the storage medium 142.

[0096] As described above, the embodiments of the method for manufacturing a substrate with chips and the substrate processing apparatus according to the present disclosure have been described, but the present disclosure is not limited to the above embodiments. Various changes, modifications, substitutions, additions, deletions, and combinations are possible within the scope described in the claims. Naturally, they also belong to the technical scope of the present disclosure.

[0097] This application claims priority based on Japanese Patent Application No. 2021-013785 filed with the Japan Patent Office on January 29, 2021, and incorporates the entire contents of Japanese Patent Application No. 2021-013785 into this application.

Explanation of Reference Numerals

[0098] 1 First substrate 2A, 2B Chips 5 Second substrate 6 Third substrate 7 Substrate with chips 8 Stacked substrate 15 Alignment mark 100 Substrate processing apparatus 110 Transfer unit 120 Laser processing unit 130 Division unit LB2 Laser beam D Division surface M Modified layer

Claims

1. Preparing a stacked substrate including a plurality of chips, a first substrate on which the plurality of chips are temporarily joined without an adhesive, and a second substrate joined to the first substrate via the plurality of chips; Separating the plurality of chips joined to the first substrate and the second substrate from the first substrate so as to join them to one side of a third substrate including a device layer; having; The first substrate separated from the chips includes alignment marks used for alignment during joining of the first substrate and the chips or for measurement of misalignment after joining; Separation of the plurality of chips from the first substrate forming a plurality of modified layers with a laser beam on a dividing surface planned to divide the first substrate in the thickness direction; dividing the first substrate starting from the plurality of modified layers; A method for manufacturing a substrate with chips, including.

2. The first substrate includes a silicon wafer and an absorption layer that absorbs the laser beam between the silicon wafer and the chips; The laser beam passes through the silicon wafer and forms the modified layer on the absorption layer. The method for manufacturing a substrate with chips according to claim 1.

3. The alignment marks are formed between the silicon wafer and the absorption layer. The method for manufacturing a substrate with chips according to claim 2.

4. The laser beam passes through the silicon wafer and the alignment marks and forms the modified layer on the absorption layer. The method for manufacturing a substrate with chips according to claim 3.

5. The alignment marks pass through the laser beam and absorb infrared rays having a wavelength different from that of the laser beam. The method for manufacturing a substrate with chips according to any one of claims 1 to 4.

6. The alignment marks include a Ge film, a SiGe film, a metal silicide film, or a blue AlN film. The method for manufacturing a substrate with chips according to claim 5.

7. The wavelength of the laser beam is 8800 nm to 11000 nm. The method for manufacturing a substrate with chips according to claim 5 or 6.

8. The wavelength of the infrared rays is 1000 nm to 2000 nm. The method for manufacturing a substrate with chips according to any one of claims 5 to 7.

9. The method for manufacturing a substrate with chips according to any one of claims 1 to 8, further comprising joining a chip different from the chips to the first substrate separated from the chips.

10. A transport unit for transporting a stacked substrate including a plurality of chips, a first substrate to which the plurality of chips are temporarily joined without an adhesive, and a second substrate joined to the first substrate via the plurality of chips, A laser processing unit that forms a plurality of modified layers on a dividing surface where the first substrate is to be divided in the thickness direction with a laser beam, A dividing unit that divides the first substrate starting from the plurality of modified layers, Comprising, The first substrate includes an alignment mark used for alignment during joining of the first substrate and the chip or measurement of misalignment after joining, The laser processing unit forms the plurality of modified layers on the dividing surface between the alignment mark and the chip, a substrate processing apparatus.

11. The first substrate includes a silicon wafer and an absorption layer that absorbs the laser beam between the silicon wafer and the chip, The laser beam passes through the silicon wafer and forms the modified layer on the absorption layer, the substrate processing apparatus according to claim 10.

12. The alignment mark is formed between the silicon wafer and the absorption layer, The laser beam passes through the silicon wafer and the alignment mark and forms the modified layer on the absorption layer, the substrate processing apparatus according to claim 11.

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