Method for manufacturing a power semiconductor device

Abstract

The active layer forming step according to an embodiment of the present invention includes the steps of preparing a SiC substrate including a first region and a second region, spraying a source gas mixed with a first doping gas, a purge gas, a reactant gas, and a purge gas in this order onto the first region of the SiC substrate to form a first active layer, and spraying a source gas mixed with a second doping gas, a purge gas, a reactant gas, and a purge gas in this order onto the second region of the SiC substrate to form a second active layer. Therefore, according to the embodiment of the present invention, the active layer can be formed at a low temperature, which prevents the substrate or the thin film formed thereon from being damaged by high temperature heat. In addition, the power or time required to heat the substrate for forming the active layer can be saved, thereby shortening the overall process time.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a power semiconductor device, and more particularly to a method for manufacturing a power semiconductor device in which an active layer is formed by atomic layer deposition.

Background Art

[0002] A field effect transistor includes an active layer formed on a substrate, source and drain electrodes formed on the upper side of the active layer, a gate electrode formed on the upper side of the active layer so as to be located between the source electrode and the drain electrode, and a well region provided between the source electrode and the drain electrode and the active layer.

[0003] The active layer is formed by a metal organic chemical vapor deposition (MOCVD) method. At this time, a thin film is deposited to form the active layer while adjusting the temperature of the substrate to a high temperature of about 1200°C. That is, when the substrate is maintained at a high temperature of about 1200°C, the active layer can be deposited on the substrate.

[0004] However, when the active layer is formed with the substrate heated to a high temperature in this way, there arises a problem that the substrate or the thin film formed on the substrate is damaged. And this acts as a factor for reducing the function of the field effect transistor or causing defects. In particular, when the field effect transistor is used for power conversion or control of an electronic device, the damage caused when the active layer is formed at a high temperature causes a significant reduction in quality or function.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] The present invention provides a method for manufacturing a power semiconductor device that can be manufactured at low temperatures.

[0007] The present invention provides a method for manufacturing a power semiconductor device that can form an active layer at low temperatures.

Means for Solving the Problems

[0008] An embodiment of the present invention is a method for manufacturing a power semiconductor including an active layer formation step of forming a first active layer and a second active layer doped with different impurities on a SiC substrate, the active layer formation step including: preparing a SiC substrate including a first region and a second region; injecting a source gas mixed with a first doping gas, a purge gas, a reactant gas, and a purge gas in this order into the first region of the SiC substrate to form a first active layer; and injecting a source gas mixed with a second doping gas, a purge gas, a reactant gas, and a purge gas in this order into the second region of the SiC substrate to form a second active layer, where the second doping gas may contain an element different from the first doping gas.

[0009] An embodiment of the present invention is a method for manufacturing a power semiconductor including an active layer formation step of forming a first active layer and a second active layer doped with different impurities on a SiC substrate, the active layer formation step including: preparing a SiC substrate including a first region and a second region; injecting a source gas, a first doping gas, a purge gas, a reactant gas, and a purge gas in this order into the first region of the SiC substrate to form a first active layer; and injecting a source gas, a second doping gas, a purge gas, a reactant gas, and a purge gas in this order into the second region of the SiC substrate to form a second active layer, where the second doping gas may contain an element different from the first doping gas.

[0010] The source gas may contain any one or two or more of Ga, In, Zn, and Si.

[0011] The reactant gas may contain any one or two or more of As, P, O, and C.

[0012] The step of forming the first and second active layers may include repeating one process cycle in which the source gas is injected, the purge gas is injected, the reactant gas is injected, and the purge gas is injected.

[0013] The step of forming the first active layer includes repeating one process cycle in which the source gas is injected, the first dopant gas is injected, the purge gas is injected, the reactant gas is injected, and the purge gas is injected. The step of forming the second active layer may include repeating one process cycle in which the source gas is injected, the second dopant gas is injected, the purge gas is injected, the reactant gas is injected, and the purge gas is injected.

[0014] The step of forming the first and second active layers may include at least one of a step of generating plasma after the step of injecting the reactant gas and a step of generating plasma between the step of injecting the source gas and the step of injecting the reactant gas.

[0015] The step of generating plasma may include a step of injecting hydrogen gas.

[0016] The method for manufacturing the power semiconductor may include a step of forming a crystalline buffer layer on the SiC substrate before the step of forming the first and second active layers.

[0017] The buffer layer may be formed of AlN.

[0018] Either one of the first and second doped gases contains Mg, and the other remaining doped gas may contain at least one of Si, In, Al, and Zn.

[0019] The method for manufacturing a power semiconductor device according to an embodiment of the present invention includes a step of preparing a SiC substrate including a first region and a second region, with a first active layer of a first conductivity type formed in the first region, and a step of injecting a source gas, a purge gas, a reactant gas, and a purge gas in this order into the second region to form a second active layer of a second conductivity type. The first conductivity type and the second conductivity type are different from each other and may be either one of the n-type and the p-type.

[0020] The first active layer is formed by injecting a source gas, a purge gas, a reactant gas, and a purge gas in this order, and the source gas injected in the step of forming the first and second active layers may contain any one or two or more of Ga, In, Zn, and Si.

[0021] The reactant gas injected in the step of forming the first and second active layers may contain any one or two or more of As, P, O, and C.

Advantages of the Invention

[0022] According to the embodiment of the present invention, an active layer can be formed at a low temperature. Therefore, it is possible to prevent the substrate or the thin film formed on it from being damaged by high-temperature heat. In addition, the power or time required to raise the temperature of the substrate for forming the active layer can be saved, and the overall process time can be shortened.

[0023] Also, the active layer can be formed by crystallization. That is, a crystallized active layer can be formed while forming the active layer at a low temperature.

Brief Description of the Drawings

[0024]

Figure 1

Figure 2

Figure 3

Figure 4

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Figure 6

Figure 7

Embodiments for Carrying Out the Invention

[0025] Hereinafter, embodiments of the present invention will be described in more detail based on the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, and can be embodied in various different forms. These embodiments are merely provided to make the disclosure of the present invention complete and to fully inform those with ordinary knowledge of the scope of the invention. The drawings may exaggerate the size for explaining the embodiments of the present invention, and in the drawings, the same reference numerals refer to the same components.

[0026] Embodiments of the present invention relate to a method for manufacturing a power semiconductor device (power semiconductor element). More specifically, the present invention relates to a method for manufacturing a power semiconductor device including a method for forming an active layer by atomic layer deposition (ALD: Atomic Layer Deposition). More specifically, the present invention relates to a method for manufacturing a power semiconductor device including a first active layer of an n-type (n-type, n-type) or p-type (p-type, p-type) and a second active layer of a type different from the first active layer, and forming the first and second active layers by atomic layer deposition. Such a power semiconductor device may be a device called a complementary metal-oxide semiconductor (CMOS: Complementary Metal-Oxide Semiconductor).

[0027] FIG. 1 is a conceptual diagram showing a substrate on which an active layer is formed by the method according to an embodiment of the present invention.

[0028] Referring to FIG. 1, the active layers 10: 10a, 10b are layers formed on the substrate S, and may be active layers constituting a power semiconductor device, more specifically, a complementary metal-oxide semiconductor device. Such an active layer 10 may be formed by atomic layer deposition (ALD). Further, when forming the active layer 10 by atomic layer deposition, after interrupting or terminating the injection of the reactant gas, plasma may be generated to form the active layer. At this time, plasma using hydrogen (H 2 ) gas (hereinafter referred to as hydrogen plasma) may be generated to form the active layer 10.

[0029] FIG. 2 is a cross-sectional view showing an example of a complementary metal-oxide semiconductor device manufactured by the method according to an embodiment of the present invention. FIG. 3 is a conceptual diagram for explaining a method for forming an active layer of a complementary metal-oxide semiconductor device by the method according to an embodiment of the present invention.

[0030] Hereinafter, with reference to FIGS. 1 to 3, a method for manufacturing a power semiconductor device including an active layer formed by the method according to an embodiment of the present invention will be described. At this time, a complementary metal-oxide semiconductor device will be described as an example.

[0031] Referring to FIG. 2, a complementary metal oxide semiconductor device manufactured by the method according to an embodiment of the present invention includes a substrate S, first and second active layers 10a and 10b formed in different regions on the substrate S and formed in different types, a first source electrode 41a and a first drain electrode 42a horizontally spaced above the first active layer 10a, a second source electrode 41b and a second drain electrode 42b horizontally spaced above the second active layer 10b, a first gate electrode 50a formed to be located between the first source electrode 41a and the first drain electrode 42a above the first active layer 10a, a second gate electrode 50b formed to be located between the second source electrode 41b and the second drain electrode 42b above the second active layer 10b, first well layers 20a formed between the first source electrode 41a and the first active layer 10a and between the first drain electrode 42a and the first active layer 10a respectively, second well layers 20b formed between the second source electrode 41b and the second active layer 10b and between the second drain electrode 42b and the second active layer 10b respectively, a first gate insulating layer 30a formed on the first active layer 10a so as to be located between the first source electrode 41a and the first drain electrode 42a, and a second gate insulating layer 30b formed on the second active layer 10b so as to be located between the second source electrode 41b and the second drain electrode 42b, and may be provided.

[0032] Here, the first and second well layers 20a and 20b formed in contact with the first and second source electrodes 41a and 41b or below the first and second source electrodes 41a and 41b may be layers that function as a source of the complementary metal oxide semiconductor device. Also, the first and second well layers 20a and 20b formed in contact with the first and second drain electrodes 42a and 42b or below the first and second drain electrodes 42a and 42b may be layers that function as a drain of the complementary metal oxide semiconductor device.

[0033] The substrate S may be a substrate containing silicon (Si), or may be a p-type substrate. More specifically, the substrate S may be a p-type SiC substrate.

[0034] As shown in FIGS. 1 and 2, a first active layer 10a and a second active layer 10b are formed on the substrate S. At this time, the first active layer 10a and the second active layer 10b are formed in different regions or at different positions on the upper surface of the substrate S. Hereinafter, for ease of explanation, among the upper surface of the substrate S, the region where the first active layer 10a is formed is referred to as the first region A 1 and the region different from the first region A 1 where the second active layer 10b is formed is referred to as the second region A 2 and is so called.

[0035] Each of the first and second active layers 10a and 10b may be formed of any one layer or thin film of gallium arsenide (GaAs), indium phosphide (InP), aluminum gallium indium phosphide (AlGaInP), indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), silicon carbide (SiC). That is, the first and second active layers 10a and 10b may be formed of any one of a GaAs layer, an InP layer, an AlGaInP layer, an IGZO layer, an IZO layer, and an SiC layer.

[0036] Then, each of the first and second active layers 10a and 10b is formed as n-type or p-type, but the first active layer 10a and the second active layer 10b are formed as different types from each other. For example, the first active layer 10a may be formed as p-type and the second active layer 10b may be formed as n-type, or the first active layer 10a may be formed as n-type and the second active layer 10b may be formed as p-type. In other words, the first active layer 10a and the second active layer 10b are formed as different conductivity types from each other. That is, when the first active layer 10a is formed as the first conductivity type which is p-type, the second active layer 10b may be formed as the second conductivity type which is n-type. As another example, when the first active layer 10a is formed as the second conductivity type which is n-type, the second active layer 10b may be formed as the first conductivity type which is p-type.

[0037] Hereinafter, when explaining the first and second active layers 10a and 10b, it will be described by taking as an example that the first active layer 10a is formed as p-type (the first conductivity type) and the second active layer 10b is formed as n-type (the second conductivity type).

[0038] The first and second active layers 10a and 10b may be formed by an atomic layer deposition (ALD) method. Further, when forming the first and second active layers 10a and 10b by the atomic layer deposition method, plasma may be generated after interrupting or terminating the injection of the reactant gas. At this time, plasma using hydrogen (H 2 ) gas (hereinafter referred to as hydrogen plasma) may be generated to form the first and second active layers 10a and 10b.

[0039] Hereinafter, a method of forming the first and second active layers 10a and 10b using the atomic layer deposition method will be described. At this time, since the doping materials of the first active layer 10a and the second active layer 10b are different from each other and their formation methods are substantially the same, the first and second active layers 10a and 10b will be collectively referred to as the active layers 10a and 10b, and their formation method will be described.

[0040] The step of forming the active layer 10 may include a step of injecting a source gas, a step of injecting a dopant gas, a step of injecting a purge gas (primary purge), a step of injecting a reactant gas, and a step of injecting a purge gas (secondary purge). And the step of forming the active layer 10 may include a step of generating plasma after the step of injecting the reactant gas. At this time, the step of generating plasma may be performed, for example, after injecting the reactant gas and after the secondary purge is completed. In such a case, the injection of the source gas, the injection of the dopant gas, the injection of the purge gas (primary purge), the injection of the reactant gas, the injection of the purge gas (secondary purge), and the generation of plasma may be performed in this order. Also, the plasma generated after the secondary purge may be hydrogen plasma. That is, when generating plasma after the completion of the secondary purge, hydrogen gas may be injected and the hydrogen gas may be discharged to generate plasma.

[0041] Also, in the step of injecting the reactant gas, plasma may be generated. That is, the reactant gas may be injected and the reactant gas may be discharged to generate plasma.

[0042] When forming the active layer 10, the above-mentioned "source gas injection - dopant gas injection - purge gas injection (primary purge) - reactant gas injection - purge gas injection (secondary purge) - plasma generation" may be regarded as one process cycle (Cycle) for forming the active layer 10. Also, by repeating the above-mentioned process cycle a plurality of times, atomic layer deposition is performed a plurality of times. And by adjusting the number of times the process cycle should be performed, the active layer 10 with a target layer thickness can be formed.

[0043] In the process cycle as described above, if a reactant gas is injected after the injection of the source gas, the injection of the dopant gas, and the injection of the purge gas (primary purge), a reaction between the source gas and the reactant gas occurs on the substrate S, and a reaction product, for example, AlGaInP, is generated. Then, this reaction product is deposited or vapor-deposited on the substrate S, and thus, a thin film made of AlGaInP is formed on the substrate S. Also, depending on the type of the dopant gas to be injected, a p-type AlGaInP thin film or an n-type AlGaInP thin film is formed.

[0044] On the other hand, conventionally, when depositing a thin film to form an active layer on a substrate, the temperature inside the chamber or the substrate was maintained at a high temperature of about 1200°C. In other words, unless the temperature inside the chamber or the substrate is maintained at a high temperature of 1200°C, the thin film cannot be deposited on the upper surface of the substrate. Thus, when forming the active layer at a high temperature, there is a risk that the substrate or the thin film formed on the substrate may be damaged, and there is also a risk that the active layer may be damaged. For this reason, there is a problem that the function or quality of the device deteriorates.

[0045] However, in the embodiment, when depositing a thin film using the atomic layer deposition method, plasma is generated. That is, plasma, for example, hydrogen plasma, is generated after the injection of the reactant gas or after the completion of the injection of the reactant gas. More specifically, after the injection of the reactant gas and the injection of the purge gas (secondary purge) are completed, plasma using hydrogen gas is generated.

[0046] At this time, the plasma can improve the reaction rate between the source gas and the reactant gas, and enable the reaction product of the source gas and the reactant gas to be easily deposited or adhered to the substrate S. Therefore, it becomes possible to form the active layer 10 by atomic layer deposition in a state where the temperature inside the chamber 100 or the substrate S is low, for example, 600 °C or lower. More preferably, the active layer 10 may be formed by atomic layer deposition at a temperature of 300 °C or higher and 550 °C or lower. That is, unlike the conventional method, the active layer 10 can be formed at a low temperature without heating the substrate to a high temperature. For this reason, damage to the substrate S, the thin film formed on the substrate, or the active layer 10 due to high heat can be prevented.

[0047] In addition, the plasma can make the thin film deposited on the substrate S crystalline by the reaction between the source gas and the reactant gas. More specifically, a polycrystalline active layer 10 can be formed. That is, when forming the active layer 10 by atomic layer deposition, by generating plasma after injecting the reactant gas, a crystalline or polycrystalline active layer 10 can be formed by the plasma.

[0048] In addition, the plasma can make it easier to decompose and remove impurities remaining inside the chamber 100. Therefore, contamination by impurities can be prevented or suppressed when forming the deposited film, that is, the active layer 10.

[0049] In the above, the injection of the dope gas after the injection of the source gas was described. That is, it was described that the source gas and the dope gas are injected separately in different stages. However, the present invention is not limited to this at all, and the source gas and the dope gas may be mixed and injected. That is, the source gas and the dope gas may be mixed, and the mixed gas (hereinafter referred to as the mixed gas) may be injected in the injection step of the source gas. In such a case, "injection of the mixed gas - plasma generation - injection of the purge gas (primary purge) - injection of the reactant gas - injection of the purge gas (secondary purge) - plasma generation" may be regarded as one process cycle.

[0050] Also, in the above, the generation of plasma after the end of the secondary purge or after the injection of the reactant gas was described. However, the present invention is not limited to this at all, and hydrogen plasma may be generated in the step between the injection of the source gas and the injection of the reactant gas. More specifically, hydrogen plasma may be generated between the injection step of the source gas and the primary purge step. That is, "injection of the source gas - plasma generation - injection of the purge gas (primary purge) - injection of the reactant gas - injection of the purge gas (secondary purge)" may be regarded as one process cycle.

[0051] As another example, hydrogen plasma may be generated between the primary purge step and the reactant gas injection step. For this reason, "injection of the source gas - injection of the purge gas (primary purge) - plasma generation - injection of the reactant gas - injection of the purge gas (secondary purge)" may be regarded as one process cycle.

[0052] As another example, plasma may be generated at each of the steps between the source gas injection and the reactant injection and after the reactant gas injection step. That is, "source gas injection - plasma generation - purge gas injection (primary purge) - reactant gas injection - purge gas injection (secondary purge) - plasma generation" may be used as a process cycle, or alternatively, "source gas injection - purge gas injection (primary purge) - plasma generation - reactant gas injection - purge gas injection (secondary purge) - plasma generation" may be used as a process cycle.

[0053] When forming the active layer 10 by the process cycle as described above, the substances of the source gas and the reactant gas may be determined according to the type of the active layer 10 to be formed.

[0054] The active layer 10 may be formed from any one of a GaAs layer, an InP layer, an AlGaInP layer, an IGZO layer, an IZO layer, and a SiC layer. In such a case, the source gas may be a gas containing any one of Ga, In, Zn, and Si, or alternatively, a gas containing two or more of them. That is, the source gas may be a gas containing any one or two or more of a gas containing Ga, a gas containing In, a gas containing Al, Ga, and In (AlGaIn-containing gas), a gas containing In, Ga, and Zn (IGZ-containing gas), a gas containing In and Zn (IZ-containing gas), and a gas containing Si. Further, the reactant gas may be a gas containing any one or two or more of As, P, O, and C. That is, the reactant gas may be a gas containing any one or two or more of an As-containing gas, a P-containing gas, an O-containing gas, and a C-containing gas.

[0055] For example, when forming a GaAs layer as the active layer 10, a gas containing Ga can be used as the source gas, and a gas containing As can be used as the reactant gas. Also, when forming an InP layer as the active layer 10, a gas containing In can be used as the source gas, and a gas containing P can be used as the reactant gas. To give another example, when forming an AlGaInP layer as the active layer 10, a gas containing Al, a gas containing Ga, and a gas containing In can be used as the source gas, and a gas containing P can be used as the reactant gas. To give yet another example, when forming an IGZO layer as the active layer 10, a gas containing In, a gas containing Ga, and a gas containing Zn can be used as the source gas, and a gas containing O can be used as the reactant gas. And when forming an IZO layer as the active layer 10, a gas containing In and a gas containing Zn can be used as the source gas, and a gas containing O can be used as the reactant gas. Also, when forming an SiC layer as the active layer 10, a gas containing Si can be used as the source gas, and a gas containing C can be used as the reactant gas.

[0056] Here, as the Ga-containing gas, for example, a gas containing trimethyl gallium (Ga(CH 3 )) 3 (TMGa) can be used. As the In-containing gas, for example, a gas containing at least one of trimethyl indium (In(CH 3 )) 3 (TMIn) and diethylamino propyl dimethyl indium (DADI) can be used. Also, as the Al-containing gas, for example, a gas containing TMA (trimethyl aluminum, (Al(CH 3 )) 3 ) can be used. As the Zn-containing gas, diethyl zinc (Zn(C 2 H5 ) 2 (DEZ) and dimethyl zinc (Zn(CH 3 ) 2 (DMZ), at least one of which can be used. As the Si-containing gas, for example, SiH 4 , Si 2 H 6 A gas containing at least one of them can be used.

[0057] Also, as the As-containing gas, a gas containing either AsH 3 or AsH 4 can be used. As the P-containing gas, for example, a gas containing phosphine (PH 3 ) can be used. Also, the O-containing gas may be oxygen. As the C-containing gas, for example, a gas containing SiH 3 CH 3 can be used.

[0058] As described above, when forming the active layer 10 of the GaAs layer, a Ga-containing gas is used as the source gas. When forming the active layer 10 of the InP layer, an In-containing gas is used as the source gas. When forming the active layer 10 of the SiC layer, a Si-containing gas is used as the source gas. Therefore, when forming the active layer 10 from any one of the GaAs layer, InP layer, and SiC layer, it can be explained that one type of source gas is used.

[0059] As another example, when forming the active layer 10 of the AlGaInP layer, three types of gases, namely, an Al-containing gas, a Ga-containing gas, and an In-containing gas, are used as the source gas. As another example, when forming the active layer 10 from the IGZO layer, three types of gases, namely, an In-containing gas, a Ga-containing gas, and a Zn-containing gas, are used as the source gas. Therefore, when forming the active layer 10 from the AlGaInP layer or the IGZO layer, it can be explained that two or more types of source gases are used.

[0060] When forming the active layer 10 using or injecting a plurality of types of source gases, a source gas mixture of the plurality of types of source gases may be injected to form the active layer 10. A specific description of the method of mixing and injecting a plurality of types of source gases will be given again when describing the vapor deposition apparatus hereinafter.

[0061] The doping gas may be injected after the injection of the source gas, or may be injected after being mixed with the source gas. At this time, the gas to be doped may be determined according to the type of the active layer 10 to be formed. For example, when attempting to form a p-type active layer 10, a gas containing Mg can be used as the doping gas, and when attempting to form an n-type active layer 10, a gas containing Si can be used as the doping gas. Here, as the doping gas containing Mg, Cp 2 A gas containing Mg can be used, and as the doping gas containing Si, for example, polysilane (H 3 Si-(SiH 2 ) n -SiH 3 )-containing gas can be used. Further, the second doping gas may be a further mixture of one or more gases among Si, In, Al, and Zn.

[0062] Then, the above-described process cycle is repeated a plurality of times to form the active layer 10. At this time, in the first, i.e., the first process cycle for forming the active layer 10, it may be performed without the step of injecting the doping gas. That is, the process cycle performed for the first time for forming the active layer 10 may be "injection of source gas - injection of purge gas (primary purge) - injection of reactant gas - injection of purge gas (secondary purge) - plasma generation", and when injecting the source gas, the doping gas may be injected together or the doping gas may not be injected separately. Then, from the next time onwards, the doping gas may be injected after injecting the source gas, or the doping gas may be injected together when injecting the source gas. Therefore, when the active layer 10 is formed on the active layer 10, the thin film deposited by the first process cycle is an undoped thin film, and the thin film deposited by the process cycle performed thereafter may be a doped thin film.

[0063] Needless to say, the doping gas may be injected from the first, i.e., the first process cycle to form the active layer 10.

[0064] As shown in FIG. 2, the active layer 10 may be provided in a stepped shape such that the surface heights are different. In other words, it can be explained that the active layer 10 includes a first layer 11 formed on the upper surface of the substrate S and a second layer 12 formed in a partial region of the first layer 11. Therefore, the thickness of the region of the active layer 10 where the second layer 12 is formed may be thicker than other regions. In other words, the active layer 10 may be provided in a shape where the height of the region where the second layer 12 is formed is higher than the portion where only the first layer 11 is formed, i.e., a stepped shape.

[0065] The shape of the active layer is not limited to the stepped shape as described above, and may be provided in any shape as long as well layers 20a and 20b can be provided between the source electrodes 41a and 41b and the active layers 10a and 10b, and between the drain electrodes 42a and 42b and the active layers 10a and 10b.

[0066] The first and second well layers 20a and 20b may usually be layers referred to as well regions in a complementary metal-oxide semiconductor device. At this time, since the well regions are formed on the active layers 10a and 10b by atomic layer deposition, for ease of explanation, they are referred to as well layers 20a and 20b. Such well layers 20a and 20b may be provided so as to be located between the source and drain electrodes and the active layer. More specifically, the first well layer 20a is provided between the first source electrode 41a and the first active layer 10a, and between the first drain electrode 42a and the first active layer 10a, and the second well layer 20b is provided between the second source electrode 41b and the second active layer 10b, and between the second drain electrode 42b and the second active layer 10b. For this reason, as shown in FIG. 2, the first well layer 20a may be provided so as to be located between the first layer 11 of the first active layer 10a and the first source electrode 41a, and between the first layer 11 and the first drain electrode 42a. Also, the second well layer 20b may be provided so as to be located between the first layer 11 of the second active layer 10b and the second source electrode 41b, and between the first layer 11 and the second drain electrode 42b. And the first and second well layers 20a and 20b may be formed by atomic layer deposition.

[0067] The first and second well layers 20a and 20b may be provided such that the same material as the active layer 10 is doped with n-type or p-type impurities. For example, when the first active layer 10a is formed of p-type AlGaInP, the first well layer 20a may be provided as an n-type by doping AlGaInP with an impurity such as Si, or when the second active layer 10b is formed of n-type AlGaInP, the second well layer 20b may be provided as a p-type by doping AlGaInP with an impurity such as Mg. Therefore, it can be explained that the first well layer 20a is an n-type AlGaInP layer doped with Si, and the second well layer 20b is a p-type AlGaInP layer doped with Mg.

[0068] Hereinafter, a method of forming the first and second well layers 20a and 20b using atomic layer deposition will be described. At this time, since the first well layer 20a and the second well layer 20b differ only in the doping material and their formation methods are substantially the same, the first and second well layers 20a and 20b will be collectively referred to as well layers 20a and 20b, and their formation method will be described.

[0069] The well layer 20 may be formed by atomic layer deposition. That is, the well layer 20 may be formed using "source gas injection - dopant gas injection - purge gas injection (primary purge) - reactant gas injection - purge gas injection (secondary purge)" as a process cycle. At this time, the source gas, dopant gas, reactant gas, and purge gas injected for the formation of the well layer 20 may be of the same type as the gas used in the formation of the active layer 10.

[0070] And the doping gas for forming the well layer 20 may be mixed with the source gas and injected. That is, the source gas and the doping gas may be mixed, and this mixed gas may be injected in the injection step of the source gas. In such a case, "injection of the mixed gas - plasma generation - injection of the purge gas (primary purge) - injection of the reactant gas - injection of the purge gas (secondary purge)" may be used as one process cycle for forming the well layer 20.

[0071] Also, when forming the well layer 20, plasma may be generated during the injection of the reactant gas, or plasma may be further generated after the secondary purge. And the plasma generated after the secondary purge may be a hydrogen plasma.

[0072] The well layer 20 formed in this way functions as source and drain regions in a complementary metal - oxide - semiconductor device. That is, the first and second well layers 20a, 20b formed under the first and second source electrodes 41a, 41b function as the source of the complementary metal - oxide - semiconductor device, and the first and second well layers 20a, 20b formed under the first and second drain electrodes 42a, 42b function as the drain of the complementary metal - oxide - semiconductor device.

[0073] The gate insulating layers 30:30a, 30b may be formed on top of the active layers 10:10a, 10b. That is, the first gate insulating layer 30a may be formed on top of the first active layer 10a, and the second gate insulating layer 30b may be formed on top of the second active layer 10b. More specifically, with respect to the vertical direction, the first gate insulating layer 30a may be formed to be positioned between the first gate electrode 50a and the first active layer 10a, and the second gate insulating layer 30b may be formed to be positioned between the second gate electrode 50b and the second active layer 10b. Also, with respect to the width direction, the first gate insulating layer 30a may be formed to be positioned between the first source electrode 41a and the first drain electrode 42a, and the second gate insulating layer 30b may be formed to be positioned between the second source electrode 41b and the second drain electrode 42b. And the first gate insulating layer 30a is formed such that the periphery of the lower surface is positioned on top of the pair of first well layers 20a and the rest is positioned on top of the first active layer 10a, and the second gate insulating layer 30b is formed such that the periphery of the lower surface is positioned on top of the pair of second well layers 20b and the rest is positioned on top of the second active layer 10b. For this reason, the periphery of the first gate insulating layer 30a and the periphery of the pair of first well layers 20a may overlap, and the periphery of the second gate insulating layer 30b and the periphery of the pair of second well layers 20b may overlap.

[0074] Such first and second gate insulating layers 30a, 30b may be formed from a high-k (high dielectric constant) thin film having a higher dielectric constant than silicon dioxide (SiO 2 ). More specifically, the first and second gate insulating layers 30a, 30b are aluminum oxide (AlO x ), titanium oxide (TiO x ), magnesium oxide (MgO x ), zirconium oxide (ZrO x ), hafnium silicon oxide (HfSiO x ), and lanthanum silicon oxide (LaSiO x) may be made from any one of these or a combination of two or more thereof, where "x" may be 1 to 3. Needless to say, the first and second gate insulating layers 30a and 30b are not limited to the above examples at all, and may be formed from various other high dielectric constant materials having a higher dielectric constant than silicon dioxide (SiO 2 ).

[0075] The source electrodes 41a and 41b and the drain electrodes 42a and 42b may be formed on the active layers 10a and 10b and the well layers 20a and 20b such that the gate insulating layers 30a and 30b and the gate electrodes 50a and 50b are located therebetween. That is, the first source electrode 41a and the first drain electrode 42a may be formed on the respective upper portions of a pair of first well layers 20a such that the first gate insulating layer 30a and the first gate electrode 50a are located therebetween. In other words, with the first gate insulating layer 30a as a reference, the first source electrode 41a may be formed on one side and the first drain electrode 42a may be formed on the other side. Also, the second source electrode 41b and the second drain electrode 42b may be formed on the respective upper portions of a pair of second well layers 20b such that the second gate insulating layer 30b and the second gate electrode 50b are located therebetween. That is, with the second gate insulating layer 30b as a reference, the second source electrode 41b may be formed on one side and the second drain electrode 42b may be formed on the other side.

[0076] The first and second source electrodes 41a and 41b and the first and second drain electrodes 42a and 42b are formed from a material containing a metal, and may be formed from, for example, at least one of the materials of Ti and Au. Also, the first and second source electrodes 41a and 41b and the first and second drain electrodes 42a and 42b may be formed by, for example, chemical vapor deposition (CVD method), metal organic chemical vapor deposition (MOCVD) method, atomic layer deposition (ALD) method, sputtering deposition method, etc.

[0077] The gate electrodes 50a and 50b may be formed on the upper portions of the gate insulating layers 30a and 30b. In other words, the first gate electrode 50a may be formed on the upper portion of the first gate insulating layer 30a so as to be positioned between the first source electrode 41a and the first drain electrode 42a, and the second gate electrode 50b may be formed on the upper portion of the second gate insulating layer 30b so as to be positioned between the second source electrode 41b and the second drain electrode 42b. At this time, the first and second gate electrodes 50a and 50b may be formed of a material containing a metal, for example, a material containing at least one of Ti and Au. Further, the first and second gate electrodes 50a and 50b may be formed by a sputtering deposition method.

[0078] FIG. 4 is a conceptual diagram showing a modified example in which a buffer layer is formed between the active layer and the substrate. FIG. 5 is a diagram showing an example of a complementary metal oxide semiconductor element according to a modified example of the embodiment.

[0079] Referring to FIGS. 4 and 5, a buffer layer 60 may be formed between the substrate S and the first and second active layers 10a and 10b. Then, as shown in FIG. 5, the complementary metal oxide semiconductor element according to the modified example may include a buffer layer 60 formed between the substrate S and the first and second active layers 10a and 10b. That is, the complementary metal oxide semiconductor element according to the modified example is different in that it includes a buffer layer 60 formed between the first and second active layers 10a and 10b and the substrate S as compared with the embodiment, and other configurations may be the same.

[0080] The buffer layer 60 is a layer that is formed on the substrate S prior to the formation of the first and second active layers 10a and 10b, and may be a seed layer that assists the first and second active layers 10a and 10b formed by atomic layer deposition to crystallize more effectively. In other words, the buffer layer 60 may be a seed layer that further assists the crystallization of the first and second active layers 10a and 10b in addition to crystallization by hydrogen plasma when forming the first and second active layers 10a and 10b by atomic layer deposition. Such a buffer layer 60 may be formed of AlN and may be formed by atomic layer deposition, chemical vapor deposition method, or the like.

[0081] If the first and second active layers 10a and 10b are deposited by atomic layer deposition on the crystalline buffer layer 60, the first and second active layers 10a and 10b can grow in the crystal direction of the buffer layer 60 which is the underlying layer. Therefore, crystalline, more specifically, polycrystalline active layers 10a and 10b can be formed more easily.

[0082] FIG. 6 is a diagram schematically showing a vapor deposition apparatus used in a method for manufacturing a power semiconductor device according to an embodiment of the present invention.

[0083] The vapor deposition apparatus may be an apparatus for depositing a thin film by atomic layer deposition (ALD). At this time, the vapor deposition apparatus may be an apparatus for forming at least the first and second active layers 10a and 10b among the components of a power semiconductor device, for example, a complementary metal oxide semiconductor device. Further, the vapor deposition apparatus may be an apparatus for forming the first and second active layers 10a and 10b and the first and second well layers 20a and 20b.

[0084] Such a vapor deposition apparatus may include a chamber 100, a support table 200 disposed in the chamber 100 for supporting a substrate S, an injection unit 300 disposed to face the support table 200 and injecting a gas for a process (hereinafter referred to as a process gas) into the chamber 100, a gas supply unit 400 for providing the process gas to the injection unit 300, first and second gas supply pipes 500a and 500b connected to the injection unit 300 so as to have different paths and supplying the gas provided from the gas supply unit 400 to the injection unit 300, and an RF power supply unit 600 for supplying power to generate plasma in the chamber 100.

[0085] Further, the vapor deposition apparatus may further include a driving unit 700 for causing the support table 200 to perform at least one of a lifting operation and a rotating operation, and an exhaust unit (not shown) disposed to be connected to the chamber 100.

[0086] The chamber 100 may have an internal space in which a thin film can be formed on the substrate S carried therein. For example, the cross-sectional shape thereof may be a quadrangle, a pentagon, a hexagon, or the like. Needless to say, the internal shape of the chamber 100 can be variously deformed and is preferably provided to correspond to the shape of the substrate S.

[0087] The support table 200 is disposed in the chamber 100 so as to face the injection unit 300 and supports the substrate S loaded into the chamber 100. A heater 210 may be provided inside such a support table 200. Therefore, when the heater 210 is operated, the substrate S placed on the support table 200 and the inside of the chamber 100 can be heated.

[0088] In addition to the heater 210 provided on the support table 200, as a means for heating the inside of the substrate S or the chamber 100, a separate heater may be provided inside or outside the chamber 100.

[0089] The injection unit 300 has a plurality of holes (hereinafter referred to as holes 311) juxtaposed so as to be separated from each other in the extending direction of the support base 200, and is arranged to face the support base 200 inside the chamber 100. A first plate 310, a plurality of nozzles 320 provided so that at least a part thereof is fitted into each of the plurality of holes 311, and a second plate 330 disposed so as to be located between the upper wall in the chamber 100 and the first plate 310 inside the chamber 100. It may be provided with.

[0090] Further, the injection unit 300 may further include an insulating portion 340 located between the first plate 310 and the second plate 330.

[0091] Here, the first plate 310 may be connected to the RF power supply unit 600, and the second plate 330 may be grounded. And the insulating part 340 can play the role of preventing the electrical connection between the first plate 310 and the second plate 330.

[0092] The first plate 310 may be a plate-like one extending in the extending direction of the support base 200. And a plurality of holes 311 are provided in the first plate 310, and each of the plurality of holes 311 may be provided so as to penetrate the first plate 310 in the vertical direction. And the plurality of holes 311 may be arranged in the extending direction of the first plate 310 or the support base 200.

[0093] Each of the plurality of nozzles 320 may have a shape extending in the vertical direction, and a passage through which gas can pass is provided inside thereof, and may have a shape with an upper end and a lower end opened. And each of the plurality of nozzles 320 may be arranged such that at least the lower part thereof is fitted into the hole 311 provided in the first plate 310 and the upper part is connected to the second plate 330. For this reason, it can be explained that the nozzle 320 has a shape protruding from the second plate 330 to the lower part.

[0094] The outer diameter of the nozzle 320 may be provided to be smaller than the inner diameter of the hole 311. When the nozzle 320 is fitted inside the hole 311, the outer peripheral surface of the nozzle 320 may be arranged to be separated from the peripheral wall of the hole 311 (that is, the inner side wall of the first plate 310). Therefore, the inside of the hole 311 can be partitioned into the outer space of the nozzle 320 and the inner space of the nozzle 320.

[0095] In the internal space of the hole 311, the passage in the nozzle 320 is a passage through which the gas provided from the first gas supply pipe 500a moves and is injected. And the outer space of the nozzle 320 in the internal space of the hole 311 is a passage through which the gas provided from the second gas supply pipe 500b moves and is injected. Therefore, hereinafter, the passage in the nozzle 320 is referred to as the first path 360a, and the outer space of the nozzle 320 inside the hole 311 is referred to as the second path 360b.

[0096] The second plate 330 may be arranged such that its upper surface is separated from the upper wall in the chamber 100 and its lower surface is separated from the first plate 310. For this reason, it becomes possible to provide empty spaces (empty spaces) respectively between the second plate 330 and the first plate 310 and between the second plate 330 and the upper wall of the chamber 100.

[0097] Here, the upper space of the second plate 330 is a space (hereinafter referred to as the diffusion space 350) through which the gas provided from the first gas supply pipe 500a diffuses and moves, and may communicate with the upper openings of the plurality of nozzles 320. In other words, the diffusion space 350 is a space that communicates with the plurality of first paths 360a. For this reason, the gas that has passed through the first gas supply pipe 500a can diffuse in the extending direction of the second plate 330 in the diffusion space 350 and then be injected downward through the plurality of first paths 360a.

[0098] In addition, a deep hole (not shown), which is a passage for gas to move, is provided inside the second plate 330. The deep hole may be connected to the second gas supply pipe 500b and provided to communicate with the second path 360b. Therefore, the gas provided from the second gas supply pipe 500b can be jetted toward the substrate S through the deep hole of the second plate 330 and the second path 360b.

[0099] The gas supply unit 400 provides the gas necessary for depositing a thin film by atomic layer deposition. Such a gas supply unit 400 may include a source gas storage unit 410 in which source gas is stored, a reactant gas storage unit 420 in which a reactant gas that reacts with the source gas is stored, a purge gas storage unit 430 in which purge gas is stored, a first transfer pipe 470a disposed to connect the source gas storage unit 410 and the first gas supply pipe 500a, and a second transfer pipe 470b disposed to connect the reactant gas storage unit 420 and the purge gas storage unit 430 and the second gas supply pipe 500b.

[0100] Here, the purge gas stored in the purge gas storage unit 430 may be, for example, N 2 gas or Ar gas.

[0101] In addition, the gas supply unit 400 may include a plasma generation gas storage unit 440 in which gas (hereinafter referred to as plasma generation gas) supplied in the step of generating plasma inside the chamber 100 after the injection of the reactant gas or after the secondary purge is stored. At this time, the plasma generation gas may be, for example, hydrogen gas.

[0102] And the gas supply unit 400 may include a dopant gas storage unit 450 in which dopant gas is stored, and a mixing unit 460 disposed in the first transfer pipe 470a so as to mix a plurality of types of gas.

[0103] Further, the gas supply unit 400 may include a plurality of first connection pipes 480a connecting the source gas storage unit 410 and the dopant gas storage unit 450 to the first transfer pipe 470a respectively, valves disposed in each of the plurality of first connection pipes 480a, a plurality of second connection pipes 480b connecting the reactant gas storage unit 420, the purge gas storage unit 430, and the gas storage unit 440 for plasma generation to the second transfer pipe 470b respectively, and valves disposed in each of the plurality of second connection pipes 480b.

[0104] The source gas storage unit 410 may be provided in plurality, and different types of source gases may be stored in the plurality of source gas storage units 410: 410a, 410b, 410c. Then, the first connection pipe 480a may be connected to each of the plurality of source gas storage units 410a, 410b, 410c, and the first connection pipe 480a connected to each of the plurality of source gas storage units 410a, 410b, 410c may be connected to the first transfer pipe 470a.

[0105] The dopant gas storage unit 450 may be provided in plurality, and different types of dopant gases may be stored in the plurality of dopant gas storage units 450: 450a, 450b. Then, the first connection pipe 480a may be connected to each of the plurality of dopant gas storage units 450a, 450b, and the first connection pipe 480a connected to each of the plurality of dopant gas storage units 450a, 450b may be connected to the first transfer pipe 470a.

[0106] The mixing unit 460 may be a means for mixing the gases provided from the plurality of source gas storage units 410a, 410b, 410c, or for mixing the gas provided from at least any one of the plurality of source gas storage units 410a, 410b, 410c and the gas provided from either one of the plurality of dopant gas storage units 450a, 450b. Such a mixing unit 460 may be provided so as to have an internal space in which the gases can be mixed. Further, the mixing unit 460 may be arranged so as to connect a first connection pipe 480a connected to each of the plurality of source gas storage units 410a, 410b, 410c and the plurality of dopant gas storage units 450a, 450b and a first transfer pipe 470a. For this reason, after the plurality of types of gases flowing into the mixing unit 460 are mixed inside the mixing unit 460, they can be transferred to a first gas supply pipe 500a via the first transfer pipe 470a.

[0107] FIG. 7 is a diagram schematically showing another example of a vapor deposition apparatus used in the method for manufacturing a power semiconductor device according to an embodiment of the present invention. The vapor deposition apparatus for forming at least one of the first and second active layers 10a, 10b and the first and second well layers 20a, 20b of the power semiconductor device according to the embodiment is not limited to the apparatus shown in FIG. 6, and the vapor deposition apparatus shown in FIG. 7 may be used.

[0108] Referring to FIG. 7, the vapor deposition apparatus includes a chamber 100, a support table 200 disposed in the chamber 100 for supporting a substrate S, first and second gas injection units 300a, 300b disposed inside the chamber 100 so as to face the support table 200, respectively, a gas supply unit 400 for supplying a process gas to the first and second gas injection units 300a, 300b, an antenna 610 including a coil for inducing an electric field in the chamber 100 for generating plasma, and a power supply unit 620 connected to the antenna 610.

[0109] Further, the vapor deposition apparatus may include a heating unit 500 disposed to face the support base 200, a driving unit 700 for raising and lowering or rotating the support base 200, and an exhaust unit 800 for exhausting the gas and impurities inside the chamber 100.

[0110] The chamber 100 may have a cylindrical internal space in which a thin film can be formed on the substrate S carried therein, for example, it may be dome-shaped as shown in FIG. 7. More specifically, the chamber 100 may include a chamber body 110, an upper body 120 disposed above the chamber body 110, and a lower body 130 disposed below the chamber body 110. The chamber body 110 may be cylindrical with upper and lower openings, the upper body 120 may be disposed to cover the upper opening of the chamber body 110, and the lower body 130 may be disposed to cover the lower opening of the chamber body 110. And the upper body 120 may be dome-shaped having a slope whose height gradually increases as it progresses toward the center in the width direction. Also, the lower body 130 may be dome-shaped having a slope whose height decreases as it progresses toward the center in the width direction. Such a chamber 100, that is, each of the chamber body 110, the upper body 120, and the lower body 130 may be made of a transparent material that can transmit light, for example, it may be made of quartz.

[0111] The gas supply unit 400 may be provided in the same configuration as described in FIG. 6. That is, the gas supply unit 400 may include a source gas storage unit 410 in which the source gas is stored, a reactant gas storage unit 420 in which the reactant gas that reacts with the source gas is stored, a purge gas storage unit 430 in which the purge gas is stored, a first transfer pipe 470a disposed to connect the source gas storage unit 410 and the first gas injection unit 300a, and a second transfer pipe 470b disposed to connect the reactant gas storage unit 420 and the purge gas storage unit 430 and the second gas injection unit 300b.

[0112] Further, the gas supply unit 400 may include a plasma generation gas storage unit 440 that stores a gas (hereinafter referred to as a plasma generation gas) that is supplied in the step of generating plasma inside the chamber 100 after the injection of the reactant gas or after the secondary purge. At this time, the plasma generation gas may be, for example, hydrogen gas.

[0113] And the gas supply unit 400 may include a dopant gas storage unit 450 that stores a dopant gas, and a mixing unit 460 disposed in the first transfer pipe 470a so as to mix a plurality of types of gases.

[0114] Further, the gas supply unit 400 may include a plurality of first connection pipes 480a that connect the source gas storage unit 410 and the dopant gas storage unit 450 to the first transfer pipe 470a, respectively, valves disposed in each of the plurality of first connection pipes 480a, a plurality of second connection pipes 480b that connect the reactant gas storage unit 420, the purge gas storage unit 430, and the plasma generation gas storage unit 440 to the second transfer pipe 470b, respectively, and valves disposed in each of the plurality of second connection pipes 480b.

[0115] The antenna 610 may be disposed above the upper body 120 of the chamber 100. At this time, the antenna 610 may be provided in a spiral shape wound around a plurality of turns, or may be configured to include a plurality of circular coils arranged concentrically and connected to each other. Needless to say, the antenna 610 is not limited to a spiral coil or a concentric circular coil, and various antennas having other shapes can be adopted.

[0116] A power supply unit 620 may be connected to one of both ends of the antenna 610, and the other end may be connected to a ground terminal. Therefore, if a power supply, for example, an RF power supply, is supplied to the antenna 610 via the power supply unit 620, the gas injected into the chamber 100 is ionized or discharged to generate plasma inside the chamber 100.

[0117] The heating unit 500 is a means for heating the interior of the chamber 100 and the support base 200, and may be disposed outside the chamber 100. More specifically, the heating unit 500 may be disposed such that at least a part thereof faces the support base 200 on the lower side outside the chamber 100. Such a heating unit 500 may be a means including a plurality of lamps, and the plurality of lamps may be arranged side by side in the width direction of the support base 200. And the plurality of lamps may include lamps such as halogen lamps that emit radiant heat.

[0118] Hereinafter, with reference to FIGS. 2 and 3, a method for manufacturing a power semiconductor device according to an embodiment of the present invention will be described. At this time, the description will be made using the vapor deposition apparatus of FIG. 6, and a complementary metal oxide semiconductor device will be taken as an example.

[0119] First, the heater 210 provided on the support base 200 is operated to heat the support base 200. At this time, the heater is operated so that the temperature of the support base 200 or the substrate S to be placed on the support base 200 becomes the process temperature, for example, 500°C to 520°C.

[0120] Next, a substrate S, for example, a substrate S made of SiC, is loaded into the chamber 100 and placed on the support base 200. At this time, the substrate S may be provided with one or more substrates on the support base 200. After that, when the substrate S placed on the support base 200 reaches the target process temperature, for example, 500°C to 520°C, the first and second active layers 10a and 10b are formed on the substrate S.

[0121] At this time, the first and second active layers 10a and 10b are formed using atomic layer deposition. The atomic layer deposition is performed in the order of injection of source gas, injection of dopant gas, injection of purge gas (primary purge), injection of reactant gas, injection of purge gas (secondary purge). At this time, plasma is generated inside the chamber 100 after the secondary purge. That is, the process cycle for forming the first and second active layers 10a and 10b by atomic layer deposition may be "injection of source gas - injection of dopant gas - injection of purge gas (primary purge) - injection of reactant gas - injection of purge gas (secondary purge) - plasma generation". Then, the above-described process cycle is repeated a plurality of times to form the first and second active layers 10a and 10b with a target layer thickness.

[0122] Hereinafter, a method for forming the first and second active layers 10a and 10b by injecting process gas into the chamber 100 using the injection unit 300 and the gas supply unit 400 will be described in more detail. At this time, a case of forming a p-type first active layer 10a made of AlGaInP and an n-type second active layer 10b made of AlGaInP will be described as an example.

[0123] Also, a description will be given of forming either one of the first active layer 10a and the second active layer 10b, for example, forming the first active layer 10a first and then forming the second active layer 10b.

[0124] For the formation of the first active layer 10a, the first region A of the substrate S is exposed above the substrate S placed on the support base 200 1 and a mask for shielding the second region A 2 is disposed. Here, the mask may be a shadow mask provided with an opening in a region corresponding to the first region A of the substrate S 1 .

[0125] If a mask is disposed above the substrate S, a source gas is injected into the interior of the chamber 100. For this purpose, the Al-containing gas stored in the first source gas reservoir 410, the Ga-containing gas stored in the second source gas reservoir 410, and the In-containing gas stored in the third source gas reservoir 410 are each supplied to the mixing section 460. Thus, inside the mixing section 460, three types of source gases, namely, the Al-containing gas, the Ga-containing gas, and the In-containing gas, are mixed.

[0126] The mixed source gas flows into the diffusion space 350 in the injection section 300 through the first transfer pipe 470a and the first gas supply pipe 500a. Then, after diffusing in the diffusion space 350, the mixed source gas passes through a plurality of nozzles 320, that is, a plurality of first paths 360a, and is injected toward the substrate S. Then, the injected source gas passes through the opening of the mask and then is adsorbed onto the first region A 1 on the upper surface of the substrate S.

[0127] If the injection of the source gas is interrupted or terminated, a first doping gas is provided through the first doping gas reservoir 450a, and the first doping gas is injected into the interior of the chamber 100. At this time, the first doping gas may be an Mg-containing gas, and more specifically, a gas containing Cp 2 Mg can be used. The first doping gas discharged from the first doping gas reservoir 450a may be injected downward through the first connection pipe 480a, the first transfer pipe 470a, the first gas supply pipe 500a, and then through the first path 360a. The injected first doping gas may pass through the opening of the mask and then be adsorbed onto the first region A 1 on the upper surface of the substrate S.

[0128] If the injection of the first doping gas is interrupted or terminated, purge gas is provided through the purge gas reservoir 430 to inject the purge gas into the chamber 100 (primary purge). At this time, the purge gas discharged from the purge gas reservoir 430 may be injected downward through the second connection pipe 480b, the second transfer pipe 470b, and the second gas supply pipe 500b, and then through the second path 360b.

[0129] Next, a reactant gas, for example, a P-containing gas, is provided from the reactant gas reservoir 420 and injected into the chamber 100. At this time, the reactant gas may be injected into the chamber 100 through the same path as the purge gas. That is, the reactant gas may be injected downward through the second connection pipe 480b, the second transfer pipe 470b, and the second gas supply pipe 500b, and then through the second path 360b. The injected reactant gas passes through the opening of the mask and reaches the first region A 1 of the substrate S. And the reactant gas that reaches the first region A 1 reacts with the source gas adsorbed on the first region A 1 so that a reaction product, that is, AlGaInP, can be generated. Then, this reaction product is deposited or vapor-deposited on the substrate S, and thus, a thin film made of AlGaInP is formed on the substrate S. At this time, an AlGaInP thin film doped with Mg by the first doping gas, that is, a p-type AlGaInP thin film, is formed.

[0130] Thus, when the reactant gas is injected into the chamber 100, the RF power supply unit 600 may be operated to supply RF power to the first plate 310. If RF power is supplied to the first plate 310, plasma can be generated in the second path 360b in the injection unit 300 and the space between the first plate 310 and the support base 200.

[0131] If the injection of the reactant gas is interrupted, purge gas is provided through the purge gas reservoir 430 to inject the purge gas into the chamber 100 (secondary purge). At this time, by-products and the like due to the reaction of the source gas and the reactant gas can be discharged outside the chamber 100 by the secondary purge.

[0132] When the secondary purge is completed, gas, for example, hydrogen gas, is provided from the gas reservoir 440 for plasma generation, and the RF power supply is operated to supply the RF power supply to the first plate 310. For this reason, plasma using hydrogen gas, that is, hydrogen plasma, is generated inside the chamber 100.

[0133] Through the process cycle performed in the order of "injection of source gas, injection of first dopant gas, injection of purge gas (primary purge), injection of reactant gas, injection of purge gas (secondary purge), plasma generation" as described above, the first region A of the substrate S 1 The first active layer 10a is formed thereon. At this time, the first active layer 10a may be made of an AlGaInP thin film doped with Mg, that is, a p-type AlGaInP thin film.

[0134] And the process cycle performed in the order of "injection of source gas, injection of first dopant gas, injection of purge gas (primary purge), injection of reactant gas, injection of purge gas (secondary purge), plasma generation" may be repeated a plurality of times. Then, the number of times the process cycle should be performed may be determined according to the target layer thickness of the first active layer 10a.

[0135] In this way, by generating plasma inside the chamber 100 after the injection of the reactant gas or after the secondary purge, the first active layer 10a can be formed on the substrate S even at a low temperature of 600 °C or lower. In addition, a crystalline, more specifically, polycrystalline first active layer 10a can be formed.

[0136] Once the first active layer 10a with the target layer thickness is formed, the second active layer 10b is then formed. For this purpose, the second region A of the substrate S is exposed on the upper side of the substrate S on which the first active layer 10a is formed 2 and a mask for shielding the first region A 1 is arranged. Here, the mask may be a shadow mask provided with an opening in a region corresponding to the second region A of the substrate S 2 .

[0137] Once the mask is arranged on the upper side of the substrate S, a thin film is deposited in the same manner as when the first active layer 10a is formed to form the second active layer 10b. However, the thin film is deposited using a doping gas different from that used when the first active layer 10a is formed. In other words, the thin film is deposited using a second doping gas containing an element different from the first doping gas containing Mg. At this time, the process cycle of "injecting the source gas, injecting the second doping gas, injecting the purge gas (primary purge), injecting the reactant gas, injecting the purge gas (secondary purge), generating plasma" is repeated a plurality of times to form the second active layer 10b. Here, the source gas, purge gas, and reactant gas may be of the same type as those used when the first active layer 10a is formed. And the second doping gas is provided from the second doping gas storage unit 450b, and a gas containing Si, for example, a gas containing polysilane (H 3 Si-(SiH 2 ) n -SiH 3 ) can be used.

[0138] In this way, by the process cycle performed in the order of "injecting the source gas, injecting the second doping gas, injecting the purge gas (primary purge), injecting the reactant gas, injecting the purge gas (secondary purge), generating plasma", the second active layer 10b is formed on the second region A of the substrate S 2 . At this time, the second active layer 10b can be composed of an AlGaInP thin film doped with Si, that is, an n-type AlGaInP thin film.

[0139] Further, the second doping gas may be a mixture of one or more gases among Si, In, Al, and Zn.

[0140] And the above-described process cycle including the step of injecting the second doping gas may be repeated a plurality of times. At this time, the number of times the process cycle should be performed may be determined according to the target layer thickness of the second active layer 10b.

[0141] Once the target layer thicknesses of the first and second active layers 10a and 10b are formed, a part of each of the first and second active layers 10a and 10b is etched. For example, in the regions outside the central regions in the width directions of the first and second active layers 10a and 10b, the first and second active layers 10a and 10b with a predetermined layer thickness are etched. For this purpose, for example, masks are provided to close the central regions of the first and second active layers 10a and 10b respectively and open a part of the regions outside the central regions, and the masks are disposed on the upper sides of the first and second active layers 10a and 10b. Then, etching gas is injected from the upper sides of the first and second active layers 10a and 10b to etch a part of the first and second active layers 10a and 10b exposed in the open regions. At this time, etching is performed so that the first and second active layers 10a and 10b facing the open regions of the masks can remain at the target layer thickness. At this time, the etching gas may be SF 6 , Cl 2 , CF 4 or O 2 At least one or a combination of two of these gases and plasma may be applied and used for etching.

[0142] By such etching, it is possible to provide recesses or wells that are recessed from the upper surface to the opposite side in each of the first and second active layers 10a and 10b. That is, a pair of first recesses spaced apart in the width direction may be provided in the first active layer 10a, and a pair of second recesses spaced apart in the width direction may be provided in the second active layer 10b. At this time, the pair of first recesses provided in the first active layer 10a are provided at positions facing the subsequently formed first source electrode 41a and first drain electrode 42a, and the pair of second recesses provided in the second active layer 10b may be provided at positions facing the subsequently formed second source electrode 41b and second drain electrode 42b. Therefore, each of the first and second active layers 10a and 10b can have a shape including a first layer 11 formed on the upper surface of the substrate S and a second layer 12 formed outside the recess on the upper part of the first layer 11. That is, the first and second active layers 10a and 10b can have a shape in which the height of the region where the second layer 12 is formed is higher than the portion where only the first layer 11 is formed, that is, a stepped shape.

[0143] As described above, the step of etching a part of the active layers 10a and 10b may be performed in a device separate from the vapor deposition device shown in FIG. 6. And the device in which etching is performed may be a device connected in-situ with the vapor deposition device.

[0144] When the etching is completed, a first well layer 20a is formed on the first layer 11 of the first active layer 10a, and a second well layer 20b is formed on the first layer 11 of the second active layer 10b. In other words, the first well layer 20a is formed inside the pair of first recesses provided in the first active layer 10a by etching, and the second well layer 20b is formed inside the pair of second recesses provided in the second active layer 10b by etching. The first and second well layers 20a and 20b may be formed, for example, by atomic layer deposition, or may be formed using the same vapor deposition device as when the active layers 10a and 10b are formed.

[0145] Next, a method for forming the first and second well layers 20a and 20b will be described, and a method for forming them using the vapor deposition apparatus shown in FIG. 6 will be described. At this time, a case where the first well layer 20a is formed from an n-type AlGaInP layer and the second well layer 20b is formed from a p-type AlGaInP layer will be described as an example.

[0146] First, a method for forming the first well layer 20a will be described. A mask with an opening provided in a region facing a pair of first recesses provided in the first active layer 10a and the rest closed is disposed above the substrate S.

[0147] Next, source gas is injected into the chamber 100. For this purpose, the Al-containing gas stored in the first source gas storage unit 410, the Ga-containing gas stored in the second source gas storage unit 410, the In-containing gas stored in the third source gas storage unit 410, and the Si-containing gas stored in the dopant gas storage unit 450 are each supplied to the mixing unit 460. For this reason, the Al-containing gas, the Ga-containing gas, the In-containing gas, and the Si-containing gas are mixed inside the mixing unit 460. The mixed gas passes through the first transfer pipe 470a, the first gas supply pipe 500a, and the first path 360a of the injection unit 300 and is injected toward the substrate S. The injected gas passes through the opening of the mask and reaches a pair of first recesses provided in the first active layer 10a, and then is adsorbed by the first recesses.

[0148] When the injection of the source gas is interrupted or terminated, a second dopant gas is provided via the second dopant gas storage unit 450b, and the second dopant gas is injected into the chamber 100. At this time, the second dopant gas may be a Si-containing gas. More specifically, polysilane (H 3 Si-(SiH 2 ) n -SiH 3A gas containing ) can be used. The second dopant gas discharged from the second dopant gas storage unit 450b may be injected downward through the first connection pipe 480a, the first transfer pipe 470a, and the first gas supply pipe 500a and then through the first path 360a. After passing through the opening of the mask, the injected second dopant gas can reach a pair of first recesses provided in the first active layer 10a.

[0149] After that, purge gas is provided from the purge gas storage unit 430, and the purge gas is injected into the chamber 100 through the second path 360b of the injection unit 300 (primary purge).

[0150] Next, a reactant gas, for example, a P-containing gas, is provided from the reactant gas storage unit 420 and injected into the chamber 100 through the second path 360b of the injection unit 300. At this time, an RF power source may be supplied to the first plate 310 to generate plasma.

[0151] When the reactant gas is injected, a reaction occurs between the source gas adsorbed in the first recess and the reactant gas, and a reaction product, that is, AlGaInP, can be generated. At this time, since the second dopant gas is injected after the source gas is injected, the reaction product becomes an Si-doped AlGaInP thin film. Therefore, a first well layer 20a made of an n-type AlGaInP thin film can be formed in the first recess of the first active layer 10a. In other words, a first well layer 20a made of an n-type AlGaInP thin film can be formed in a pair of well regions provided in the first active layer 10a by etching. In still other words, a first well layer 20a made of an n-type AlGaInP thin film can be formed on the first layer 11 of the first active layer 10a.

[0152] Also, the second dopant gas may be a mixture of one or more gases among Si, In, Al, and Zn.

[0153] Once the injection of the reactant gas is completed, purge gas is provided from the purge gas storage unit 430 and injected into the chamber 100 (secondary purge).

[0154] Once the secondary purge is completed, a step of generating plasma inside the chamber 100 may be added. That is, a gas, for example, hydrogen gas, is provided from the gas storage unit 440 for plasma generation, the hydrogen gas is injected into the chamber 100, and an RF power source is supplied to the first plate 310. As a result, plasma using hydrogen gas, that is, hydrogen plasma, is generated inside the chamber 100.

[0155] After that, the process cycle of "source gas injection, second dopant gas injection, purge gas injection (primary purge), reactant gas injection, purge gas injection (secondary purge), plasma generation" is performed multiple times to form the first well layer 20a with the target layer thickness.

[0156] Once the first well layer 20a with the target layer thickness is formed, then the second well layer 20b is formed. For this purpose, an opening is provided in a region facing a pair of second recesses provided in the second active layer 10b, and a mask with the rest closed is placed above the substrate S.

[0157] Once the mask is placed above the substrate S, a thin film is deposited in the second recess in the same manner as when forming the first well layer 20a to form the second well layer 20b. However, the thin film is deposited using a dopant gas different from that used when forming the first well layer 20a. That is, the thin film is deposited using a first dopant gas containing an element different from the second dopant gas containing Si. At this time, the process cycle of "source gas injection, first dopant gas injection, purge gas injection (primary purge), reactant gas injection, purge gas injection (secondary purge), plasma generation" is repeated multiple times to form the second well layer 20b.

[0158] Here, the source gas, purge gas, and reactant gas may be of the same type as those used when forming the first well layer 20a. And the first doping gas is provided from the first doping gas reservoir 450a, and a gas containing Mg, for example, Cp 2 A gas containing Mg can be used.

[0159] Through the process cycle performed in the order of "source gas injection, first doping gas injection, purge gas injection (primary purge), reactant gas injection, purge gas injection (secondary purge), plasma generation", the second well layer 20b is formed in a pair of second recesses provided in the second active layer 10b. At this time, the second well layer 20b can be made of an AlGaInP thin film doped with Mg, that is, a p-type AlGaInP thin film.

[0160] And the above-described process cycle including the first doping gas injection step may be repeated a plurality of times, and the number of times the process cycle should be performed may be determined according to the target layer thickness of the second well layer 20b.

[0161] In the above, when forming the first and second well layers 20a and 20b, the generation of plasma after the secondary purge has been described. However, the present invention is not limited thereto, and the step of generating plasma after the secondary purge may be omitted.

[0162] Once the first and second well layers 20a and 20b with the target layer thickness are formed, the first and second active layers 10a and 10b, and the gate insulating layers 30a and 30b positioned above the first and second well layers 20b are formed. That is, the first gate insulating layer 30a is formed on top of the first active layer 10a and the first well layer 20a, and the second gate insulating layer 30b is formed on top of the second active layer 10b and the second well layer 20b. At this time, the first gate insulating layer 30a is formed such that the periphery of the lower surface is positioned above the pair of first well layers 20a, and the rest is positioned above the first active layer 10a between the pair of first well layers 20a. Also, the second gate insulating layer 30b is formed such that the periphery of the lower surface is positioned above the pair of second well layers 20b, and the rest is positioned above the second active layer 10b between the pair of second well layers 20b. At this time, the first and second gate insulating layers 30a and 30b may be formed of, for example, Al 2 O 3 and may be formed by any one of chemical vapor deposition, metal-organic chemical vapor deposition, and atomic layer deposition methods.

[0163] Next, the first and second source electrodes 41a and 41b and the first and second drain electrodes 42a and 42b are formed. That is, the first source electrode 41a is formed on top of either one of the pair of first well layers 20a, and the first drain electrode 42a is formed on top of the remaining other first well layer 20a. Also, the second source electrode 41b is formed on top of either one of the pair of second well layers 20b, and the second drain electrode 42b is formed on top of the remaining other second well layer 20b.

[0164] Then, gate electrodes 50a and 50b are formed on top of each of the first and second gate insulating layers 30a and 30b. At this time, the gate electrodes 50a and 50b may be fabricated from the same material and in a similar manner as the source and drain electrodes 41a, 41b, 42a, and 42b. For example, the gate electrodes 50a and 50b may be formed of at least one of the materials Ti and Au and may be formed by sputtering deposition.

[0165] Thus, according to the method for manufacturing a power semiconductor device according to the embodiment, the active layers 10:10a, 10b can be formed at a low temperature. Therefore, it is possible to prevent the thin film formed on the substrate S or on top of it from being damaged by high-temperature heat. Also, the power or time required to raise the temperature of the substrate S for forming the active layer 10 can be saved, and the overall process time can be shortened.

[0166] Also, the active layer 10 can be formed by crystallization. That is, even while forming the active layer 10 at a low temperature, a crystallized active layer can be formed.

Industrial Applicability

[0167] According to the embodiment of the present invention, the active layer can be formed at a low temperature. Therefore, it is possible to prevent the thin film formed on the substrate or on top of it from being damaged by high-temperature heat. Also, the power or time required to raise the temperature of the substrate for forming the active layer can be saved, and the overall process time can be shortened.

[0168] Also, the active layer can be formed by crystallization. That is, even while forming the active layer at a low temperature, a crystallized active layer can be formed.

Claims

1. A method for manufacturing a power semiconductor, comprising an active layer forming step of forming a first active layer and a second active layer doped with different impurities on a SiC substrate, wherein the active layer forming step includes: preparing a SiC substrate including a first region and a second region; injecting a source gas, a purge gas, a reactant gas, and a purge gas in this order into the first region of the SiC substrate to form a first active layer; injecting a source gas, a purge gas, a reactant gas, and a purge gas in this order into the second region of the SiC substrate to form a second active layer; and the steps of forming the first and second active layers include: repeating a plurality of times a single process cycle in which injection of the source gas, injection of the purge gas, injection of the reactant gas, and injection of the purge gas are performed in this order; when repeating the process cycle to form the first active layer, in the process cycle performed after the first process cycle, a first doping gas is mixed with the source gas and injected, and in the first process cycle, the source gas without the first doping gas is injected; when repeating the process cycle to form the second active layer, in the process cycle performed after the first process cycle, a second doping gas is mixed with the source gas and injected, and in the first process cycle, the source gas without the second doping gas is injected; wherein the second doping gas contains an element different from the first doping gas, a method for manufacturing a power semiconductor device.

2. A method for manufacturing a power semiconductor, comprising an active layer forming step of forming a first active layer and a second active layer doped with different impurities on a SiC substrate, wherein the active layer forming step includes: preparing a SiC substrate including a first region and a second region; injecting a source gas, a purge gas, a reactant gas, and a purge gas in this order into the first region of the SiC substrate to form a first active layer; injecting a source gas, a purge gas, a reactant gas, and a purge gas in this order into the second region of the SiC substrate to form a second active layer; and the step of forming the first active layer includes: performing a first process cycle in which injection of the source gas, injection of the purge gas, injection of the reactant gas, and injection of the purge gas are performed in this order; A step of repeatedly performing a plurality of times one process cycle that is performed after the first process cycle and is performed in the order of injection of source gas, injection of first dopant gas, injection of purge gas, injection of reactant gas, and injection of purge gas; comprising; The step of forming the second active layer: A step of performing a first process cycle that is performed in the order of injection of source gas, injection of purge gas, injection of reactant gas, and injection of purge gas; A step of repeatedly performing a plurality of times one process cycle that is performed after the first process cycle and is performed in the order of injection of source gas, injection of second dopant gas, injection of purge gas, injection of reactant gas, and injection of purge gas; comprising; The second dopant gas contains an element different from the first dopant gas, a method for manufacturing a power semiconductor device.

3. The source gas contains any one or two or more of Ga, In, Zn, and Si, the method for manufacturing a power semiconductor device according to claim 1 or claim 2.

4. The reactant gas contains any one or two or more of As, P, O, and C, the method for manufacturing a power semiconductor device according to claim 1 or claim 2.

5. The steps of forming the first and second active layers: The method for manufacturing a power semiconductor device according to claim 1 or claim 2, including at least one of a step of generating plasma after the step of injecting the reactant gas and a step of generating plasma between the step of injecting the source gas and the step of injecting the reactant gas.

6. The step of generating plasma includes a step of injecting hydrogen gas, the method for manufacturing a power semiconductor device according to claim 5.

7. Before the steps of forming the first and second active layers, including a step of forming a crystalline buffer layer on the SiC substrate, the method for manufacturing a power semiconductor device according to claim 1 or claim 2.

8. The buffer layer is formed of AlN, the method for manufacturing a power semiconductor device according to claim 7.

9. Either one of the first and second dopant gases contains Mg, The remaining other dopant gas contains at least one of Si, In, Al, and Zn, the method for manufacturing a power semiconductor device according to claim 1 or claim 2.

10. The step of forming the first and second active layers The method for manufacturing a power semiconductor device according to claim 1 or 2, including the step of discharging the reactant gas to generate plasma.

11. The step of forming the first and second active layers The method for manufacturing a power semiconductor device according to claim 10, including at least one of the step of generating plasma after the step of injecting the reactant gas and the step of generating plasma between the step of injecting the source gas and the step of injecting the reactant gas.

12. The step of preparing a SiC substrate including a first region and a second region, with a first active layer of a first conductivity type formed in the first region The step of repeatedly performing a plurality of process cycles of injecting a source gas, a purge gas, a reactant gas, and a purge gas in this order into the second region to form a second active layer of a second conductivity type including The first active layer is formed by repeatedly performing a plurality of process cycles of injecting a source gas, a purge gas, a reactant gas, and a purge gas in this order When repeatedly performing a plurality of process cycles to form the first active layer, in the process cycle performed after the primary process cycle, a first doping gas is mixed into the source gas, or the first doping gas is injected between the step of injecting the source gas and the step of injecting the reactant gas, and in the primary process cycle, the first doping gas is not injected When repeatedly performing a plurality of process cycles to form the second active layer, in the process cycle performed after the primary process cycle, a second doping gas is mixed into the source gas, or the second doping gas is injected between the step of injecting the source gas and the step of injecting the reactant gas, and in the primary process cycle, the second doping gas is not injected The second doping gas contains an element different from the first doping gas, the first conductivity type and the second conductivity type are different from each other, and the method for manufacturing a power semiconductor device is either n-type or p-type.

13. The manufacturing method of the power semiconductor device according to claim 12, wherein the source gas injected in the step of forming the first and second active layers contains any one or more of Ga, In, Zn, and Si.

14. The manufacturing method of the power semiconductor device according to claim 13, wherein the reactant gas injected in the step of forming the first and second active layers contains any one or more of As, P, O, and C.

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