Semiconductor device

Abstract

To provide a semiconductor storage device which does not require high voltage in writing, generates fewer defects, and requires shorter time in writing, and in which data cannot be rewritten without increasing cost.SOLUTION: The semiconductor storage device includes a first transistor connected to a diode, a second transistor with a gate connected to one terminal of a source electrode and a drain electrode of the first transistor connected to the diode, and a memory element with a capacitor connected to the gate of the second transistor and to the one terminal of the source electrode and the drain electrode of the first transistor connected to the diode.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a semiconductor memory device and a method for manufacturing the same.

Background Art

[0002] In recent years, many of various electronic devices such as computers operate by using various data. These data can be used temporarily or permanently by being held in, for example, a semiconductor memory device (also referred to as a memory).

[0003] A semiconductor memory device, in a broad sense, also includes an external storage device (auxiliary storage device) such as a hard disk and a flexible disk, but most often means a semiconductor memory device such as a CPU (Central Processing Unit).

[0004] Semiconductor memory devices can be classified into volatile memories and non-volatile memories. A volatile memory is a semiconductor memory device in which data is lost when the power is turned off. Also, a non-volatile memory is a semiconductor memory device that continues to hold data even after the power is turned off, and can hold the data semi-permanently after the data is written.

[0005] Although there is a possibility that data is lost in a volatile memory, it has the merit of short access time. Also, a non-volatile memory has the demerit of high power consumption although it can hold data. As described above, semiconductor memory devices each have characteristics, and each semiconductor memory device is used appropriately according to the type or application of data to be handled.

[0006] Among non-volatile memories, there is a write-protected ROM (Read Only Memory) There are various types such as flash memories and EEPROMs (Electrically Erasable and Programmable Read Only Memories) that can be written and erased multiple times. Among them, the write-once memory that can be written only once is preferable in terms of security because data tampering is difficult to occur. cally Erasable and Programmable Read Onl y Memory), etc. Among them, the write-once memory that can be written only once is preferable in terms of security because data tampering is difficult to occur. As an example of a write-once memory, there is an anti-fuse type memory in which a voltage is applied to both ends of an element using amorphous silicon to form a silicide on the electrodes and short-circuit them. Also, by providing a memory area that is not erased while using a rewritable memory such as a flash memory or EEPROM, it may be logically used as a write-once memory (see Patent Document 1).

[0007] As an example of a write-once memory, there is an anti-fuse type memory in which a voltage is applied to both ends of an element using amorphous silicon to form a silicide on the electrodes and short-circuit them. Also, by providing a memory area that is not erased while using a rewritable memory such as a flash memory or EEPROM, it may be logically used as a write-once memory (see Patent Document 1). As an example of a write-once memory, there is an anti-fuse type memory in which a voltage is applied to both ends of an element using amorphous silicon to form a silicide on the electrodes and short-circuit them. Also, by providing a memory area that is not erased while using a rewritable memory such as a flash memory or EEPROM, it may be logically used as a write-once memory (see Patent Document 1). As an example of a write-once memory, there is an anti-fuse type memory in which a voltage is applied to both ends of an element using amorphous silicon to form a silicide on the electrodes and short-circuit them. Also, by providing a memory area that is not erased while using a rewritable memory such as a flash memory or EEPROM, it may be logically used as a write-once memory (see Patent Document 1). As an example of a write-once memory, there is an anti-fuse type memory in which a voltage is applied to both ends of an element using amorphous silicon to form a silicide on the electrodes and short-circuit them. Also, by providing a memory area that is not erased while using a rewritable memory such as a flash memory or EEPROM, it may be logically used as a write-once memory (see Patent Document 1). As an example of a write-once memory, there is an anti-fuse type memory in which a voltage is applied to both ends of an element using amorphous silicon to form a silicide on the electrodes and short-circuit them. Also, by providing a memory area that is not erased while using a rewritable memory such as a flash memory or EEPROM, it may be logically used as a write-once memory (see Patent Document 1).

Prior Art Documents

Patent Documents

[0008]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0009] However, conventional write-once memories have a problem that high-voltage writing is required. In a write-once memory, in order to give a permanent change to the memory element, it is necessary to apply a voltage larger than the voltage used in the read operation. For example, in the case of a silicide type write-once memory that uses silicide as a memory element during writing, a voltage of 6 to 8 However, conventional write-once memories have a problem that high-voltage writing is required. In a write-once memory, in order to give a permanent change to the memory element, it is necessary to apply a voltage larger than the voltage used in the read operation. For example, in the case of a silicide type write-once memory that uses silicide as a memory element during writing, a voltage of 6 to 8 However, conventional write-once memories have a problem that high-voltage writing is required. In a write-once memory, in order to give a permanent change to the memory element, it is necessary to apply a voltage larger than the voltage used in the read operation. For example, in the case of a silicide type write-once memory that uses silicide as a memory element during writing, a voltage of 6 to 8 However, conventional write-once memories have a problem that high-voltage writing is required. In a write-once memory, in order to give a permanent change to the memory element, it is necessary to apply a voltage larger than the voltage used in the read operation. For example, in the case of a silicide type write-once memory that uses silicide as a memory element during writing, a voltage of 6 to 8 However, conventional write-once memories have a problem that high-voltage writing is required. In a write-once memory, in order to give a permanent change to the memory element, it is necessary to apply a voltage larger than the voltage used in the read operation. For example, in the case of a silicide type write-once memory that uses silicide as a memory element during writing, a voltage of 6 to 8 When used, a voltage of 15 to 18 V is required. To generate such a high potential, a boost circuit is necessary, which increases the power consumption during writing. Also, to apply a high voltage to the memory element, it is necessary to apply a high-potential voltage to the peripheral circuits such as the decoder during writing. As a result, in order to increase the breakdown voltage so that the peripheral circuits can withstand the high voltage, it is necessary to increase the channel length, form an LDD region, etc., which increases the

[0010] number of manufacturing steps and hinders high integration. Also, in the case of a silicide-type write-once memory, due to insufficient write voltage or the like, there may be a short state with a high resistance (a state where the resistance is so high that it is not recognized as data 1 described later during the read operation). An

[0011] element in the short state with a high resistance becomes a defective element in substance. Also, in the case of a silicide-type write-once memory, it is not possible to write to multiple memory cells simultaneously, and it is difficult to write to many memory

[0012] elements in a short time. Also, in the case of a flash memory or EEPROM, it is possible to write to multiple memory cells simultaneously, but the write time is about 100 μs, which is long. In the case of a flash memory or EEPROM that can be used as a write-once memory by the In addition, a malicious user may cause the logic circuit to malfunction, resulting in a write-once message. There is a risk that the data in the memory may be tampered with.

[0013] In view of the above, one embodiment of the present invention is to provide a method for writing data without requiring a high voltage for writing data without increasing costs. A semiconductor memory device that is not prone to defects, has a short write time, and cannot be rewritten. The objective of the present invention is to provide a place where [Means for solving the problem]

[0014] One aspect of the present invention is a diode-connected first transistor and a diode-connected first A second transistor having a gate connected to one of the source and drain electrodes of the transistor. The semiconductor memory device includes a memory element having a first transistor. One of the source and drain terminals of the first transistor is connected to the diode-connected first transistor. A parasitic capacitance is formed between the source electrode of the transistor and one of the drain electrodes.

[0015] In addition, one embodiment of the present invention is a diode-connected first transistor and a diode-connected A second transistor having a gate connected to one of the source and drain electrodes of the first transistor. The second transistor and the source electrode and drain electrode of the first transistor connected in diode connection A memory element having a capacitance element connected to one terminal of the electrode and the gate of the second transistor. The semiconductor memory device includes a

[0016] When the second transistor is in an on-state, i.e., when a voltage higher than the threshold voltage is applied to the gate, When the gate is in the off state, that is, when a voltage lower than the threshold voltage is applied, the data is written. When voltage is applied to the gate, data is not written. One of the source and drain terminals of the first transistor functions as an anode. In addition, the channel region of the diode-connected first transistor is made of an oxide semiconductor. By forming it, 1×10 -19 A / μm or less, even 1×10 -20 A / μm or less Therefore, the second current that is increased by writing data can be reduced. The potential of the gate of the transistor or the potential of the second transistor raised by writing data The potential of the gate and the capacitance element leaks from the diode-connected first transistor. In other words, the potential of the gate of the second transistor can be maintained. The data can be retained.

[0017] For this reason, the write voltage is set to a voltage that can turn on the second transistor, i.e., It is possible to set the write voltage to be equal to or higher than the threshold voltage of the transistor, and the write voltage can be reduced. In addition, it is not necessary to provide a boost circuit for the write voltage, and power consumption during writing can be reduced. It is possible to reduce the power dissipation, and to increase the channel length and LDD region shape to increase the breakdown voltage. This eliminates the need for a separate memory cell, making it possible to reduce the size of the memory element and achieve high integration.

[0018] In addition, unlike silicide-type write-once memory, the memory element is made of a transistor. Since the above-mentioned method can be used to form the semiconductor memory device, write failures can be reduced.

[0019] In the semiconductor memory device according to one aspect of the present invention, the write time is The on-state current of the first transistor is determined by the on-state current of the second transistor and the capacitance of the capacitance element. With a current of 10 -6 A. Even if the capacitance of the capacitive element is 1 pF, writing is completed in about 1 μs. Also, it is possible to write to multiple memory elements simultaneously. Therefore, the writing time is significantly shortened.

[0020] Also, since the memory cell included in the semiconductor memory device according to one embodiment of the present invention is a write-once memory, data rewriting due to malfunction of the logic circuit does not occur. Also, by only changing the wiring layout of the memory element of the write-once memory, a rewritable memory can also be formed. Therefore, a semiconductor memory device in which a rewritable memory and a write-once memory are mixed can also be manufactured. From these facts, the data retention safety of the semiconductor memory device can be enhanced.

Advantages of the Invention

[0021] A semiconductor memory device that does not require a high voltage for writing, is less likely to cause defects, has a short writing time, and cannot rewrite data can be manufactured without increasing costs.

Brief Description of the Drawings

[0022]

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Embodiments for Carrying Out the Invention

[0023] Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the aspects and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In describing the configuration of the present invention with reference to the drawings, the same reference numerals are commonly used among different drawings to indicate the same components. It is not limited to the following description, and it will be easily understood by those skilled in the art that the aspects and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In describing the configuration of the present invention with reference to the drawings, the same reference numerals are commonly used among different drawings to indicate the same components. It is not limited to the following description, and it will be easily understood by those skilled in the art that the aspects and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In describing the configuration of the present invention with reference to the drawings, the same reference numerals are commonly used among different drawings to indicate the same components. It is not limited to the following description, and it will be easily understood by those skilled in the art that the aspects and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In describing the configuration of the present invention with reference to the drawings, the same reference numerals are commonly used among different drawings to indicate the same components. When describing the configuration of the present invention with reference to the drawings, the same reference numerals are commonly used among different drawings to indicate the same components. Hereinafter, embodiments of the present invention will be described with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the aspects and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments shown below. In describing the configuration of the present invention with reference to the drawings, the same reference numerals are commonly used among different drawings to indicate the same components.

[0024] In the drawings and the like of each embodiment, the size, layer thickness, or region of each configuration shown may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. In the drawings and the like of each embodiment, the size, layer thickness, or region of each configuration shown may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale. In the drawings and the like of each embodiment, the size, layer thickness, or region of each configuration shown may be exaggerated for clarity. Therefore, it is not necessarily limited to that scale.

[0025] The ordinal terms such as first, second, and third used in this specification are for convenience in identifying components and do not limit the number thereof. The ordinal terms such as first, second, and third used in this specification are for convenience in identifying components and do not limit the number thereof.

[0026] Also, voltage often refers to the potential difference between a certain potential and a reference potential (e.g., ground potential). Therefore, it is possible to interchangeably refer to voltage, potential, and potential difference as potential, voltage, and voltage difference, respectively. Also, voltage often refers to the potential difference between a certain potential and a reference potential (e.g., ground potential). Therefore, it is possible to interchangeably refer to voltage, potential, and potential difference as potential, voltage, and voltage difference, respectively. Also, voltage often refers to the potential difference between a certain potential and a reference potential (e.g., ground potential). Therefore, it is possible to interchangeably refer to voltage, potential, and potential difference as potential, voltage, and voltage difference, respectively.

[0027] In addition, the source electrode and the drain electrode of the transistor are both connected to the semiconductor layer. When a voltage is applied to the gate electrode, the potential between the source electrode and the drain electrode Since current flows according to the difference between the source and drain electrodes, the source and drain electrodes are switched depending on the operation. In some cases, it is difficult to identify the location of a transistor. In this case, they are called the source electrode and the drain electrode. The electrodes are referred to as one electrode and the other electrode. Alternatively, they are referred to as the first electrode and the second electrode. There is no particular difference in meaning depending on how it is done.

[0028] (Embodiment 1) In this embodiment, a configuration of a semiconductor memory device according to one embodiment of the present invention will be described with reference to drawings. In this embodiment, an n-type transistor (n The following describes the case where a n-channel transistor is used instead of a n-type transistor. It goes without saying that a p-type transistor in which holes are the majority carriers can be used. .

[0029] FIG. 1 illustrates a memory element according to one embodiment of the present invention. The memory element 101 illustrated in FIG. The semiconductor device includes a diode-connected transistor 102, a transistor 103, and a capacitor 104. The gate of the transistor 103 is connected to the first potential of the capacitor 104 and the transistor 102. In addition, the second electrode and the gate of the transistor 102 are connected to each other. The gate of the transistor 103, the first electrode of the capacitor 104, and the The connection region of the first electrode is node A, and the connection region of the second electrode and the gate of the transistor 102 is node B. The connected region is called node B.

[0030] The memory element shown in this embodiment causes the first electrode of the diode-connected transistor 102 to function as an anode. Further, the channel region of the diode-connected transistor 102 is formed of an oxide semiconductor. The transistor 102 having an oxide semiconductor in the channel region has a low off-current. Also, the transistor 102 is diode-connected and the gate and the second electrode are connected. Therefore, when the transistor 102 is on a current flows from node B to node A, but when it is off, the current flowing from node A to node B is extremely small.

[0031] Here, in the memory element 101, a state where the potential of node A is low (i.e., the transistor 103 is off) is defined as data 0, and a state where the potential of node A is high (i.e., the transistor 103 is on is on) is defined as data 1.

[0032] By turning on the diode-connected transistor 102 and charging the capacitor element 104 with a voltage higher than the threshold voltage of the transistor 103, that is, by applying a voltage that turns on the transistor 103 to node A, data 1 can be written into the memory element 101.

[0033] On the other hand, after the data writing is completed, the transistor 102 is turned off, and even if the potential of node B to which the gate and the second electrode of the transistor 102 are connected decreases, the transistor 102 has an extremely low off-current and is diode-connected, so it is difficult for a current to flow from the first electrode of the transistor 102 to the second electrode. Therefore, the voltage charged at node A is ​​It is possible to maintain the voltage of node A without reduction for a long period of time. As a result, the written information (Data 1) cannot be rewritten, and the memory element 101 can be operated as a substantially write-once memory. Note that the capacitance of the capacitance element 104 is appropriately designed according to the required data retention time.

[0034] In addition, when a parasitic capacitance is formed at the first electrode or the second electrode of the transistor 103 and the first electrode of the diode-connected transistor 102, there is no need to deliberately provide the capacitance element 104. In this case, the memory element has a diode-connected transistor 102 and a transistor 103 as shown in FIG. 1(B), and the gate of the transistor 103 is connected to the first electrode of the transistor 102. Also, the second electrode and the gate of the transistor 102 are connected.

[0035] Next, FIGS. 2 and 3 show the form of a memory cell array in which memory cells having the memory element of FIG. 1(A) are arranged in a matrix.

[0036] FIG. 2(A) is a diagram showing one form of a NOR-type memory cell array.

[0037] The memory cell 110 includes a memory element 111, a transistor 115 whose gate is connected to the write word line WL1, whose first electrode is connected to the memory element 111, and whose second electrode is connected to the write bit line BL1, and a transistor 116 whose gate is connected to the read word line WL2, whose first electrode is connected to the read bit line BL2, and whose second electrode is connected to the memory element 111. The transistor 115 functions as a write selection transistor, and the transistor 116 functions as a read selection transistor. ​​​​​​​​​​​​

[0038] The memory element 111 includes a diode-connected transistor 112, a transistor 113, and a capacitor element 114. The second electrode of the transistor 112 is connected to the gate and also to the first electrode of the transistor 115. The gate of the transistor 113 is connected to the first electrode of the capacitor element 114 and the first electrode of the transistor 112. Further, the first electrode of the transistor 113 is connected to the second electrode of the transistor 116, and the second electrode of the transistor 113 is at a fixed potential. The second electrode of the capacitor element 114 is at a fixed potential.

[0039] FIG. 2(B) shows a form of a NOR type memory cell array different from that of FIG. 2(A).

[0040] The memory cell 130 includes a memory element 131 and a transistor 135 whose gate is connected to the write word line WL1, the first electrode is connected to the memory element 131, and the second electrode is connected to the write bit line BL1. The transistor 135 functions as a write selection transistor.

[0041] The memory element 131 includes a diode-connected transistor 132, a transistor 133, and a capacitor element 134. The second electrode of the transistor 132 is connected to the gate and also to the first electrode of the transistor 135. The gate of the transistor 133 is connected to the first electrode of the capacitor element 134 and the first electrode of the transistor 132. Further, the first electrode of the transistor 133 is connected to the read bit line BL2, and the second electrode is at a fixed potential. The second electrode of the capacitor element 134 is connected to the read word line WL2. ​​

[0042] FIG. 3 is a diagram showing one form of a NAND-type memory cell array.

[0043] The memory cell 120 includes a memory element 121, and a transistor 125 whose gate is connected to a write word line WL, a first electrode of which is connected to the memory element 121, and a second electrode of which is connected to a write bit line BL. The transistor 125 functions as a write select transistor.

[0044] The memory element 121 includes a diode-connected transistor 122, a transistor 123, and a capacitor element 124. A second electrode of the transistor 122 is connected to a gate and also to a first electrode of the transistor 125. A gate of the transistor 123 is connected to a first electrode of the capacitor element 124 and a first electrode of the transistor 122. A first electrode of the transistor 123 is connected to a read data line DL, and a second electrode of the transistor 123 is connected to a first electrode of the transistor 123 in the next column. A second electrode of the capacitor element 124 is at a fixed potential.

[0045]

[0046] The channel regions of the diode-connected transistors 112, 122, and 132 are formed of an oxide semiconductor. The transistors 112, 122, and 132 having an oxide semiconductor in the channel region have a low off-current. Also, the transistors 112, 122, and 132 are diode-connected, and the gates and the second electrodes are connected. Therefore, when the transistors 112, 122, and 132 are in the on state, current flows from node B to node A, but when they are in the off state, the current flowing from node A to node B is extremely small.

[0046] ​​​​Channel regions of transistors 113, 115, 116, 123, 125, 133, and 135 an amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, or a single crystal silicon layer Also, the diode-connected transistors 112, 122, and 13 As in the case of 2, the second insulating film 2 may be formed of an oxide semiconductor.

[0047] The semiconductor memory device described in this embodiment has a channel of a diode-connected first transistor. By forming the junction region using an oxide semiconductor, -19 A / μm or less, and even 1×10 -20 This allows the off-state current to be reduced to less than A / μm. The potential of the gate of the second transistor and the capacitance element, which is increased by the input, is connected to the diode. The first transistor is less likely to leak and the potential of the gate of the second transistor is maintained. In other words, data that has been written once can be retained.

[0048] The data write voltage is a voltage that can turn on the second transistor, i.e., It is possible to set the threshold voltage of the transistor or higher, thereby reducing the write voltage. In addition, it is not necessary to provide a boost circuit for the write voltage, and the power consumption during writing is It is possible to reduce the stress, and to increase the channel length to increase the breakdown voltage and to reduce the LDD Since no region formation is required, the memory element can be reduced in size and can be highly integrated.

[0049] In addition, the write time of the semiconductor memory device shown in this embodiment mode is longer than that of the first transistor connected by a diode. It is determined by the on-current of the first transistor and the capacitance of the capacitor. 0 -6Even if the capacitance of the capacitance element is 1 pF, writing is completed in about 1 μs. Also, it is possible to write to a plurality of memory elements simultaneously. Therefore, the writing time can be significantly shortened.

[0050] Also, the memory cells included in the semiconductor memory device shown in this embodiment are write-once memories so that data rewriting due to malfunction of the logic circuit does not occur. From this the data retention safety of the semiconductor memory device can be enhanced.

[0051] Note that the forms of the memory cells and the memory cell array shown in this embodiment are one form and do not limit the configuration.

[0052] (Embodiment 2) In this embodiment, the writing and reading of data in the semiconductor memory device shown in Embodiment 1 will be described with reference to the drawings.

[0053] Regarding the writing of data in the NOR-type memory cell 110 shown in Fig. 2(A), Fig. 4(A) will be used for the description.

[0054] First, a first potential is applied to the write bit line BL1 and the write word line WL1 connected to the memory cell 110 to be written, and the read bit line BL2 and the read word line WL2 are set to the ground potential. The first potential is a potential that turns on the transistors 113 and 115, and is a potential higher than the threshold voltages of the transistors 113 and 115, here 2 V shall be. When the potential of the write word line WL1 becomes the first potential, the write selection transistor is turned on, and the write bit line BL1 is connected to the source of the transistor 113. At this time, the potential of the write bit line BL1 is the first potential 2 V.

[0055] When the potential of the write word line WL1 becomes the first potential, the write selection transistor The transistor 115 functioning as a resistor and the diode-connected transistor 112 are turned on, and the potential of node A, that is, the gate of the capacitor element 114 and the transistor 113, rises to almost the same potential as the bit line BL1 for writing, and the transistor 113 is turned on. Through the above process, data 1 can be written.

[0056] Note that for writing data 1, only the charge sufficient to turn on the transistor 113 needs to be charged to node A, so a boost circuit for writing is unnecessary, and the write voltage is supplied with voltage from the power supply to the logic circuit that drives the memory cell 110. Also, since the write time is sufficient with only the time to charge the capacitor element 104, when the on-currents of the transistors 112 and 115 are 10 A and the capacitance of the capacitor element 114 is 1 pF, the writing is completed in a short time of about 1 μs. -6 A and the capacitance of the capacitor element 114 is 1 pF, the writing is completed in a short time of about 1 μs.

[0057] After the writing is completed, as shown in Fig. 4(B), the potentials of the bit line BL1 for writing and the word line WL1 for writing are set to 0 V. As a result, the transistor 115 functioning as the selection transistor for writing and the diode-connected transistor 112 are turned off, but since the off-current of the transistor 112 formed using an oxide semiconductor is very small, the voltage of node A is maintained for a long time. Specifically, since the off-current of the transistor 112 formed using an oxide semiconductor is 1×10 A / μm or less, and further 1×10 A / μm or less -19 -20 when a capacitance of 1 pF is added to the capacitor element 114, the data can be held for 20 to 200 days, and the memory element 111 functions as a write-once memory. ​​​​​​​​Well, the "data retention" here means the state where the potential of the capacitive element 114 becomes 90% or more of the potential at the time of writing data 1, that is, 1.8 V or more.

[0058] Next, the data reading of the memory cell 110 shown in Fig. 2(A) will be described with reference to Fig. 5. Fig. 5(A) shows the data 1 reading method, and Fig. 5(B) shows the data 0 reading method. Data reading is performed by changing the potential of the read word line WL2, turning on the transistor 116 that functions as the read selection transistor, and determining the output of the read circuit 117 according to the voltage of the read bit line BL2. At the time of reading, the write bit line BL1 and the write word line WL1 are set to the ground potential, and the transistors 112 and 115 are in the off state.

[0059] In the case of reading data 1, as shown in Fig. 5(A), a second potential is applied to the read word line WL2 belonging to the column where reading is performed to turn on the transistor 116. Also, a third potential, which is a negative potential, is applied to the read word line WL2 belonging to the column where reading is not performed. The second potential is a potential that turns on the transistor 116, and is set to a potential higher than the threshold voltage of the transistor 116, here 2 V. In the case of data 1, since the transistor 113 is on, the output of the read circuit 117 is determined by the ratio of the sum of the on-resistances of the transistor 113 and the transistor 116 to the resistance (denoted as R1) included in the read circuit 117. Here, by making the resistance R1 in the read circuit larger than the sum of the on-resistances of the transistor 113 and the transistor 116, the read bit ​​​​​​​​The potential at node C of bit line BL2 becomes approximately 0V. The potential at node C is inverted by inverter 118 included in read circuit 117 and output as data 1.

[0060] In the case of reading data 0, as shown in FIG. 5(B), a second potential is applied to read word line WL2 to turn on transistor 116. In the case of data 0, since transistor 113 is off, the output of read circuit 117 is determined by comparison with the sum of the off-resistance of transistor 113 and the on-resistance of transistor 116 and resistance R1 included in read circuit 117. Here, by making resistance R1 included in read circuit 117 smaller than the sum of the off-resistance of transistor 113 and the on-resistance of transistor 116, the potential at node C of bit line BL2 for reading becomes approximately 2V by read circuit 117. This potential is inverted by inverter 118 included in read circuit 117 and output as data 0.

[0061] Note that in a memory cell belonging to a column where reading is not performed, a third potential which is a negative potential is applied to read word line WL2. The third potential is a potential that turns off transistor 116, a negative potential lower than the threshold voltage of transistor 116, here -2V. Transistor 116 turns off. Therefore, there is no possibility that data of a memory cell for which reading is not selected is read.

[0062] Next, writing and reading of data in NOR-type memory cell 130 shown in FIG. 2(B) in Embodiment 1 will be described with reference to the drawings.

[0063] ​​​​​​​​​​​​​​First, the writing of data to the NOR-type memory cell 130 shown in FIG. 2(B) will be described with reference to FIG. 6.

[0064] First, a first potential is applied to the write bit line BL1 and the write word line WL1 belonging to the memory cell 130 to be written, and the read word line WL2 is set to the ground potential. The first potential is a potential that turns on the transistors 133 and 135, and is a potential higher than the threshold voltages of the transistors 133 and 135. Here, it is set to 2V. When the write word line WL1 and the write bit line BL1 reach the first potential, the transistor 135 turns on, the diode-connected transistor 132 turns on, and the NOR

[0065] A, that is, the capacitor element 134 and the gate of the transistor 133 are charged with electric charge and rise to almost the same potential as the write bit line BL1, and the transistor 133 turns on. Through the above process, data 1 can be written. After the writing is completed, the potentials of the write bit line BL1 and the write word line WL1 are set to 0V. As a result, the transistor 135 and the diode-connected transistor 132 that function as the write selection transistor are turned off. However, since the off-current of the transistor 132 formed using an oxide semiconductor is very small, the voltage of the node A is maintained for a long time. As a result, the memory element 131 functions as a write-once memory. Next, the reading of data from the memory cell 130 shown in FIG. 2(B) will be described with reference to FIG. 7.

[0066] FIG. 7(A) shows the method of reading data 1, and FIG. 7(B) shows the method of reading data 0. formed using an oxide semiconductor is very small, the voltage of the node A is maintained for a long time. As a result, the memory element 131 functions as a write-once memory.

[0067] Next, the reading of data from the memory cell 130 shown in FIG. 2(B) will be described with reference to FIG. 7. FIG. 7(A) shows the method of reading data 1, and FIG. 7(B) shows the method of reading data 0. It is as follows. For data reading, the potential of the read word line WL2 is changed, and reading is performed according to the voltage of the read bit line BL2. For data reading, the potential of the read word line WL2 is changed, and reading is performed according to the voltage of the read bit line BL2.

[0068] In the case of reading data 1, as shown in Fig. 7(A), the read word line WL2 belonging to the column where reading is performed is set to the ground potential, and the other read word lines WL2 are set to the third potential which is a negative potential. In the case of reading data 1, as shown in Fig. 7(A), the read word line WL2 belonging to the column where reading is performed is set to the ground potential, and the other read word lines WL2 are set to the third potential which is a negative potential. of the potential.

[0069] When the memory cell 130 to be read stores data 1, that is, when the capacitor element 134 of the memory cell 130 is charged with the voltage of 1, the transistor 133 is turned on, and the potential at the node C of the read bit line BL2 becomes approximately 0V. The potential at the node C is inverted by the inverter included in the read circuit 117 and output as data 1. When the memory cell 130 to be read stores data 1, that is, when the capacitor element 134 of the memory cell 130 is charged with the voltage of 1, the transistor 133 is turned on, and the potential at the node C of the read bit line BL2 becomes approximately 0V. The potential at the node C is inverted by the inverter included in the read circuit 117 and output as data 1. 2, and the potential at the node C is inverted by the inverter included in the read circuit 117 and output as data 1. of the potential.

[0070] In the case of reading data 0, as shown in Fig. 7(B), the read word line WL2 belonging to the column where reading is performed is set to the ground potential, and the other read word lines WL2 are set to the third potential which is a negative potential. In the case of reading data 0, as shown in Fig. 7(B), the read word line WL2 belonging to the column where reading is performed is set to the ground potential, and the other read word lines WL2 are set to the third potential which is a negative potential. of the potential.

[0071] When the memory cell 130 to be read stores data 0, that is, when the capacitor element 134 of the memory cell 130 is not charged with electric charge, the transistor 133 is turned off, so the potential at the node C of the read bit line BL2 becomes approximately 2V by the read circuit 117. This potential is inverted by the inverter included in the read circuit 117 and output as data 0. When the memory cell 130 to be read stores data 0, that is, when the capacitor element 134 of the memory cell 130 is not charged with electric charge, the transistor 133 is turned off, so the potential at the node C of the read bit line BL2 becomes approximately 2V by the read circuit 117. This potential is inverted by the inverter included in the read circuit 117 and output as data 0. When the memory cell 130 to be read stores data 0, that is, when the capacitor element 134 of the memory cell 130 is not charged with electric charge, the transistor 133 is turned off, so the potential at the node C of the read bit line BL2 becomes approximately 2V by the read circuit 117. This potential is inverted by the inverter included in the read circuit 117 and output as data 0. is inverted by the inverter included in the read circuit 117 and output as data 0. is output.

[0072] Note that the third potential which is a negative potential is applied to the read word line WL2 of the memory cell belonging to the column where reading is not performed. The potential of the capacitor element 134 of the memory cell is stored at the node A. Note that the third potential which is a negative potential is applied to the read word line WL2 of the memory cell belonging to the column where reading is not performed. The potential of the capacitor element 134 of the memory cell is stored at the node A. It becomes the value obtained by adding a third potential to the potential that has been applied. Since the third potential is a negative potential, the memo The potential of the capacitive element 134 of the memory cell decreases, and regardless of the data written to the memory cell, The transistor 133 turns off. Therefore, there is no possibility that the data of the non-selected memory cell will be read out.

[0073] Next, the writing and reading of data in the NAND-type memory cell 120 shown in FIG. 3 in Embodiment 1 will be described with reference to the drawings. will be described.

[0074] The writing of data in the NAND-type memory cell 120 shown in FIG. 3 will be described with reference to FIG. 8. will be described.

[0075] First, a first potential is applied to the bit line BL and the word line WL belonging to the memory cell 120 to be written. The first potential is a potential that turns on the transistors 123 and 125. Also, in the capacitive element 124, the second electrode not connected to the transistors 123 and 125 is set to the ground potential. is. Further, in the capacitive element 124, the second electrode not connected to the transistors 123 and 125 is set to the ground potential. is set to the ground potential.

[0076] When the write word line WL becomes the first potential, the transistor 125 turns on, the diode-connected transistor 122 turns on, and the potential of the node A, that is, the gate of the capacitive element 124 and the transistor 123, rises to almost the same potential as the write bit line BL, and the transistor 123 turns on. By the above steps, data 1 can be written. can be written.

[0077] After the writing is completed, the potential of the write bit line BL is set to 0V. As a result, the transistor 125 that functions as a write selection transistor and the diode-connected transistor transistor 122 is in the off state, and the off current of the transistor 122 formed using an oxide semiconductor is extremely small. Therefore, the potential of node A is maintained for a long time. As a result, the memory element 121 functions as a one-time write memory. Since the current is extremely small, the potential of node A is maintained for a long time. As a result, the memory element 121 functions as a one-time write memory.

[0078] Next, the data reading of the memory cell 120 shown in FIG. 3 will be described with reference to FIG. 9. FIG. 9(A) shows a method of reading data 1, and FIG. 9(B) shows a method of reading data 0. The data reading is performed by applying a voltage to the second electrode of the capacitive element 124 included in all the memory cells connected to a certain bit line, that is, the memory cells 120 surrounded by the region 129, which is not connected to the transistor 123. A ground potential is applied to the second electrode of the capacitive element 124 of the memory cells belonging to the column for reading, and a fourth potential is applied to the second electrode of the capacitive element 124 of the memory cells included in the other region 129, and the output of the reading circuit 117 is determined according to the voltage of the bit line BL for reading. The fourth potential is a potential higher than the threshold voltage of the transistor 123, and here, the fourth potential is set to 2V. In the case of reading data 1, as shown in FIG. 9(A), charge is stored in the capacitive element 124 of the memory cell for reading, and the first potential is applied to the first electrode. Therefore, by setting the second electrode of the capacitive element 124 to the ground potential, the transistor 123 is turned on. On the other hand, by applying the fourth potential to the second electrode of the capacitive element 124 of the memory cells in the region 129 that do not perform reading, the potential of the first electrode of the capacitive element 124 is pushed up, so that the transistor 123 is turned on. As a result, the transistor 123 connected to the data line DL is connected to the capacitive element 124 included in the memory cells surrounded by the region 129. is not connected to the transistor 123. A voltage is applied to the second electrode of the capacitive element 124 of the memory cells belonging to the column for reading, and a fourth potential is applied to the second electrode of the capacitive element 124 of the memory cells included in the other region 129, and the output of the reading circuit 117 is determined according to the voltage of the bit line BL for reading. The fourth potential is a potential higher than the threshold voltage of the transistor 123, and here, the fourth potential is set to 2V. is turned on, and the potential of the data line DL changes. The reading circuit 117 determines whether the data read is 1 or 0 based on the change in the potential of the data line DL. is turned on, and the potential of the data line DL changes. The reading circuit 117 determines whether the data read is 1 or 0 based on the change in the potential of the data line DL. is turned on, and the potential of the data line DL changes. The reading circuit 117 determines whether the data read is 1 or 0 based on the change in the potential of the data line DL. is a potential higher than the threshold voltage of the transistor 123, and here, the fourth potential is set to 2V.

[0079] In the case of reading data 1, as shown in FIG. 9(A), charge is stored in the capacitive element 124 of the memory cell for reading, and the first potential is applied to the first electrode. Therefore, by setting the second electrode of the capacitive element 124 to the ground potential, the transistor 123 is turned on. On the other hand, by applying the fourth potential to the second electrode of the capacitive element 124 of the memory cells in the region 129 that do not perform reading, the potential of the first electrode of the capacitive element 124 is pushed up, so that the transistor 123 is turned on. As a result, the transistor 123 connected to the data line DL is turned on, and the potential of the data line DL changes. The reading circuit 117 determines whether the data read is 1 or 0 based on the change in the potential of the data line DL. In the region 129, when the second electrode of the capacitive element 124 of the memory cells that do not perform reading is set to the ground potential, the transistor 123 is turned on. On the other hand, when the fourth potential is applied to the second electrode of the capacitive element 124 of the memory cells in the region 129 that do not perform reading, the potential of the first electrode of the capacitive element 124 is pushed up, so that the transistor 123 is turned on. As a result, the transistor 123 connected to the data line DL is turned on, and the potential of the data line DL changes. The reading circuit 117 determines whether the data read is 1 or 0 based on the change in the potential of the data line DL. Everything is in the on state, and the potential of node C in the data line DL becomes 0V. At node C the potential is inverted by the inverter included in the read circuit 117 and output as data 1 .

[0080] In the case of reading data 0, as shown in Fig. 9(B), the first electrode of the capacitance element 124 of the memory cell 120 for reading is 0V. For this reason, the transistor 123 of the memory cell for reading is in the off state. On the other hand, in region 129, by applying a fourth potential to the second electrode of the capacitance element 124 of the memory cell that does not perform reading, the potential of the first electrode of the capacitance element 124 is pushed up, so that the transistor 123 turns on. As a result, the potential at node C of the data line DL becomes approximately 2V by the read circuit 117.

[0081] According to this embodiment, a semiconductor memory device that does not require a high voltage for writing, is less likely to cause defects, has a short writing time, and cannot rewrite data can be provided.

[0082] (Embodiment 3) In this embodiment, one form of the semiconductor memory device shown in Embodiment 1 and Embodiment 2 will be described with reference to the drawings.

[0083] Fig. 10(A) is an example of a semiconductor memory device having the memory cell array shown in Embodiment 1. The semiconductor memory device 300 includes a memory cell array 301, a column decoder 302, a row decoder 303, and an interface circuit 304. The memory cell array 301 includes a plurality of memory cells 305 arranged in a matrix.

[0084] ​​​​​​​​The interface circuit 304 generates signals for driving the column decoder 302 and the row decoder 3 03 from an external signal, and outputs the data of the read memory cell 305 to the external part.

[0085] The column decoder 302 receives signals for driving the memory cell 305 from the interface circuit 304 and generates signals to be sent to the bit lines for writing or reading . The row decoder 303 receives signals for driving the memory cell 305 from the interface circuit 304 and generates signals to be sent to the word lines for writing or reading . The signals output from the column decoder 302 to the bit lines and the signals output from the row decoder 303 to the word lines uniquely determine the memory cell to be accessed in the memory cell array 301 . .

[0086] Also, as shown in FIG. 10(B), it is possible to fabricate a semiconductor memory device having a memory cell array in which the write-once memory shown in Embodiment 1 and Embodiment 2 and a rewritable memory are mixed . The semiconductor memory device 310 shown in FIG. 10(B) includes a first memory cell array 311, a second memory cell array 312, a column decoder 302, a row decoder 3 03, and an interface circuit 304. In the first memory cell array 311, memory cells 313 having write-once memory elements shown in Embodiment 1 and Embodiment 2 are arranged in a matrix form, and in the second memory cell array 312, memory cells 314 having rewritable memory elements are arranged in a matrix . .

[0087] The rewritable memory element is the write-once memory shown in Embodiment 1 and Embodiment 2 It is possible to fabricate it using the same process as that for the element. The configuration of the rewritable memory element will be described with reference to FIGS. 11(A) and 11(B).

[0088] FIG. 11(A) is a diagram showing a memory cell and a memory cell array having a NOR-type rewritable memory element. The memory cell 400 includes a memory element 401, and a transistor 402 whose gate is connected to the write word line WL1, whose first electrode is connected to the memory element 401, and whose second electrode is connected to the write bit line BL1 for writing, and a transistor 406 whose gate is connected to the read word line WL2 and whose first electrode is connected to the read bit line BL2 and whose second electrode is connected to the memory element 40 1. The transistor 406 functions as a selection transistor for reading.

[0089] The memory element 401 includes a transistor 403 and a capacitor element 404. The gate of the transistor 4 03 is connected to the first electrode of the capacitor element 404 and the first electrode of the transistor 402. Also, the first electrode of the transistor 403 is connected to the second electrode of the transistor 406, and the second electrode of the transistor 403 is at a fixed potential. The second electrode of the capacitor element 404 is at a fixed potential.

[0090] The transistor 402 is fabricated using an oxide semiconductor in the same manner as the transistor 102 shown in Embodiment 1. The transistors 403 and 406 can be fabricated in the same manner as the transistor 10 3 shown in Embodiment 1.

[0091] Regarding the writing of data in the NOR-type memory cell 400 shown in FIG. 11(A), FIG. 12 will be used This will be described below. FIG. 12(A) shows the method of writing data 1, and FIG. 12(B) shows the method of writing data 0. It is shown as follows.

[0092] In the case of writing data 1, as shown in FIG. 12(A), a first potential is applied to the write bit line BL1 and the write word line WL1 connected to the memory cell 400 to be written. The read word line WL2 is set to the ground potential. The first potential is a potential that turns on the transistors 402 and 403, and is a potential higher than the threshold voltages of the transistors 402 and 403. Here, it is 2V. When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, rises to almost the same potential as the write bit line BL1, and the transistor 403 turns on. By the above process, data 1 can be written. When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, rises to almost the same potential as the write bit line BL1, and the transistor 403 turns on. By the above process, data 1 can be written. When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, rises to almost the same potential as the write bit line BL1, and the transistor 403 turns on. By the above process, data 1 can be written.

[0093] When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, rises to almost the same potential as the write bit line BL1, and the transistor 403 turns on. By the above process, data 1 can be written. When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, rises to almost the same potential as the write bit line BL1, and the transistor 403 turns on. By the above process, data 1 can be written. When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, rises to almost the same potential as the write bit line BL1, and the transistor 403 turns on. By the above process, data 1 can be written. When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, rises to almost the same potential as the write bit line BL1, and the transistor 403 turns on. By the above process, data 1 can be written.

[0094] In the case of writing data 0, as shown in FIG. 12(B), the write bit line BL1 connected to the memory cell 400 to be written is set to the ground potential, the first potential is applied to the write word line WL1, and the read word line WL2 is set to the ground potential. The first potential is a potential that turns on the transistor 402, and is a potential higher than the threshold voltage of the transistor 402. Here, it is 2V. When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, drops to the potential of the write bit line BL1, which is the ground potential. As a result, the transistor 403 When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, drops to the potential of the write bit line BL1, which is the ground potential. As a result, the transistor 403 When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, drops to the potential of the write bit line BL1, which is the ground potential. As a result, the transistor 403 When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, drops to the potential of the write bit line BL1, which is the ground potential. As a result, the transistor 403

[0095] When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, drops to the potential of the write bit line BL1, which is the ground potential. As a result, the transistor 403 When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, drops to the potential of the write bit line BL1, which is the ground potential. As a result, the transistor 403 When the potential of the write word line WL1 becomes the first potential, the transistor 402 turns on, and the potential of node A, that is, the gate of the capacitor element 404 and the transistor 403, drops to the potential of the write bit line BL1, which is the ground potential. As a result, the transistor 403 is turned off, and data 0 can be written. Note that to prevent the reading of unintended data during the writing period, the read word line WL2 is set to the ground potential, and the transistor 406 is turned off.

[0096] Next, the reading of the data of the memory cell 400 shown in Fig. 11(A) will be described with reference to Fig. 13 . Fig. 13(A) shows the method of reading data 1, and Fig. 13(B) shows the method of reading data 0 . The reading of data is performed by changing the potential of the read word line WL2, turning on the transistor 406 that functions as the read selection transistor, and determining the output of the read circuit 117 according to the voltage of the read bit line BL2 .

[0097] In the case of reading data 1, as shown in Fig. 13(A), a second potential is applied to the read word line WL2 belonging to the column where the reading is performed, and the transistor 406 is turned on. In the case of data 1 , since the transistor 403 is on, the node C of the read bit line BL2 becomes the ground potential in the same way as the NOR type reading method shown in Fig. 2(A) of the second embodiment. The potential at the node C is inverted by the inverter included in the read circuit 117 and output as data 1 . In the case of reading data 0, as shown in Fig. 13(B), a second potential is applied to the read word line WL2, and the transistor 406 is turned on. In the case of data 0, since the transistor 403

[0098] is off, the read bit line BL2 becomes approximately 2V by the read circuit 117 . The potential is inverted by the inverter included in the read circuit 117 and output as data 0 . .

[0099] In addition, in the memory cells of the columns in which reading is not performed, a negative potential is applied to the read word line WL2. The third potential is applied to the transistor 406. The potential is a negative potential lower than the threshold voltage of the transistor 406, which is −2 V in this example. The transistor 406 is turned off. Therefore, the data of the memory cells not selected for reading is not read. There is no risk of it being leaked out.

[0100] FIG. 11B shows a rewritable memory element of a NOR type different from that of FIG. 11A. FIG. 11B is a diagram showing a memory cell. The memory cell shown in FIG. 11B is the same as the memory cell shown in FIG. A transistor 405 is provided between the transistor 402 and the write bit line BL1. This configuration is obtained by changing the gate connection of the transistor 112 shown in the first embodiment. The gate is connected to the write word line WL1. A slight change in the lines can transform a write-once memory into a rewritable memory or back again. The method of writing and reading data is shown in FIG. ) and therefore omitted.

[0101] In this embodiment, the write-once memory element and the rewritable memory element are configured as NOR Although the type is shown, a NAND type can be used as appropriate.

[0102] In this way, write-once memory and rewritable memory are mounted on the same semiconductor storage device. The rewritable memory is the same as that shown in the first and second embodiments. It can be fabricated using the same process as the write-once memory, and is compatible with logic signals. Regardless of the operation, the one-time write memory is treated as a one-time write memory, and the rewritable memory can be treated as a rewritable memory. Therefore, it is possible to provide a semiconductor memory device in which data rewriting due to malfunction of the logic circuit does not occur in principle. The rewritable memory can be treated as a rewritable memory. Therefore, it is possible to provide a semiconductor memory device in which data rewriting due to malfunction of the logic circuit does not occur in principle. Regardless of the operation, the one-time write memory is treated as a one-time write memory, and the rewritable memory can be treated as a rewritable memory. Therefore, it is possible to provide a semiconductor memory device in which data rewriting due to malfunction of the logic circuit does not occur in principle. Regardless of the operation, the one-time write memory is treated as a one-time write memory, and the rewritable memory can be treated as a rewritable memory. Therefore, it is possible to provide a semiconductor memory device in which data rewriting due to malfunction of the logic circuit does not occur in principle.

[0103] (Embodiment 4) In this embodiment, the configuration of the semiconductor memory device and its manufacturing method shown in Embodiments 1 to 3 will be described with reference to FIGS. 14 to 16. In this embodiment, the configuration of the semiconductor memory device shown in Embodiment 1 will be described with reference to a top view and a cross-sectional view, but it can be appropriately applied to Embodiments 2 and 3.

[0104] In this embodiment, the configuration of the semiconductor memory device shown in Embodiment 1 will be described with reference to a top view and a cross-sectional view, but it can be appropriately applied to Embodiments 2 and 3. In this embodiment, the configuration of the semiconductor memory device shown in Embodiment 1 will be described with reference to a top view and a cross-sectional view, but it can be appropriately applied to Embodiments 2 and 3.

[0105] FIG. 14 is a form of a top view of the memory cell 110 of the semiconductor memory device shown in Embodiment 1, and the cross-sectional views taken along A-B, C-D, and E-F in FIG. 14 are shown in FIG. 15. FIG. 14 is a form of a top view of the memory cell 110 of the semiconductor memory device shown in Embodiment 1, and the cross-sectional views taken along A-B, C-D, and E-F in FIG. 14 are shown in FIG. 15.

[0106] The transistor 502 shown in FIG. 14 corresponds to the transistor 113 shown in FIG. 2(A), the transistor 503 corresponds to the transistor 116 shown in FIG. 2(A), the diode-connected transistor 505 corresponds to the diode-connected transistor 112 shown in FIG. 2(A), and the transistor 506 corresponds to the transistor 115 shown in FIG. 2(A). Also, the capacitor 504 corresponds to the capacitor 114 shown in FIG. 2(A). The transistor 502 shown in FIG. 14 corresponds to the transistor 113 shown in FIG. 2(A), the transistor 503 corresponds to the transistor 116 shown in FIG. 2(A), the diode-connected transistor 505 corresponds to the diode-connected transistor 112 shown in FIG. 2(A), and the transistor 506 corresponds to the transistor 115 shown in FIG. 2(A). Also, the capacitor 504 corresponds to the capacitor 114 shown in FIG. 2(A). The transistor 502 shown in FIG. 14 corresponds to the transistor 113 shown in FIG. 2(A), the transistor 503 corresponds to the transistor 116 shown in FIG. 2(A), the diode-connected transistor 505 corresponds to the diode-connected transistor 112 shown in FIG. 2(A), and the transistor 506 corresponds to the transistor 115 shown in FIG. 2(A). Also, the capacitor 504 corresponds to the capacitor 114 shown in FIG. 2(A). The transistor 502 shown in FIG. 14 corresponds to the transistor 113 shown in FIG. 2(A), the transistor 503 corresponds to the transistor 116 shown in FIG. 2(A), the diode-connected transistor 505 corresponds to the diode-connected transistor 112 shown in FIG. 2(A), and the transistor 506 corresponds to the transistor 115 shown in FIG. 2(A). Also, the capacitor 504 corresponds to the capacitor 114 shown in FIG. 2(A). The transistor 502 shown in FIG. 14 corresponds to the transistor 113 shown in FIG. 2(A), the transistor 503 corresponds to the transistor 116 shown in FIG. 2(A), the diode-connected transistor 505 corresponds to the diode-connected transistor 112 shown in FIG. 2(A), and the transistor 506 corresponds to the transistor 115 shown in FIG. 2(A). Also, the capacitor 504 corresponds to the capacitor 114 shown in FIG. 2(A).

[0107] It should be noted that although all the above transistors are described as n-channel type transistors, it goes without saying that p-channel type transistors can be used. Also, the disclosure It should be noted that although all the above transistors are described as n-channel type transistors, it goes without saying that p-channel type transistors can be used. Also, the disclosure The technical essence of the invention lies in forming the channel region of the diode-connected transistor 505 with an oxide semiconductor layer. Therefore, it is not necessary to limit the specific configuration of the semiconductor memory device here. As shown in FIG. 15, a transistor 502 and a capacitor element 504 are provided on an insulating layer 510 and an insulating layer 512 laminated on a substrate 508, and a transistor 505 is provided on the laminated insulating layers 510, 512, insulating layer 536, insulating layer 538, and insulating layer 540.

[0108] As shown in FIG. 15, a transistor 502 and a capacitor element 504 are provided on an insulating layer 510 and an insulating layer 512 laminated on a substrate 508, and a transistor 505 is provided on the laminated insulating layers 510, 512, insulating layer 536, insulating layer 538, and insulating layer 540. insulating layer 536, insulating layer 538, and insulating layer 540.

[0109] The semiconductor memory device shown in this embodiment has a transistor 502, a transistor 503 (not shown), a capacitor element 504, and a transistor 506 (not shown) at the lower part, and has a diode-connected transistor 505 at the upper part. Note that the capacitor element 504 may be provided at the upper part instead of the lower part. a capacitor element 504, and a transistor 506 (not shown) at the lower part, and has a diode-connected transistor 505 at the upper part. Note that the capacitor element 504 may be provided at the upper part instead of the lower part. a capacitor element 504, and a transistor 506 (not shown) at the lower part, and has a diode-connected transistor 505 at the upper part. Note that the capacitor element 504 may be provided at the upper part instead of the lower part.

[0110] The transistor 502 includes a semiconductor layer 519 formed on the insulating layer 512, a gate insulating layer 522 provided on the semiconductor layer 519, a gate electrode 526 provided on the gate insulating layer 522, and wirings 534a and 534b electrically connected to the semiconductor layer 519. The semiconductor layer 519 includes a channel region 514, a low-concentration impurity region 516 and a high-concentration impurity region 518 (collectively also simply referred to as an impurity region) provided so as to sandwich the channel region 514. includes a channel region 514, a low-concentration impurity region 516 and a high-concentration impurity region 518 (collectively also simply referred to as an impurity region) provided so as to sandwich the channel region 514. includes a channel region 514, a low-concentration impurity region 516 and a high-concentration impurity region 518 (collectively also simply referred to as an impurity region) provided so as to sandwich the channel region 514. includes a channel region 514, a low-concentration impurity region 516 and a high-concentration impurity region 518 (collectively also simply referred to as an impurity region) provided so as to sandwich the channel region 514.

[0111] Here, a sidewall insulating layer 530 is provided on the side surface of the gate electrode 526. Also, the low-concentration impurity region 516 overlaps with the sidewall insulating layer 530.

[0112] The capacitive element 504 is composed of a semiconductor layer formed as a high-concentration impurity region on the insulating layer 512. 520, a gate insulating layer 524 provided on the semiconductor layer 520, and on the gate insulating layer 524 a capacitive electrode 528 provided thereon, a wiring 534c electrically connected to the semiconductor layer 520, and a capacitive electrode 528 is connected to a wiring 534b. Here, a sidewall insulating layer 532 is provided on the side surface of the capacitive electrode 528.

[0113] An insulating layer 536, an insulating layer 538, and an insulating layer 540 are provided so as to cover the transistor 502 and the capacitive element 504.

[0114] The diode-connected transistor 505 includes an oxide semiconductor layer 542 electrically connected to a wiring 534c and a wiring 534d provided on the insulating layer 540, a gate insulating layer 544 covering the wiring 534c, the wiring 534d, and the oxide semiconductor layer 542, and a gate electrode 546a provided so as to overlap the oxide semiconductor layer 542 on the gate insulating layer 544. 534d, and a gate insulating layer 544 covering the oxide semiconductor layer 542, and a gate electrode 546a provided so as to overlap the oxide semiconductor layer 542 on the gate insulating layer 544. The gate electrode 546a seals an opening formed in the gate insulating layer 544 and is diode-connected by being electrically connected to the wiring 534d.

[0115] An insulating layer 552 and an insulating layer 554 are provided so as to cover the transistor 505.

[0116] As shown in FIG. 14, a wiring 546b that functions as a ground wiring is electrically connected to the wiring 534a of the transistor 502 through an opening formed in the gate insulating layer 544. Since the capacitive electrode 528 is electrically connected to the wiring 534a, the capacitive electrode 528 of the capacitive element 504 is electrically connected to the wiring 546b.

[0117] The wiring 534a is electrically connected to the high-concentration impurity region 518 and the capacitor electrode 528 of the capacitor element 504 through openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540. The wiring 534b is electrically connected to the high-concentration impurity region 518 through openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540. The wiring 534c is electrically connected to the semiconductor layer 520, which is a high-concentration impurity semiconductor, and the gate electrode 526 of the transistor 502 (see FIG. 14) through openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540.

[0118] Also, as shown in FIG. 14, the wiring 534d is electrically connected to the high-concentration impurity region of the transistor 506 and is electrically connected to the oxide semiconductor layer 542 of the transistor 505 through openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540. The wiring 534e is electrically connected to the high-concentration impurity region of the transistor 506 through openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540. The wiring 534f is electrically connected to the high-concentration impurity region of the transistor 503 through openings formed in the insulating layer 536, the insulating layer 538, and the insulating layer 540.

[0119] The substrate 508 needs to be a substrate having at least heat resistance enough to withstand subsequent heat treatment. When a glass substrate is used as the substrate 508, it is preferable to use one having a strain point of 730° C. or higher. For the glass substrate, for example, glass materials such as aluminosilicate glass, aluminoborosilicate glass, and barium borosilicate glass are used. Note that B 2 O3 It is preferable to use a glass substrate containing more BaO.

[0120] Instead of the above glass substrate, a substrate made of an insulator such as a ceramic substrate, a quartz substrate, or a sapphire substrate can be used. Also, crystallized glass or the like can be used. Moreover, a substrate having an insulating layer formed on the surface of a semiconductor substrate such as a silicon wafer or the surface of a conductive substrate made of a metal material can also be used. Also, a plastic substrate can be used. When a plastic substrate is used as the substrate 508, an adhesive may be provided between the substrate 508 and the insulating layer 510. Moreover, a substrate having an insulating layer formed on the surface of a semiconductor substrate such as a silicon wafer or the surface of a conductive substrate made of a metal material can also be used. Also, a plastic substrate can be used. When a plastic substrate is used as the substrate 508, an adhesive may be provided between the substrate 508 and the insulating layer 510. Moreover, a substrate having an insulating layer formed on the surface of a semiconductor substrate such as a silicon wafer or the surface of a conductive substrate made of a metal material can also be used. Also, a plastic substrate can be used. When a plastic substrate is used as the substrate 508, an adhesive may be provided between the substrate 508 and the insulating layer 510. Moreover, a substrate having an insulating layer formed on the surface of a semiconductor substrate such as a silicon wafer or the surface of a conductive substrate made of a metal material can also be used. Also, a plastic substrate can be used. When a plastic substrate is used as the substrate 508, an adhesive may be provided between the substrate 508 and the insulating layer 510. Moreover, a substrate having an insulating layer formed on the surface of a semiconductor substrate such as a silicon wafer or the surface of a conductive substrate made of a metal material can also be used. Also, a plastic substrate can be used. When a plastic substrate is used as the substrate 508, an adhesive may be provided between the substrate 508 and the insulating layer 510.

[0121] The insulating layer 510 is preferably formed of a nitride insulating layer, and the insulating layer 512 is preferably formed of an oxide insulating layer. Examples of the nitride insulating layer include a silicon nitride layer, a silicon oxynitride layer, and an aluminum nitride layer. Examples of the oxide insulating layer include a silicon oxide layer, a silicon oxynitride layer, and an aluminum oxide layer. The insulating layer 510 is preferably formed of a nitride insulating layer, and the insulating layer 512 is preferably formed of an oxide insulating layer. Examples of the nitride insulating layer include a silicon nitride layer, a silicon oxynitride layer, and an aluminum nitride layer. Examples of the oxide insulating layer include a silicon oxide layer, a silicon oxynitride layer, and an aluminum oxide layer. The insulating layer 510 is preferably formed of a nitride insulating layer, and the insulating layer 512 is preferably formed of an oxide insulating layer. Examples of the nitride insulating layer include a silicon nitride layer, a silicon oxynitride layer, and an aluminum nitride layer. Examples of the oxide insulating layer include a silicon oxide layer, a silicon oxynitride layer, and an aluminum oxide layer. The insulating layer 510 is preferably formed of a nitride insulating layer, and the insulating layer 512 is preferably formed of an oxide insulating layer. Examples of the nitride insulating layer include a silicon nitride layer, a silicon oxynitride layer, and an aluminum nitride layer. Examples of the oxide insulating layer include a silicon oxide layer, a silicon oxynitride layer, and an aluminum oxide layer.

[0122] The semiconductor layer 519 of the transistor 502 and the semiconductor layer 520 which is a high-concentration impurity semiconductor of the capacitor element 504 can be formed of an amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, or a single-crystalline silicon layer. As for a transistor using a single-crystalline silicon layer in the channel region, in addition to a transistor using a single-crystalline semiconductor substrate in the channel region, a so-called SOI (Silicon on Insulator) substrate in which a single-crystalline silicon layer serving as the channel region is formed on an insulating region can be used. Moreover, a transistor diode-connected to the semiconductor layer 519 of the transistor 502 can be used. The semiconductor layer 519 of the transistor 502 and the semiconductor layer 520 which is a high-concentration impurity semiconductor of the capacitor element 504 can be formed of an amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, or a single-crystalline silicon layer. As for a transistor using a single-crystalline silicon layer in the channel region, in addition to a transistor using a single-crystalline semiconductor substrate in the channel region, a so-called SOI (Silicon on Insulator) substrate in which a single-crystalline silicon layer serving as the channel region is formed on an insulating region can be used. Moreover, a transistor diode-connected to the semiconductor layer 519 of the transistor 502 can be used. The semiconductor layer 519 of the transistor 502 and the semiconductor layer 520 which is a high-concentration impurity semiconductor of the capacitor element 504 can be formed of an amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, or a single-crystalline silicon layer. As for a transistor using a single-crystalline silicon layer in the channel region, in addition to a transistor using a single-crystalline semiconductor substrate in the channel region, a so-called SOI (Silicon on Insulator) substrate in which a single-crystalline silicon layer serving as the channel region is formed on an insulating region can be used. Moreover, a transistor diode-connected to the semiconductor layer 519 of the transistor 502 can be used. The semiconductor layer 519 of the transistor 502 and the semiconductor layer 520 which is a high-concentration impurity semiconductor of the capacitor element 504 can be formed of an amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, or a single-crystalline silicon layer. As for a transistor using a single-crystalline silicon layer in the channel region, in addition to a transistor using a single-crystalline semiconductor substrate in the channel region, a so-called SOI (Silicon on Insulator) substrate in which a single-crystalline silicon layer serving as the channel region is formed on an insulating region can be used. Moreover, a transistor diode-connected to the semiconductor layer 519 of the transistor 502 can be used. The semiconductor layer 519 of the transistor 502 and the semiconductor layer 520 which is a high-concentration impurity semiconductor of the capacitor element 504 can be formed of an amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, or a single-crystalline silicon layer. As for a transistor using a single-crystalline silicon layer in the channel region, in addition to a transistor using a single-crystalline semiconductor substrate in the channel region, a so-called SOI (Silicon on Insulator) substrate in which a single-crystalline silicon layer serving as the channel region is formed on an insulating region can be used. Moreover, a transistor diode-connected to the semiconductor layer 519 of the transistor 502 can be used. The semiconductor layer 519 of the transistor 502 and the semiconductor layer 520 which is a high-concentration impurity semiconductor of the capacitor element 504 can be formed of an amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, or a single-crystalline silicon layer. As for a transistor using a single-crystalline silicon layer in the channel region, in addition to a transistor using a single-crystalline semiconductor substrate in the channel region, a so-called SOI (Silicon on Insulator) substrate in which a single-crystalline silicon layer serving as the channel region is formed on an insulating region can be used. Moreover, a transistor diode-connected to the semiconductor layer 519 of the transistor 502 can be used. The semiconductor layer 519 of the transistor 502 and the semiconductor layer 520 which is a high-concentration impurity semiconductor of the capacitor element 504 can be formed of an amorphous silicon layer, a microcrystalline silicon layer, a polycrystalline silicon layer, or a single-crystalline silicon layer. As for a transistor using a single-crystalline silicon layer in the channel region, in addition to a transistor using a single-crystalline semiconductor substrate in the channel region, a so-called SOI (Silicon on Insulator) substrate in which a single-crystalline silicon layer serving as the channel region is formed on an insulating region can be used. Moreover, a transistor diode-connected to the semiconductor layer 519 of the transistor 502 can be used. An oxide semiconductor layer similar to the oxide semiconductor layer described in 05 may be formed.

[0123] The gate insulating layer 522 and the gate insulating layer 524 may be a silicon oxide layer, a silicon nitride layer, an oxide silicon nitride layer, a silicon oxynitride layer, or an aluminum oxide layer, formed either as a single layer or as a stack.

[0124] In addition, the gate insulating layer 522 and the gate insulating layer 524 may be hafnium silicate (HfSi O x ), hafnium silicate with nitrogen added (HfSi x O y N z ), hafnium aluminate with nitrogen added (HfAl ), hafnium oxide, yttrium oxide, or other high-k materials. By using these materials, the gate leakage current can be reduced. Furthermore, x O y N z a stacked structure can be formed with one or more of the high-k materials and a silicon oxide layer, a silicon nitride layer, a silicon oxynitride layer, a silicon nitride oxide layer, or an aluminum oxide layer. The thickness of the gate insulating layer 522 and the gate insulating layer 524 can be set to be 10 nm or more and 300 nm or less.

[0125] The gate electrode 526 and the capacitor electrode 528 can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or an alloy containing one of the above-mentioned metal elements as a component, or an alloy combining the above-mentioned metal elements. In addition, one or more metal elements selected from manganese, magnesium, zirconium, and beryllium may be used. Also, the gate electrode 526 and the capacitor electrode 528 may be a single layer. It may be a structure or a laminated structure of two or more layers. For example, of the aluminum layer containing silicon a single layer structure, a two-layer structure in which a titanium layer is laminated on the aluminum layer, a titanium layer on the titanium nitride layer a two-layer structure in which a layer is laminated, a two-layer structure in which a tungsten layer is laminated on the titanium nitride layer, tantalum nitride a two-layer structure in which a tungsten layer is laminated on the layer, a titanium layer, and an aluminum layer is laminated on the titanium layer and a three-layer structure in which a titanium layer is further formed thereon, etc. Also, aluminum may be used with a layer of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, scandium or a layer of an alloy or a nitride layer formed by combining a plurality of them.

[0126] Further, the gate electrode 526 and the capacitor electrode 528 may be applied with a conductive material having translucency such as indium tin oxide, indium oxide containing tungsten oxide indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide indium oxide containing silicon oxide, etc. Also, it may be a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal element.

[0127] The sidewall insulating layer 530 and the sidewall insulating layer 532 can be formed using the same materials as the gate insulating layer 522 and the gate insulating layer 524. Note that there may be cases where the sidewall insulating layer is not formed for the integration of transistors and capacitor elements.

[0128] The insulating layer 536 and the insulating layer 540 can be formed in the same manner as the gate insulating layer 522 and the gate insulating layer 524. The insulating layer 538 can be formed using an organic resin layer. ​​​​​ Examples of the organic resin layer include acrylic, epoxy, polyimide, polyamide, polyvinyl fluoride, phenol, benzocyclobutene, etc. Siloxane polymers can also be used.

[0129] Wiring 534a to wiring 534f can be formed using a metal element selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, an alloy containing the above-mentioned metal element as a component, or an alloy combining the above-mentioned metal elements. Additionally, a metal element selected from any one or more of manganese, magnesium, zirconium, and beryllium can be used. Also, wiring 534a to wiring 534f can have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of an aluminum layer containing silicon, a two-layer structure with a titanium layer laminated on an aluminum layer, a two-layer structure with a titanium layer laminated on a titanium nitride layer, a two-layer structure with a tungsten layer laminated on a titanium nitride layer, a two-layer structure with a tungsten layer laminated on a tantalum nitride layer, a three-layer structure with a titanium layer, an aluminum layer laminated on the titanium layer, and further a titanium layer formed thereon, etc. Moreover, a layer of an element selected from titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium, or an alloy layer or nitride layer formed by combining multiple of them can be used for aluminum.

[0130] Also, wiring 534a to wiring 534f can be indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium zinc oxide containing titanium oxide. It is also possible to apply a conductive material having translucency, such as indium tin oxide added with silicon. In addition, it is also possible to form a laminated structure of the above-mentioned conductive material having translucency and the above-mentioned metal element. It is possible.

[0131] Note that the transistor 505 and the transistor 506 can have the same configuration as the transistor 502. It can be done.

[0132] The oxide semiconductor layer 542 is a quaternary metal oxide such as In-Sn-Ga-Zn-O-based metal oxide, or a ternary metal oxide such as In-Ga-Zn-O-based metal oxide, In-Sn-Zn-O-based metal oxide, In-Al-Zn-O-based metal oxide, Sn-Ga-Zn-O-based metal oxide, Al-Ga-Zn-O-based metal oxide, Sn-Al-Zn-O-based metal oxide, or a binary metal oxide such as In-Zn-O-based metal oxide, Sn-Zn-O-based metal oxide, Al-Zn-O-based metal oxide, Zn-Mg-O-based metal oxide, Sn-Mg-O-based metal oxide, In-Mg-O-based metal oxide, etc. can be used. Here, the n - element metal oxide is composed of n types of metal oxides. Note that the oxide semiconductor layer may contain, as an impurity, an element other than the main - component metal oxide in an amount of 1% or less, preferably 0.1% or less. In addition, the oxide semiconductor layer 542 is a ternary metal oxide, and a metal oxide represented by InMZnO (Y = 0.5 to 5) may be used. Here, M represents one or more elements selected from Group 13 elements such as gallium (Ga), aluminum (Al), and boron (B). Note that the contents of In, M, Zn, and O are arbitrary, and the content of M is zero. -O - based metal oxide, In - Al - Zn - O - based metal oxide, Sn - Ga - Zn - O - based metal oxide, Al - Ga - Zn - O - based metal oxide, Sn - Al - Zn - O - based metal oxide, or a binary -O - based metal oxide, Sn - Ga - Zn - O - based metal oxide, Al - Ga - Zn - O - based metal oxide, Sn - Al - Zn - O - based metal oxide, or a binary -O - based metal oxide, Sn - Zn - O - based metal oxide, Al - Zn - O - based metal oxide, Zn - Mg - O - based metal oxide, Sn - Mg - O - based metal oxide, I n - Mg - O - based metal oxide, etc. can be used. Here, the n - element metal oxide is composed of n types of metal oxides. Note that the oxide semiconductor layer may contain, as an impurity, an element other than the main - component metal oxide in an amount of 1% or less, preferably 0.1% or less. It may contain, as an impurity, an element other than the main - component metal oxide in an amount of 1% or less, preferably 0.1% or less.

[0133] In addition, the oxide semiconductor layer 542 is a ternary metal oxide, and a metal oxide represented by InM X Zn Y O Z (Y = 0 .5 to 5) may be used. Here, M represents one or more elements selected from Group 13 elements such as gallium (Ga), aluminum (Al), and boron (B). Note that the contents of In, M, Zn, and O are arbitrary, and the content of M is zero. It can be expressed as (Y = 0.5 to 5). Here, M represents one or more elements selected from Group 13 elements such as gallium (Ga), aluminum (Al), and boron (B). Note that the contents of In, M, Zn, and O are arbitrary, and the content of M is zero. (i.e., x = 0) is included. On the other hand, the contents of In and Zn are not zero. That is , the above notations include In-Ga-Zn-O based metal oxides and In-Zn-O based metal oxides and the like.

[0134] In addition, the metal oxide forming the oxide semiconductor layer 542 has an energy gap of 2 eV or more , preferably 2.5 eV or more, more preferably 3 eV or more.

[0135] The oxide semiconductor layer 542 can appropriately use an oxide semiconductor having an amorphous structure, a microcrystalline structure, a polycrystalline structure, or a single crystal structure. Further, an oxide semiconductor having a crystal with a c-axis substantially parallel in the direction perpendicular to the surface can be used.

[0136] The oxide semiconductor layer 542 is formed of an i-type or substantially i-type oxide semiconductor layer. The i-type or substantially i-type oxide semiconductor layer has a carrier density of 5×10 / cm 14 less than, preferably less than 1×10 3 / cm 12 less than, more preferably less than 1×10 3 / c 11 / cm m 3 or less. Further, it is preferable that there are few hydrogen and oxygen defects contributing as donors, and the hydrogen concentration is preferably 1×10 16 / cm 3 or less. The carrier density is obtained by Hall effect measurement. Further, measurement of a lower carrier density is obtained from the measurement results of CV measurement (Capacitance-Voltage-Measurement). Also , measurement of the hydrogen concentration in the oxide semiconductor layer is obtained by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectroscopy). ​

[0137] A transistor using an i-type or substantially i-type oxide semiconductor layer 542 in the channel region The off-current of the transistor 505 is 1 × 10 -19 A / μm or less, and further 1 × 10 -20 A / μm or less. This is because the i-type or substantially i-type oxide semiconductor layer has a wide bandgap and requires a large amount of thermal energy for electron excitation Therefore, direct recombination and indirect recombination are less likely to occur. For this reason, in the state where a negative potential is applied to the gate electrode (off state), since the minority carriers, holes, are substantially zero, direct recombination and indirect recombination are less likely to occur, and the current becomes extremely low. As a result, in the non-conducting (off, also referred to as OFF) state of the transistor, the oxide semiconductor layer can be regarded as an insulator and circuit design can be performed. On the other hand, the i-type or substantially i-type oxide semiconductor layer has a higher current supply capacity than the semiconductor layer formed of amorphous silicon in the conducting state of the transistor Therefore, the transistor 505 becomes a normally-off state with extremely low leakage current in the off state and has excellent switching characteristics

[0138]

[0139] The gate insulating layer 544 can appropriately use the materials shown in the gate insulating layer 522 and the gate insulating layer 524. When the gate insulating layer 544 has a laminated structure, by forming the layer on the side in contact with the oxide semiconductor layer 542 with an oxide insulating layer, it is possible to supply oxygen to the oxygen vacancies contained in the oxide semiconductor layer 542 and make the oxide semiconductor layer 542 i-type or substantially i-type

[0139] ​​​​The insulating layer 552 and the insulating layer 554 can be formed in the same manner as the insulating layer 536, the insulating layer 538, or the insulating layer 540. It can be formed in the same manner.

[0140] In this embodiment, since the channel region of the diode-connected transistor 505 is formed of an i-type or substantially i-type oxide semiconductor layer, the off-current can be extremely reduced. Therefore, the voltage applied to the capacitor element 504 can be held for a long time.

[0141] Next, in the semiconductor memory device shown in FIG. 15, the manufacturing process of the transistor 505 will be described with reference to FIG. 16. Note that the manufacturing processes of the transistors 502, 503, and 506 may appropriately use known manufacturing processes of transistors. As shown in FIG. 16(A), wirings 534c and 534d that function as the source electrode and the drain electrode of the transistor 505 are formed over the insulating layer 540.

[0142] The insulating layer 540 can be formed by a sputtering method, a CVD method, a printing method, a coating method, or the like. Alternatively, a high-quality insulating layer 540 that is dense and has a high breakdown voltage can be formed by high-density plasma CVD using microwaves (for example, a frequency of 2.45 GHz). By bringing the oxide semiconductor layer into close contact with the high-quality insulating layer 540, interface levels can be reduced and interface characteristics can be improved. In addition, the insulating layer 540 obtained by high-density plasma CVD can be formed to have a constant thickness, and thus has excellent step coverage. Also, the thickness of the insulating layer 540 obtained by high-density plasma CVD can be precisely controlled. Note that the i-type or substantially i-type

[0143] Since the patterned oxide semiconductor layer is extremely sensitive to interface levels and interface charges, insulation By forming the layer 540 by high-density plasma CVD using microwaves, the interface level can be reduced and the interface characteristics can be improved.

[0144] When forming the insulating layer 540, by heating the substrate 508, hydrogen, water, hydroxyl groups, hydrides, etc. contained in the insulating layer 540 can be reduced.

[0145] Also, in order to reduce hydrogen, water, hydroxyl groups, hydrides, etc. contained in the insulating layer 540, when forming the insulating layer 540 by sputtering, it is preferable to form the insulating layer 540 while removing hydrogen, water, hydroxyl groups or hydrides remaining in the processing chamber. To remove hydrogen, water, hydroxyl groups, hydrides, etc. remaining in the processing chamber, it is preferable to use an adsorption type vacuum pump. Representative examples of adsorption type vacuum pumps are cryopumps, ion pumps, and titanium sublimation pumps. Also, as the exhaust means, a turbo pump with a cold trap added can be used.

[0146] Also, by setting the purity of the sputtering gas used when forming the insulating layer 540 to 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less), hydrogen, water, hydroxyl groups, hydrides, etc. contained in the insulating layer 540 can be reduced.

[0147] The wirings 534c and 534d can be manufactured by using a printing method, an inkjet method, etc., thereby reducing the number of processes. Or, on the insulating layer 540, by sputtering, CV ​​​​​​​​​​​After forming the conductive layer by a CVD method, an evaporation method, or the like, the conductive layer is etched using the resist formed by a photolithography process as a mask to form wirings 534c and 534d. This can be done.

[0148] Next, as shown in FIG. 16(B), an oxide semiconductor layer 541 is formed over the insulating layer 540, the wiring 534c, and the wiring 534d. The oxide semiconductor layer 541 can be formed using a printing method, an inkjet method, or the like. Alternatively, an oxide semiconductor layer is formed over the insulating layer 540 by a sputtering method, a CVD method, a coating method, a pulsed laser deposition method, or the like, and the oxide semiconductor layer is etched using the resist formed by a photolithography process as a mask to form an island-shaped oxide semiconductor layer 541. This can be done.

[0149] The carrier density of the oxide semiconductor layer depends on the hydrogen concentration and oxygen concentration of the source gas and target, the material to be formed and its composition, and the heat treatment conditions in the film formation conditions. By reducing the hydrogen concentration of the oxide semiconductor layer or increasing the oxygen concentration of the oxide semiconductor layer to reduce oxygen deficiency, the oxide semiconductor layer becomes an i-type or substantially an i-type. In this embodiment, since the treatment for making the oxide semiconductor layer an i-type or substantially an i-type is performed later, the oxide semiconductor layer 5 41 may be an i-type or an n-type.

[0150] Note that when the oxide semiconductor layer is formed by a sputtering method, heating the substrate can reduce impurities such as hydrogen, water, hydroxyl groups, and hydrides contained in the oxide semiconductor layer. In addition, crystal growth can be promoted in the first heat treatment.

[0151] Also, when forming the oxide semiconductor layer by sputtering, gold in the metal oxide target The relative density of the metal oxide is 80% or more, preferably 95% or more, more preferably 99.9% or more, so that the impurity concentration in the oxide semiconductor layer can be reduced, and transistors with good electrical characteristics and high reliability can be obtained.

[0152] Also, by performing a preheating treatment before forming the oxide semiconductor layer, hydrogen, water, hydroxyl groups, hydrides, etc. remaining on the inner wall of the sputtering apparatus, on the target surface, and in the target material can be removed. Therefore, impurities such as hydrogen, water, hydroxyl groups, and hydrides contained in the oxide semiconductor layer can be reduced.

[0153] Also, similar to the insulating layer 540, in order to remove hydrogen, water, hydroxyl groups, hydrides, etc. remaining in the sputtering apparatus before, during, or after forming the oxide semiconductor layer, it is preferable to use an adsorption type vacuum pump. As a result, hydrogen, water, hydroxyl groups, hydrides, etc. are exhausted, so that the concentration of hydrogen, water, hydroxyl groups, hydrides, etc. contained in the oxide semiconductor layer can be reduced.

[0154] Next, a first heat treatment is performed to remove impurities such as hydrogen, water, hydroxyl groups, and hydrides contained in the oxide semiconductor layer 541. That is, at least one of dehydration and dehydrogenation can be performed. Note that oxygen vacancies are formed in the oxide semiconductor layer 541 during the first heat treatment.

[0155] The temperature of the first heat treatment is 400°C or more and 750°C or less, preferably 400°C or more and less than the distortion point of the substrate. The heat treatment apparatus used for the first heat treatment is not particularly limited, and may be a resistance heating element or the like. It may also be provided with a device for heating the object to be processed by heat conduction or heat radiation from the heating element. Yes. For example, as the heat treatment device, an electric furnace, a GRTA (Gas Rapid Ther mal Anneal) device, an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal An neal) device, etc. can be used. The LRTA device is a device for heating the object to be processed by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. The GRTA device is a device for performing heat treatment using high-temperature gas.

[0156] In the first heat treatment, it is preferable that nitrogen or noble gases such as helium, neon, and argon do not contain hydrogen, water, hydroxyl groups, or hydrides, etc. Or, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment device is 6N (99.9999%) or more, preferably 7N (99.99999%) or more (that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0157] Also, in the first heat treatment, the inside of the furnace may be set to a nitrogen atmosphere during heating and the inside of the furnace may be set to an oxygen atmosphere during cooling to switch the atmosphere. After dehydration or dehydrogenation is performed in a nitrogen atmosphere, the atmosphere is switched to an oxygen atmosphere to supply oxygen to the oxygen deficiency in the oxide semiconductor layer so that it is possible to supply oxygen to the oxygen deficiency in the oxide semiconductor layer with a reduced hydrogen concentration and formed oxygen deficiency, and an i-type or substantially i-type oxide semiconductor layer can be formed. ​

[0158] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the oxide semiconductor layer may crystallize and become an oxide semiconductor layer having crystals. For example, it may become an oxide semiconductor layer having crystals with a crystallization rate of 90% or more, or 80% or more.

[0159] Also, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystals with a c-axis substantially parallel in the direction perpendicular to the surface may be formed in the surface layer portion of the amorphous oxide semiconductor layer, resulting in an oxide semiconductor layer.

[0160] Here, the substrate is introduced into an electric furnace and heat-treated at 450 °C for 1 hour in an inert gas atmosphere such as nitrogen or a rare gas.

[0161] Next, as shown in FIG. 16(C), a gate insulating layer 544 is formed.

[0162] The gate insulating layer 544 can be formed in the same manner as the insulating layer 540. When a silicon oxide layer is formed as the gate insulating layer 544 by sputtering, oxygen can be supplied to the oxygen vacancies contained in the oxide semiconductor layer 541 generated by the first heat treatment, reducing the oxygen vacancies contributing as donors and achieving a composition that satisfies the stoichiometric ratio. As a result, an i-type or substantially i-type oxide semiconductor layer 542 can be formed. Also, by closely contacting the oxide semiconductor layer and the high-quality insulating layer 540, the interface states can be reduced and the interface characteristics can be improved. Note that the i-type or substantially i-type oxide semiconductor layer has low interface states and interface charges 542 can be formed. Also, by closely contacting the oxide semiconductor layer and the high-quality insulating layer 540, the interface states can be reduced and the interface characteristics can be improved. By closely contacting the oxide semiconductor layer and the high-quality insulating layer 540, the interface states can be reduced and the interface characteristics can be improved.

[0163] Note that the i-type or substantially i-type oxide semiconductor layer has low interface states and interface charges Because it is extremely sensitive, the insulating layer 540 is formed by high density plasma CVD using microwaves. This makes it possible to reduce the interface state density and improve the interface characteristics.

[0164] Next, a second heat treatment (preferably at 200 The second heat treatment is performed at a temperature of 250° C. or higher and 400° C. or lower, for example, 250° C. or higher and 350° C. or lower. This may be performed after forming a protective insulating layer or a planarizing insulating layer on the base insulating layer 544. The process converts the oxide insulating layer of the gate insulating layer 544 into the oxide semiconductor generated by the first heat treatment. It is possible to supply oxygen to oxygen vacancies in the cellular layer, and oxygen that contributes as a donor It is possible to reduce defects and achieve a structure that satisfies the stoichiometric ratio. As a result, it is possible to achieve a more i-type structure. Alternatively, a substantially i-type oxide semiconductor layer 542 can be formed.

[0165] In this embodiment mode, the second heat treatment is performed in a nitrogen atmosphere at 250° C. for one hour.

[0166] Next, as shown in FIG. 16(D), an opening is formed in the gate insulating layer 544, and then the gate insulating A gate electrode 546a is formed on the layer 544 and the wiring 534d. Therefore, a transistor in which the output electrode 546a and the wiring 534d are diode-connected can be fabricated. The gate electrode 546a can be formed in a manner similar to that of the wirings 534c and 534d. Cut.

[0167] Next, as shown in FIG. 16(E), an insulating layer is formed on the gate insulating layer 544 and the gate electrode 546a. A layer 552 and an insulating layer 554 are formed.

[0168] In addition, heat treatment at 100°C to 200°C in air for 1 hour to 30 hours is performed. This is also acceptable. By performing such a heat treatment, the reliability of the transistor can be improved.

[0169] In FIG. 16, after forming the wiring 534c and the wiring 534d, an oxide semiconductor layer 541 is formed. However, after forming the oxide semiconductor layer 541 on the insulating layer 540, the wiring 534 c and the wiring 534d may be formed.

[0170] Also, in FIG. 16, a gate electrode 546a is formed on the insulating layer 540, a gate insulating layer 5 44 is formed on the gate electrode 546a, an oxide semiconductor layer 541 is formed on the gate insulating layer 544 and wirings that function as source and drain electrodes may be formed on the oxide semiconductor layer 541. In this case, one of the wirings that function as source and drain electrodes is electrically connected to the wiring 534c. Also, the other of the wirings that function as source and drain electrodes is electrically connected to the gate electrode 546a.

[0171] Through the above steps, a transistor 505 having an i - type or substantially i - type oxide semiconductor layer in the channel region and having an extremely low off - current can be fabricated.

[0172] (Embodiment 5) In this embodiment, the form of the RFID tag having the semiconductor memory device shown in Embodiments 1 to 4 will be described with reference to the drawings. The circuit shown in FIG. 17 is an RFID tag. RFID (Radio Frequency

[0173] IDentification: Non - contact automatic identification technology using radio frequency) has features such as non - contact readability of recorded information, battery - free operation, excellent durability, and weather resistance. Battery - free operation enables reading of recorded information without contact, and the device operates without a battery and has excellent durability and weather resistance. Battery - free The reason it can operate in the pond is because the antenna on the RFID tag receives radio waves (which contain operating instructions). This is because the power generated by rectifying the current (which includes current, etc.) in the circuit is RFID tags can be written or rewritten by users to improve their functionality. It is often the case that a memory capable of storing data is provided.

[0174] The RFID tag 1520 includes an antenna circuit 1521 and a signal processing circuit 1522. The signal processing circuit 1522 includes a rectifier circuit 1523, a power supply circuit 1524, a demodulation circuit 1525, an oscillator circuit 1526, and an oscillator circuit 1528. circuit 1526, logic circuit 1527, memory control circuit 1528, memory circuit 152 9, a logic circuit 1530, an amplifier 1531, and a modulation circuit 1532. 9 has the semiconductor memory device of the above embodiment.

[0175] A communication signal received by the antenna circuit 1521 is input to a demodulation circuit 1525. A communication signal transmitted between the antenna circuit 1521 and the reader / writer. The frequencies of the signals in the ultra-high frequency band are 13.56MHz, 915MHz, 2.45GHz, etc. Of course, there are antenna circuits 1521 and relays. The frequency of the signal transmitted between the reader / writer is not limited to this, and may be, for example, a submillimeter wave. 300GHz~3THz, millimeter wave 30GHz~300GHz, microwave 3GHz~30GHz, ultra-high frequency 300MHz~3GHz, ultra-high frequency 30MHz Any frequency between 1000 and 300 MHz can be used. The signal transmitted between the and the reader / writer is a signal modulated on a carrier wave. The modulation method is analog modulation or digital modulation, and can be any one of amplitude modulation, phase modulation, frequency modulation, and spread spectrum. Preferably, it is amplitude modulation or frequency modulation.

[0176] The oscillation signal output from the oscillation circuit 1526 is supplied to the logic circuit 1527 as a clock signal. Also, the modulated carrier wave is demodulated by the demodulation circuit 1525. The demodulated signal is also sent to the logic circuit 1527 for analysis. The signal analyzed by the logic circuit 1527 is sent to the memory control circuit 1528. The memory control circuit 1528 controls the memory circuit 1529, retrieves the data stored in the memory circuit 1529, and sends it to the logic circuit 1530. The signal sent to the logic circuit 1530 is encoded by the logic circuit 1530 and then amplified by the amplifier 1531. The signal amplified by the amplifier 1531 modulates the carrier wave by the modulation circuit 1532. With this modulated carrier wave, the reader / writer recognizes the signal from the RFID tag 1520.

[0177] The carrier wave entering the rectifier circuit 1523 is rectified and then input to the power supply circuit 1524. The power supply voltage obtained in this way is supplied from the power supply circuit 1524 to the demodulation circuit 1525, the oscillation circuit 1526, the logic circuit 1527, the memory control circuit 1528, the memory circuit 1529, the logic circuit 1530, the amplifier 1531, the modulation circuit 1532, etc.

[0178] The connection between the signal processing circuit 1522 and the antenna in the antenna circuit 1521 is not particularly limited. For example, the antenna and the signal processing circuit 1522 are connected using wire bonding connection or bump connection, or one side of the chipized signal processing circuit 1522 is used as an electrode. ​​​​​​​​​Attach it to the antenna. For attaching the signal processing circuit 1522 and the antenna, an ACF (a nisotropic conductive film; anisotropic conductive film) can be used. It can be used.

[0179] The antenna is provided by being laminated on the same substrate together with the signal processing circuit 1522, or an external antenna is used. Of course, the antenna is provided above or below the signal processing circuit. The antenna can be provided above or below the signal processing circuit.

[0180] The rectifier circuit 1523 converts the AC signal induced by the carrier wave received by the antenna circuit 1521 into a DC signal. Convert it into a DC signal.

[0181] The RFID tag 1520 may have a battery 1581 as shown in FIG. 18. When the power supply voltage output from the rectifier circuit 1523 is not sufficient to operate the signal processing circuit 1522, the battery 1581 also supplies the power supply voltage to each circuit constituting the signal processing circuit 1522, for example, the demodulation circuit 1525, the oscillation circuit 1526, the logic circuit 1527, the memory control circuit 1528, the memory circuit 1529, the logic circuit 1530, the amplifier 1531, the modulation circuit 1532, etc. When the power supply voltage output from the rectifier circuit 1523 is not sufficient to operate the signal processing circuit 1522, the battery 1581 also supplies the power supply voltage to each circuit constituting the signal processing circuit 1522, for example, the demodulation circuit 1525, the oscillation circuit 1526, the logic circuit 1527, the memory control circuit 1528, the memory circuit 1529, the logic circuit 1530, the amplifier 1531, the modulation circuit 1532, etc. When the power supply voltage output from the rectifier circuit 1523 is not sufficient to operate the signal processing circuit 1522, the battery 1581 also supplies the power supply voltage to each circuit constituting the signal processing circuit 1522, for example, the demodulation circuit 1525, the oscillation circuit 1526, the logic circuit 1527, the memory control circuit 1528, the memory circuit 1529, the logic circuit 1530, the amplifier 1531, the modulation circuit 1532, etc. For example, the demodulation circuit 1525, the oscillation circuit 1526, the logic circuit 1527, the memory control circuit 1528, the memory circuit 1529, the logic circuit 1530, the amplifier 1531, the modulation circuit 1532 1528, the memory circuit 1529, the logic circuit 1530, the amplifier 1531, the modulation circuit 1532 And so on.

[0182] Also, the surplus of the power supply voltage output from the rectifier circuit 1523 can be used to charge the battery 1581. By providing an antenna circuit and a rectifier circuit separately from the antenna circuit 1521 and the rectifier circuit 1523 in the RFID tag, energy stored in the battery 1581 can be obtained from randomly generated electromagnetic waves and the like. By charging the battery with power, the RFID tag can be used continuously. The battery is By providing an antenna circuit and a rectifier circuit separately from the antenna circuit 1521 and the rectifier circuit 1523 in the RFID tag, energy stored in the battery 1581 can be obtained from randomly generated electromagnetic waves and the like. Energy stored in the battery 1581 can be obtained from randomly generated electromagnetic waves and the like.

[0183] By charging the battery with power, the RFID tag can be used continuously. The battery is A battery formed in a sheet shape can be used. For example, a lithium polymer battery, a lithium-ion battery, a lithium secondary battery, etc. can be used to make the battery compact. Also, as the battery, a nickel-metal hydride battery, a nickel-cadmium battery, or a large-capacity capacitor, etc. can be used.

[0184] (Embodiment 6) In this embodiment, the usage example of the RFID tag 1520 shown in Embodiment 5 will be described with reference to the drawings.

[0185] The uses of the RFID tag 1520 are extensive. For example, banknotes, coins, securities, bearer bonds, certificates (driver's license, residence card, etc. (see Fig. 19(A)).), recording media (DVD software, video tape, etc. (see Fig. 19(B)).), packaging containers (wrapping paper, bottles, etc. (see Fig. 19(C)).), vehicles (bicycles, etc. (see Fig. 19(D)).), personal items such as bags and glasses), food items, plants, animals, the human body, clothing, daily necessities, or electronic devices (liquid crystal display devices, EL display devices, television sets, or mobile phones), etc., or labels attached to each item (see Figs. 19(E) and 19(F)).) can be provided and used.

[0186] The RFID tag 1520 is fixed to an item by being mounted on a printed circuit board, pasted on the surface, or embedded. For example, if it is a book, it can be embedded in the paper, or if it is a package made of an organic resin, it can be embedded in the organic resin and fixed to each item. The RFID tag 1520 is compact, thin, and lightweight, so even after being fixed to an item, it does not impair the design of the item itself. ​​​This is not possible. Also, by providing an RFI D tag 1520 on banknotes, coins, securities, bearer bonds, or certificates, etc., an authentication function can be provided, and by utilizing this authentication function counterfeiting can be prevented. Further, by attaching the RFID tag of the present invention to packaging containers, recording media, personal items, food products, clothing, daily necessities, or electronic devices, etc., the efficiency of systems such as inspection systems can be improved. Also, for vehicles by attaching the RFID tag 1520, the security against theft, etc. can be enhanced.

Example

[0187] In this example, the results of verifying the data retention time of the memory elements shown in Embodiments 1 to 3 by circuit simulation are shown.

[0188] Fig. 20 shows a circuit diagram for simulation and its results. The circuit shown in Fig. 20(A) is a memory element which is an aspect of the present invention, and has a diode-connected transistor 601, a transistor 602, and a capacitance element 603. A simulation-equivalent circuit is shown in Fig. 20(B). The circuit shown in Fig. 20(B) has a resistor 611, a transistor 612 , a capacitance 613, a resistor 614, and a resistor 615. The resistor 611 is equivalent to the diode-connected transistor 601 in the off state, the resistor 614 represents the gate leakage component of the transistor 612 , and the resistor 615 represents the electrode-to-electrode leakage component of the capacitance 613.

[0189] Assuming the state immediately after writing, simulation was performed with the initial voltage of node A set to 2V. As the simulation software, SIMUCAD DESIGN AUTOMATI ​ The Gateway, Version 2.6.12.R of ON Company was used. The potential of Node A is , the resistance 611 assuming the off-current of the diode-connected transistor 601, the resistance 614 assuming the gate leakage component of the transistor 612, and the resistance 615 assuming the inter-electrode leakage component of the capacitor 613 each decrease monotonically with the passage of time. The time until the potential drops and the transistor 612 can no longer maintain the off state is the data retention time. In this embodiment, the period until the voltage drops by 10%, that is, until it reaches 1.8 V, is defined

[0190] as the period during which Data 1 can be retained, that is, the Data 1 retention time. For Conditions 1 and 2, the resistance value of the resistance 611 was set to the value of the off-current of a transistor in which the channel region of the diode-connected transistor 601 was formed of an oxide semiconductor layer. Condition 3 was that the resistance value of the resistance 611 was set to the value of the off-current 20 of a transistor in which the channel region of the diode-connected transistor 601 was not formed of an oxide semiconductor layer. -20 Condition 1: 2×10 19 Ω (10 -1 9 A in terms of off-current), Condition 2: 2×10 9 Ω (10 -9 A in terms of off-current), Condition 3: 2×10 Ω (10

[0191] The simulation results are shown in Fig. 20(C). Fig. 20(C) is a graph with the elapsed time on the horizontal axis and the voltage of Node A on the vertical axis. Under Condition 3, the Data 1 retention time was 176.3 μs, while under Condition 1, the Data 1 retention time was 17.63×10 6s (about 200 days) , in Condition 2, the data 1 retention time was 1.763×10 6 s (about 20 days). From this res ult, it was found that by forming the channel region of the diode-connected transistor 601 with an oxide semiconductor layer , it is possible to hold data 1 for a significantly longer period.

Example

[0192] In this example, the results of obtaining the off-current of a transistor using an i-type or substantially i-type oxide semiconductor layer in the channel region will be described. First, considering that the off-current of a transistor using an i-type or substantially i-type oxide semiconductor layer in the channel region is sufficiently small, a transistor with a sufficiently large channel width W of 1 m was prepared and the off-current was measured. The results of measuring the off-current of a transistor with a channel width W of 1 m are shown in FIG. 21. In FIG. 21, the horizontal axis is the gate voltage VG and the vertical axis is

[0193] the drain current ID. When the drain voltage VD is +1V or +10V, in the range where the gate voltage VG is from -5V to -20V, the off-current of the transistor is found to be below 1×10 A. Also, the off-current of the transistor (here, the value per unit channel width ( 1 μm)) is found to be 1 aA / μm (1×10 A / μm) or less. A. -12 below Next, the results of more accurately obtaining the off-current of a transistor using an i-type or substantially i-type oxide semiconductor layer will be described. As described above, the off-current of a transistor using an i-type or substantially i-type oxide semiconductor layer in the channel region is 1×1 -18 A / μm (1×10 A / μm) or less.

[0194] Next, the results of more accurately obtaining the off-current of a transistor using an i-type or substantially i-type oxide semiconductor layer will be described. As described above, the off-current of a transistor using an i-type or substantially i-type oxide semiconductor layer in the channel region is 1×1 A / μm (1×1 0 -12 It was found to be A or less. Therefore, a device for characteristic evaluation was fabricated, and the results of obtaining the value of the offset current (a value below the detection limit of the measuring instrument in the above measurement) will be described. Regarding the results of obtaining the value of the offset current (a value below the detection limit of the measuring instrument in the above measurement), an explanation will be given.

[0195] First, the device for characteristic evaluation used in the current measurement method will be described with reference to FIG. 22.

[0196] The device for characteristic evaluation shown in FIG. 22 has three measurement systems 800 connected in parallel. The measurement system 80 0 includes a capacitive element 802, transistors 804, 805, 806 , and a transistor 808. Transistors 804, 805, and 806 are applied with transistors using an i-type or substantially i-type oxide semiconductor layer in the channel region.

[0197] In the measurement system 800, one of the source terminal and the drain terminal of the transistor 804, one of the terminals of the capacitive element 802, and one of the source terminal and the drain terminal of the transistor 805 are connected to a power supply (a power supply that supplies V2). Also, the other of the source terminal and the drain terminal of the transistor 804, one of the source terminal and the drain terminal of the transistor 808, the other of the terminals of the capacitive element 802, and the gate terminal of the transistor 805 are connected in series. Further, the other of the source terminal and the drain terminal of the transistor 808, one of the source terminal and the drain terminal of the transistor 806, and the gate terminal of the transistor 806 are connected to a power supply (a power supply that supplies V1). Also, the other of the source terminal and the drain terminal of the transistor 805, one of the source terminal and the drain terminal of the transistor 806, and the source terminal and the drain of the transistor 806 are connected to a power supply (a power supply that supplies V1). Also, the other of the source terminal and the drain terminal of the transistor 805, one of the source terminal and the drain terminal of the transistor 806, and the source terminal and the drain ​The other side of the terminal is connected and serves as the output terminal Vout.

[0198] Note that a potential Vext_b2 for controlling the on-state and off-state of the transistor 804 is supplied to the gate terminal of the transistor 804, and a potential Vext_b1 for controlling the on-state and off-state of the transistor 808 is supplied to the gate terminal of the transistor 808. Note that a potential Vext_b2 for controlling the on-state and off-state of the transistor 804 is supplied to the gate terminal of the transistor 804, and a potential Vext_b1 for controlling the on-state and off-state of the transistor 808 is supplied to the gate terminal of the transistor 808. Note that a potential Vext_b2 for controlling the on-state and off-state of the transistor 804 is supplied to the gate terminal of the transistor 804, and a potential Vext_b1 for controlling the on-state and off-state of the transistor 808 is supplied to the gate terminal of the transistor 808. Also, a potential Vout is output from the output terminal.

[0199] Next, a current measurement method using the above-described element for characteristic evaluation will be described.

[0200] First, an outline of the initialization period for applying a potential difference to measure the off-current will be described. During the initialization period, a potential Vext_b1 for turning on the transistor 808 is input to the gate terminal of the transistor 808, and a potential V1 is applied to a node A (that is, one of the source terminal and drain terminal of the transistor 808, the other side of the terminal of the capacitive element 802, and the node connected to the gate terminal of the transistor 805) that is connected to the other side of the source terminal or drain terminal of the transistor 804. Here, the potential V1 is, for example, a high potential. Also, the transistor 804 is kept in the off-state. During the initialization period, a potential Vext_b1 for turning on the transistor 808 is input to the gate terminal of the transistor 808, and a potential V1 is applied to a node A (that is, one of the source terminal and drain terminal of the transistor 808, the other side of the terminal of the capacitive element 802, and the node connected to the gate terminal of the transistor 805) that is connected to the other side of the source terminal or drain terminal of the transistor 804. Here, the potential V1 is, for example, a high potential. Also, the transistor 804 is kept in the off-state. During the initialization period, a potential Vext_b1 for turning on the transistor 808 is input to the gate terminal of the transistor 808, and a potential V1 is applied to a node A (that is, one of the source terminal and drain terminal of the transistor 808, the other side of the terminal of the capacitive element 802, and the node connected to the gate terminal of the transistor 805) that is connected to the other side of the source terminal or drain terminal of the transistor 804. Here, the potential V1 is, for example, a high potential. Also, the transistor 804 is kept in the off-state. During the initialization period, a potential Vext_b1 for turning on the transistor 808 is input to the gate terminal of the transistor 808, and a potential V1 is applied to a node A (that is, one of the source terminal and drain terminal of the transistor 808, the other side of the terminal of the capacitive element 802, and the node connected to the gate terminal of the transistor 805) that is connected to the other side of the source terminal or drain terminal of the transistor 804. Here, the potential V1 is, for example, a high potential. Also, the transistor 804 is kept in the off-state. During the initialization period, a potential Vext_b1 for turning on the transistor 808 is input to the gate terminal of the transistor 808, and a potential V1 is applied to a node A (that is, one of the source terminal and drain terminal of the transistor 808, the other side of the terminal of the capacitive element 802, and the node connected to the gate terminal of the transistor 805) that is connected to the other side of the source terminal or drain terminal of the transistor 804. Here, the potential V1 is, for example, a high potential. Also, the transistor 804 is kept in the off-state. During the initialization period, a potential Vext_b1 for turning on the transistor 808 is input to the gate terminal of the transistor 808, and a potential V1 is applied to a node A (that is, one of the source terminal and drain terminal of the transistor 808, the other side of the terminal of the capacitive element 802, and the node connected to the gate terminal of the transistor 805) that is connected to the other side of the source terminal or drain terminal of the transistor 804. Here, the potential V1 is, for example, a high potential. Also, the transistor 804 is kept in the off-state.

[0201] Thereafter, a potential Vext_b1 for turning off the transistor 808 is input to the gate terminal of the transistor 808 to turn off the transistor 808. After turning off the transistor 808, the potential V1 is set to a low potential. Here too, the transistor 804 is kept in the off-state. Also, the potential V2 is set to the same potential as the potential V1. Thus, the initialization period ends. In the state where the initialization period has ended, between the node A and the source terminal of the transistor 804 Thereafter, a potential Vext_b1 for turning off the transistor 808 is input to the gate terminal of the transistor 808 to turn off the transistor 808. After turning off the transistor 808, the potential V1 is set to a low potential. Here too, the transistor 804 is kept in the off-state. Also, the potential V2 is set to the same potential as the potential V1. Thus, the initialization period ends. In the state where the initialization period has ended, between the node A and the source terminal of the transistor 804 Thereafter, a potential Vext_b1 for turning off the transistor 808 is input to the gate terminal of the transistor 808 to turn off the transistor 808. After turning off the transistor 808, the potential V1 is set to a low potential. Here too, the transistor 804 is kept in the off-state. Also, the potential V2 is set to the same potential as the potential V1. Thus, the initialization period ends. In the state where the initialization period has ended, between the node A and the source terminal of the transistor 804 Thereafter, a potential Vext_b1 for turning off the transistor 808 is input to the gate terminal of the transistor 808 to turn off the transistor 808. After turning off the transistor 808, the potential V1 is set to a low potential. Here too, the transistor 804 is kept in the off-state. Also, the potential V2 is set to the same potential as the potential V1. Thus, the initialization period ends. In the state where the initialization period has ended, between the node A and the source terminal of the transistor 804 Thereafter, a potential Vext_b1 for turning off the transistor 808 is input to the gate terminal of the transistor 808 to turn off the transistor 808. After turning off the transistor 808, the potential V1 is set to a low potential. Here too, the transistor 804 is kept in the off-state. Also, the potential V2 is set to the same potential as the potential V1. Thus, the initialization period ends. In the state where the initialization period has ended, between the node A and the source terminal of the transistor 804 A potential difference is generated between one of the source and drain terminals, and a potential difference is also generated between node A and the other of the source and drain terminals of transistor 808 Therefore, a slight amount of charge will flow through transistors 804 and 808. That is, an off-current is generated

[0202] Next, an outline of the off-current measurement period will be described. During the measurement period, the potential of one of the source or drain terminals of transistor 804 (i.e., V2), and the potential of the other of the source or drain terminals of transistor 808 (i.e., V1) are fixed at a low potential. On the other hand, during the measurement period, the potential of the above node A is not fixed (in a floating state). As a result, charge flows through transistor 804, and the amount of charge held at node A varies with the passage of time. Then, as the amount of charge held at node A varies, the potential of node A varies. That is, the output potential Vout of the output terminal also varies

[0203] The details (timing chart) of the relationship between each potential during the initialization period for applying the potential difference and the subsequent measurement period are shown in FIG. 23

[0204] During the initialization period, first, the potential Vext_b2 is set to a potential (high potential) such that transistor 804 is turned on. As a result, the potential of node A becomes V2, that is, a low potential (VSS). Then, the potential Vext_b2 is set to a potential (low potential) such that transistor 804 is turned off, and transistor 804 is turned off. Next, the potential Vext_b1 is set to a potential (high potential) such that transistor 808 is turned on ​​​​​​​​​​​​​​. As a result, the potential of node A becomes V1, that is, the high potential (VDD). Then, the potential Vext_b1 is set to a potential such that transistor 808 is in the off state. Thus, node A becomes in a floating state, and the initialization period ends.

[0205] In the subsequent measurement period, the potential V1 and the potential V2 are set to potentials such that charge flows into node A, or charge flows out from node A. Here, the potential V1 and the potential V 2 are set to the low potential (VSS). However, at the timing of measuring the output potential Vout, since it is necessary to operate the output circuit, V1 is temporarily set to the high potential (VDD) for a certain period. The period during which V1 is set to the high potential (VDD) is set to a short period that does not affect the measurement.

[0206] When the potential difference is applied as described above and the measurement period starts, as time passes, the amount of charge held in node A varies, and accordingly, the potential of node A varies. This means that the potential of the gate terminal of transistor 805 varies, so as time passes, the potential of the output potential Vout at the output terminal also changes.

[0207] A method for calculating the off - current from the obtained output potential Vout will be described below.

[0208] Prior to calculating the off - current, the relationship between the potential VA of node A and the output potential Vout is obtained and stored. Thus, the potential VA of node A can be obtained from the output potential Vout. From the above relationship, the potential VA of node A can be expressed as a function of the output potential Vout as follows:

[0209] ​​

Number

[0210] Also, the charge QA of node A is expressed as follows using the potential VA of node A, the capacitance CA connected to node A, and a constant (const). Here, the capacitance CA connected to node A is the sum of the capacitance of the capacitive element 802 and other capacitances.

Number

[0211]

Number

[0212] Since the current IA of node A is the time derivative of the charge flowing into (or flowing out of) node A, the current IA of node A is expressed as follows.

Number

[0213]

Number

[0214] In this way, the current IA of node A can be obtained from the capacitance CA connected to node A and the output potential Vout of the output terminal.

Number

[0215] By the method shown above, the leakage current (off-current) flowing between the source and drain of the transistor in the off state can be measured.

Number

[0216] In this embodiment, transistors 804, 805, 806, and 808 were fabricated using a highly purified oxide semiconductor with a channel length L = 10 μm and a channel width W = 50 μm. Also, in each parallel measurement system 800, the capacitance values of capacitive elements 802a to 802c were set such that the capacitance of capacitive element 802a was 100 fF and the capacitance of capacitive element 802b was...

Number

Number

[0217] In the measurement according to this embodiment, VDD = 5V and VSS = 0V. Also, during the measurement period the potential V1 was set to VSS in principle, and every 10 to 300 seconds, for a period of 100 mse Vout was measured as VDD only for that period. Also, the Δt used for calculating the current I flowing through the element was set to approximately 30000 seconds.

[0218] Fig. 24 shows the relationship between the elapsed time Time related to the above current measurement and the output potential Vout. From Fig. 24, it can be confirmed that the potential changes as time elapses.

[0219] Fig. 25 shows the off-current at room temperature (25 °C) calculated by the above current measurement. Note that Fig. 25 shows the relationship between the source-drain voltage V and the off-current I. Fig. From Fig. 25, it was found that the off-current is about 40 zA / μm under the condition that the source-drain voltage is 4V. Also, it was found that the off-current is 10 zA / μm or less under the condition that the source-drain voltage is 3.1V. Note that 1 zA represents 10 -21 A.

[0220] Furthermore, the off-current in the temperature environment of 85 °C calculated by the above current measurement is shown in Fig. 26. Fig. 26 shows the relationship between the source-drain voltage V and the off current I in the temperature environment of 85 °C. From Fig. 26, under the condition that the source-drain voltage is 3.1V it was found that the off-current is 100 zA / μm or less.

[0221] As described above, according to this embodiment, an i-type or substantially i-type oxide semiconductor layer is used as the channel region In the transistor used for the field, it was confirmed that the off-current became sufficiently small. Also, as shown in Embodiment 1 to Embodiment 3, transistors 102, 112, 1 22, 132 using an i-type or substantially i-type oxide semiconductor layer in the channel region and diode-connected also have an off-current that becomes sufficiently small.

Explanation of Signs

[0222] 101 Memory element 102 Transistor 103 Transistor 104 Capacitor element 110 Memory cell 111 Memory element 112 Transistor 113 Transistor 114 Capacitor element 115 Transistor 116 Transistor 117 Circuit 118 Inverter 120 Memory cell 121 Memory element 122 Transistor 123 Transistor 124 Capacitor element 125 Transistor 129 Region 130 Memory cell 131 Memory element 132 Transistor 133 Transistor 134 Capacitor element 135 Transistor 300 Semiconductor memory device 301 Memory cell array 302 Column decoder 303 Row decoder 304 Interface circuit 305 Memory cell 310 Semiconductor memory device ​​311 Memory cell array 312 Memory cell array 313 Memory cell 314 Memory cell 400 Memory cell 401 Memory element 402 Transistor 403 Transistor 404 Capacitive element 405 Transistor 406 Transistor 502 Transistor 503 Transistor 504 Capacitive element 505 Transistor 506 Transistor 508 Substrate 510 Insulating layer 512 Insulating layer 514 Channel region 516 Low-concentration impurity region 518 High-concentration impurity region 519 Semiconductor layer 520 Semiconductor layer 522 Gate insulating layer 524 Gate insulating layer 526 Gate electrode 528 Capacitive electrode 530 Sidewall insulating layer 532 Sidewall insulating layer 534a Wiring 534b Wiring 534c Wiring 534d Wiring 534e Wiring 534f Wiring 536 Insulating layer 538 Insulating layer 540 Insulating layer 541 Oxide semiconductor layer 542 Oxide semiconductor layer 544 Gate insulating layer 546a Gate electrode 546b Wiring 552 Insulating layer 554 Insulating layer 601 Transistor 602 Transistor 603 Capacitive element 611 Resistor 612 Transistor 613 Capacitance 614 Resistor 615 Resistor 800 Measurement system 802 Capacitive element 802a Capacitive element 802b Capacitive element 802c Capacitive element 804 Transistor 805 Transistor 806 Transistor 808 Transistor 1520 RFID tag 1521 Antenna circuit 1522 Signal processing circuit 1523 Rectifier circuit 1524 Power supply circuit 1525 Demodulation circuit 1526 Oscillator circuit 1527 Logic circuit 1528 Memory control circuit 1529 Memory circuit 1530 Logic circuit 1531 Amplifier 1532 Modulation circuit 1581 Battery

Claims

1. a first transistor, a second transistor, a third transistor, and a fourth transistor; one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor; the other of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the third transistor; the other of the source and the drain of the first transistor is electrically connected to the gate of the first transistor; one of a source and a drain of the second transistor is electrically connected to one of a source and a drain of the fourth transistor; the other of the source and the drain of the third transistor is electrically connected to a first wiring; the other of the source and the drain of the second transistor is electrically connected to a second wiring; the other of the source and the drain of the fourth transistor is electrically connected to a third wiring; the gate of the third transistor is electrically connected to a fourth wiring; The gate of the fourth transistor is electrically connected to a fifth wiring. a channel formation region of the first transistor having a region through which carriers flow in a first direction; a channel formation region of the second transistor having a region through which carriers flow in a direction along the first direction; a channel formation region of the third transistor has a region through which carriers flow in a direction along the first direction, a channel formation region of the fourth transistor has a region in which carriers flow in a direction along the first direction, In a plan view, the first wiring, the second wiring, and the third wiring each have a region extending in a direction intersecting the first direction, In a plan view, the fourth wiring and the fifth wiring have a region extending in the first direction, the first transistor has an oxide semiconductor in a channel formation region; the first wiring is provided in contact with an upper surface of an insulating layer, The third wiring is provided in contact with an upper surface of the insulating layer.

2. In claim 1, the second transistor has an oxide semiconductor in a channel formation region, the third transistor has an oxide semiconductor in a channel formation region, The fourth transistor is a semiconductor device including an oxide semiconductor in a channel formation region.

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