Selective Carbon Deposition on the Top and Bottom Surfaces of a Semiconductor Substrate

Abstract

A semiconductor processing method is described that includes providing a substrate including a substrate trench having a top surface and a bottom surface to a reaction chamber. A deposition gas including a carbon-containing gas and a nitrogen-containing gas is flowed into a plasma excitation region of the reaction chamber. A deposition plasma having an electron temperature of about 4 eV or less is generated from the deposition gas. The method further includes depositing a carbon-containing layer on the top and bottom surfaces of the substrate trench, the as-deposited carbon-containing layer having a top-to-bottom thickness ratio of about 3:1 or greater. Also described is a semiconductor structure that includes an as-deposited carbon-containing layer on the top and bottom surfaces of at least a first trench and a second trench, the carbon-containing layer having a top-to-bottom thickness ratio of about 3:1 or greater.

Description

Technical Field

[0001] Cross-reference

[0001] This application claims priority to U.S. Application No. 17 / 359,947, filed June 28, 2021. The disclosure thereof is hereby incorporated by reference in its entirety for all purposes.

[0002]

[0002] This technology relates to semiconductor systems, processes, and devices. More specifically, this technology relates to processes and structures for selectively depositing carbon films.

Background Art

[0003]

[0003] Integrated circuits are enabled by a process that produces intricately patterned material layers on a substrate surface. To produce patterned material on a substrate, a controlled method for the formation and removal of exposed material is required. The properties of the material can affect the operation of the device and also how the films are removed relative to each other. Plasma-assisted deposition can produce films with specific properties. Many of the films formed require additional processing to adjust or enhance the material properties of the film to obtain suitable properties.

[0004]

[0004] Accordingly, there is a need for improved systems and methods that can be used to manufacture high-quality devices and structures. These and other needs are addressed by this technology.

Summary of the Invention

[0005]

[0005] An embodiment of the present technology includes supplying a substrate to a reaction chamber, the substrate including a substrate trench having a top surface and a bottom surface, and the method of semiconductor processing includes supplying the substrate to the reaction chamber. The method also includes flowing a deposition gas into a plasma excitation region of the reaction chamber, the deposition gas including a carbon-containing gas and a nitrogen-containing gas. A deposition plasma having an electron temperature of about 4 eV or less is generated from the deposition gas. The method further includes depositing a carbon-containing layer on the top surface and the bottom surface of the substrate trench, and the as-deposited carbon-containing layer has a top surface to bottom surface thickness ratio of about 3:1 or more.

[0006]

[0006] In a further embodiment, the deposition gas does not include argon. In a further embodiment, the deposition gas does not include helium. In yet a further embodiment, the method further includes heating the substrate to a temperature of about 100 °C or more before depositing the carbon-containing layer. In another further embodiment, the method also includes etching through at least a portion of the carbon-containing layer on the bottom surface of the substrate trench, the carbon-containing layer still covering the top surface of the substrate trench. In a further embodiment, the method also includes removing the carbon-containing layer from the substrate after etching at least a portion of the carbon-containing layer on the bottom surface of the substrate trench. In yet a further embodiment, the carbon-containing gas includes methane. In yet a further embodiment, the nitrogen-containing gas includes molecular nitrogen (N 2 ). In a further embodiment, the deposition plasma is generated by supplying RF power to the deposition gas, and the RF power is characterized by a power of about 300 watts or less. In a further embodiment, the deposition plasma is characterized by a pressure of about 10 mTorr or less.

[0007]

[0007] An embodiment of the present technology is to supply a substrate to a reaction chamber, where the substrate includes a first trench with a first aspect ratio of about 2:1 or more and a second trench with a second aspect ratio of about 1:2 or less. A semiconductor processing method including supplying the substrate to the reaction chamber is also included. Also, the first trench and the second trench each have a top surface and a bottom surface. The method further includes heating the substrate to a temperature of about 100 °C or more. The method also includes flowing a deposition gas into a plasma excitation region of the reaction chamber, where the deposition gas includes a carbon-containing gas and a nitrogen-containing gas. A deposition plasma is generated from the deposition gas. The method also further includes depositing a carbon-containing layer on the heated substrate, where the as-deposited carbon-containing layer has a top surface to bottom surface thickness ratio of about 3:1 or more in both the first trench and the second trench.

[0008]

[0008] In a further embodiment, the method may also include etching through at least a portion of the carbon-containing layer on the bottom surfaces of the first substrate trench and the second substrate trench, where the carbon-containing layer still covers the top surfaces of the first substrate trench and the second substrate trench. In a further embodiment, the method may further include removing the carbon-containing layer from the substrate after etching at least a portion of the carbon-containing layer on the bottom surfaces of the first substrate trench and the second substrate trench. In yet a further embodiment, the deposition plasma is characterized by an electron temperature of about 4 eV or less. In another further embodiment, the first substrate trench is characterized by a first bottom width of about 50 nm or less, and the second substrate trench is characterized by a second bottom width of about 100 nm or more. In a further embodiment, the carbon-containing layer is characterized by a top surface thickness of about 5 nm or more and a bottom surface thickness of about 1.6 nm or less. In yet a further embodiment, the carbon-containing layer includes solid carbon.

[0009]

[0009] Embodiments of the present technology further include a semiconductor structure including a first trench and a second trench formed in at least one semiconductor material. The first trench and the second trench have a top surface and a bottom surface, the first trench is characterized by a first aspect ratio of about 2:1 or more, and the second trench is characterized by a second aspect ratio of about 1:2 or less. The semiconductor structure may also include a dielectric layer in contact with at least one semiconductor material, the dielectric layer forming the top surface and the bottom surface of the first trench and the second trench. The semiconductor structure may also include a carbon-containing layer in contact with the dielectric layer at the top surface and the bottom surface of the first trench and the second trench. The carbon-containing layer is characterized by a top-to-bottom thickness ratio of about 3:1 or more in both the first trench and the second trench.

[0010]

[0010] In a further embodiment, the dielectric layer may include silicon nitride. In a further embodiment, the carbon-containing layer may include solid carbon. In yet a further embodiment, the dielectric layer is characterized by a bottom thickness of about 5 nm or more. In yet a further embodiment, the carbon-containing layer is characterized by a top thickness of about 5 nm or more and a bottom thickness of about 1.6 nm or less. In a further embodiment, the semiconductor structure includes a contact region positioned below the carbon-containing layer and the dielectric layer at the bottom surface of the first trench.

[0011]

[0011] The above technique provides several advantages over conventional methods and structures in providing a thin and easily removable mask layer that protects the top and sidewall surfaces of the semiconductor trench while etching the opening on the bottom surface. Embodiments of the method include the use of a selective deposition gas that deposits more carbon-containing layer on the top surface of the trench than on the bottom surface of the trench. By thickening the carbon-containing layer on the top surface, after forming a hole that penetrates the layer on the bottom surface in the etching process, the coverage of the layer on the top surface can be made seamless. Thereby, openings such as contact holes and vias are formed on the bottom surface without etching the top and side surfaces of the trench. Embodiments of the method also include heating the bottom surface of the substrate trench to a temperature that slows the deposition of the carbon-containing layer on the bottom surface relative to the top surface. These embodiments also selectively deposit more carbon-containing layer on the top surface of the trench than on the bottom surface of the trench. These embodiments and other embodiments will be described in more detail below in conjunction with the following description and the accompanying figures, along with their many advantages and features.

[0012]

[0012] A further understanding of the nature and advantages of the disclosed technology can be obtained by reference to the remainder of this specification and the drawings.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

DETAILED DESCRIPTION OF THE INVENTION

[0014]

[0021] Some of the drawings are included as schematic diagrams. It should be understood that the figures are for illustrative purposes and are not to be considered to be to scale unless a scale is specified. Further, as schematic diagrams, the figures are provided to aid understanding and may not include all aspects or information compared to a realistic representation, and may include exaggerated materials for illustrative purposes.

[0015]

[0022] In the accompanying drawings, similar components and / or features may be labeled with the same reference label. Further, various components of the same type may be distinguished by attaching letters after the reference label to distinguish similar components. When only the first reference label is used in this specification, the description is applicable to any one of the similar components having the same first reference label regardless of the letters.

[0016]

[0023] A feature seen in many semiconductor structures is a conductive contact that extends from a semiconductor device layer to a metallization layer. In many cases, these contacts are fabricated by dry etching an opening in a dielectric material and filling the opening with a conductive material such as aluminum, copper, or tungsten. In most of these cases, the deposition of a mask layer to protect unetched portions of the semiconductor device during the etching process is also included in the manufacturing process. As the size of semiconductor devices continues to shrink and the distance between adjacent devices also decreases, the etching process of forming an opening without unintentionally etching a portion of the device becomes more difficult.

[0017]

[0024] One approach for protecting a semiconductor device during an etching process to form contacts is to cover the device structure with a layer of a protective material such as carbon. The protective layer prevents the upper and sidewall surfaces of the device structure from being etched while openings are etched in the bottom surface that are subsequently filled with a conductive material by an etching process. As the semiconductor device structure becomes smaller, the protective layer becomes thinner. Unfortunately, a protective layer made of an easily removable material such as carbon is very thin (e.g., less than 10 nm), and it is common for the etching process to break through the layer on both the upper and bottom surfaces of the trenches of the semiconductor device. The etching process does not have the spatial or temporal precision to etch an opening in the bottom surface of the trench without breaking through the protective layer deposited on the upper surface and damaging the semiconductor device.

[0018]

[0025] Embodiments of the present technology address, among other problems, the problem that the protective layer on the upper surface of a trench of a semiconductor device is destroyed during etching of the bottom surface of the trench. Embodiments of the present technology include a method of depositing a carbon-based protective layer thicker on the upper surface of the trench than on the bottom surface. The thicker the carbon-containing layer remaining deposited on the upper surface of the trench, the lower the likelihood that the etching process will break through the carbon-containing layer on the upper surface. The etching process for forming an opening that penetrates the carbon-containing layer on the bottom surface of the trench often etches through one or more additional layers, but the upper surface of the device remains unetched.

[0019]

[0026] Embodiments of the present technology include a plasma deposition gas that increases the selectivity of plasma deposition of a carbon-containing layer with respect to the upper surface of a trench relative to its bottom surface. In an embodiment, the deposition gas includes a carbon-containing gas such as methane. In a further embodiment, the deposition gas includes a nitrogen-containing gas such as molecular nitrogen. In yet a further embodiment, the deposition gas does not include argon and does not include other inert elements and compounds having a molecular weight higher than that of molecular nitrogen. In a further embodiment, the deposition gas does not include helium and does not include other gases of relatively low atomic / molecular weight that significantly increase the temperature of the deposition plasma.

[0020]

[0027] A complex relationship has been observed among the temperature of the plasma, the mass of the gas in the plasma, and the difference in the carbon deposition rate at the upper and lower surfaces of the trench. In the case of plasma gases with a high molecular weight such as nitrogen and argon, an increase in the molecular weight of the gas correlates with an increase in the deposition rate of the bottom surface relative to the upper surface of the trench. This is thought to be caused by an increase in the rate at which deposition molecules (e.g., methane) are carried to the bottom surface of the trench by heavier carrier species. However, in the case of helium, another problem occurs in that the deposition rates of the carbon-containing protective layers observed at the upper and lower surfaces of the trench are not far apart but rather close to each other. Despite having a smaller atomic mass than nitrogen and argon, helium-containing plasmas produce a higher plasma temperature than nitrogen- or argon-containing plasmas. The increase in plasma temperature has a significant impact on the deposition rate of the carbon-containing layer at the upper surface of the trench compared to the bottom surface, thereby reducing the amount of deposition along the upper surface of the trench.

[0021]

[0028] Although not wishing to be bound by a particular theory, carbon films deposit preferentially or to a greater extent on cooler surfaces due to their higher adhesion coefficient. Helium plasmas generate hot electrons, increasing the plasma temperature and the temperature of the upper surface of the trench. As the temperature increases, the deposition rate of the carbon-containing layer at the upper surface of the trench decreases relative to the bottom surface. In the case of helium, the decrease in the deposition rate at the upper surface of the trench is so large that it exceeds the decrease in the deposition rate at the bottom surface due to the reduced transport rate of the carbon-containing deposition molecules. Therefore, a deposition plasma containing helium as the main carrier species forms a carbon-containing layer with a thickness of the upper and lower surfaces that is closer than that of a nitrogen-containing deposition plasma characterized by a low plasma temperature. On the other hand, in a deposition plasma containing argon as the main carrier species, a carbon-containing layer with a thickness of the upper and lower surfaces that is close to each other is formed, similar to the helium-containing deposition plasma. In such an argon-containing deposition plasma, the high deposition rate at the bottom surface due to the increased transport rate of the heavy argon species exceeds the favorable deposition conditions at the upper surface due to the low plasma temperature.

[0022]

[0029] Furthermore, it has been observed that a difference in the deposition rate of the carbon-containing layer between the top and bottom surfaces of the trench can occur over a range of substrate temperatures and trench widths. Thus, embodiments of the present technology can be used not only with substrates at temperatures above about 100 °C, but also with substrates at temperatures below about 100 °C. In addition, embodiments of the present technology can be used to deposit carbon-containing layers of different thicknesses on the top and bottom surfaces of trenches having widths of about 50 nm or less, as well as trenches having widths of about 100 nm or more. In a further embodiment, the as-deposited carbon-containing layer can be deposited on a substrate having trenches with a plurality of different widths, in which case the layer is thicker on the top surface than on the bottom surface of each trench.

[0023]

[0030] In the remaining disclosure, while specific deposition and etching processes that utilize the present technology are always identified, it will be readily understood that the present system and method are equally applicable to a variety of other processes and semiconductor structures that can be used in the described chambers. Accordingly, the present technology should not be considered limited to use only with the described systems, methods, and chambers. In this disclosure, before describing the system and method or steps of an exemplary process sequence according to some embodiments of the present technology, possible systems and chambers that can be used with the present technology are described. It should be understood that the present technology is not limited to the described equipment, and the processes described can be performed in any number of processing chambers and systems.

[0024]

[0031] FIG. 1 is a top plan view showing one embodiment of a processing system 10 of a deposition, etching, firing, and / or curing chamber according to an embodiment. The tool or processing system 10 shown in FIG. 1 can include a plurality of process chambers 24a-d, a transfer chamber 20, a service chamber 26, an integrated metrology chamber 28, and a pair of load lock chambers 16a-b. The process chambers can include any number of structures or components, as well as any number or combination of process chambers.

[0025]

[0032] To transport the substrate between chambers, the transfer chamber 20 may include a robotic transport mechanism 22. The transport mechanism 22 may have a pair of substrate transport blades 22a respectively attached to the distal ends of the extendable arms 22b. The blades 22a can be used to carry individual substrates in and out of the process chamber. In the process, one of the substrate transport blades such as the blade 22a of the transport mechanism 22 can take out the substrate W from one of the load lock chambers such as the chambers 16a - b, and carry the substrate W to the first processing stage as described later in the chambers 24a - d, for example, to the processing process. The chamber may be included to perform the individual or combined processes of the described technology. For example, one or more chambers can be configured to perform deposition or etching processes, and one or more other chambers can be configured to perform the described pre - treatment processes and / or one or more post - treatment processes. Any number of configurations capable of performing any number of additional manufacturing processes commonly performed in semiconductor processing are included in this technology.

[0026]

[0033] When the chamber is occupied, the robot can wait until the processing is completed, and then remove the processed substrate from the chamber with one blade 22a and insert a new substrate with the second blade. Once the substrate is processed, it can then be moved to the second processing stage. For each movement, the transport mechanism 22 generally can have one blade for carrying the substrate and one empty blade for performing substrate exchange. The transport mechanism 22 can wait in each chamber until the exchange can be completed.

[0027]

[0034] Once the processing is completed within the process chamber, the transport mechanism 22 can move the substrate W from the last process chamber and transport the substrate W to the cassette within the load lock chambers 16a - b. The substrate can be moved from the load lock chambers 16a - b into the factory interface 12. The factory interface 12 can generally operate to transfer substrates between the pod loaders 14a - d within the atmospheric pressure clean environment and the load lock chambers 16a - b. The clean environment of the factory interface 12 can generally be obtained through an air filtration process such as HEPA filtration, for example. The factory interface 12 may also include a substrate orienter / aligner that can be used to properly align the substrate before processing. At least one substrate robot, such as robots 18a - b, can be positioned within the factory interface 12 to transport substrates between various positions / places within the factory interface 12 and to other locations connected thereto. The robots 18a - b can be configured to move along a track system within the factory interface 12 from a first end to a second end of the factory interface 12.

[0028]

[0035] The processing system 10 may further include an integrated measurement chamber 28 for providing control signals, and this integrated measurement chamber can provide adaptive control for any of the processes being executed in the processing chamber. The integrated measurement chamber 28 may include any of various measurement devices for measuring various film properties such as thickness, roughness, composition, etc., and the measurement devices may further be capable of characterizing grating parameters such as critical dimensions, sidewall angles, and feature heights, etc. under vacuum in an automated manner.

[0029]

[0036] Each of the processing chambers 24a-d may be configured to perform one or more process steps in the manufacture of semiconductor structures, and any number of processing chambers and combinations of processing chambers may be used on the multi-chamber processing system 10. For example, any of the processing chambers may be configured to perform a number of substrate processing steps including any number of deposition processes such as periodic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, and other processes including etching, pre-cleaning, pre-treatment, post-treatment, annealing, plasma treatment, degassing, orientation, and other substrate processes. Some specific processes that may be performed in any of the chambers, or combinations of chambers, may include metal deposition, surface cleaning and pre-preparation, thermal annealing such as rapid thermal processing, and plasma treatment. As will be readily understood by those skilled in the art, any other process including any of the processes described below may equally be performed in a particular chamber incorporated in the multi-chamber processing system 10.

[0030]

[0037] Figure 2 is a schematic cross-sectional view showing an exemplary processing chamber 100 suitable for patterning a material layer disposed on a substrate 302 in the processing chamber 100. The exemplary processing chamber 100 is suitable for performing a patterning process, but aspects of the present technology can be implemented in any number of chambers, and it should be understood that the substrate support according to the present technology can be included in an etching chamber, a deposition chamber, a processing chamber, or any other processing chamber. The plasma processing chamber 100 can include a chamber body 105 that defines a chamber region 101 in which a substrate can be processed. The chamber body 105 can have a sidewall 112 and a bottom 118 coupled to ground 126. The sidewall 112 can have a liner 115 to protect the sidewall 112 and extend the time between maintenance cycles of the plasma processing chamber 100. The dimensions of the chamber body 105 and related components of the plasma processing chamber 100 are not limited and can generally be proportionally larger than the size of the substrate 302 processed therein. Examples of substrate sizes include, among others, 200 mm in diameter, 250 mm in diameter, 300 mm in diameter, 450 mm in diameter, etc., and the same applies to display substrates, solar cell substrates, etc.

[0031]

[0038] The chamber body 105 can support a chamber lid assembly 110 and surround the chamber region 101. The chamber body 105 can be made of aluminum or other suitable materials. A substrate access port 113 can be formed through the sidewall 112 of the chamber body 105 to facilitate the transfer of the substrate 302 into and out of the plasma processing chamber 100. As described above, the access port 113 can be coupled to a transfer chamber and / or other chambers of the substrate processing system. A pumping port 145 can be formed through the sidewall 112 of the chamber body 105 and connected to the chamber region 101. A pumping device can be connected to the chamber region 101 through the pumping port 145 to evacuate and control the pressure in the processing region. The pumping device can include one or more pumps and throttle valves.

[0032]

[0039] To supply process gas into the chamber region 101, the gas panel 160 may be connected to the chamber body 105 by the gas line 167. The gas panel 160 may include one or more process gas sources 161, 162, 163, 164, and may further include an inert gas, a non-reactive gas, and a reactive gas so as to be used in any number of processes. Examples of process gases that may be provided by the gas panel 160 include methane, sulfur hexafluoride, silicon chloride, carbon tetrafluoride, hydrogen bromide, hydrocarbon-containing gas, argon gas, chlorine, nitrogen, helium, or hydrocarbon-containing gas containing oxygen gas, as well as any number of additional materials, but are not limited thereto. Further, the process gas includes, among any number of additional precursors, nitrogen, chlorine, fluorine, oxygen, and BCl 3 、C 2 F 4 、C 4 F 8 、C 4 F 6 、CHF 3 、CH 2 F 2 、CH 3 F、NF 3 、NH 3 、CO 2 、SO 2 、CO、N 2 、NO 2 、N 2 O、and hydrogen-containing gases such as H 2 etc. may be included.

[0033]

[0040] Valve 166 can control the flow of process gas from the supply sources 161, 162, 163, 164 of the gas panel 160 and can be managed by the controller 165. The gas flow supplied from the gas panel 160 to the chamber body 105 can include a combination of gases from one or more supply sources. The lid assembly 110 can include the nozzle 114. The nozzle 114 can be one or more ports for introducing process gas from the supply sources 161, 162, 164, 163 of the gas panel 160 into the chamber region 101. After the process gas is introduced into the plasma processing chamber 100, a voltage can be applied to the gas to form a plasma. An antenna 148, such as one or more inductor coils, can be provided adjacent to the plasma processing chamber 100. The antenna power supply 142 can supply power to the antenna 148 through the matching circuit 141 to inductively couple energy, such as RF energy, to the process gas to maintain the plasma formed from the process gas in the chamber region 101 of the plasma processing chamber 100. Instead of or in addition to the antenna power supply 142, a process electrode below and / or above the substrate 302 can be used to capacitively couple RF power to the process gas to maintain the plasma in the chamber region 101. The operation of the power supply 142 can be controlled by a controller, such as the controller 165, which also controls the operation of other components of the plasma processing chamber 100.

[0034]

[0041] During processing, a substrate support pedestal 135 for supporting a substrate 302 can be disposed in the chamber region 101. The substrate support pedestal 135 can include an electrostatic chuck 122 for holding the substrate 302 during processing. The electrostatic chuck ("ESC") 122 can hold the substrate 302 to the substrate support pedestal 135 using electrostatic attraction. The ESC 122 can be powered by an RF power supply 125 integrated with a matching circuit 124. The ESC 122 can include an electrode 121 embedded within a dielectric. The electrode 121 is connected to the RF power supply 125 and can provide a bias that attracts plasma ions formed by the process gas in the chamber region 101 to the ESC 122 and the substrate 302 seated on the pedestal. The RF power supply 125 repeats on and off or supplies pulses during processing of the substrate 302. The ESC 122 can have an isolator 128 to extend the maintenance cycle life of the ESC 122 by preventing plasma from being attracted to the sidewalls of the ESC 122. Further, the substrate support pedestal 135 can have a cathode liner 136 to protect the sidewalls of the substrate support pedestal 135 from the plasma gas and extend the maintenance interval of the plasma processing chamber 100.

[0035]

[0042] The electrode 121 can be connected to a power supply 150. The power supply 150 can supply a chucking voltage of from about 200 volts to about 2000 volts to the electrode 121. The power supply 150 can also include a system controller for controlling the operation of the electrode 121 by sending a direct current for chucking and de-chucking the substrate 302 to the electrode 121. The ESC 122 can include a heater disposed within the pedestal and connected to a power supply for heating the substrate, and the cooling base 129 supporting the ESC 122 can include conduits for circulating a heat transfer fluid for maintaining the temperature of the ESC 122 and the substrate 302 disposed thereon. The ESC 122 can be configured to operate within a temperature range required by the heat balance of the device fabricated on the substrate 302. For example, the ESC 122 can be configured to maintain the substrate 302 at a temperature from about -150 °C or less to about 500 °C or more, depending on the process being performed.

[0036]

[0043] The cooling base 129 can be provided to assist in controlling the temperature of the substrate 302. To mitigate process drift and time, the temperature of the substrate 302 can be maintained substantially constant by the cooling base 129 while the substrate 302 is within the cleaning chamber. In some embodiments, the temperature of the substrate 302 can be maintained at a temperature from about -150 °C to about 500 °C throughout a subsequent cleaning process, although any temperature can be used. A covering 130 can be disposed on the ESC 122 and along the periphery of the substrate support pedestal 135. The covering 130 can be configured to confine an etching gas to a desired portion of the exposed upper surface of the substrate 302 while shielding the upper surface of the substrate support pedestal 135 from the plasma environment inside the plasma processing chamber 100. The lift pins can be selectively translated through the substrate support pedestal 135 to lift the substrate 302 above the substrate support pedestal 135, facilitating access to the substrate 302 by a transfer robot or other suitable transfer mechanism as described above.

[0037]

[0044] The controller 165 can be used to control the process sequence, regulate the gas flow from the gas panel 160 into the plasma processing chamber 100, and control other process parameters. A software routine, when executed by a CPU, can transform the CPU into a special-purpose computer, such as a controller, that can control the plasma processing chamber 100 such that the process is executed in accordance with the present disclosure. The software routine can also be stored and / or executed by a second controller that may be associated with the plasma processing chamber 100.

[0038]

[0045] Chamber 100, and other embodiments of the processing chamber and system can be used to fabricate semiconductor structures according to embodiments of the present technology. FIG. 3 is a diagram showing exemplary steps in a method 300 for fabricating a semiconductor structure according to some embodiments of the present technology. Method 300 can be executed in one or more processing chambers such as, for example, chamber 100. Method 300 may or may not include one or more steps prior to the start of the method, including front-end processing, deposition, etching, polishing, cleaning, or any other steps that can be performed prior to the steps described. For example, steps for forming a semiconductor structure including one or more trenches having top and bottom surfaces and sidewall surfaces can be performed prior to the start of method 300. The method may or may not be particularly related to some embodiments of the methods according to the present technology and may include a number of optional steps.

[0039]

[0046] FIG. 3 is a diagram showing exemplary steps in a method 300 for etching openings in the bottom surfaces of trenches in a semiconductor structure while protecting the top surfaces of the trenches according to embodiments of the present technology. Method 300 describes steps for forming embodiments of semiconductor devices 400, 500, and 600 shown in simplified schematic form in FIGS. 4, 5, and 6A-6C, and the illustrations thereof will be described in conjunction with the steps of method 300. These semiconductor devices 400, 500, and 600 can include semiconductor logic devices such as CPUs and GPUs, memory devices such as DRAMs, and display devices such as LEDs, among other types of semiconductor devices. FIGS. 4, 5, 6A-6C show only partial schematic views with limited details, and it should be understood that in some embodiments, the substrate can include any number of semiconductor sections having an aspect as illustrated in the figures, as well as alternative structural aspects that can still benefit from any aspect of the present technology.

[0040]

[0047] Method 300 includes supplying a substrate in step 305. In an embodiment, the substrate can include a wafer made of silicon, silicon oxide, germanium, gallium arsenide, or aluminum nitride, among other substrate materials. In a further embodiment, the substrate can include a semiconductor device structure such as structure 405 formed on substrate 402, structure 505 formed on substrate 502, and structure 605 formed on substrate 602, as shown in FIGS. 4, 5, and 6A - 6C, respectively. In the embodiment shown in FIG. 4, each structure 405 can include a base structure 407 and one or more layers 409 positioned on the base structure. In a further embodiment, one or more layers 409 can extend up to the sidewalls of the base structure 407 and across the entire bottom surface of the trench between adjacent base structures. In another further embodiment, each of the one or more layers 409 can include a liner layer or a spacer layer, among other types of layers. In the embodiment shown in FIG. 5, each structure 505 can include a base structure 507 and one or more layers 509 positioned on the base structure. In a further embodiment, one or more layers 509 can extend up to the sidewalls of the base structure 507 and across the entire bottom surface of the trench between adjacent base structures. In another further embodiment, each of the one or more layers 509 can include a liner layer or a spacer layer, among other types of layers. In the embodiments shown in FIGS. 6A - 6C, each structure 605 can include a base structure 607 and one or more layers 609 positioned on the base structure. In a further embodiment, one or more layers 609 can extend up to the sidewalls of the base structure 607 and across the entire bottom surface of the trench between adjacent base structures. In another further embodiment, each of the one or more layers 609 can include a liner layer or a spacer layer, among other types of layers.

[0041]

[0048] In an embodiment, the base structures 407, 507, and 607 may include at least one of a semiconductor material or a dielectric material. In an embodiment, the semiconductor material may include silicon, silicon carbide, germanium, gallium arsenide, gallium nitride, gallium phosphide, and cadmium sulfide among other semiconductor materials. In a further embodiment, the dielectric material may include silicon oxide, silicon carbonate, silicon nitride, silicon oxynitride, titanium dioxide, aluminum oxide, and zinc oxide among other dielectric materials. In yet another embodiment, the one or more layers 409, 509, and 609 may include one or more semiconductor materials or dielectric materials.

[0042]

[0049] In an embodiment, the structures 405 and 605 include one or more trenches 410 and 610 that include top surfaces 412 and 612 and bottom surfaces 414 and 614. The trenches 410 and 610 may be characterized by an aspect ratio comparing the height of the trench to the bottom width of the trench. In a further embodiment, the trenches 410 and 610 may have an aspect ratio of about 2:1 or greater, about 2.5:1 or greater, about 3:1 or greater, about 3.5:1 or greater, about 4:1 or greater, about 4.5:1 or greater, about 5:1 or greater, about 5.5:1 or greater, about 6:1 or greater, about 6.5:1 or greater, about 7:1 or greater, about 7.5:1 or greater, about 8:1 or greater, about 8.5:1 or greater, about 9:1 or greater, about 9.5:1 or greater, about 10:1 or greater, or more. In another further embodiment, the trench bottom width may be about 50 nm or less, about 45 nm or less, about 40 nm or less, about 35 nm or less, about 30 nm or less, about 25 nm or less, about 20 nm or less, about 15 nm or less, about 10 nm or less, or less.

[0043]

[0050] In a further embodiment, the structure 505 may also include one or more trenches 510 having a top surface 512 and a bottom surface 514. In contrast to the trenches 410 and 610 of the structures 405 and 605, the trenches 510 may be characterized by a lower aspect ratio and a wider trench bottom. In an embodiment, the trenches 510 may be characterized by an aspect ratio of about 1:1 or less, about 1:2 or less, about 1:5 or less, about 1:10 or less, about 1:20 or less, about 1:50 or less, about 1:80 or less, about 1:100 or less, or less. In a further embodiment, the trenches 510 may have a trench bottom width of about 100 nm or more, about 110 nm or more, about 120 nm or more, about 130 nm or more, about 140 nm or more, about 150 nm or more, about 160 nm or more, about 170 nm or more, about 180 nm or more, about 190 nm or more, about 200 nm or more, or more.

[0044]

[0051] In a further embodiment, semiconductor device structures such as the structures 405, 505, and 605 can be combined on the same substrate. In these embodiments, a first portion of the semiconductor device structure may have spatial characteristics similar to those of the structures 405 and 605, while a second portion of the device structure may have spatial characteristics similar to those of the structure 505. In a further embodiment, the first and second portions of the device structure may be disposed in separate regions on the substrate, while in a further embodiment, the first and second portions of the device structure may be intermingled across a portion or the entire substrate.

[0045]

[0052] Method 300 may also include heating the provided substrates, such as substrates 402, 502, and 602, in the reaction chamber in optional step 310. In embodiments where the substrate is heated, the heating can be performed from below the substrate. In further embodiments, the heating of the substrate can be performed by one or more heating elements of an electrostatic chuck (ESC) that contacts the substrate. In another further embodiment, the substrate can be heated such that the bottom surface of the trench is characterized by a temperature of about 50 °C or more, about 60 °C or more, about 70 °C or more, about 80 °C or more, about 90 °C or more, about 100 °C or more, about 110 °C or more, about 120 °C or more, about 130 °C or more, about 140 °C or more, about 150 °C or more, or more. As described above, embodiments of the present technology can cause a higher deposition rate on the upper surface of the trench than on the bottom surface over a wide range of ESC and substrate temperatures.

[0046]

[0053] Method 300 may further include flowing a deposition gas into the reaction chamber in step 315. In embodiments, the deposition gas may include a carbon-containing gas. In further embodiments, the carbon-containing gas may include a carbon-hydrogen-containing gas such as methane. In another further embodiment, the deposition gas may also include one or more additional compounds having a molecular weight that balances the mass transport effect and the electron temperature effect that enhance the selectivity to deposit a carbon-containing layer thicker than the bottom surface on the upper surface of the trench. Embodiments of the deposition gas may include one or more additional gases having an atomic mass or molecular mass of about 30 g / mol or less. In further embodiments, the additional gas may have an atomic mass or molecular mass of about 5 g / mol or more. In another further embodiment, the additional gas may include a nitrogen-containing gas. In another further embodiment, the nitrogen-containing gas may be molecular nitrogen (N 2 )).

[0047]

[0054] In an embodiment, the deposition gas may include a carbon-containing gas and an additional gas (e.g., a carrier gas). In a further embodiment, the carbon-containing gas may be supplied to the plasma excitation region of the substrate-containing reaction chamber at a flow rate of about 50 standard cubic centimeters per minute (sccm) or less, about 40 sccm or less, about 30 sccm or less, about 20 sccm or less, about 10 sccm or less, or less. In a further embodiment, the additional gas may be supplied to the plasma excitation region of the substrate-containing reaction chamber at a flow rate of about 200 sccm or more, about 250 sccm or more, about 300 sccm or more, about 350 sccm or more, about 400 sccm or more, about 450 sccm or more, about 500 sccm or more, or more. In a further embodiment, the deposition gas may be characterized by a flow rate ratio of the carbon-containing gas to one or more additional gases of about 1:5 or less, about 1:10 or less, about 1:15 or less, about 1:20 or less, or less.

[0048]

[0055] In a further embodiment, the additional gas has an atomic mass or molecular mass that is not so large as to increase the transport rate of the carbon-containing gas to the bottom of the trench. Compounds having a molecular mass of approximately that of diatomic nitrogen (N 2 ) or less have been found to have a significantly lower transport rate of the carbon-containing compound in the deposition gas than heavier compounds. In an embodiment, the deposition gas may not include these heavier compounds such as argon, which is commonly used as a carrier gas in the deposition of carbon-containing layers and may increase deposition along the base of the trench by increasing supply through the trench. Also, compounds significantly lighter than the molecular mass of diatomic nitrogen (N 2 ) have been found to be able to substantially increase the electron temperature of the deposition plasma formed from the deposition gas and may increase the surface temperature of the substrate. In an embodiment, the deposition gas may not include these light compounds such as helium and / or hydrogen molecules (H 2 ), which are commonly used as carrier gases and reactive gases in the deposition of carbon-containing layers.

[0049]

[0056] Method 300 further includes generating a deposition plasma from a deposition gas in step 320. In an embodiment, the deposition plasma can be generated by supplying power from an RF power source to the deposition gas. In a further embodiment, the RF power source can be a capacitively coupled plasma power source or an inductively coupled plasma power source. In a further embodiment, the RF power source can supply RF power characterized by a power of about 500 watts or less, about 450 watts or less, about 400 watts or less, about 350 watts or less, about 300 watts or less, about 250 watts or less, about 200 watts or less, or less to the deposition gas and the deposition plasma. In yet another embodiment, during the generation of the deposition plasma, the reaction chamber can be characterized by a deposition plasma pressure of about 10 mTorr or less, about 9 mTorr or less, about 8 mTorr or less, about 7 mTorr or less, about 6 mTorr or less, about 5 mTorr or less, about 4 mTorr or less, about 3 mTorr or less, about 2 mTorr or less, about 1 mTorr or less, or less.

[0050]

[0057] The power supplied to generate the deposition plasma and the plasma deposition temperature can affect the plasma temperature (i.e., the electron temperature). As described above, it has been found that the electron temperature of the deposition plasma affects the selectivity of the deposition rate of the carbon-containing layer between the top and bottom surfaces of the trench of the semiconductor device structure. In an embodiment, the electron temperature of the deposition plasma can be characterized as about 5 eV or less, about 4.5 eV or less, about 4 eV or less, about 3.5 eV or less, about 3 eV or less, about 2.5 eV or less, about 2 eV or less, about 1.5 eV or less, about 1 eV or less, or less. By generating a low-temperature plasma in combination with the temperature rise at the bottom of the trench due to the bottom-up heating as described above, the present technology can create a temperature difference between the top and bottom surfaces of the trench due to the heat transport effect described below. Accordingly, in some embodiments of the present technology, during deposition, the temperature of the top surface of the trench may be about 1 °C or more lower than the bottom temperature of the trench, about 2 °C or more lower than the bottom temperature of the trench, about 3 °C or more lower than the bottom temperature of the trench, about 4 °C or more lower than the bottom temperature of the trench, about 5 °C or more lower than the bottom temperature of the trench, about 6 °C or more lower than the bottom temperature of the trench, about 7 °C or more lower than the bottom temperature of the trench, or more lower than that. Thereby, since the adhesion of the carbon material due to the low temperature increases, the deposition at the upper part of the trench may further increase.

[0051]

[0058] Method 300 further includes depositing a protective layer from the deposition plasma in step 325. In an embodiment of the present technology, this protective layer may be carbon-containing layers 450, 550, and 650 selectively deposited on substrates 402, 502, and 602, respectively. In a further embodiment, the selective deposition deposits a carbon-containing layer thicker than the bottom surface of the trench of the substrate on the top surface of the trench. In another further embodiment, the as-deposited carbon-containing layer can be characterized by a ratio of top surface thickness to bottom surface thickness of about 3:1 or more, about 3.25:1 or more, about 3.5:1 or more, about 3.75:1 or more, about 4:1 or more, about 4.25:1 or more, about 4.5:1 or more, about 4.75:1 or more, about 5:1 or more, or more.

[0052]

[0059] In an embodiment, the as-deposited carbon-containing layer may have a top surface thickness of about 5 nm or more, about 6 nm or more, about 7 nm or more, about 8 nm or more, about 9 nm or more, about 10 nm or more, or more. In another further embodiment, the as-deposited carbon-containing layer may have a bottom surface thickness of about 2 nm or less, about 1.9 nm or less, about 1.8 nm or less, about 1.7 nm or less, about 1.6 nm or less, about 1.5 nm or less, about 1.4 nm or less, about 1.3 nm or less, about 1.2 nm or less, about 1.1 nm or less, about 1 nm or less, or less. In an embodiment, the as-deposited carbon layer may also be formed on the sidewalls of the trench. In a further embodiment, the as-deposited carbon layer may have a sidewall thickness thinner than the top surface thickness. In another further embodiment, the as-deposited carbon layer may have a sidewall thickness the same as or thicker than the bottom surface thickness. In a further embodiment, the carbon-containing layer can be deposited in about 60 seconds or less, about 50 seconds or less, about 40 seconds or less, about 30 seconds or less, about 20 seconds or less, about 10 seconds or less, about 5 seconds or less, or less.

[0053]

[0060] In a further embodiment, the difference in the deposition rate of the carbon-containing layer between the top surface and the bottom surface of the trench may vary depending on the aspect ratio of each trench. Trenches having a higher aspect ratio may have a significant difference in the deposition rate of the carbon-containing layer under the same deposition conditions compared to trenches having a lower aspect ratio. This may be due, at least in part, to the difference in thermal conductivity between trenches with a narrow bottom width and those with a wide bottom width. Trenches with a narrow bottom width may have a lower thermal conductivity of the bottom surface material because the mean free path of phonon conduction in the material is short. In contrast, trenches with a wide bottom width may have a higher thermal conductivity of the bottom surface material because the mean free path of phonon conduction in the material is long. In an embodiment, as the bottom of the trench is wider, the thermal conductivity of the bottom surface material becomes higher, resulting in a higher bottom surface temperature and a possible decrease in the deposition rate of the carbon-containing layer on the bottom surface compared to the top surface of the trench. In an embodiment, narrower trenches having an aspect ratio of about 2:1 or more may have a higher top surface to bottom surface thickness ratio than wider trenches having an aspect ratio of about 1:1 or less. In a further embodiment, the difference in the thickness ratio between the narrower trench and the wider trench may be about 1% or more, about 2.5% or more, about 5% or more, about 7.5% or more, about 10% or more, about 15% or more, about 20% or more, about 25% or more, about 30% or more, about 40% or more, about 50% or more, or more. As described above, embodiments of the present technology can cause a higher deposition rate on the top surface of the trench than on the bottom surface over a wide range of trench widths.

[0054]

[0061] In a further embodiment, the carbon-containing layer may include solid carbon. In another further embodiment, the solid carbon may include a carbon polymer. In another further embodiment, the carbon-containing layer may each be silicon, oxygen, and carbon in an amount of about 5 wt% or less, about 4 wt% or less, about 3 wt% or less, about 2 wt% or less, about 1 wt% or less, about 0.5 wt% or less, about 0.1 wt% or less, or less.

[0055]

[0062] In an embodiment, a substrate including a carbon-containing layer of the present invention formed with different top and bottom thicknesses on a trench of the substrate can be used in various processes for forming an opening at the bottom of the trench. In a further embodiment, these processes can include, among other processes, high aspect ratio deposition, via formation, and electrical contact formation.

[0056]

[0063] In the embodiment described by method 300, the method includes, in step 330, etching an opening at the bottom of a trench of a semiconductor device structure. In an embodiment, the opening can be etched by a dry etching process such as reactive ion etching (RIE). In a further embodiment, etching step 330 can be performed in the same reaction chamber without breaking vacuum by exhausting a carbon-containing deposition gas and supplying an etching gas to the chamber. In another further embodiment, an etching plasma can be formed from the etching gas, and an ionized etchant can be anisotropically accelerated toward the substrate by applying a bias voltage between the etching plasma and the substrate. In an embodiment, the etching gas is CF 3 fluorine-containing gas such as H, and nitrogen (N 2) may include a carrier gas such as. In a further embodiment, the reaction chamber may be characterized by a pressure of about 1 mTorr or more, about 2 mTorr or more, about 3 mTorr or more, about 4 mTorr or more, about 5 mTorr or more, or more during the etching process. In a further embodiment, the etching plasma may be formed by supplying power from a plasma power source such as an RF power source to the etching gas. In an embodiment, the supplied power may be characterized as about 300 W or more, about 400 W or more, about 500 W or more, about 600 W or more, about 700 W or more, about 800 W or more, or more. In a further embodiment, the bias voltage between the etching plasma and the substrate may be characterized as about 150 VDC or more, about 160 VDC or more, about 170 VDC or more, about 180 VDC or more, about 190 VDC or more, about 200 VDC or more, or more. In another further embodiment, the bias power may be characterized as about 50 W or more, about 60 W or more, about 70 W or more, about 80 W or more, about 90 W or more, about 100 W or more, or more.

[0057]

[0064] In an embodiment, the ionized etchant may collide with and react with the carbon-containing layers on both the top and bottom surfaces of the trench. In a further embodiment, the ionized etchant removes a portion of the carbon-containing layer on the bottom surface of the trench to form a part of the opening on the bottom surface. In another further embodiment, the ionized etchant also reduces the thickness of the portion of the carbon-containing layer formed on the top surface of the trench, but does not break through to the top layer. In another further embodiment, the ionized etchant also reduces the thickness of the upper portion of the carbon-containing layer to about 90% or less, about 80% or less, about 70% or less, about 60% or less, about 50% or less, about 40% or less, or less.

[0058]

[0065] Method 300 may include forming a conductive contact in the etched opening in optional step 335. In embodiments, a conductive contact, such as a low-resistance ohmic contact, may be formed by depositing a conductive material in the etched opening. In further embodiments, the deposition technique may include sputtering, physical vapor deposition, and chemical vapor deposition, among other deposition techniques. In another further embodiment, the conductive material may be one or more metals such as aluminum, silicon, tungsten, copper, and titanium, among other metals.

[0059]

[0066] Method 300 may optionally include removing a protective layer in step 340. In embodiments, this may include removing a carbon-containing layer 650 from structure 605, as indicated by the absence of the carbon-containing layer 650 in FIG. 6C. In further embodiments, the protective layer is a carbon-containing layer that may be removed by exposing the layer to an oxidizing gas or plasma that reacts with carbon to form gaseous carbon monoxide and / or carbon dioxide that is exhausted from the reaction chamber. In further embodiments, the carbon layer may be removed by an oxygen plasma or a plasma formed from nitrogen (N 2 ) gas and hydrogen (H 2 ) gas. In another further embodiment, the carbon layer can be removed in the same reaction chamber used for the deposition and etching steps, or the carbon layer can be removed in a separate chamber configured to remove a carbon polymer layer.

[0060]

[0067] Embodiments of the present technology, such as method 300, include steps for fabricating a semiconductor device structure with reduced damage to the upper region of the device structure caused by the etching process. These steps include selectively depositing a protective layer, such as a carbon-containing layer, over the trenches of the device structure. This selective deposition forms a thick layer of the protective layer on the upper surface of the trenches compared to the bottom surface where the openings for the contacts can be etched. Thus, embodiments of the present technology provide a manufacturing method that reduces damage to the semiconductor device structure as the size of the device structure shrinks and the density of the structures on the semiconductor substrate increases.

[0061]

[0068] In the previous descriptions, for the purpose of explanation, numerous details have been set forth to enable an understanding of various embodiments of the present technology. However, it will be apparent to those skilled in the art that some of these details may be omitted or additional details added to implement a particular embodiment.

[0062]

[0069] Although several embodiments have been disclosed, it will be recognized by those skilled in the art that various modifications, alternative structures, and equivalents can be used without departing from the gist of the embodiments. Further, to avoid unnecessarily obscuring the present technology, some well-known processes and elements have not been described. Therefore, the above descriptions should not be construed as limiting the scope of the present technology.

[0063]

[0070] It should be understood that when a range of values is provided, unless the context clearly dictates otherwise, each intervening value, to the minimum part of the unit of the lower limit, between the upper and lower limits of that range is also specifically disclosed. Any narrower range between any of the recited values or the unrecited intervening values of the recited range and any other recited value or intervening value of that recited range is also included. The upper and lower limits of these smaller ranges may independently be included in or excluded from the range, and each range that includes one or both of the limiting values, or neither of the limiting values, of the smaller range is also included within the present technology, in accordance with any specifically excluded limiting value in the recited range. When one or both of the limiting values of the recited range are included, ranges excluding one or both of those included limiting values are also included.

[0064]

[0071] As used in this specification and the appended claims, the singular forms "a", "an", and "the" include plural references unless the context clearly dictates otherwise. Thus, for example, reference to "a layer" includes a plurality of such layers, and reference to "the protrusion" includes reference to one or more protrusions known to those skilled in the art and their equivalents, etc.

[0065]

[0072] Also, as used in this specification and the following claims, the terms "comprise," "comprising," "contain," "containing," "include," and "including" specify the presence of the stated feature, integer, component, or step, but do not preclude the presence or addition of one or more other features, integers, components, steps, acts, or groups.

Claims

1. 1. A semiconductor processing method comprising: providing a substrate to a reaction chamber, the substrate including a substrate trench having a top surface and a bottom surface; flowing a deposition gas into a plasma excitation region of the reaction chamber, the deposition gas including a carbon-containing gas and a nitrogen-containing gas; generating a deposition plasma from the deposition gas, the deposition plasma having an electron temperature of about 4 eV or less; depositing a carbon-containing layer on top and bottom surfaces of the substrate trench, the as-deposited carbon-containing layer having a top-to-bottom thickness ratio of about 3:1 or greater; The method includes:

2. The semiconductor processing method of claim 1 , wherein said deposition gas is free of argon and helium.

3. 10. The semiconductor processing method of claim 1, further comprising heating the substrate to a temperature of about 100[deg.] C. or greater prior to depositing the carbon-containing layer.

4. 10. The semiconductor processing method of claim 1, further comprising etching through at least a portion of said carbon-containing layer on a bottom surface of said substrate trench, said carbon-containing layer still covering a top surface of said substrate trench.

5. 5. The semiconductor processing method of claim 4, further comprising removing the carbon-containing layer from the substrate after etching at least a portion of the carbon-containing layer on a bottom surface of the substrate trench.

6. 2. The semiconductor processing method of claim 1, wherein said carbon containing gas comprises methane and said nitrogen containing gas comprises molecular nitrogen.

7. 2. The semiconductor processing method of claim 1, wherein said deposition plasma is generated by supplying RF power to said deposition gas, said RF power being characterized by a power of about 300 Watts or less.

8. 10. The semiconductor processing method of claim 1, wherein the deposition plasma is characterized by a pressure of about 10 mTorr or less.

9. 1. A semiconductor processing method comprising: providing a substrate to a reaction chamber, the substrate comprising a first substrate trench having a first aspect ratio of about 2:1 or greater and a second substrate trench having a second aspect ratio of about 1:2 or less, the first substrate trench and the second substrate trench each having a top surface and a bottom surface; heating the substrate to a temperature of about 100° C. or greater; flowing a deposition gas into a plasma excitation region of the reaction chamber, the deposition gas comprising a carbon-containing gas and a nitrogen-containing gas; generating a deposition plasma from the deposition gas, the deposition plasma being characterized by an electron temperature of about 4 eV or less; depositing a carbon-containing layer on the heated substrate, the as-deposited carbon-containing layer having a top-to-bottom thickness ratio of about 3:1 or greater in both the first substrate trench and the second substrate trench; The method includes:

10. etching through at least a portion of the carbon-containing layer at a bottom surface of a first substrate trench and a second substrate trench, the carbon-containing layer still covering a top surface of the first substrate trench and the second substrate trench; removing the carbon-containing layer from the substrate after etching at least a portion of the carbon-containing layer on a bottom surface of the first substrate trench and the second substrate trench; The semiconductor processing method of claim 9 further comprising:

11. 10. The semiconductor processing method of claim 9, wherein the first substrate trench is characterized by a first bottom width of about 50 nm or less, and the second substrate trench is characterized by a second bottom width of about 100 nm or more.

12. 10. The semiconductor processing method of claim 9, wherein the carbon-containing layer is characterized by a top thickness of about 5 nm or more and a bottom thickness of about 1.6 nm or less.

13. The semiconductor processing method of claim 9 , wherein the carbon-containing layer comprises solid carbon.

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