Non-volatile memory

Abstract

The present invention comprises: first and second transistors of which the gates are connected in common; a resistor having a first end and a second end, the first end being connected to a source of the first transistor; a lead voltage supply circuit configured so as to supply a lead voltage for turning on either the first or the second transistor between the gate of the first transistor and the second end of the resistor and between the gate and source of the second transistor; and a signal output circuit configured so as to output a signal associated with a first value or a second value on the basis of drain currents of the first and second transistors during a lead operation in which the lead voltage is supplied by the voltage supply circuit.

Description

Technical Field

[0001] The present disclosure relates to non-volatile memories.

Background Art

[0002] There is a non-volatile memory that utilizes hot carrier injection into a transistor. This type of non-volatile memory includes first and second transistors (corresponding to m1 and m2 in FIG. 22) whose characteristics are aligned in an initial state as memory elements, and hot carriers are injected only into one of the transistors to deteriorate the characteristics. In a subsequent read operation, based on the magnitude relationship of the drain currents when a common gate voltage is supplied to the first and second transistors, it is determined whether "0" data or "1" data is stored. For example, a state where the drain current of the first transistor is smaller (a state where the first transistor is deteriorated) corresponds to a state where "0" data is stored, and a state where the drain current of the second transistor is smaller (a state where the second transistor is deteriorated) corresponds to a state where "1" data is stored.

[0003] However, in the above non-volatile memory, the stored data in the initial state is indeterminate. There has also been proposed a non-volatile memory configured such that in the initial state, more drain current flows through one of the first and second transistors so that the stored data in the initial state does not become indeterminate.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In many cases, it is required to reduce the size of memory elements (first and second transistors) in order to reduce the size of the entire circuit. As the size of the memory elements becomes smaller, the characteristic mismatch between the memory elements becomes larger. The characteristics of a plurality of transistors formed aiming to align the characteristics may actually deviate significantly, and this deviation corresponds to the mismatch. Such a mismatch causes inconveniences such as inhibiting the storage and reading of correct data (this will be described in detail later). The development of a non-volatile memory that is less affected by mismatch is expected.

[0006] An object of the present disclosure is to provide a non-volatile memory that is less affected by mismatch.

Means for Solving the Problem

[0007] The non-volatile memory according to the present disclosure includes a first transistor, a second transistor having a gate commonly connected to the gate of the first transistor, a resistor having a first end and a second end, and the first end being connected to the source of the first transistor, and a lead voltage supply circuit configured to supply a lead voltage for turning on at least one of the first and second transistors between the gate of the first transistor and the second end of the resistor and between the gate and the source of the second transistor, and a signal output circuit configured to output a signal associated with a first value or a signal associated with a second value based on the drain current of each of the first and second transistors in a read operation in which the lead voltage is supplied by the lead voltage supply circuit.

[0008] Other non-volatile memories according to the present disclosure include a first transistor, a second transistor having a gate commonly connected to the gate of the first transistor, a resistor having a first end and a second end, with the first end connected to the source of the first transistor, a lead voltage supply circuit configured to supply a lead voltage for turning on at least one of the first and second transistors, and a signal output circuit configured to output a signal associated with a first value or a signal associated with a second value based on the drain current of each of the first and second transistors in a lead operation in which the lead voltage is supplied by the lead voltage supply circuit.

Advantages of the Invention

[0009] According to the present disclosure, it is possible to provide a non-volatile memory that is less affected by mismatches.

Brief Description of the Drawings

[0010]

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Mode for Carrying Out the Invention

[0011] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are denoted by the same reference numerals, and redundant descriptions regarding the same parts are omitted in principle. In the present specification, for the sake of simplicity of description, the name of information, signal, physical quantity, element, or part corresponding to a symbol or reference numeral may be omitted or abbreviated by writing the symbol or reference numeral referring to the information, signal, physical quantity, element, or part. For example, the read voltage supply circuit referred to by "20" described later (see FIG. 4) may be denoted as the read voltage supply circuit 20, or may be abbreviated as circuit 20, but they all refer to the same thing.

[0012] First, some terms used in the description of the embodiments of the present disclosure will be explained. "Ground" refers to a reference conductive part having a reference potential of 0 V (zero volts) or the 0 V potential itself. The reference conductive part is formed of a conductor such as metal. The 0 V potential may also be referred to as the ground potential. In the embodiments of the present disclosure, a voltage shown without particularly setting a reference represents a potential seen from the ground. "Level" refers to the level of a potential. For any signal or voltage of interest, the high level has a higher potential than the low level. For any signal or voltage of interest, that the signal or voltage is at the high level means that the level of the signal or voltage is at the high level, and that the signal or voltage is at the low level means that the level of the signal or voltage is at the low level. The level of a signal may be expressed as a signal level, and the level of a voltage may be expressed as a voltage level.

[0013] For any transistor configured as a FET (field effect transistor) including a MOSFET, the on state refers to a state in which the drain and source of the transistor are conducting, and the off state refers to a state in which the drain and source of the transistor are non-conducting (blocked state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-mode MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor".

[0014] The electrical characteristics of a MOSFET include the gate threshold voltage. For any transistor that is an N-channel and enhancement-mode MOSFET, when the gate potential of the transistor is higher than the source potential of the transistor, and the magnitude of the gate-source voltage (gate potential as seen from the source potential) of the transistor is equal to or higher than the gate threshold voltage of the transistor, the transistor is in the on state; otherwise, the transistor is in the off state. For any transistor that is a P-channel and enhancement-mode MOSFET, when the gate potential of the transistor is lower than the source potential of the transistor, and the magnitude of the gate-source voltage (gate potential as seen from the source potential) of the transistor is equal to or higher than the gate threshold voltage of the transistor, the transistor is in the on state; otherwise, the transistor is in the off state.

[0015] Any switch can be composed of one or more FETs (field effect transistors). When a certain switch is in the on state, conduction occurs between both ends of the switch; when a certain switch is in the off state, non-conduction occurs between both ends of the switch. Hereinafter, for any transistor or switch, the on state and the off state may also be simply expressed as on and off.

[0016] For any signal having a high-level or low-level signal level, the period during which the level of the signal is high is referred to as the high-level period, and the period during which the level of the signal is low is referred to as the low-level period. The same applies to any voltage having a high-level or low-level voltage level.

[0017] <<Basic Embodiment>> The basic embodiment of the present disclosure will be described. FIG. 1 is a configuration diagram showing a main part of a memory circuit 901 according to the basic embodiment. The memory circuit 901 is a non-volatile memory that stores 1-bit of data, and includes a memory unit 910, a read voltage supply circuit 920, a signal output circuit 930, and a program circuit 940. The memory circuit 901 may be configured by a semiconductor integrated circuit.

[0018] The memory unit 910 consists of memory elements 911 and 912, and stores data of "0" or "1" in the memory unit 910. Each of the memory elements 911 and 912 is a transistor. Therefore, the memory elements 911 and 912 are also referred to as transistors 911 and 912. Each of the transistors 911 and 912 is configured as an N-channel type MOSFET. However, while the transistor 911 is formed by a single unit MOSFET, as shown in FIG. 2, the transistor 912 is formed by a parallel circuit of n unit MOSFETs. n is an arbitrary integer of 2 or more. The unit MOSFET constituting the transistor 911 and each unit MOSFET constituting the transistor 912 have the same structure as each other and have the same electrical characteristics (including the gate threshold voltage) as each other before the execution of the program operation by the program circuit 940.

[0019] The gates of the transistors 911 and 912 are commonly connected to each other. Each source of the transistors 911 and 912 is connected to the ground. Each drain of the transistors 911 and 912 is connected to the signal output circuit 930.

[0020] In the memory circuit 901, a read operation for reading the data stored in the memory unit 910 and a program operation (write operation) for rewriting the data stored in the memory unit 910 from "0" to "1" can be executed.

[0021] The read voltage supply circuit 920 is a circuit that functions effectively in the read operation, and supplies a read voltage for turning on at least one of the transistors 911 and 912 to each gate of the transistors 911 and 912 in the read operation. The read voltage is higher than at least the gate threshold voltage of the transistor 911. The signal output circuit 930 outputs a signal corresponding to the value of the data stored in the memory unit 910 based on the magnitude relationship of the drain currents of the transistors 911 and 912 in the read operation.

[0022] The program operation is realized by the program circuit 940. In the program operation, the program circuit 940 injects hot carriers into the transistor 912 to deteriorate the electrical characteristics of the transistor 912, and this deterioration increases (raises) the gate threshold voltage of the transistor 912.

[0023] Refer to FIG. 3. In FIG. 3, the solid line waveform 962 INI represents the gate-source voltage dependence of the drain current of the transistor 912 before the execution of the program operation (i.e., in the initial state of the memory circuit 901), and the solid line waveform 962 PRG represents the gate-source voltage dependence of the drain current of the transistor 912 after the execution of the program operation. The dashed line waveform 961 represents the gate-source voltage dependence of the drain current of the transistor 911. Since no hot carriers are injected into the transistor 911 in the program operation, the electrical characteristics of the transistor 911 remain unchanged before and after the execution of the program operation.

[0024] Before the execution of the program operation, since each unit MOSFET constituting the transistors 911 and 912 has the same electrical characteristics, when a common voltage exceeding their gate threshold voltages is supplied to the gates of the transistors 911 and 912, the drain current of the transistor 912 is larger than the drain current of the transistor 911. The state where the drain current of the transistor 912 is larger than the drain current of the transistor 911 corresponds to the state where the data "0" is stored in the memory unit 910. Therefore, in the read operation, when the drain current of the transistor 912 is larger than the drain current of the transistor 911, the signal output circuit 930 outputs a signal (for example, a low-level signal) corresponding to the data "0".

[0025] By injecting hot carriers into each unit MOSFET of the transistor 912 by executing the program operation, the gate threshold voltage of each unit MOSFET of the transistor 912 increases. This corresponds to an increase in the gate threshold voltage of the transistor 912. The program operation is executed so that the gate threshold voltage of the transistor 912 becomes sufficiently higher than the gate threshold voltage of the transistor 911 after the execution of the program operation. The gate threshold voltage of the transistor 912 after the execution of the program operation may be higher than the read voltage. When the read operation is performed after the execution of the program operation, the drain current of the transistor 911 becomes larger than the drain current of the transistor 912. The state where the drain current of the transistor 911 is larger than the drain current of the transistor 912 corresponds to the state where the data "1" is stored in the memory unit 910. Therefore, in the read operation, when the drain current of the transistor 911 is larger than the drain current of the transistor 912, the signal output circuit 930 outputs a signal (for example, a high-level signal) corresponding to the data "1".

[0026] It is also possible to configure a non-volatile memory in which the stored data in the initial state is indeterminate. However, when such a non-volatile memory is used, it is necessary to perform processing for dealing with the indeterminate stored data in other peripheral circuits, which may be inconvenient from the viewpoint of circuit scale and the like. According to the memory circuit 901 of FIG. 1, the stored data can be determined to be "0" in the initial state, and the stored data can be set to "1" only when the program operation is executed.

[0027] However, in many cases, the size reduction of the memory elements (911, 912) is required to reduce the size of the entire circuit. When the size of the memory elements becomes smaller, the characteristic mismatch between the memory elements becomes larger. That is, each unit MOSFET of the transistors 911 and 912 is formed on the semiconductor substrate aiming for the same electrical characteristics of each unit MOSFET. However, in reality, variations occur in the electrical characteristics of each unit MOSFET. This variation corresponds to the mismatch. Such a mismatch inhibits the correct storage and reading of data. Alternatively, in order to realize the correct storage and reading of data in consideration of the mismatch, a countermeasure such as significantly increasing the value of the above "n" is required. In the following first embodiment, a memory circuit that is less affected by the above mismatch will be described.

[0028] <<First Embodiment>> The first embodiment of the present disclosure will be described. FIG. 4 is a configuration diagram showing a main part of a memory circuit 1 according to the first embodiment. The memory circuit 1 is a non-volatile memory that stores 1-bit data, and includes a memory unit 10, a read voltage supply circuit 20, a signal output circuit 30, and a program circuit 40, and also includes a resistor R1. The memory circuit 1 may be configured by a semiconductor integrated circuit.

[0029] The memory unit 10 includes memory elements M1 and M2, and stores data of "0" or "1" in the memory unit 10. Each of the memory elements M1 and M2 is a transistor. Therefore, the memory elements M1 and M2 are also referred to as transistors M1 and M2 (first and second transistors). Each of the transistors M1 and M2 is configured as an N-channel MOSFET. The transistors M1 and M2 have the same structure as each other and have the same electrical characteristics as each other before the execution of the program operation by the program circuit 40. Therefore, before the execution of the program operation by the program circuit 40, the transistors M1 and M2 have the same gate threshold voltage as each other. Here, regarding the transistor, the structure is a concept including the size of the transistor. Therefore, for any plurality of transistors, the fact that the structures are the same as each other means that the sizes of the plurality of transistors are also the same as each other. However, regarding the structures and electrical characteristics (such as gate threshold voltage) of any plurality of transistors, the fact that the structures or electrical characteristics are the same means that they are the same in design, and actually may include errors (that is, the same is a concept including errors).

[0030] The gates of the transistors M1 and M2 are commonly connected to each other. The source of the transistor M1 is connected to the ground via the resistor R1. That is, the source of the transistor M1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the ground. In contrast, the source of the transistor M2 is directly connected to the ground. Each drain of the transistors M1 and M2 is connected to the signal output circuit 30. The drain current of the transistor M1 is referred to by the symbol "I D1 ", and the drain current of the transistor M2 is referred to by the symbol "I D2 ".

[0031] In the memory circuit 1, a read operation for reading the data stored in the memory unit 10 and a program operation (write operation) for rewriting the data stored in the memory unit 10 from "0" to "1" can be executed.

[0032] The lead voltage supply circuit 20 is a circuit that functions effectively during the lead operation, and supplies a lead voltage for turning on at least one of the transistors M1 and M2 to the gates of the transistors M1 and M2 during the lead operation. However, since the source of the transistor M1 is connected via the resistor R1, during the lead operation, a voltage obtained by subtracting the voltage drop of the resistor R1 from the lead voltage is applied between the gate and source of the transistor M1 (that is, the lead voltage is applied between one end connected to the ground and the gate of the transistor M1 among both ends of the resistor R1). On the other hand, during the lead operation, the lead voltage is directly applied between the gate and source of the transistor M2. The lead voltage is higher than at least the gate threshold voltage of the transistor M1. Therefore, during the lead operation, at least the transistor M1 is turned on, and a state is achieved in which the drain current I D1 can flow. The signal output circuit 30 outputs a signal D OUT corresponding to the value of the data stored in the memory unit 10 based on the magnitude relationship of the drain currents of the transistors M1 and M2 during the lead operation.

[0033] The program operation is realized by the program circuit 40. The program circuit 40 deteriorates the electrical characteristics of the transistor M2 by injecting hot carriers into the transistor M2 during the program operation, and increases (raises) the gate threshold voltage of the transistor M2 due to this deterioration.

[0034] Refer to FIG. 5. In FIG. 5, the solid line waveform 800M2 INI represents the gate-source voltage dependence of the drain current of the transistor M2 before the execution of the program operation (that is, in the initial state of the memory circuit 1), and the solid line waveform 800M2 PRGrepresents the gate-source voltage dependence of the drain current of transistor M2 after the execution of the program operation. The dashed waveform 800M1 represents the gate-source voltage dependence of the drain current of transistor M1. Since no hot carriers are injected into transistor M1 during the program operation, the electrical characteristics of transistor M1 remain unchanged before and after the execution of the program operation. Ideally, waveforms 800M1 and 800M2 INI overlap each other. In FIG. 5, for the sake of illustration, waveforms 800M1 and 800M2 INI are shown slightly shifted.

[0035] Before the execution of the program operation, since transistors M1 and M2 have the same electrical characteristics, when a common voltage exceeding their gate threshold voltages is supplied to the respective gates of transistors M1 and M2, the drain current I D2 of transistor M2 is larger than the drain current I D1 of transistor M1. The state where the drain current I D2 is larger than the drain current I D1 corresponds to the state where the data "0" is stored in the memory section 10. Therefore, in the read operation, when the drain current I D2 is larger than the drain current I D1 , the signal output circuit 30 outputs a signal D OUT (for example, a low-level signal D OUT ) corresponding to the data "0". In the read operation before the execution of the program operation, the drain current I D2 is larger than the drain current I D1 .

[0036] By injecting hot carriers into the transistor M2 by executing the program operation, the gate threshold voltage of the transistor M2 increases. The program operation is executed so that the gate threshold voltage of the transistor M2 becomes sufficiently higher than the gate threshold voltage of the transistor M1 after the execution of the program operation. The gate threshold voltage of the transistor M2 after the execution of the program operation may be higher than the read voltage. When the read operation is performed after the execution of the program operation, the drain current I D1 is larger than the drain current I D2 . The state where the drain current I D1 is larger than the drain current I D2 corresponds to the state where the data "1" is stored in the memory unit 10. Therefore, in the read operation, when the drain current I D1 is larger than the drain current I D2 , the signal output circuit 30 outputs a signal D OUT (for example, a high-level signal D OUT ) corresponding to the data "1".

[0037] By adopting the circuit configuration of FIG. 4, a memory circuit that is less affected by the above mismatch can be configured.

[0038] Note that the connection relationship of FIG. 4 and the connection relationship described above for the circuit of FIG. 4 represent the connection relationship when the read operation is executed. When the program operation is executed, the source and drain of the transistor M2 may be swapped (however, this is not essential). That is, among the first electrode and the second electrode of the transistor M2, the electrode on the high potential side functions as the drain and the electrode on the low potential side functions as the source. However, among the first electrode and the second electrode of the transistor M2, the electrode (the electrode that functions as the source) connected to the ground in the read operation functions as the drain when the program operation is executed. The connection relationship of each circuit may be changed using a switch or the like (not shown in FIG. 4) (a detailed circuit example for realizing this will be described later).

[0039] The first embodiment includes the following examples EX1_1 to EX1_4. The matters described above in the first embodiment are applied to the following examples EX1_1 to EX1_4 unless otherwise specified and without contradiction. In each example, for matters conflicting with those described above in the first embodiment, the description in each example may take precedence. Also, without contradiction, matters described in any of the examples EX1_1 to EX1_4 can be applied to any other example (that is, it is also possible to combine any two or more of the plurality of examples).

[0040] [Example EX1_1] Example EX1_1 will be described. FIG. 6 shows the configuration of the memory circuit 1A according to Example EX1_1. The memory circuit 1A is an example of the memory circuit 1 in FIG. 4. The memory circuit 1A includes transistors M1 to M4, M11 to M14, M21, and M22, switches SW1 to SW12, resistors R1, R3, and R4, capacitors C1 and C2, inverters INV1 to INV5, constant current circuits CC IG and CC OTPG and a control circuit 60. The memory circuit 1A may be configured by a semiconductor integrated circuit.

[0041] Transistors M1 to M4 and M11 to M14 are N-channel MOSFETs, and transistors M21 and M22 are P-channel MOSFETs. Signals XRST and PRG are output from the control circuit 60. The signals XRST and PRG are binary signals having a signal level of low level or high level. The on / off of switches SW1 to SW12 is controlled based on the signals XRST and PRG. In FIG. 6, the state when all the switches are off is shown (the same applies to FIG. 7 described later).

[0042] The connection relationship of each component of the memory circuit 1A will be described. A positive power supply voltage VDD is applied to the power supply line LN VDD . The power supply voltage VDD has a predetermined positive DC voltage value. The ground line LN GND has a ground potential of 0V.

[0043] The sources of transistors M21 and M22 and one ends of switches SW3 and SW4 are connected to power line LN VDD . The other end of switch SW3 is connected to the gate of transistor M21, and the other end of switch SW4 is connected to the gate of transistor M22. The wiring connected to the gate of transistor M21 is referred to as line LN2, and the voltage applied to line LN2 is referred to as voltage V2. The wiring connected to the gate of transistor M22 is referred to as line LN1, and the voltage applied to line LN1 is referred to as voltage V1. The drain of transistor M21 is connected to line LN1, and the drain of transistor M22 is connected to line LN2.

[0044] The input terminal of inverter INV1 is connected to line LN1. The output terminal of inverter INV1 is connected to the input terminal of inverter INV2. The output terminal of inverter INV2 is connected to the input terminal of inverter INV3 and is also connected to line LN1 via capacitor C1. The input terminal of inverter INV4 is connected to line LN2. The output terminal of inverter INV4 is connected to the input terminal of inverter INV5. The output terminal of inverter INV5 is connected to line LN2 via capacitor C2.

[0045] One end of switch SW5 is connected to line LN1, and the other end of switch SW5 is connected to one end of switch SW1. The other end of switch SW1 is connected to ground line LN GND . One end of switch SW6 is connected to line LN2, and the other end of switch SW6 is connected to one end of switch SW2. The other end of switch SW2 is connected to ground line LN GND .

[0046] The gates of transistors M11 to M14 are commonly connected to gate line LN IG . The voltage applied to gate line LN IG is referred to as gate voltage V IG . The gates of transistors M1 to M3 are commonly connected to gate line LN OTPG . The voltage applied to gate line LN OTPG is referred to as gate voltage VOTPG is referred to as

[0047] The drain of transistor M11 is connected to line LN1, and the source of transistor M11 is connected to the drain of transistor M1. The source of transistor M1 is connected to the ground line LN GND through resistor R1. That is, the source of transistor M1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the ground line LN GND is connected to.

[0048] The drain of transistor M12 is connected to line LN2, and the source of transistor M12 is connected to electrode E1 of transistor M2. A switch SW9 is inserted in series between electrode E1 of transistor M2 and the ground line LN GND . A switch SW10 is inserted in series between electrode E2 of transistor M2 and the ground line LN GND . A switch SW11 is inserted in series between electrode E2 of transistor M2 and the power supply line LN VDD . In transistor M2, among electrodes E1 and E2, the electrode on the high potential side functions as the drain and the electrode on the low potential side functions as the source. As will be clear from the following description, in the read operation, switches SW9, SW10, and SW11 are turned off, on, and off respectively, so that electrode E1 functions as the drain, and in the program operation, switches SW9, SW10, and SW11 are turned on, off, and on respectively, so that electrode E2 functions as the drain.

[0049] The power supply line LN VDD and the gate line LN OTPG a switch SW12 is inserted in series between them, and a switch SW7 is inserted in series between the gate line LN OTPG and the ground line LN GND . The drain of transistor M13 is connected to the gate line LN OTPG , and the source of transistor M13 is connected to the drain of transistor M3. The source of transistor M3 is connected to the ground line LN GNDis connected to.

[0050] Gate line LN IG and ground line LN GND A switch SW8 is inserted in series between. The drain of transistor M14 is connected to gate line LN IG The source of transistor M14 is connected to the drain of transistor M4. The gate and drain of transistor M4 are connected to each other. The source of transistor M4 is connected to ground line LN GND is connected to.

[0051] Constant current circuit CC IG is connected to gate line LN IG Constant current circuit CC IG generates a constant current IG based on the power supply voltage VDD and supplies the constant current IG to gate line LN IG during a necessary period including the period when a read operation is performed. Constant current circuit CC OTPG is connected to gate line LN OTPG Constant current circuit CC OTPG generates a constant current OTPG based on the power supply voltage VDD and supplies the constant current OTPG to gate line LN OTPG during a necessary period including the period when a read operation is performed.

[0052] An inverter, which is any one of inverters INV1 to INV5, outputs an inverted signal of an input signal to its own input terminal from its own output terminal. Specifically, when the input voltage to its own input terminal is less than a predetermined threshold voltage, the inverter outputs a high-level signal that is sufficiently higher than the threshold voltage from its own output terminal, and when the input voltage to its own input terminal is equal to or higher than the predetermined threshold voltage, the inverter outputs a low-level signal that is sufficiently lower than the threshold voltage from its own output terminal. Inverters INV1 to INV5 are driven based on the power supply voltage VDD, and the threshold voltage of each inverter is approximately half of the power supply voltage VDD. However, the threshold voltage of each inverter may be given a hysteresis characteristic. The output signal of inverter INV3 is the output signal D of memory circuit 1A OUTIt is. A signal corresponding to the value of the data stored in the memory unit 10 composed of the transistors M1 and M2 is output as the output signal D through a read operation. OUT is output.

[0053] The control terminal of the switch SW5 is connected to the output terminal of the inverter INV1. The switch SW5 is turned on and off when the output signal of the inverter INV1 is at a high level and a low level, respectively. The control terminal of the switch SW6 is connected to the output terminal of the inverter INV4. The switch SW6 is turned on and off when the output signal of the inverter INV4 is at a high level and a low level, respectively.

[0054] As described above, the transistors M1 and M2 have the same structure as each other and have the same electrical characteristics (including the gate threshold voltage) as each other before the execution of the program operation. Further, here, it is assumed that the memory circuit 1A employs the configuration as shown below (see FIG. 7). That is, the first to fifth unit MOSFETs of the N-channel type are formed in the memory circuit 1A, and the transistors M1, M2, and M3 are formed by the first, second, and third unit MOSFETs, respectively, while the transistor M4 is formed by the parallel circuit of the fourth and fifth unit MOSFETs. The first to fifth unit MOSFETs have the same structure as each other and have the same electrical characteristics (including the gate threshold voltage) as each other before the execution of the program operation. In addition, the resistance values of the resistors R1 and R3 are made the same as each other, and the resistance value of the resistor R4 is set to half of the resistance value of the resistor R1. The constant current IG is set to twice the constant current OTPG. Also, the transistors M1 to M14 may be transistors having the same structure and electrical characteristics (including the gate threshold voltage) as each other.

[0055] ---Read operation RD before program operation INI --- Hereinafter, for convenience of explanation, the read operation executed before the execution of the program operation is sometimes particularly referred to as the read operation RD INI and the read operation executed after the execution of the program operation is referred to as the read operation RD PRGmay be referred to as. When simply referring to the read operation, it refers to the read operation before or after the execution of the program operation.

[0056] FIG. 8 is a timing chart of the read operation RD INI . In the read operation, the low-level period of the signal XRST is referred to as the precharge period, and the period during which both switches SW5 and SW6 are in the off state within the high-level period of the signal XRST is referred to as the read period. The read operation is realized during the read period after the precharge period. During the period when the program operation is not performed (including the precharge period and the read period), the signal PRG is maintained at the low level. On the premise that the signal PRG is at the low level, when the signal XRST switches from the low level to the high level, the transition from the precharge period to the read period occurs, and a signal corresponding to the data stored in the memory unit 10 passes through the read period and is output as the output signal D OUT .

[0057] During the precharge period, based on the low-level signals XRST and PRG, as shown in FIG. 9, switches SW1 and SW2 are turned off while switches SW3, SW4, SW7, and SW8 are turned on, and the generation and output operations of the constant current by the constant current circuits CC IG and CC OTPG are stopped. Also, during the low-level period of the signal PRG, based on the low-level signal PRG, switches SW9, SW11, and SW12 are turned off and switch SW10 is turned on. During the period when the program operation is not performed (including the precharge period and the read period), in the transistor M2, electrode E1 functions as the drain and electrode E2 functions as the source.

[0058] In FIG. 8, the dashed waveform INI V1 represents the waveform of the voltage V1 in the read operation RD INI , and the solid waveform INI V2 represents the waveform of the voltage V2 in the read operation RD INI . From the precharge period to the first half of the read period, the waveforms INI V1 and INI V2overlap each other. During the precharge period, voltage V IG and V OTPG are 0V, so all of the transistors M1 to M4 and M11 to M14 are in the off state. Also, during the precharge period, positive charges are supplied to lines LN1 and LN2 through switches SW4 and SW3, and voltages V1 and V2 reach the level of the power supply voltage VDD. Therefore, during the precharge period, the output signals of inverters INV1 and INV4 are at the low level. As a result, switches SW5 and SW6 are off.

[0059] The transition from the precharge period to the read period occurs when the signal XRST switches from the low level to the high level. In the read period, based on the high-level signal XRST and the low-level signal PRG, as shown in FIG. 10, switches SW1 and SW2 are turned on while switches SW3, SW4, SW7, and SW8 are turned off. Further, in the read period, the constant current circuits CC IG and CC OTPG generate and output a constant current. As a result, in the read period, the gate voltage V IG increases with the constant current I IG while the gate voltage V OTPG increases with the constant current I OTPG . At this time, by making the constant current I IG larger than the constant current I OTPG (for example, setting “I IG = I OTPG ×2”), the gate voltage V IG = I OTPG ×2” so that the gate voltage V IG increases at twice the speed compared to the gate voltage V OTPG ), before the gate voltage V OTPG reaches the gate threshold voltage of transistor M1 or M2, transistors M11 to M14 can be turned on. In FIG. 8, among the gate voltages V IG and V OTPG , the waveform of either one of the voltages is illustrated as a representative (the same applies to FIG. 12 described later).

[0060] During the lead period, as the gate voltages V IG and V OTPG rise, transistors M4 and M11 to M14 turn on, and drain current flows through transistors M1 to M3. During the lead period, the drain current flowing through transistor M1 is referred to by the symbol "I D1 ", and the drain current flowing through transistor M2 is referred to by the symbol "I D2 " (see Fig. 10). Also, the gate voltage V OTPG during the lead period corresponds to the above-mentioned lead voltage. The voltage obtained by subtracting the voltage drop across resistor R1 from the gate voltage V OTPG (lead voltage) is applied across the gate-source of transistor M1, while the gate voltage V OTPG (lead voltage) is directly applied across the gate-source of transistor M2 (assuming the on-resistance of switch SW10 is negligibly small). Therefore, during the lead period before the program operation is executed, the drain current I D2 is larger than the drain current I D1 , and as a result, the voltage V2 drops faster than the voltage V1. Also, since drain current starts to flow through transistor M21 as the voltage V2 drops, the drop of voltage V1 stops when the voltage V2 has dropped to a certain extent, and the voltage V1 rises to the level of the power supply voltage VDD.

[0061] When the voltage V2 falls below the threshold voltage of inverter INV4 in the state of "V1 > V2", the output signal of inverter INV4 switches from the low level to the high level, and switch SW6 switches from the off state to the on state. As shown in Fig. 11, the signal END is the logical OR signal of the output signals of inverter INV1 and inverter INV4. Therefore, when at least one of the output signals of inverters INV1 and INV4 becomes high level, the signal END becomes high level. The signal END can be regarded as an internal signal generated within the control circuit 60.

[0062] In response to the signal END becoming high level, the control circuit 60 activates the constant current circuits CC IG and CC OTPGStop the generation and output operation of the constant current according to and switch the switches SW7 and SW8 from off to on. As a result, the gate voltages V IG and V OTPG drop to 0V.

[0063] In the read operation, after the signal END becomes high level, the signal D OUT is specifically referred to as the read confirmation signal D OUT . The read confirmation signal D OUT represents the value of the data stored in the memory unit 10 (the value of the data read from the memory unit 10). The fact that the read confirmation signal D OUT is at a low level means that the value of the data is "0", and the fact that the read confirmation signal D OUT is at a high level means that the value of the data is "1". In the read operation RD INI , since the output signal of the inverter INV1 is maintained at a low level, the read confirmation signal D OUT also becomes low level, and the data of "0" (i.e., the initial value data) is read out. After the signal END becomes high level in the read operation RD INI , the read confirmation signal D OUT representing the data of "0" continues to be output. Therefore, there is no need to provide a latch circuit in the subsequent stage, and the read confirmation signal D OUT can be directly supplied to the circuit that requires the read confirmation signal D OUT (for example, a trimming switch that is turned on / off according to the stored data in the memory unit 10).

[0064] ---Read operation RD PRG ---after the program operation Figure 12 is a timing chart of the read operation RD PRG (that is, the read operation performed after the execution of the program operation). In Figure 12, the dashed waveform PRG V1 represents the waveform of the voltage V1 in the read operation RD PRG , and the solid waveform PRG V2 represents the waveform of the voltage V1 in the read operation RD PRGrepresents the waveform of voltage V2. From the precharge period to the first half of the read period, waveforms PRG V1 and PRG V2 overlap each other.

[0065] The content of the read operation including the state control of each switch in the precharge period and the read period is the same before and after the execution of the program operation. However, due to the program operation executed before the read operation RD PRG only transistor M2 among transistors M1 and M2 has deteriorated, and only the gate threshold voltage of transistor M2 has increased significantly. Therefore, in the read period of the read operation RD PRG drain current I D1 is larger than drain current I D2 , and as a result, voltage V1 drops faster than voltage V2. Also, since drain current starts to flow through transistor M22 as voltage V1 drops, the drop of voltage V2 stops when voltage V1 has dropped to a certain extent, and voltage V2 rises to the level of the power supply voltage VDD.

[0066] When voltage V1 falls below the threshold voltage of inverter INV1 in the state of "V1 < V2", the output signal of inverter INV1 switches from the low level to the high level, and switch SW5 switches from the off state to the on state. Also, when the output signal of inverter INV1 switches from the low level to the high level, signal END also switches from the low level to the high level (see Fig. 11). In response to signal END becoming high, control circuit 60 stops the generation and output operations of the constant current by constant current circuits CC IG and CC OTPG and switches switches SW7 and SW8 from off to on. Thereby, gate voltages V IG and V OTPG drop to 0V.

[0067] After signal END becomes high in the read operation, signal D OUT is, as described above, particularly the read confirmation signal D OUTis referred to as. Read operation RD PRG In, since the output signal of the inverter INV1 becomes high level in response to the decrease in the voltage V1, the read confirmation signal D OUT becomes high level and represents the data of "1". Read operation RD PRG After the signal END becomes high level in the read operation RD OUT the read confirmation signal D representing the data of "1" continues to be output, so there is no need to provide a latch circuit in the subsequent stage, and the read confirmation signal D OUT can be directly supplied to a circuit that requires it (for example, a trimming switch that is turned on / off according to the stored data in the memory unit 10). OUT

[0068] ---Program operation--- In this way, in the read operation (read period), the drain current I D2 is larger than the drain current I D1 which corresponds to the state where the data of "0" is stored in the memory unit 10. In the read operation RD of FIG. 8 INI the drain current I D2 is larger than the drain current I D1 so the read confirmation signal D corresponding to the data of "0" OUT (here the low-level signal D OUT ) is output. Conversely, in the read operation (read period), the drain current I D1 is larger than the drain current I D2 which corresponds to the state where the data of "1" is stored in the memory unit 10. In the read operation RD of FIG. 12 PRG the drain current I D1 is larger than the drain current I D2 so the read confirmation signal D corresponding to the data of "1" OUT (here the high-level signal D OUT ) is output.

[0069] In the memory circuit 1A of FIG. 6, from the read operation RD of FIG. 8 INI to the read operation RD of FIG. 12 PRG ​The program operation that brings about the change is realized as follows.

[0070] Fig. 13 shows the states of the respective switches in the memory circuit 1A during the period in which the program operation is executed (hereinafter referred to as the program period). In the program period, the signal XRST is at a low level and the signal PRG is at a high level. Based on these signals XRST and PRG, switches SW1, SW2, SW7, and SW10 are turned off, while switches SW3, SW4, SW8, SW9, SW11, and SW12 are turned on. Also, the constant current generation and output operations by the constant current circuits CC IG and CC OTPG are stopped. As a result, the power supply voltage VDD is applied to the electrode E2 and the gate of the transistor M2, while the potential of the electrode E1 of the transistor M2 becomes 0V. Also, when the switch SW8 is turned on, all of the transistors M11 to M14 are turned off.

[0071] In the program period, the electrode E2 functions as the drain of the transistor M2 and the electrode E1 functions as the source of the transistor M2, and a current flows from the electrode E2 toward the electrode E1. In the process of this current flowing, hot carriers are injected into the transistor M2, and the characteristics of the transistor M2 deteriorate, and the gate threshold voltage of the transistor M2 increases. After maintaining the state of Fig. 13 for a time sufficient to sufficiently increase the gate threshold voltage of the transistor M2, the program operation is terminated by switching the signal PRG from a high level to a low level.

[0072] ---Correspondence relationship between the memory circuits 1 and 1A--- Supplementary explanation will be given regarding the correspondence relationship between the memory circuit 1 of Fig. 4 and the memory circuit 1A of Fig. 6. First, the fact that the memory section 10 is constituted by the transistors M1 and M2 is common between the memory circuits 1 and 1A.

[0073] The read voltage supply circuit 20 of Fig. 4 is mainly composed of the transistor M3, the resistor R3, and the constant current circuit CC in the memory circuit 1A of Fig. 6 OTPGand is composed of the switch SW7, and it is also possible to interpret that the transistor M13 is also included in the components of the circuit 20. In the memory circuit 1A of FIG. 6, it can be said that a drain current control circuit for permitting or blocking the supply of drain currents (I D1 , I D2 ) to the transistors M1 and M2 is provided, and the drain current control circuit includes the transistors M11 to M14 and M4, the resistor R4, the constant current circuit CC IG and the switch SW8.

[0074] The signal output circuit 30 of FIG. 4 is mainly composed of the transistors M21 and M22, the switches SW1 to SW6, the inverters INV1 to INV5, and the capacitors C1 and C2 in the memory circuit 1A of FIG. 6. Depending on the magnitude of the parasitic capacitance added to the lines LN1 and LN2, the capacitors C1 and C2 and the inverter INV5 can also be omitted.

[0075] The program circuit 40 of FIG. 4 includes the switches SW9 to SW12 in the memory circuit 1A of FIG. 6. For the injection of hot carriers, of course, the power supply voltage VDD is required, so it can also be interpreted that a power supply circuit (not shown) for generating and outputting the power supply voltage VDD is also included in the components of the program circuit 40. The same applies to the read voltage supply circuit 20 and the signal output circuit 30.

[0076] The control circuit 60 of FIG. 6 can be interpreted as a circuit that controls the operations of the read voltage supply circuit 20, the signal output circuit 30, and the program circuit 40 of FIG. 4 (and further a circuit that controls the operation of the above-mentioned drain current control circuit). Alternatively, it is also possible to consider that the control circuit 60 is a circuit that is shared by the circuits 20, 30, and 40 to realize the read operation and the program operation as a part of each of the circuits 20, 30, and 40.

[0077] In the memory circuits 1 and 1A, in the read operation, when “I D2 >I D1 ”, the signal D associated with the first value OUT(Read confirmation signal D OUT ) is output, and when “I D2 <I D1 ” is satisfied, the signal D OUT (Read confirmation signal D OUT ) is output. In the above operation example, the first value is “0” and the second value is “1”. However, as long as the first and second values are different, the first and second values can be arbitrary. Also, the circuit configuration may be modified such that the signal D OUT associated with the first value becomes a high-level signal and the signal D OUT associated with the second value becomes a low-level signal.

[0078] [Embodiment EX1_2] Embodiment EX1_2 will be described. The memory circuit 1 or 1A shown in FIG. 4 or FIG. 6 is a first non-volatile memory that stores data for 1 bit. However, a second non-volatile memory that includes a plurality of the memory circuits 1 or 1A as unit cells and stores data for a plurality of bits can also be configured.

[0079] Alternatively, a unit cell may be configured by a combination of the memory unit 10 and the signal output circuit 30, and a third non-volatile memory provided with a plurality of such unit cells may be configured. In the third non-volatile memory, the read voltage supply circuit 20 and the program circuit 40 are shared among the plurality of unit cells. That is, for example, in the third non-volatile memory, when performing a read operation on two or more unit cells included in the plurality of unit cells, the read voltage supply circuit 20 may supply a read voltage to each gate of the transistors M1 and M2 in each of the two or more unit cells. Similarly, for example, in the third non-volatile memory, when performing a program operation on two or more unit cells included in the plurality of unit cells, the program circuit 40 may inject hot carriers into the transistor M2 in each of the two or more unit cells.

[0080] In any case, in the non-volatile memory according to the present disclosure, the number of bits of the stored data can be arbitrary as long as it is 1 or more, and the memory unit 10 is provided for the number of bits of the stored data.

[0081] [Example EX1_3] Example EX1_3 will be described. In Example EX1_1, a circuit configuration for generating a lead voltage using a constant current was given. However, the lead voltage supply circuit 20 in FIG. 4 may be a DC voltage source that supplies a DC lead voltage to each gate of transistors M1 and M2 during the lead operation.

[0082] [Example EX1_4] Example EX1_4 will be described. The non-volatile memory according to the first embodiment (for example, any of the non-volatile memories given in Example EX1_2 above) can be incorporated into any circuit or device that realizes a predetermined functional operation.

[0083] When a power supply voltage is supplied to a circuit or device in which a non-volatile memory is incorporated and the circuit or the device is activated, the circuit or the device reads out the data stored in the non-volatile memory by a read operation and realizes a predetermined functional operation according to the read data.

[0084] For example, a non-volatile memory can be incorporated into an amplifier circuit (not shown) capable of varying the amplification factor according to trimming data, and the amplification factor of the amplifier circuit can be optimally adjusted by supplying one or more pieces of data stored in the non-volatile memory as trimming data to the amplifier circuit.

[0085] Also, the non-volatile memory according to the first embodiment can be incorporated into semiconductor integrated circuits for various applications, such as a semiconductor integrated circuit for a DC / DC converter and a semiconductor integrated circuit for a motor driver. The above amplifier circuit is an example of a circuit provided in these semiconductor integrated circuits.

[0086] <<Second Embodiment>> A second embodiment of the present disclosure will be described. As shown in FIG. 14A, a general constant voltage source 1910 that requires a corresponding current output capability includes a reference voltage source 1911 composed of a bandgap reference or the like, and a buffer amplifier 1912 that outputs the output voltage of the reference voltage source 1911 with a low impedance. The output voltage Vo is output from the buffer amplifier 1912. FIG. 14B shows the configuration of the constant voltage source 1910 including an internal circuit example of the buffer amplifier 1912.

[0087] When a constant voltage source is required for each of a plurality of circuits in an arbitrary semiconductor integrated circuit, as shown in FIG. 15A, the wiring to which the output voltage Vo of a single buffer amplifier 1912 is applied is routed to the necessary locations in the semiconductor integrated circuit, or, as shown in FIG. 15B, it is necessary to arrange the constant voltage source 1910 at each location that requires the voltage Vo.

[0088] However, in the method of FIG. 15A, it is necessary to consider the influence of crosstalk, noise, etc. on the routed wiring, and considering the influence, the routing itself may become impossible. In the method of FIG. 15B, a reference voltage source 1911 composed of a bandgap reference or the like is required for each constant voltage source 1910, and the circuit area increases.

[0089] If a constant voltage source can be configured with a simple structure, it is possible to form a constant voltage source with a small area at the necessary locations, which is very advantageous. Although the circumstances related to the constant voltage source have been described above, the same circumstances also apply to the constant current source and the comparator. If a constant current source or a comparator can be configured with a simple structure, it is possible to form a constant current source or a comparator with a small area, which is very advantageous.

[0090] The second embodiment includes the following Examples EX2_1 to EX2_3, and in Examples EX2_1 to EX2_3, techniques contributing to simplification of the configuration and the like will be described.

[0091] [Example EX2_1] Describe Example EX2_1. FIG. 16 shows a circuit diagram of a constant voltage source 1100 according to Example EX2_1. The constant voltage source 1100 includes transistors Ma and Mb (first and second differential transistors), transistors Mc and Md forming a current mirror circuit CM1, an output transistor Mo, and resistors Rs and Rb. The constant voltage source 1100 may be configured by a semiconductor integrated circuit.

[0092] Transistors Ma and Mb are N-channel MOSFETs, and their gates are connected to each other. That is, transistors Ma and Mb form a differential pair with their gates commonly connected to each other. However, as a characteristic configuration, the gate threshold voltages of transistors Ma and Mb are different from each other. Specifically, transistor Ma is a depletion-type MOSFET and has a negative gate threshold voltage, and transistor Mb is an enhancement-type MOSFET and has a positive gate threshold voltage.

[0093] Since transistor Ma has a negative gate threshold voltage, even if the gate potential of transistor Ma is lower than the source potential of transistor Ma, if the gate potential of transistor Ma (e.g., -0.3V) as seen from the source potential of transistor Ma is higher than the gate threshold voltage of transistor Ma (e.g., -0.5V), transistor Ma will be in the on state.

[0094] Transistors Mc and Md and output transistor Mo are P-channel MOSFETs. The sources of transistors Mc, Md, and Mo are connected to a power supply voltage line LNVdd to which a predetermined positive power supply voltage Vdd is applied. The gates of transistors Mc and Md, the drain of transistor Mc, and the drain of transistor Mb are connected to each other. The drain of transistor Md, the drain of transistor Ma, and the gate of output transistor Mo are connected to each other. The sources of transistors Ma and Mb are connected to ground via resistors Rs (more specifically, connected to a ground line LNgnd having a ground potential). The gate of transistor Mb is connected to ground (i.e., ground line LNgnd) via resistor Rb, while the gate of transistor Ma is directly connected to ground (i.e., ground line LNgnd). The drain of output transistor Mo is connected to the gate of transistor Mb.

[0095] Transistor Mc functions as the input - side transistor of the current in current - mirror circuit CM1, while transistor Md can be considered to function as the output - side transistor of the current in current - mirror circuit CM1. Here, transistors Mc and Md are a pair of transistors having the same structure and the same electrical characteristics as each other. Therefore, in current - mirror circuit CM1, it acts such that a drain current having the same current value as the drain current of transistor Mc flows through transistor Md. At this time, the drain current of transistor Mc is output toward transistor Mb, while the drain current of transistor Md is output toward transistor Ma. That is, current - mirror circuit CM1 operates such that a uniform current (i.e., a current having the same current value as each other) is output toward the drain of transistor Ma and the drain of transistor Mb. However, "uniform" and "same" here are concepts including errors (the same applies to any other embodiments described later). Also, regarding a transistor, the structure is a concept including the size of the transistor. Therefore, for any plurality of transistors, the fact that the structures are the same as each other means that the sizes of the plurality of transistors are also the same as each other (the same applies to any other embodiments described later).

[0096] The drain of output transistor Mo is connected to the output terminal OUT of constant - voltage source 1100, and the output voltage Vout of constant - voltage source 1100 is generated at output terminal OUT. Constant - voltage source 1100 can supply current to the load (not shown; the load receiving output voltage Vout) of constant - voltage source 1100 through output transistor Mo and output terminal OUT. In the example of FIG. 16, in order to form output transistor Mo, two basic MOSFETs having the same structure as transistor Mc or Mb are prepared, and output transistor Mo is formed by the parallel circuit of the two basic MOSFETs.

[0097] In FIG. 17, waveform C_Ma represents the relationship between the gate - source voltage and the drain current in transistor Ma, and waveform C_Mb represents the relationship between the gate - source voltage and the drain current in transistor Mb.

[0098] With the above configuration, the circuit can be balanced in a state where the drain current values of transistors Ma and Mb are the same as each other. In a state where the drain current values of transistors Ma and Mb are the same as each other, due to the difference in the electrical characteristics of transistors Ma and Mb, the gate voltage V G _Mb of transistor Mb becomes higher than the gate voltage of transistor Ma. In FIG. 17, the current value I_blns represents the value of each drain current of transistors Ma and Mb in the balanced state. The voltage V GS _Ma_blns represents the gate-source voltage of transistor Ma when a drain current with a current value I_blns flows through transistor Ma, and the voltage V GS _Mb_blns represents the gate-source voltage of transistor Mb when a drain current with a current value I_blns flows through transistor Mb.

[0099] While the gate voltage of transistor Ma is zero, the gate voltage V G _Mb of transistor Mb is the sum of the gate-source voltage of transistor Mb and the voltage drop V_Rs across resistor Rs.

[0100] The sum of the voltage drop V_Rs and the voltage V GS _Mb_blns (V_Rs + V GS _Mb_blns) is referred to as the balance gate voltage. The balance gate voltage has a positive voltage value corresponding to the electrical characteristics of transistors Ma and Mb. Since the gate voltage of output transistor Mo is adjusted by transistors Ma to Md so that the gate voltage V G _Mb of transistor Mb coincides with the balance gate voltage, the output voltage Vout is stabilized at the balance gate voltage (substantially coincides with the balance gate voltage). That is, an output voltage Vout corresponding to the balance gate voltage is generated.

[0101] By the method of this embodiment, a constant voltage source can be formed with a simple configuration (therefore with a small area). In the configuration according to this embodiment, the accuracy of the output voltage Vout is not necessarily high. However, there are many applications of constant voltage sources that do not require such high voltage accuracy, and the configuration according to this embodiment is particularly suitable for such applications.

[0102] The constant voltage source 1100 includes a voltage output circuit that generates an output voltage Vout according to the gate voltage (V G _Mb) of the transistor Mb based on the drain voltage of the transistor Ma. In the configuration of FIG. 16, the voltage output circuit is configured to include an output transistor Mo. By applying a predetermined DC voltage (Vdd) to the series circuit of the output transistor Mo and the resistor Rb, the output voltage Vout is generated through the output transistor Mo.

[0103] In the configuration of FIG. 16, the output voltage Vout has the same voltage value as the gate voltage V G _Mb of the transistor Mb, but the constant voltage source 1100 may be modified so that the output voltage Vout and the gate voltage V G _Mb are different. For example, the constant voltage source 1100 in FIG. 16 may be modified like the constant voltage source 1100' in FIG. 18. In the constant voltage source 1100' of FIG. 18, a resistor Rb' is inserted between the connection node 1121 between the drain of the output transistor Mo and the output terminal OUT and the connection node 1122 between the gate of the transistor Mb and the resistor Rb. Except for this insertion, the configurations of the constant voltage sources 1100 and 1100' are common. When the resistor Rb' is inserted, a predetermined DC voltage (Vdd) is applied to the series circuit of the output transistor Mo, the resistors Rb' and Rb, and the output voltage Vout is stabilized at a voltage determined by the ratio of the resistance values between the gate voltage V G _Mb and the resistors Rb and Rb'.

[0104] If the gate threshold voltages of transistors Ma and Mb are different from each other, both transistors Ma and Mb may be enhancement-type MOSFETs (the same applies to any other embodiments described later). However, in that case, it is necessary to apply a positive bias voltage to the gate of transistor Ma. Also, although a configuration in which resistors Rs are inserted between the sources of transistors Ma and Mb and the ground has been described, an active load may be inserted between the sources of transistors Ma and Mb and the ground instead of the resistors Rs (the same applies to any other embodiments described later).

[0105] [Embodiment EX2_2] Embodiment EX2_2 will be described. A constant current source can also be formed by applying the configuration shown in Embodiment EX2_1. FIG. 19 shows a circuit diagram of a constant current source 1200 according to Embodiment EX2_2. The constant current source 1200 includes transistors Ma and Mb (first and second differential transistors), transistors Mc and Md that form a current mirror circuit CM1, transistors Me and Mf that form a current mirror circuit CM2, and resistors Rs and Rb. The constant current source 1200 may be configured in a semiconductor integrated circuit.

[0106] In the constant current source 1200, transistors Ma, Mb, Mc, and Md and resistors Rs and Rb are the same as those shown in Embodiment EX2_1, and their connection relationships are as shown in Embodiment EX2_1. That is, the sources of transistors Mc and Md are connected to a power supply voltage line LNVdd to which a predetermined positive power supply voltage Vdd is applied. The gates of transistors Mc and Md, the drain of transistor Mc, and the drain of transistor Mb are connected to each other, and the drains of transistors Ma and Md are connected to each other. The sources of transistors Ma and Mb are connected to the ground via resistors Rs (more specifically, connected to a ground line LNgnd having a ground potential). The gate of transistor Mb is connected to the ground (i.e., the ground line LNgnd) via resistor Rb, while the gate of transistor Ma is directly connected to the ground (i.e., the ground line LNgnd).

[0107] In the current mirror circuit CM1, it operates such that a drain current having the same current value as the drain current of the transistor Mc flows through the transistor Md. At this time, while the drain current of the transistor Mc is output toward the transistor Mb, the drain current of the transistor Md is output toward the transistor Ma. That is, the current mirror circuit CM1 operates so that a uniform current is output toward the drain of the transistor Ma and the drain of the transistor Mb (that is, currents having the same current value as each other are output).

[0108] The transistors Me and Mf are P-channel MOSFETs. Each source of the transistors Me and Mf is connected to the power supply voltage line LNVdd, and each gate of the transistors Me and Mf is connected to the drain of the transistor Ma. The drain of the transistor Me is connected to the gate of the transistor Mb.

[0109] It can be considered that the transistor Me functions as the input-side transistor of the current in the current mirror circuit CM2, while the transistor Mf functions as the output-side transistor of the current in the current mirror circuit CM2. Here, the transistors Me and Mf are a pair of transistors having the same structure as each other and the same electrical characteristics as each other. Therefore, a drain current having the same current value as the drain current of the transistor Me flows through the transistor Mf (assuming that a load not shown in FIG. 19 is connected to the drain of the transistor Mf). In the example of FIG. 19, in order to form the transistor Me, two basic MOSFETs having the same structure as the transistor Mc or Mb are prepared, and the transistor Me is formed by a parallel circuit of the two basic MOSFETs. The same applies to the transistor Mf.

[0110] Due to the configuration of FIG. 19, similar to the configuration of FIG. 16, the circuit is balanced in a state where the values of the drain currents of the transistors Ma and Mb are the same as each other. For this reason, similar to what was described in the embodiment EX2_1, the gate voltage V of the transistor Mb GThe gate voltages of transistors Me and Mf are adjusted by transistors Ma to Md so that _Mb matches the above balance gate voltage. As a result, a drain current having a current value obtained by dividing the balance gate voltage by the value of resistor Rb flows through transistor Me, and a constant current I CC having the same current value flows as the drain current of transistor Mf (assuming that a load not shown in FIG. 19 is connected to the drain of transistor Mf).

[0111] Note that in the constant current source 1200 of FIG. 19, a predetermined DC voltage (Vdd) is applied to the series circuit of transistor Me and resistor Rb, but another resistor (not shown) may be inserted between the drain of transistor Me and the connection node between the gate of transistor Mb and resistor Rb.

[0112] Also, the value of the constant current I CC may be adjusted by arbitrarily adjusting the ratio of the number of basic MOSFETs constituting transistor Me to the number of basic MOSFETs constituting transistor Mf.

[0113] Further, for the current mirror circuit CM2, if one or more other transistors (not shown) having the same structure and the same electrical characteristics as transistor Me or Mf are added and the gates of transistor Me or Mf and the gates of the one or more other transistors are commonly connected, a constant current can also be obtained from the drains of the one or more other transistors.

[0114] By the method of this embodiment, a constant current source can be formed with a simple configuration (therefore, a small area).

[0115] For example, using the constant current source 1200 according to Embodiment EX2_2, at least one of the constant current circuits CC IG and CC OTPG (see FIG. 6) may be formed. In this case, when forming the constant current circuit CC IG using the constant current source 1200, in the case of forming the constant current I CCfunctions as a constant current IG (see FIG. 6), and forms a constant current circuit CC using a constant current source 1200 OTPG in the case where, the constant current I CC functions as a constant current OTPG (see FIG. 6). When the second embodiment (particularly Example EX2_2) is combined with the first embodiment, the power supply voltage lines LNVdd and LN VDD refer to the same ones as each other (therefore "Vdd = VDD"), and it is understood that the ground lines LNgnd and LN GND refer to the same ones as each other (see FIGS. 6 and 19).

[0116] In addition, as shown in FIG. 20, a configuration may be adopted in which the drain of the transistor Mf in the constant current source 1200 is connected to the ground via a resistor Rf. In the configuration of FIG. 20, an output voltage Vout' having a voltage value determined by each value of the resistor Rf and the constant current I CC is generated between both ends of the resistor Rf. That is, the configuration of FIG. 20 functions as a constant voltage source. At this time, for example, if the values of the resistors Rb and Rf are set to be the same, a voltage obtained by replicating the gate voltage V G _Mb (balance gate voltage) of the transistor Mb can be obtained as the output voltage Vout'.

[0117] [Example EX2_3] Example EX2_3 will be described. A comparator can also be formed by applying the configuration shown in Example EX2_1. FIG. 21 shows a circuit diagram of a comparator 1300 according to Example EX2_3. The comparator 1300 includes transistors Ma and Mb (first and second differential transistors), transistors Mc and Md forming a current mirror circuit CM1, a resistor Rs, and an output circuit 1310. The comparator 1300 may be configured by a semiconductor integrated circuit.

[0118] In the comparator 1300, the transistors Ma, Mb, Mc, and Md and the resistor Rs are the same as those shown in the Example EX2_1, and their connection relationships are as shown in the Example EX2_1. That is, the sources of the transistors Mc and Md are connected to a power supply voltage line LNVdd to which a predetermined positive power supply voltage Vdd is applied. The gates of the transistors Mc and Md, the drain of the transistor Mc, and the drain of the transistor Mb are connected to each other, and the drains of the transistors Ma and Md are connected to each other. The sources of the transistors Ma and Mb are connected to the ground via the resistor Rs (specifically, connected to a ground line LNgnd having a ground potential). The gate of the transistor Ma is directly connected to the ground (i.e., the ground line LNgnd).

[0119] In the current mirror circuit CM1, it operates such that a drain current having the same current value as the drain current of the transistor Mc flows through the transistor Md. At this time, the drain current of the transistor Mc is output toward the transistor Mb, while the drain current of the transistor Md is output toward the transistor Ma. That is, the current mirror circuit CM1 operates such that a uniform current is output toward the drain of the transistor Ma and the drain of the transistor Mb (i.e., currents having the same current value as each other are output). However, whether a uniform current is actually output depends on the input voltage Vin.

[0120] In the comparator 1300 of FIG. 21, the output circuit 1310 is configured by an inverter. Therefore, the output circuit 1310 is also referred to as the inverter 1310. The input terminal of the inverter 1310 is connected to the drain of the transistor Ma, and the signal CMPout is output from the output terminal of the inverter 1310. The inverter 1310 outputs, from its output terminal, an inverted signal of the input signal to its input terminal. Specifically, when the input voltage to its input terminal is less than a predetermined threshold voltage, the inverter 1310 outputs a high-level signal from its output terminal, and when the input voltage to its input terminal is greater than or equal to the predetermined threshold voltage, the inverter 1310 outputs a low-level signal from its output terminal. The inverter 1310 is driven based on the power supply voltage Vdd, and the threshold voltage of the inverter 1310 is approximately half of the power supply voltage Vdd. However, the threshold voltage of the inverter 1310 may be given a hysteresis characteristic.

[0121] In the comparator 1300, the voltage Vin is input to the gate of the transistor Mb. The voltage Vin is the input voltage to the comparator 1300, and the comparator 1300 outputs a signal CMPout indicating the higher or lower relationship between the input voltage Vin and a predetermined voltage. This predetermined voltage is the above-described balance gate voltage determined by the electrical characteristics of the transistors Ma and Mb.

[0122] Based on the state where the input voltage Vin matches the balance gate voltage, when the input voltage Vin is lower than the balance gate voltage, the drain voltage of the transistor Ma decreases and falls below the threshold voltage of the inverter 1310, so that the signal CMPout becomes high level. Conversely, when the input voltage Vin is higher than the balance gate voltage, the drain voltage of the transistor Ma increases and exceeds the threshold voltage of the inverter 1310, so that the signal CMPout becomes low level. That is, the higher or lower relationship between the input voltage Vin and the predetermined voltage (balance gate voltage) is indicated by the signal CMPout.

[0123] By the method of this embodiment, a comparator can be formed with a simple configuration (and thus a small area).

[0124] Further, the output circuit 1310 may be a circuit other than an inverter (for example, a buffer circuit). The output circuit 1310 can output a signal of a first level based on a decrease in the drain voltage of the transistor Ma in response to the input voltage Vin being lower than the balance gate voltage, and can output a signal of a second level based on an increase in the drain voltage of the transistor Ma in response to the input voltage Vin being higher than the balance gate voltage, as long as it is a circuit that can do so (the first and second levels are different from each other).

[0125] [Appendix 1] An appendix is provided for the present disclosure for which a specific configuration example was shown in the above-described embodiment.

[0126] The non-volatile memory according to the present disclosure includes a first transistor, a second transistor having a gate commonly connected to the gate of the first transistor, a resistor having a first end and a second end, with the first end connected to the source of the first transistor, a lead voltage supply circuit configured to supply a lead voltage for turning on at least one of the first and second transistors between the gate of the first transistor and the second end of the resistor and between the gate and the source of the second transistor, and a signal output circuit configured to output a signal associated with a first value or a signal associated with a second value based on the drain currents of the first and second transistors in a read operation in which the lead voltage is supplied by the lead voltage supply circuit (a first configuration).

[0127] In the non-volatile memory according to the first configuration, the signal output circuit may be configured to output a signal associated with the first value when the drain current of the second transistor is greater than the drain current of the first transistor in the read operation, and to output a signal associated with the second value when the drain current of the first transistor is greater than the drain current of the second transistor (a second configuration).

[0128] In the non-volatile memory according to the second configuration, it may further include a program circuit configured to perform a program operation of increasing the gate threshold voltage of the second transistor by injecting hot carriers into the second transistor (third configuration).

[0129] In the non-volatile memory according to the third configuration, in the read operation executed before the program operation, the drain current of the second transistor is larger than the drain current of the first transistor, and in the read operation executed after the program operation, as the gate threshold voltage of the second transistor increases due to the program operation, the drain current of the first transistor is larger than the drain current of the second transistor (fourth configuration).

[0130] In the non-volatile memory according to the third or fourth configuration, the first and second transistors have the same structure as each other, and before the program operation, the first and second transistors have the same gate threshold voltage as each other (fifth configuration).

[0131] Another non-volatile memory according to the present disclosure includes a first transistor, a second transistor having a gate commonly connected to the gate of the first transistor, a resistor having a first end and a second end, the first end being connected to the source of the first transistor, a read voltage supply circuit configured to be able to supply a read voltage for turning on at least one of the first and second transistors, and a signal output circuit configured to be able to output a signal associated with a first value or a signal associated with a second value based on the drain currents of the first and second transistors in a read operation in which the read voltage is supplied by the read voltage supply circuit (sixth configuration).

[0132] In the non-volatile memory according to the sixth configuration, when the read operation is performed, the signal output circuit is configured to be able to output a signal associated with the first value when the drain current of the second transistor is larger than the drain current of the first transistor, and is configured to be able to output a signal associated with the second value when the drain current of the first transistor is larger than the drain current of the second transistor (seventh configuration).

[0133] The non-volatile memory according to the seventh configuration may further include a program circuit configured to be able to execute a program operation for increasing the gate threshold voltage of the second transistor by injecting hot carriers into the second transistor (eighth configuration).

[0134] In the non-volatile memory according to the eighth configuration, when the read operation is performed before the program operation, in the read operation, the drain current of the second transistor is larger than the drain current of the first transistor, and when the read operation is performed after the program operation, in the read operation, as the gate threshold voltage of the second transistor increases due to the program operation, the drain current of the first transistor is larger than the drain current of the second transistor (ninth configuration).

[0135] In the non-volatile memory according to the eighth or ninth configuration, the first and second transistors have the same structure as each other, and before the program operation, the first and second transistors have the same gate threshold voltage as each other (tenth configuration).

[0136] [Appendix 2] An explanation of the constant voltage source according to the present disclosure, which was exemplified in the second embodiment, will be added.

[0137] The constant voltage source according to the present disclosure (see FIG. 16) includes a differential pair composed of a first differential transistor (Ma) and a second differential transistor (Mb) whose sources are connected to each other and have different gate threshold voltages, a drain-side circuit (CM1) connected to the drains of the first and second differential transistors and outputting a current toward the drains of the first differential transistor and the second differential transistor, and a voltage output circuit (Mo) that generates an output voltage (Vout) corresponding to the gate voltage of the second differential transistor based on the drain voltage of the first differential transistor, and has a configuration W B1 has.

[0138] Configuration W B1 In the constant voltage source according to Configuration W, the first differential transistor is a depletion-type MOSFET, while the second differential transistor is an enhancement-type MOSFET. The gate of the first differential transistor is directly connected to the ground, while the gate of the second differential transistor is connected to the ground via a resistor (Rb), and has a configuration W B2 may be.

[0139] Configuration W B2 In the constant voltage source according to Configuration W, the voltage output circuit has an output transistor (Mo) that receives the drain voltage of the first differential transistor as a gate voltage, a predetermined DC voltage (Vdd) is applied to a series circuit including the output transistor and the resistor, and the output voltage is generated through the output transistor, and has a configuration W B3 may be.

[0140] Configuration W B1 ~W B3 In the constant voltage source according to any of ~W, the drain-side circuit is a drain-side current mirror circuit (CM1) that operates to output a uniform current toward the drains of the first differential transistor and the second differential transistor, and has a configuration W B4 may be.

[0141] The constant current source according to the present disclosure (see FIG. 19) includes a differential pair composed of a first differential transistor (Ma) and a second differential transistor (Mb) whose sources are connected to each other and have different gate threshold voltages, and drains of the first and second differential transistors, and a drain side circuit (CM1) that outputs a current toward the drain of the first differential transistor and the drain of the second differential transistor. Based on the drain voltage of the first differential transistor and the gate voltage of the second differential transistor, a constant current (I CC ) is generated in configuration W C1 and has.

[0142] Configuration W C1 In the constant current source according to, the first differential transistor is a depletion type MOSFET, while the second differential transistor is an enhancement type MOSFET. The gate of the first differential transistor is directly connected to the ground, while the gate of the second differential transistor is connected to the ground via a resistor. Configuration W C2 can be.

[0143] Configuration W C2 In the constant current source according to, a current mirror circuit (CM2) composed of a plurality of transistors that receive the drain voltage of the first differential transistor as a gate voltage is provided. The plurality of transistors include a first mirror transistor (Me) and a second mirror transistor (Mf). A predetermined DC voltage (Vdd) is applied to the series circuit including the first mirror transistor and the resistor, and the constant current is output through the second mirror transistor. Configuration W C3 can be.

[0144] Configuration W C1 ~W C3 In the constant current source according to any of, the drain side circuit is a drain side current mirror circuit (CM1) that operates to output a uniform current toward the drain of the first differential transistor and the drain of the second differential transistor. Configuration W C4 can be.

[0145] The comparator according to the present disclosure (see FIG. 21) includes a differential pair composed of a first differential transistor (Ma) and a second differential transistor (Mb) whose sources are connected to each other and have different gate threshold voltages, and is connected to the drains of the first and second differential transistors, and outputs a current toward the drain of the first differential transistor and the drain of the second differential transistor. And a drain-side circuit (CM1), and receives an input voltage (Vin) at the gate of the second differential transistor, and outputs a signal (CMPout) indicating a high / low relationship between the input voltage and a predetermined voltage. Configuration W D1 has.

[0146] Configuration W D1 In the comparator according to Configuration W, the first differential transistor is a depletion-type MOSFET, while the second differential transistor is an enhancement-type MOSFET, and the gate of the first differential transistor is connected to ground. Configuration W D2 may be.

[0147] Configuration W D2 In the comparator according to Configuration W, the predetermined voltage is determined based on the electrical characteristics of each differential transistor, and based on the drain voltage of the first differential transistor, the signal indicating the high / low relationship between the input voltage and the predetermined voltage is output. Configuration W D3 may be.

[0148] Configuration W D1 ~W D3 In the comparator according to any one of ~W, the drain-side circuit is a drain-side current mirror circuit (CM1) that operates to output a uniform current toward the drain of the first differential transistor and the drain of the second differential transistor. Configuration W D4 may be.

[0149] <<Modifications, etc.>> Embodiments of the present disclosure can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and of course, they can be changed to various numerical values.

[0150] Regarding any signal or voltage, the relationship between their high level and low level can be reversed from that described above in a form that does not impair the above gist.

[0151] The type of the channel of the FET (field effect transistor) shown in each embodiment is an example, and the configuration of the circuit including the FET can be modified so that the N-channel type FET is changed to a P-channel type FET, or the P-channel type FET is changed to an N-channel type FET.

[0152] Unless it causes inconvenience, any of the above transistors can be any type of transistor. For example, any transistor described as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor unless it causes inconvenience. Any transistor has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is a drain and the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector and the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector and the other is an emitter, and the control electrode is a base.

Description of Reference Numerals

[0153] 1 Storage circuit 10 Memory unit 20 Read voltage supply circuit 30 Signal output circuit 40 Program Circuit

Claims

1. A first transistor; a second transistor having a gate commonly connected to the gate of the first transistor; a resistor having a first end and a second end, the first end being connected to the source of the first transistor; a lead voltage supply circuit configured to supply a lead voltage for turning on at least one of the first and second transistors between the gate of the first transistor and the second end of the resistor and between the gate and the source of the second transistor; a signal output circuit configured to output a signal associated with a first value or a signal associated with a second value based on the drain currents of the first and second transistors in a lead operation in which the lead voltage is supplied by the lead voltage supply circuit; and a non-volatile memory.

2. In the lead operation, when the drain current of the second transistor is greater than the drain current of the first transistor, the signal output circuit outputs a signal associated with the first value, and when the drain current of the first transistor is greater than the drain current of the second transistor, the signal output circuit outputs a signal associated with the second value. The non-volatile memory according to claim 1.

3. The non-volatile memory according to claim 2, further comprising a program circuit configured to perform a program operation of increasing the gate threshold voltage of the second transistor by injecting hot carriers into the second transistor. The non-volatile memory according to claim 2.

4. In the lead operation executed before the program operation, the drain current of the second transistor is greater than the drain current of the first transistor. In the lead operation executed after the program operation, as the gate threshold voltage of the second transistor increases due to the program operation, the drain current of the first transistor is greater than the drain current of the second transistor. The non-volatile memory according to claim 3.

5. The first and second transistors have the same structure as each other. Before the program operation, the first and second transistors have the same gate threshold voltage as each other. The non-volatile memory according to claim 3 or 4.

6. A first transistor; a second transistor having a gate commonly connected to the gate of the first transistor; A resistor having a first end and a second end, with the first end connected to the source of the first transistor, A lead voltage supply circuit configured to supply a lead voltage for turning on at least one of the first and second transistors, A signal output circuit configured to output a signal associated with a first value or a signal associated with a second value based on the drain currents of the first and second transistors in a lead operation in which the lead voltage is supplied by the lead voltage supply circuit, A non-volatile memory.

7. When the lead operation is performed, the signal output circuit is configured to output a signal associated with the first value when the drain current of the second transistor is greater than the drain current of the first transistor, and is configured to output a signal associated with the second value when the drain current of the first transistor is greater than the drain current of the second transistor. The non-volatile memory according to claim 6.

8. The non-volatile memory further includes a program circuit configured to execute a program operation for increasing the gate threshold voltage of the second transistor by injecting hot carriers into the second transistor. The non-volatile memory according to claim 7.

9. When the lead operation is executed before the program operation, in the lead operation, the drain current of the second transistor is greater than the drain current of the first transistor. When the lead operation is executed after the program operation, in the lead operation, as the gate threshold voltage of the second transistor increases due to the program operation, the drain current of the first transistor is greater than the drain current of the second transistor. The non-volatile memory according to claim 8.

10. The first and second transistors have the same structure as each other. Before the program operation, the first and second transistors have the same gate threshold voltage as each other. The non-volatile memory according to claim 8 or 9.

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