Information processing apparatus and control method

Abstract

Reduce data corruption in the SSD and guarantee the data retention period. 【Solution means】The information processing apparatus 1 includes a solid state drive (SSD) including a nonvolatile memory unit that is electrically rewritable and is configured by a plurality of bit cells that store data of a plurality of bits in one memory cell, and a main control unit that executes processing based on the data stored in the SSD. The SSD includes a memory control unit 420 that controls access to the nonvolatile memory unit. When storing data of a plurality of bits in the plurality of bit cells, if the number of rewrite times executed on the plurality of bit cells is equal to or greater than a threshold number of times, the memory control unit stores the data of the plurality of bits in a high-quality memory mode in which the variation width of the threshold voltage is narrower than that in the normal memory mode.

Description

Technical Field

[0001] The present invention relates to an information processing apparatus and a control method.

Background Art

[0002] In recent years, among information processing apparatuses such as personal computers, those equipped with a solid state drive (SSD) as a storage device instead of a hard disk drive (HDD) have become widespread (see, for example, Patent Document 1). In addition, in order to increase the capacity of SSDs, there are known SSDs equipped with flash memories using memory cells capable of storing multiple bits in one memory cell (hereinafter referred to as multi-bit cells), such as multi-level cells (MLC), triple-level cells (TLC), and quad-level cells (QLC).

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in conventional information processing apparatuses, while the use of multi-bit cells enables an increase in the capacity of SSDs, the data retention (data holding period) tends to be shortened. In addition, the more the number of rewrite cycles, which is the cycle of data erasure and writing (PE cycle (Program and Erase Cycle)), of multi-bit cells increases, the shorter the data retention (data holding period) tends to be. Therefore, in conventional information processing apparatuses, for example, when a user uses it for a long period of time or when the user is a heavy user who rewrites a large amount of data, the number of rewrite cycles increases, so there is a possibility that the data retention (data holding period) cannot be guaranteed.

[0005] The present invention has been made to solve the above problems, and an object thereof is to provide an information processing apparatus and a control method capable of reducing data corruption in an SSD and guaranteeing a data retention period.

Means for Solving the Problems

[0006] To solve the above problems, one aspect of the present invention includes a solid state drive (SSD) including a non-volatile memory unit that is electrically rewritable and is composed of a plurality of multi-bit cells that store a plurality of bits of data in one memory cell, and a main control unit that executes processing based on data stored in the SSD. The SSD is a memory control unit that controls access to the non-volatile memory unit. When storing the plurality of bits of data in the plurality of multi-bit cells, if the number of rewrite times executed on the plurality of multi-bit cells is equal to or greater than a threshold number of times, the memory control unit stores the plurality of bits of data in a high-quality memory mode in which the variation width of the threshold voltage is narrower than that in the normal memory mode. When the high-quality memory mode is enabled, the memory control unit notifies the main control unit that the high-quality memory mode has been enabled, and the main control unit outputs a notification indicating that the high-quality memory mode has been enabled to the user. An information processing apparatus.

[0007] Also, in one aspect of the present invention, in the above information processing apparatus, the SSD includes a rewrite count storage unit that stores the rewrite count in units of blocks that erase the data of the plurality of multi-bit cells at once. When storing the plurality of bits of data, the memory control unit acquires the rewrite count corresponding to the block that stores the plurality of bits of data from the rewrite count storage unit, and if the acquired rewrite count is equal to or greater than the threshold number of times, the memory control unit may store the plurality of bits of data in the high-quality memory mode.

[0008] Also, in one aspect of the present invention, in the above information processing apparatus, in the high-quality storage mode, the storage control unit applies a voltage for storing data to the plurality of bit cells for a predetermined period obtained by dividing the application period, and after the application process, a confirmation process for checking whether the threshold voltage is within the variation range of the threshold voltage, and a repetition process for repeating the application process and the confirmation process until the threshold voltage is within the variation range of the threshold voltage may be executed.

[0010] Also, in one aspect of the present invention, in the above information processing apparatus, when the high-quality storage mode is enabled in a predetermined ratio or more of the storage capacity of the SSD, the main control unit may cause the display unit to display the notification.

[0011] Also, in one aspect of the present invention, in the above information processing apparatus, as the notification, the main control unit may cause the display unit to display information indicating a ratio of the SSD's storage capacity in which the high-quality storage mode is enabled.

[0012] Also, in one aspect of the present invention, there is provided a control method for an information processing apparatus including a solid state drive (SSD) including a non-volatile storage unit configured by a plurality of bit cells that store a plurality of bits of data in one memory cell and that is electrically rewritable, and a main control unit that executes processing based on data stored in the SSD. The method includes a step of controlling access to the non-volatile storage unit by a storage control unit of the SSD. When storing the plurality of bits of data in the plurality of bit cells, if the number of rewrite operations performed on the plurality of bit cells is equal to or greater than a threshold number, the plurality of bits of data are stored in a high-quality storage mode in which the variation range of the threshold voltage is narrower than that in a normal storage mode. The step in which the memory control unit notifies the main control unit that the high-quality memory mode has been enabled when the high-quality memory mode is enabled, and the step in which the main control unit outputs a notification indicating that the high-quality memory mode has been enabled to the user. The control method includes the above step.

Advantages of the Invention

[0013] According to the above aspect of the present invention, it is possible to reduce data corruption in the SSD and guarantee the data retention period.

Brief Description of the Drawings

[0014]

Figure 1

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Embodiments for Carrying Out the Invention

[0015] Hereinafter, an information processing apparatus and a control method according to an embodiment of the present invention will be described with reference to the drawings.

[0016] FIG. 1 is a diagram showing an example of the main hardware configuration of the information processing apparatus 1 and the SSD 40 according to the first embodiment. As shown in FIG. 1, the information processing apparatus 1 is, for example, a notebook personal computer, and includes a CPU 11, a main memory 12, a video subsystem 13, a display unit 14, a chipset 21, a BIOS memory 22, an embedded controller 31, an input unit 32, a power supply circuit 33, and an SSD 40.

[0017] The CPU (Central Processing Unit) 11 executes various arithmetic processes under program control and controls the entire information processing apparatus 1.

[0018] The main memory 12 is a writable memory that is used as a loading area for the execution program of the CPU 11 or as a working area for writing the processing data of the execution program. The main memory 12 is composed of, for example, a plurality of DRAM (Dynamic Random Access Memory) chips. This execution program includes an OS (Operating System), various drivers for operating peripheral devices in hardware, various services / utilities, application programs, and the like.

[0019] The video subsystem 13 is a subsystem for realizing functions related to image display and includes a video controller. This video controller processes the drawing commands from the CPU 11, writes the processed drawing information into the video memory, reads out this drawing information from the video memory, and outputs it to the display unit 14 as drawing data (display data).

[0020] The display unit 14 is, for example, a liquid crystal display, and displays a display screen based on the drawing data (display data) output from the video subsystem 13.

[0021] The chipset 21 includes controllers such as USB (Universal Serial Bus), Serial ATA (AT Attachment), SPI (Serial Peripheral Interface) bus, PCI (Peripheral Component Interconnect) bus, PCI-Express bus, and LPC (Low Pin Count) bus, and a plurality of devices are connected thereto. In FIG. 1, as an example of devices, a BIOS memory 22 and an SSD 40 are connected to the chipset 21. In this embodiment, the CPU 11 and the chipset 21 correspond to the main control unit 10.

[0022] The BIOS (Basic Input Output System) memory 22 is composed of an electrically rewritable non-volatile memory such as an EEPROM (Electrically Erasable Programmable Read Only Memory) or a flash ROM (flash memory), for example. The BIOS memory 22 stores system firmware for controlling the BIOS, the embedded controller 31, and the like.

[0023] The embedded controller 31 is a one-chip microcomputer that monitors and controls various devices (peripheral devices, sensors, etc.) regardless of the system state of the information processing apparatus 1. Further, the embedded controller 31 has a power management function for controlling the power circuit 33. The embedded controller 31 is composed of a CPU, a ROM, a RAM, etc., which are not shown, and includes a plurality of channels of A / D input terminals, D / A output terminals, timers, and digital input / output terminals. For example, an input unit 32 and a power circuit 33 are connected to the embedded controller 31 via those input / output terminals, and the embedded controller 31 controls the operations thereof.

[0024] The input unit 32 is, for example, an input device such as a keyboard or a pointing device such as a touch pad.

[0025] The power supply circuit 33 includes, for example, a DC / DC converter, a charge / discharge unit, an AC / DC adapter, etc., and converts a DC voltage supplied from an external power supply via, for example, an AC / DC adapter or from a battery into a plurality of voltages necessary for operating the information processing apparatus 1. Further, the power supply circuit 33 supplies power to each part of the information processing apparatus 1 based on control from the embedded controller 31.

[0026] The SSD (Solid State Drive) 40 is a memory drive device having a rewritable non-volatile memory, and stores an OS, various drivers, various services / utilities, application programs, and various data. The information processing apparatus 1 executes various information processes using the data stored in the SSD 40. The SSD 40 is connected to the chipset 21, for example, via Serial ATA or a PCI-Express bus. Further, the SSD 40 includes a plurality of flash memories 41 and an SSD controller 42.

[0027] The flash memory 41 is, for example, a NAND flash memory. The flash memory 41 includes, for example, a memory cell of a floating gate type, a memory cell of a charge trap type that stores data by trapping electrons in a charge trap layer without a floating gate, etc. Further, the memory cells of the flash memory 41 are multi-bit cells that store data of a plurality of bits in one memory cell, and are, for example, MLC (Multiple Level Cell), TLC (Triple Level Cell), and QLC (Quad Level Cell). Here, the multi-bit cell is a memory cell capable of storing the equivalent of a plurality of bits in one memory cell by providing a plurality of data write thresholds.

[0028] The SSD controller 42 is a processor including, for example, a CPU, a ROM, a RAM, etc. (not shown), and comprehensively controls the SSD 40. The SSD controller 42 executes, for example, control processing of a host interface (host I / F) with the chipset 21, control processing of a memory interface (memory I / F) with the flash memory 41, data management processing of the flash memory 41, and the like.

[0029] The SSD controller 42 controls, for example, a storage process (a write process for writing data) for storing data in a plurality of bit cells and a read process for reading data from the plurality of bit cells.

[0030] Next, with reference to FIG. 2, the functional configuration of the information processing apparatus 1 according to the present embodiment will be described. FIG. 2 is a functional block diagram showing an example of the functional configuration of the information processing apparatus 1 according to the present embodiment.

[0031] As shown in FIG. 2, the information processing apparatus 1 includes a main control unit 10, an SSD 40, and a storage unit 50. The SSD 40 includes an SSD storage unit 410 and a memory control unit 420.

[0032] The SSD storage unit 410 is a storage unit realized by, for example, the flash memory 41 of the SSD 40, and includes a management information storage unit 411, a mode information storage unit 412, and a data storage unit 413.

[0033] The management information storage unit 411 is a storage unit realized by a memory such as a RAM (not shown) built in the flash memory 41 or the SSD controller 42, and stores the management information of the SSD 40. The management information storage unit 411 stores, for example, conversion table information between the physical address and the logical address (e.g., LBA: Logical Block Addressing (logical location information)) of the flash memory 41, management information of the free area and the used area of the flash memory 41, and the number of rewrite times of each block of the flash memory 41, etc. Here, a block is a capacity unit for erasing data of a plurality of bit cells in the flash memory 41 at once. The flash memory 41 can erase data in block units and rewrite the data.

[0034] In addition, the management information storage unit 411 stores mode information indicating the write mode (memory mode) to a plurality of bit cells together with the number of rewrite times in block units. In the present embodiment, the write mode (memory mode) includes a normal mode (normal memory mode) and a protection mode (high-quality memory mode), and the details will be described later.

[0035] The mode information storage unit 412 is a storage unit realized by a memory such as a RAM (not shown) built in the SSD controller 42, and stores write control information for the normal mode (normal memory mode) and the protection mode (high-quality memory mode). The write control information includes, for example, the application period (application time) of the divided write voltage, the variation range (allowable range) of Vth, etc.

[0036] Note that the normal mode (normal memory mode) is a mode in which the variation range (allowable range) of Vth is wider than that of the protection mode (high-quality memory mode), and the write time required for writing is short. Also, the protection mode is a mode in which the variation range (allowable range) of Vth is narrower than that of the normal memory mode, and the write time required for writing is long.

[0037] The data storage unit 413 is a storage unit realized by, for example, the flash memory 41, and stores various data. The data storage unit 413 stores, for example, various data of the information processing apparatus 1. The data storage unit 413 is accessed from the main control unit 10 using the LBA set by the management processing unit 421 described later.

[0038] The memory control unit 420 (an example of a storage control unit) is a functional unit realized by, for example, causing a CPU (not shown) of the SSD controller 42 to execute a program stored in a ROM (not shown). The memory control unit 420 controls access to the SSD storage unit 410.

[0039] When storing multi-bit data in a plurality of bit cells of the SSD storage unit 410, for example, the memory control unit 420 executes a storage process capable of changing the variation width of Vth (threshold voltage). When the number of rewrite times executed on a plurality of bit cells is equal to or greater than a threshold number of times when storing multi-bit data in the plurality of bit cells, the memory control unit 420 stores multi-bit data in a protection mode (high-quality storage mode) in which the variation width of the threshold voltage is narrower than that in the normal mode (normal storage mode).

[0040] When storing multi-bit data, for example, the memory control unit 420 acquires the number of rewrite times corresponding to the block in which the multi-bit data is to be stored from the management information storage unit 411, and when the acquired number of rewrite times is equal to or greater than the threshold number of times, stores the multi-bit data in the protection mode.

[0041] Further, when the protection mode becomes effective, the memory control unit 420 notifies the main control unit 10 that the protection mode has become effective. The memory control unit 420 includes a management processing unit 421, a write processing unit 422, and a read processing unit 423.

[0042] The management processing unit 421 manages the free area and the used area of the flash memory 41, and using the conversion table in the management information storage unit 411, converts the LBA received from the main control unit 10 into a physical address, and controls access to the flash memory 41.

[0043] Also, when the management processing unit 421 receives a write request from the main control unit 10, it updates the number of rewrite times of the block corresponding to the LBA, and stores it in the management information storage unit 411. Further, when the number of rewrite times reaches a preset threshold number of times, the management processing unit 421 changes the write mode for the block from the normal mode to the protection mode, and notifies the main control unit 10 that the protection mode has become effective.

[0044] The write processing unit 422 executes data storage processing (write processing) to the plurality of bit cells of the SSD storage unit 410. The write processing unit 422 executes, for example, data write processing to the SSD storage unit 410 in block units. The write processing unit 422 acquires the mode information corresponding to the block of the LBA for which the write processing is to be performed from the management information storage unit 411, and when the mode information is the normal mode, uses the control information of the normal mode stored in the mode information storage unit 412 to execute the data write processing. Also, when the mode information is the protection mode, the write processing unit 422 uses the control information of the protection mode stored in the mode information storage unit 412 to execute the data write processing.

[0045] Note that since the protection mode is permitted when the number of rewrite times corresponding to the block is equal to or more than the threshold number of times, the write processing unit 422 executes the data write processing using the control information of the protection mode when the number of rewrite times is equal to or more than the threshold number of times.

[0046] In the protection mode, the writing processing unit 422 executes an application process of applying a voltage for storing data in a plurality of bit cells for a predetermined period obtained by dividing the application period, and after the application process, executes a confirmation process of checking whether or not the Vth is within the variation range of the Vth. The writing processing unit 422 executes a repetition process of repeating the application process and the confirmation process until the Vth is within the variation range of the Vth in the protection mode.

[0047] The reading processing unit 423 reads the data of the designated LBA designated from the main control unit 10 based on the management information stored in the management information storage unit 411, and outputs it to the main control unit 10.

[0048] Next, with reference to FIGS. 3 and 4, the difference in the storage process for a plurality of bit cells between the above-described normal mode and the protection mode will be described. FIG. 3 is a diagram showing an example of the Vth distribution in the normal mode of the SSD 40 of the information processing apparatus 1 according to the present embodiment.

[0049] In FIG. 3, the horizontal axis of the graph indicates the Vth when the storage process (writing process) corresponding to each data is performed in the normal mode, and the vertical axis indicates the number of cells. In FIG. 3, the waveform W11 indicates the Vth distribution when the data "001" is stored in a plurality of bit cells in the normal mode, and the waveform W12 indicates the Vth distribution when the data "010" is stored in a plurality of bit cells in the normal mode. The waveform W13 indicates the Vth distribution when the data "011" is stored in a plurality of bit cells in the normal mode, and the waveform W14 indicates the Vth distribution when the data "100" is stored in a plurality of bit cells in the normal mode.

[0050] In the normal mode, the writing processing unit 422 executes a data storage process (writing process) with a variation range D1 of the Vth as shown in the waveforms W11 to W14 of FIG. 3 according to the write data (stored data).

[0051] Further, when reading data from a plurality of bit cells, the read processing unit 423 determines the data as “001” when Vth is between the voltage Vt1 and the voltage Vt2, and determines the data as “010” when Vth is between the voltage Vt2 and the voltage Vt3. Further, when reading data from a plurality of bit cells, the read processing unit 423 determines the data as “011” when Vth is between the voltage Vt3 and the voltage Vt4, and determines the data as “100” when Vth is between the voltage Vt4 and the voltage Vt5. Note that the combination of Vth and data is not limited to the above example, and various combinations are possible, and other combinations may be used.

[0052] Further, the waveform W13E shows an example in which Vth has moved downward due to deterioration of a plurality of bit cells or the passage of time since data writing. In this case, in some of the plurality of bit cells, Vth is lower than the voltage Vt3, so data corruption occurs.

[0053] FIG. 4 is a diagram showing an example of the Vth distribution in the protection mode of the SSD 40 of the information processing apparatus 1 according to the present embodiment.

[0054] In FIG. 4, the horizontal axis of the graph indicates Vth when storage processing (writing processing) corresponding to each data is performed in the high-quality storage mode, and the vertical axis indicates the number of cells. In FIG. 4, the waveform W21 shows the Vth distribution when data “001” is stored in a plurality of bit cells in the protection mode, and the waveform W22 shows the Vth distribution when data “010” is stored in a plurality of bit cells in the protection mode. Further, the waveform W23 shows the Vth distribution when data “011” is stored in a plurality of bit cells in the protection mode, and the waveform W24 shows the Vth distribution when data “100” is stored in a plurality of bit cells in the protection mode.

[0055] The writing processing unit 422 executes the data storage process in a distribution having a variation width D2 of Vth as shown in waveforms W21 to W24 in FIG. 4 according to the write data (stored data) depending on the protection mode. Note that the variation width D2 of Vth in the protection mode is narrower than the variation width D1 of Vth in the normal mode.

[0056] Returning to the description of FIG. 2 again, the storage unit 50 is a storage unit realized by, for example, the main memory 12 or the SSD 40, and stores various information used by the information processing apparatus 1. The storage unit 50 includes a notification information storage unit 51.

[0057] The notification information storage unit 51 is a storage unit realized by, for example, the main memory 12, and stores notification information indicating that the protection mode has become effective. The notification information may include information indicating the ratio of the storage capacity of the SSD 40 in which the protection mode has become effective.

[0058] The main control unit 10 is a functional unit realized by the CPU 11 and the chipset 21 executing a program stored in the main memory 12, and executes various processes based on the OS. The main control unit 10 executes various processes based on, for example, data stored in the SSD 40. The main control unit 10 includes an AP processing unit 101, an SSD device driver unit 102, and an SSD management processing unit 103.

[0059] The AP processing unit 101 is a functional unit that processes application programs executed on the OS. The AP processing unit 101 performs write processing and read processing of various application data in, for example, the data storage unit 413 of the SSD 40. When accessing the data storage unit 413, the AP processing unit 101 accesses the data storage unit 413 using the LBA. Note that the AP processing unit 101 accesses the SSD 40 via the SSD device driver unit 102 described later.

[0060] The SSD device driver unit 102 is a functional unit that implements a device driver for accessing the SSD 40. The SSD device driver unit 102 transmits a write request to store (write) data of a specified LBA to the SSD 40, and stores the data in the specified LBA. Also, the SSD device driver unit 102 transmits a read request to read data of a specified LBA to the SSD 40, and reads the data of the specified LBA.

[0061] The SSD management processing unit 103 is a functional unit realized by, for example, executing a resident program that manages the SSD 40 executed on the OS. The SSD management processing unit 103 outputs, to the user, a notification indicating that the protection mode has become effective, for example, when receiving a notification indicating that the protection mode has become effective from the SSD 40. The SSD management processing unit 103 causes the display unit 14 to display the notification information stored in the notification information storage unit 51, for example.

[0062] Note that the SSD management processing unit 103 may cause the display unit 14 to display a notification when the protection mode becomes effective in a predetermined ratio or more of the storage capacity of the SSD 40. Also, in this case, the SSD management processing unit 103 may cause the display unit 14 to display, as the notification, information indicating the ratio of the storage capacity of the SSD 40 in which the protection mode has become effective.

[0063] Next, with reference to the drawings, the operation of the information processing apparatus 1 according to the present embodiment will be described. FIG. 5 is a flowchart showing an example of the write mode switching process of the SSD 40 in the present embodiment.

[0064] As shown in FIG. 5, the memory control unit 420 of the SSD 40 first determines whether a data write request has been received (step S101). The management processing unit 421 of the memory control unit 420 determines whether a data write request has been received from the main control unit 10. When the management processing unit 421 receives a data write request from the main control unit 10 (step S101: YES), the process proceeds to step S102. Also, when the management processing unit 421 has not received a data write request from the main control unit 10 (step S101: NO), the process returns to step S101.

[0065] In step S102, the management processing unit 421 updates the rewrite count of the block corresponding to the data write position. For example, when performing an erase process in a block corresponding to the designated LBA specified by a data write request, the management processing unit 421 acquires the rewrite count of the block from the management information storage unit 411, adds "1" to the rewrite count, and stores and updates it in the management information storage unit 411.

[0066] Next, the management processing unit 421 determines whether the rewrite count of the block has reached the threshold count (step S103). When the updated rewrite count has reached the threshold count (rewrite count = threshold count) (step S103: YES), the management processing unit 421 proceeds to step S104. Also, when the updated rewrite count has not reached the threshold count (is less than or equal to the threshold count) (step S103: NO), the management processing unit 421 proceeds to step S106.

[0067] In step S104, the management processing unit 421 sets it from the normal mode to the protection mode. The management processing unit 421 changes the mode information corresponding to the block in the management information storage unit 411 from the normal mode to the protection mode.

[0068] Next, the management processing unit 421 notifies the OS that the block for writing data has entered the protection mode (step S105). The management processing unit 421 transmits a notification indicating that the block for writing data has entered the protection mode to the main control unit 10. After the processing of step S105, the management processing unit 421 returns the process to step S101.

[0069] Also, in step S106, the management processing unit 421 maintains the normal mode. After the processing of step S106, the management processing unit 421 returns the process to step S101.

[0070] Next, with reference to FIG. 6, the write process of the SSD 40 will be described. FIG. 6 is a flowchart showing an example of the write process of the SSD 40 in the present embodiment.

[0071] As shown in FIG. 6, the write processing unit 422 of the memory control unit 420 determines whether a write request for data has been received (step S201). When the write processing unit 422 receives a write request for data from the main control unit 10 (step S201: YES), the process proceeds to step S202. Also, when the write processing unit 422 has not received a write request for data from the main control unit 10 (step S201: NO), the process returns to step S201.

[0072] In step S202, the write processing unit 422 determines whether the corresponding block has been erased. When the block corresponding to the specified LBA has been erased (step S202: YES), the write processing unit 422 proceeds to step S204. Also, when the block corresponding to the specified LBA has not been erased (step S202: NO), the write processing unit 422 proceeds to step S203.

[0073] In step S203, the write processing unit 422 executes an erase process on the corresponding block. The write processing unit 422 executes the erase process in block units.

[0074] Also, in step S204, the writing processing unit 422 determines whether the block to which data is to be written is set to the protection mode. The writing processing unit 422 checks the mode information corresponding to the block in the management information storage unit 411, and determines whether the corresponding block is set to the protection mode. When the corresponding block is set to the protection mode (step S204: YES), the writing processing unit 422 advances the process to step S205. Also, when the corresponding block is not set to the protection mode (step S204: NO), the writing processing unit 422 advances the process to step S206.

[0075] In step S205, the data writing process is executed in the protection mode. The writing processing unit 422 acquires the setting information of the protection mode from the mode information storage unit 412, and executes the storage process (writing process) of the protection mode as shown in FIG. 4 according to the setting information. After the process of step S205, the writing processing unit 422 returns the process to step S201.

[0076] In step S206, the data writing process is executed in the normal mode. The writing processing unit 422 acquires the setting information of the normal mode from the mode information storage unit 412, and executes the storage process (writing process) of the normal mode as shown in FIG. 3 according to the setting information. After the process of step S206, the writing processing unit 422 returns the process to step S201.

[0077] Next, with reference to FIG. 7, the details of the storage process in the protection mode, which is the process of step S205 described above, will be described. FIG. 7 is a flowchart showing an example of the storage process in the protection mode by the information processing apparatus 1 according to the present embodiment.

[0078] As shown in FIG. 7, the write processing unit 422 of the memory control unit 420 applies a write voltage for a set predetermined period to write data into the memory cells (step S301). The write processing unit 422 applies a write voltage to a plurality of bit cells of the designated LBA for the application period (predetermined period) of the protection mode stored in the mode information storage unit 412.

[0079] Next, the write processing unit 422 reads the data to detect Vth (step S302). The write processing unit 422 executes a read confirmation to detect the written Vth.

[0080] Next, the write processing unit 422 determines whether the detected Vth is within the range of the variation width of Vth corresponding to the data (step S303). The write processing unit 422 determines whether the detected Vth is within the range of the variation width of Vth corresponding to the written data (within the allowable range) (confirmation process). When the detected Vth is within the range of the variation width of Vth corresponding to the written data (step S303: YES), the write processing unit 422 ends the storage process (write process). Also, when the detected Vth is not within the range of the variation width of Vth corresponding to the written data (step S303: NO), the write processing unit 422 returns the process to step S301.

[0081] In this way, the write processing unit 422 repeats the processes of step S301 and step S302 until the Vth is within the range of the variation width of Vth corresponding to the written data. As a result, the write processing unit 422 executes the writing of the variation width D2 of Vth as shown in FIG. 4 described above.

[0082] Note that in the normal mode, the write processing unit 422 may widen the predetermined period and the range of the variation width of Vth more than in the protection mode and execute the same process as shown in FIG. 8 described above. Also, in the normal mode, the write processing unit 422 may execute the storage process (write process) with a preset application period of the write voltage once.

[0083] Next, with reference to FIGS. 8 and 9, notification processing by the information processing apparatus according to the embodiment will be described. FIG. 8 is a flowchart showing an example of notification processing by the information processing apparatus 1 according to the present embodiment.

[0084] As shown in FIG. 8, the main control unit 10 of the information processing apparatus 1 determines whether it has received a notification from the SSD 40 (step S401). Here, the notification indicates that the block for writing data has entered the protection mode. When the SSD management processing unit 103 of the main control unit 10 receives a notification indicating that the protection mode has been entered (step S401: YES), the process proceeds to step S402. Also, when the SSD management processing unit 103 has not received a notification indicating that the protection mode has been entered (step S401: NO), the process returns to step S401.

[0085] In step S402, the SSD management processing unit 103 causes the display unit 14 to display information indicating that the protection mode has been entered. The SSD management processing unit 103, for example, acquires notification information indicating that the protection mode has been entered, which is stored in the notification information storage unit 51, and causes the display unit 14 to display the notification information. After the processing in step S402, the SSD management processing unit 103 returns the process to step S401.

[0086] Further, FIG. 9 is a flowchart showing another example of notification processing by the information processing apparatus 1 according to the present embodiment.

[0087] As shown in FIG. 9, the main control unit 10 of the information processing apparatus 1 determines whether it has received a notification from the SSD 40 (step S501). Here, the notification is a notification indicating that the block for writing data has entered the protection mode, similar to FIG. 8 described above. When the SSD management processing unit 103 of the main control unit 10 receives a notification indicating that the protection mode has been entered (step S501: YES), the process proceeds to step S502. Also, when the SSD management processing unit 103 has not received a notification indicating that the protection mode has been entered (step S501: NO), the process returns to step S501.

[0088] In step S502, the SSD management processing unit 103 totals the ratio of the blocks that have entered the protection mode. The SSD management processing unit 103 totals the ratio of the blocks that have entered the protection mode out of the storage capacity of the SSD 40.

[0089] Next, the SSD management processing unit 103 determines whether the ratio of the blocks that have entered the protection mode is equal to or greater than a predetermined ratio (step S503). When the ratio of the blocks that have entered the protection mode is equal to or greater than the predetermined ratio (step S503: YES), the SSD management processing unit 103 advances the process to step S504. Also, when the ratio of the blocks that have entered the protection mode is less than the predetermined ratio (step S503: NO), the SSD management processing unit 103 returns the process to step S501.

[0090] In step S504, the SSD management processing unit 103 causes the display unit 14 to display information indicating the ratio of the blocks that have entered the protection mode. The SSD management processing unit 103 may acquire the notification information indicating that the protection mode has been entered, which is stored in the notification information storage unit 51, and cause the display unit 14 to display it together with the information indicating the ratio of the blocks. After the process of step S504, the SSD management processing unit 103 returns the process to step S501.

[0091] As described above, the information processing apparatus 1 according to the present embodiment includes an SSD 40 and a main control unit 10. The SSD 40 is composed of a plurality of bit cells that store multiple bits of data in one memory cell, and includes an SSD storage unit 410 (non-volatile storage unit) that can be electrically rewritten. The main control unit 10 executes processing based on the data stored in the SSD 40. The SSD 40 includes a memory control unit 420 (storage control unit) that controls access to the SSD storage unit 410. When storing multiple bits of data in the plurality of bit cells, the memory control unit 420 stores the multiple bits of data in a protection mode (high-quality storage mode) in which the variation width of the threshold voltage is narrower than that in the normal mode (normal storage mode) when the number of rewrite times executed on the plurality of bit cells is equal to or greater than the threshold number of times.

[0092] Thereby, when the number of rewrite times is equal to or greater than the threshold number of times, the information processing apparatus 1 according to the present embodiment stores multiple bits of data in a protection mode (high-quality storage mode) in which the variation width of the threshold voltage is narrow, so that data corruption of the SSD 40 can be reduced and the data retention period can be guaranteed. The information processing apparatus 1 according to the present embodiment can guarantee a long data retention period of three to five years, for example, in a state where the information processing apparatus 1 is powered off (a state where power is not supplied to the SSD 40), even when the user has used it for a long time or when the user is a heavy user who rewrites a large amount of data, by switching to the protection mode.

[0093] Also, in the present embodiment, the SSD 40 includes a management information storage unit 411 (rewrite count storage unit) that stores the number of rewrite times in units of blocks that erase the data of the plurality of bit cells at once. When storing multiple bits of data, the memory control unit 420 acquires the number of rewrite times corresponding to the block in which the multiple bits of data are stored from the management information storage unit 411, and when the acquired number of rewrite times is equal to or greater than the threshold number of times, stores the multiple bits of data in the protection mode.

[0094] As a result, the information processing apparatus 1 according to the present embodiment can appropriately change to the protection mode with a simple configuration in order to manage the number of write cycles in units of blocks that erase data of a plurality of bit cells at once. Therefore, the information processing apparatus 1 according to the present embodiment can guarantee a long data retention period with a simple configuration.

[0095] Also, in the present embodiment, the memory control unit 420 executes an application process, a confirmation process, and a repeating process that repeats in the protection mode (high-quality memory mode). In the application process, the memory control unit 420 applies a voltage for storing data to a plurality of bit cells for a predetermined period obtained by dividing the application period. In the confirmation process, the memory control unit 420 confirms whether or not the Vth is within the variation range of the Vth after the application process. In the repeating process, the memory control unit 420 repeats the application process and the confirmation process until the Vth is within the variation range of the Vth.

[0096] As a result, the information processing apparatus 1 according to the present embodiment can perform a storage process in the protection mode (high-quality memory mode) in which the variation range of the Vth is narrowed by a simple method, because the information processing apparatus 1 divides a plurality of bit cells into predetermined periods, applies a voltage for storing data, and repeats while confirming the Vth.

[0097] Also, in the present embodiment, when the protection mode becomes effective, the memory control unit 420 notifies the main control unit 10 that the protection mode has become effective. The main control unit 10 outputs a notification indicating that the protection mode has become effective to the user.

[0098] As a result, the user of the information processing apparatus 1 according to the present embodiment can know that the protection mode has become effective, and can appropriately consider replacing the SSD 40 or the like.

[0099] Also, in the present embodiment, when the protection mode is enabled in a predetermined ratio or more of the storage capacity of the SSD 40, the main control unit 10 causes the display unit 14 to display a notification.

[0100] Thereby, the information processing apparatus 1 according to the present embodiment can cause the user to recognize the degree of deterioration of the SSD 40 and can prompt the user to replace the SSD 40.

[0101] Also, in the present embodiment, the main control unit 10 causes the display unit 14 to display, as a notification, information indicating the ratio of the storage capacity of the SSD 40 in which the protection mode is enabled.

[0102] Thereby, in the information processing apparatus 1 according to the present embodiment, the main control unit 10 can cause the user to quantitatively recognize the degree of deterioration of the SSD 40 by causing the display unit 14 to display information indicating the ratio of the protection mode being enabled, and can prompt the user to replace the SSD 40.

[0103] Also, the control method according to the present embodiment is a control method of the information processing apparatus 1 including the SSD 40 and the main control unit 10, and includes a writing process step. The SSD 40 is composed of a plurality of bit cells that store data of a plurality of bits in one memory cell, and includes an SSD storage unit 410 that can be electrically rewritten. The main control unit 10 executes processing based on the data stored in the SSD 40. The memory control unit 420 of the SSD 40 controls access to the SSD storage unit 410. In the writing process step, when the number of rewrite times executed on the plurality of bit cells is equal to or greater than a threshold number of times when the memory control unit 420 stores data of a plurality of bits in the plurality of bit cells, the data of the plurality of bits is stored in a protection mode in which the variation range of the threshold voltage is narrower than that in the normal mode. Thereby, the control method according to the present embodiment has the same effect as the information processing apparatus 1 described above, can reduce data corruption of the SSD, and can guarantee the data retention period.

[0104] Note that the present invention is not limited to the above-described embodiments, and can be modified without departing from the spirit of the present invention. In the power supply system of the present invention, For example, in the above embodiment, an example in which the information processing apparatus 1 is a notebook personal computer (mobile computer) has been described. However, the present invention is not limited thereto, and for example, other information processing apparatuses such as a desktop personal computer or a tablet terminal device may be used.

[0105] Also, in the above embodiment, an example in which the information processing apparatus 1 switches between two types of writing processes (storage processes), namely, a normal mode and a protection mode, has been described. However, depending on the application, three or more storage modes with different Vth variations may be provided and switched for use.

[0106] Also, in the above embodiment, part of the processing of the memory control unit 420 of the SSD 40 may be performed by the information processing apparatus 1 (for example, the main control unit 10 or the embedded controller 31). Also, part of the processing of the main control unit 10 may be executed by the memory control unit 420. For example, in the above-described embodiment, an example in which the main control unit 10 totals the ratio of enabling the protection mode has been described. However, the present invention is not limited thereto, and the memory control unit 420 may total and notify the main control unit 10.

[0107] Also, in the above embodiment, an example in which the plurality of bit cells are any of MLC, TLC, and QLC has been described. However, the present invention is not limited thereto, and other plurality of bit cells may be used. Also, the degradation of the cell is not limited to the plurality of bit cells, and the same occurs even in a single bit cell (SLC: Single Level Cell). Therefore, the present invention may be applied to a single bit cell (SLC).

[0108] In the above-described embodiment, the information processing apparatus 1 has been described as a configuration example of a personal computer including an embedded controller 31. However, the present invention is not limited to this, and a configuration without the embedded controller 31 may also be used. Further, the OS of the information processing apparatus 1 is not limited to Windows (registered trademark), and may be applied to other OSs such as Android (registered trademark) and iOS (registered trademark).

[0109] Each configuration included in the above-described information processing apparatus 1 and SSD 40 has a computer system inside. Then, a program for realizing the functions of each configuration included in the above-described information processing apparatus 1 and SSD 40 is recorded on a computer-readable recording medium, and the program recorded on this recording medium is read into the computer system and executed, whereby the processing in each configuration included in the above-described information processing apparatus 1 and SSD 40 may be performed. Here, "reading and executing the program recorded on the recording medium into the computer system" includes installing the program in the computer system. The "computer system" referred to here is assumed to include hardware such as an OS and peripheral devices.

[0110] Further, the "computer system" may include a plurality of computer devices connected via a network including a communication line such as the Internet, WAN, LAN, or dedicated line. The "computer-readable recording medium" refers to a portable medium such as a flexible disk, magneto-optical disk, ROM, or CD-ROM, or a storage device such as a hard disk built in the computer system. As described above, the recording medium storing the program may be a non-transitory recording medium such as a CD-ROM.

[0111] In addition, the recording medium also includes an internal or external recording medium that can be accessed from a distribution server for distributing the program. Note that the program may be divided into a plurality of parts and downloaded at different timings, and then combined by each component provided in the information processing apparatus 1 and the SSD 40, or the distribution servers for distributing each of the divided programs may be different. Further, the "computer-readable recording medium" includes those that hold a program for a certain period of time, such as a volatile memory (RAM) inside a computer system that becomes a server or a client when a program is transmitted via a network. Also, the above program may be for realizing a part of the functions described above. Further, it may be a so-called differential file (differential program) that can realize the above functions in combination with a program already recorded in the computer system.

[0112] Also, part or all of the functions described above may be realized as an integrated circuit such as an LSI (Large Scale Integration). Each of the functions described above may be made into a processor individually, or part or all of them may be integrated and made into a processor. Also, the method of integrating into a circuit is not limited to LSI, and it may be realized by a dedicated circuit or a general-purpose processor. Also, when a technology for integrating into a circuit that replaces LSI appears due to the progress of semiconductor technology, an integrated circuit using such technology may be used.

Explanation of Reference Numerals

[0113] 1 Information processing apparatus 10 Main control unit 11 CPU 12 Main memory 13 Video subsystem 14 Display unit 21 Chipset 22 BIOS memory 31 Embedded controller (EC) 32 Input unit 33 Power supply circuit 40 SSD 41 Flash memory 42 SSD Controller 50 Memory Unit 51 Notification Information Memory Unit 101 AP Processing Unit 102 SSD Device Driver Unit 103 SSD Management Processing Unit 410 SSD Memory Unit 411 Management Information Memory Unit 412 Mode Information Memory Unit 413 Data Memory Unit 420 Memory Control Unit 421 Management Processing Unit 422 Writing Processing Unit 423 Reading Processing Unit

Claims

1. An SSD (Solid State Drive) including a non-volatile memory unit configured by a plurality of multi-bit cells that store data of a plurality of bits in one memory cell and is electrically rewritable, and a main control unit that executes processing based on data stored in the SSD are provided, wherein the SSD is a memory control unit that controls access to the non-volatile memory unit, and when storing the data of the plurality of bits in the plurality of multi-bit cells, if the number of rewrite times executed on the plurality of multi-bit cells is equal to or more than a threshold number of times, stores the data of the plurality of bits in a high-quality memory mode in which the variation width of the threshold voltage is narrower than that in the normal memory mode, and includes a memory control unit for storing the data of the plurality of bits; when the high-quality memory mode becomes effective, the memory control unit notifies the main control unit that the high-quality memory mode has become effective; the main control unit outputs a notification indicating that the high-quality memory mode has become effective to a user information processing apparatus.

2. The SSD includes a rewrite count storage unit that stores the rewrite count in units of blocks that erase data of the plurality of multi-bit cells collectively, when storing the data of the plurality of bits, the memory control unit acquires the rewrite count corresponding to the block that stores the data of the plurality of bits from the rewrite count storage unit, and if the acquired rewrite count is equal to or more than the threshold number of times, stores the data of the plurality of bits in the high-quality memory mode The information processing apparatus according to claim 1.

3. In the high-quality memory mode, the memory control unit performs an application process of applying a voltage for storing data to the plurality of multi-bit cells for a predetermined period obtained by dividing an application period, after the application process, performs a confirmation process of confirming whether the threshold voltage is within the variation width of the threshold voltage, and performs a repetition process of repeating the application process and the confirmation process until the threshold voltage is within the variation width of the threshold voltage The information processing apparatus according to claim 1.

4. When the high-quality memory mode becomes effective in a predetermined ratio or more of the storage capacity of the SSD, the main control unit causes the display unit to display the notification The information processing apparatus according to claim 1.

5. As the notification, the main control unit causes the display unit to display information indicating the ratio of the storage capacity of the SSD in which the high-quality memory mode has become effective The information processing apparatus according to claim 4.

6. An SSD (Solid State Drive) including a non-volatile memory unit that is electrically rewritable and is composed of a plurality of multi-bit cells that store data of a plurality of bits in one memory cell, A main control unit that executes processing based on the data stored in the SSD A control method for an information processing apparatus comprising: A step in which a storage control unit of the SSD controls access to the non-volatile memory unit, and when storing the data of the plurality of bits in the plurality of multi-bit cells, if the number of rewrite times executed on the plurality of multi-bit cells is equal to or greater than a threshold number of times, storing the data of the plurality of bits in a high-quality storage mode in which the variation width of the threshold voltage is narrower than that in the normal storage mode; A step in which the storage control unit notifies the main control unit that the high-quality storage mode has become effective when the high-quality storage mode becomes effective; A step in which the main control unit outputs a notification indicating that the high-quality storage mode has become effective to the user A control method including the above.

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