Non-volatile semiconductor memory device

Abstract

To provide a complementary read-out type non-volatile semiconductor memory device in which information indicating whether or not all of a plurality of memory cells are in an erase state is generated without adding and arranging memory cells.SOLUTION: In each of n twin cells 12, n fist sense amplifiers SA1 to SAn form a current path between one memory cell having a smaller or larger cell current in a data reading state among two memory cells 10x and 10y and power source lines PLs. A second sense amplifier SAv generates erase verifying information RTDv indicating whether or not it is the erase state where all stored data of the memory cells 10x and 10y of the n twin cells 12 are the same level, based on a verification current Ivf flowing through the power source lines PLs as the sum of currents by the n first sense amplifiers SA1 to SAn.SELECTED DRAWING: Figure 15

Description

Technical Field

[0001] The present disclosure relates to a non-volatile semiconductor memory device, and more particularly to a complementary read type non-volatile semiconductor memory device.

Background Art

[0002] In a non-volatile semiconductor memory device, data storage is performed by changing the current flowing through a memory cell (hereinafter referred to as cell current) when reading data, depending on whether the stored data in the memory cell is "1" or "0". For example, in a flash memory, in a memory cell composed of a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), one of "1" and "0" can be stored by changing the threshold voltage of the transistor according to the presence or absence of charge injection into the floating gate.

[0003] When reading the stored data of one memory cell, a method of determining whether the stored data is "1" or "0" by comparing the cell current with a reference current (hereinafter also referred to as "reference current read type") can be applied. However, in the reference current read type, there is a concern that if the cell current varies due to manufacturing variations or the like, an incorrect determination of the stored data may occur.

[0004] As a technique for improving the read accuracy, a complementary read type configuration in which two memory cells constituting a pair store "0" and "1" complementarily is described, for example, in Japanese Patent Application Laid-Open No. 2008-117510 (Patent Document 1).

[0005] Patent Document 1 describes a configuration in which a twin cell is constituted by two memory cells that store binary data depending on the difference in threshold voltage, and the stored data of the twin cell is determined by comparing the magnitudes of the cell currents of the two memory cells by a sense amplifier.

Prior Art Documents

Patent Documents

[0006] Patent Document 1 Japanese Patent Application Laid-Open No. 2008-117510 SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0007] Generally, in a flash memory or the like, data is not directly overwritten on a memory cell in a written state, and data writing is executed on a memory cell in an erased state. Specifically, after an erase operation is performed to set all of a plurality of memory cells in a block to an erased state (stored data is "1"), a write operation is performed on the memory cells in the erased state.

[0008] Therefore, during the operation of a flash memory, information indicating whether all of a plurality of memory cells included in a predetermined fixed section, which is a data writing target unit, are in an erased state (hereinafter also referred to as "erase verification information") is necessary for confirming whether the fixed section is writable.

[0009] However, in a complementary read type flash memory, in an erased state, the stored data of both of the two memory cells of each twin cell is the same ("1"). For this reason, it is difficult to generate erase verification information by reading data from the twin cell.

[0010] On the other hand, if additional memory cells for storing the erase verification information are arranged, particularly in a complementary read type configuration that requires memory cells twice the number of memory bits, further arrangement of a large number of memory cells for storing the erase verification information is feared to cause an increase in the size and cost of the device.

[0011] The present disclosure is for solving the above problems, and provides a complementary read type nonvolatile semiconductor memory device capable of generating information indicating whether all of a plurality of memory cells are in an erased state without arranging additional memory cells.

[0012] Other problems and novel features will become apparent from the description of this specification and the accompanying drawings.

Means for Solving the Problems

[0013] A non-volatile semiconductor memory device according to an embodiment includes a plurality of twin cells classified into a plurality of sections, a first amplifier, a second amplifier, and a first power supply line. Each of the plurality of twin cells includes first and second memory cells in which a cell current passing through in a data read state differs according to binary storage data. Each of the plurality of sections includes n (n: an integer of 2 or more) of the twin cells. Each of the twin cells is either an erased state in which the storage data is the same or a written state in which the storage data is different between the first and second memory cells. The first amplifier is connected in parallel to n twin cells. The second amplifier generates erase verification information indicating whether or not all of the n twin cells are in an erased state. Each of the n first amplifiers forms a current path between one of the first memory cell and the second memory cell having a smaller cell current and one of the first memory cell and the second memory cell having a larger cell current, which are predetermined, and the first power supply line in an erase verification operation for generating the erase verification information. The second amplifier generates the erase verification information based on the current flowing through the first power supply line in the erase verification operation.

Advantages of the Invention

[0014] According to the above embodiment, in a complementary read type non-volatile semiconductor memory device, information indicating whether or not all of a plurality (n) of memory cells are in an erased state can be generated without adding additional memory cells.

Brief Description of the Drawings

[0015]

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Embodiments for Carrying Out the Invention

[0016] Hereinafter, each embodiment will be described in detail with reference to the drawings. In the following description, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated.

[0017] <Description of Comparative Example> First, a comparative example for generating erase verification information in a complementary read type nonvolatile semiconductor memory device will be described in order. Hereinafter, in the present disclosure, a flash memory will be described as a representative example of the nonvolatile semiconductor memory device.

[0018] FIG. 1 is a conceptual circuit diagram for explaining the basic data read principle of a flash memory.

[0019] As shown in FIG. 1, in the memory cell 10 of the flash memory, in the erased state where charges are released from the floating gate, the threshold voltage becomes negative and the stored data becomes "1". On the other hand, in the erased state, when a writing operation of injecting charges into the floating gate is performed, the memory cell 10 enters the written state. In the written state, the memory cell 10 has a positive threshold voltage and the stored data becomes "0". That is, the threshold voltage of the memory cell 10 composed of a field effect transistor in the erased state is lower than the threshold voltage in the written state.

[0020] For the memory cell 10 to be read, a read voltage (positive voltage) is input to the gate to generate a cell current Icell depending on the threshold voltage. In the same memory cell 10, the cell current Icell in the erased state is larger than the cell current in the written state where the threshold voltage increases by charge injection.

[0021] The memory cell 10 is electrically connected to one of the input nodes (-terminal) of the sense amplifier SA via a selector 11 to which a selection signal SLb is input to the gate. The selector 11 is composed of, for example, a P-type MOS transistor. When the selection signal SLb input to the selector 11 corresponding to the memory cell 10 to be read is set to "0", the cell current Icell flows to the -terminal of the sense amplifier SA.

[0022] By inputting a reference voltage Vref to the gate, the reference cell 15 generates a reference current Iref. The reference cell 15 is connected to the other (+ terminal) of the input node of the sense amplifier SA. As a result, the reference current Iref flows into the + terminal of the sense amplifier SA.

[0023] The sense amplifier SA receives the supply of the power supply voltage from the power supply wiring PLs and outputs read data RDT indicating the comparison result of the magnitude between the reference current Iref at the + terminal and the cell current Icell at the - terminal. In this way, in the reference current readout method, based on the comparison result of the cell current Icell and the reference current Iref, the read data RDT indicating the stored data of the memory cell 10 can be generated.

[0024] In the present disclosure, when the current flowing into the + terminal (Iref in FIG. 1) is larger than the current flowing into the - terminal (Iecll in FIG. 1), the read data RDT = "0". On the other hand, when the current flowing into the - terminal (Iecll in FIG. 1) is larger than the current flowing into the + terminal (Iref in FIG. 1), the read data RDT = "1".

[0025] Although not shown in the figure, a series circuit of the memory cell 10 and the selector 11 similar to that shown is connected in plurality to one (- terminal) of the input node of the sense amplifier SA, and the sense amplifier SA and the reference cell 15 (reference current Iref) are shared by the plurality of memory cells 10.

[0026] FIG. 2 is a distribution diagram of the cell current for explaining the data readout by the reference current readout type of FIG. 1. In FIG. 2, a distribution curve 200 of the cell current Icell when the stored data is "0" and a distribution curve 201 of the cell current Icell when the stored data is "1" are shown for the entire plurality of memory cells 10 constituting the nonvolatile memory device.

[0027] In the reference current readout type, it is required to set the reference current Iref in the current region where the distribution curves 200 and 201 do not overlap. Thus, for the memory cell 10 in the erased state, when Icell > Iref is detected by the sense amplifier SA, the readout data RDT = “1” is set. On the other hand, for the memory cell 10 in the written state, when Icell < Iref is detected by the sense amplifier SA, the readout data RDT = “0” is set.

[0028] As understood from FIG. 2, when a current region where the distribution curves 200 and 201 overlap occurs due to the influence of manufacturing variations or the like, an incorrect determination of the stored data will occur where the level (“0”, “1”) of the stored data in the memory cell 10 and the readout data RDT do not match.

[0029] Therefore, including degradation, the write and erase margins are determined by the relationship between the maximum value of the cell current in the distribution curve 200 and the minimum value of the cell current in the distribution curve 201, that is, the current value of the worst bit, and the reference current Iref, and the number of rewrite cycles and other reliability limits are determined. For example, in the reference readout type, in order to make the distribution curve 200 sufficiently on the low current side, it is necessary to apply a voltage to the memory cell 10 so as to sufficiently discharge the charge from the floating gate during the erase operation of the memory cell 10. Such voltage conditions are disadvantageous for the degradation of the memory cell 10, so the number of rewritable times may be limited.

[0030] Next, the data readout of the complementary readout type will be described with reference to FIGS. 3 and 4. As shown in FIG. 3, in the complementary readout type, 1-bit data is stored in the twin cell 12 including two memory cells 10x and 10y.

[0031] Referring to FIG. 3(a), the memory cell 10x is input to one (- terminal) of the input nodes of the sense amplifier SA via the selector 11x. The memory cell 10y is input to the other (+ terminal) of the input nodes of the sense amplifier SA via the selector 11y.

[0032] Selectors 11x and 11y are composed of P-type MOS transistors, and a common selection signal SLb is input to each gate. When the selection signal SLb input to the selectors 11x and 11y corresponding to the twin cell 12 to be read is set to "0", the cell current Icellx of the memory cell 10x flows to the - terminal of the sense amplifier SA, and the cell current Icelly of the memory cell 10y flows to the + terminal of the sense amplifier SA.

[0033] In the erased state, for the twin cell 12, the stored data of both the memory cells 10x and 10y is "1". On the other hand, in the twin cell 12 in the write state, by setting the stored data of the memory cells 10x and 10y to one of "0" and "1" respectively, "0" or "1" is stored.

[0034] As shown in Fig. 3(a), when a write operation is performed on the memory cell 10x with respect to the twin cell 12 in the erased state, the stored data of the memory cell 10x changes to "0". On the other hand, the stored data of the memory cell 10y is "1". At this time, since Icellx < Icelly, the sense amplifier SA outputs the read data RDT = "0". That is, the stored data of the twin cell 12 is "0".

[0035] Conversely, when a write operation is performed on the memory cell 10y with respect to the twin cell 12 in the erased state, the stored data of the memory cell 10y changes to "0". On the other hand, the stored data of the memory cell 10x remains "1". At this time, since Icellx > Icelly, the sense amplifier SA outputs the read data RDT = "1". That is, the stored data of the twin cell 12 is "1".

[0036] Similar to Fig. 3, Fig. 4 shows the distribution curves 200 of the cell currents Icellx and Icelly when the stored data is "0" for all the memory cells 10 constituting the non-volatile memory device, and the distribution curves 201 of the cell currents Icellx and Icelly when the stored data is "1".

[0037] As described with reference to FIG. 2, in the reference current read type, when the distribution curves 200 and 201 for the entire memory cell 10 overlap, an erroneous determination occurs in data reading by comparing the magnitudes of the reference currents Iref. On the other hand, in the complementary read type, even if the distribution curves 200 and 201 for the entire plurality of memory cells 10 overlap, if the magnitude relationship of the cell currents of the two memory cells 10x and 10y within each twin cell 12 matches the stored data, the stored data can be correctly read out.

[0038] Therefore, in the complementary read type, while two memory cells are required for storing 1 bit of data, the reliability of data reading is improved. Also, since the voltage applied to the memory cells 10x and 10y during the erase operation can be relaxed compared to the reference current read type, the number of rewritable times can be increased. That is, the complementary read type is suitable for applications with a small capacity and a large number of rewrite times.

[0039] Next, the erase verification information is compared between the reference current read type and the complementary read type. As described above, in a flash memory, data is not directly overwritten to a memory cell that has already been written, and data writing is performed on a memory cell in an erased state. For this reason, during the operation of the flash memory, it is necessary to obtain erase verification information indicating whether a predetermined data writing target unit (i.e., a certain section) is writable, that is, whether all of the plurality of memory cells included in the certain section are in an erased state, for each of the predetermined sections indicating the data writing target unit.

[0040] Hereinafter, in the present embodiment, in a non-volatile semiconductor memory device in which n-bit (n: an integer of 2 or more) data is stored for each address, each address will be described as the certain section. That is, the erase verification information is generated for each address.

[0041] First, with reference to FIGS. 5 and 6, the generation of the erase verification information in the reference current read type will be described.

[0042] FIG. 5 shows a conceptual circuit diagram for explaining the read data RDT from a memory cell in an erased state in the reference current read type.

[0043] As shown in FIG. 5, in the reference current readout type, in order to store n-bit data BT1 to BTn corresponding to one address, n memory cells 10 are arranged. When reading the data of the address, the sense amplifiers SA1 to SAn output read data RDT1 to RDTn indicating the stored data (“0” or “1”) of the n memory cells 10.

[0044] When all of the n memory cells 10 are in the erased state, the address becomes writable. At this time, the stored data of the n memory cells 10 are all “1”.

[0045] FIG. 6 shows a conceptual diagram for explaining the distribution of cell currents in the writable state in the reference current readout type shown in FIG. 5.

[0046] As shown in FIG. 6, in the reference current readout type, since all of the n memory cells 10 are in the erased state in the writable state, the distribution curve 201 of the cell current Icell is on the higher current side than the reference current Iref.

[0047] As a result, as shown in FIG. 5, since the stored data of “1” is read from the n memory cells 10, all of the read data RDT1 to RDTn become “1”. Therefore, when performing a write operation to a certain address, data reading is performed on the n memory cells 10 corresponding to the address, and erasure verification information for determining whether writing is possible can be generated depending on whether all of the read data RDT1 to RDTn become “1”. For example, 1-bit erasure verification information can be generated by the logical product (AND) of the read data RDT1 to RDTn for each address.

[0048] FIG. 7 shows a conceptual circuit diagram for explaining the read data RDT from a memory cell in the erased state in the complementary readout type.

[0049] As shown in FIG. 7, in the complementary readout type, n twin cells 12 are arranged to store n-bit data BT1 to BTn corresponding to one address. Each of the n twin cells 12 has a pair of memory cells 10x and 10y. When reading the data of the address, the sense amplifiers SA1 to SAn output read data RDT1 to RDTn based on the comparison result of the cell currents of the memory cells 10x and 10y in each of the n twin cells 12.

[0050] When all of the n twin cells 12 are in the erased state, the address becomes writable. At this time, in each twin cell 12, the stored data of the memory cells 10x and 10y both become "1".

[0051] As a result, each of the read data RDT1 to RDTn from the n twin cells 12 is set to "0" or "1" due to the subtle difference in the cell current caused by the manufacturing variation of the threshold voltage under the condition that the stored data is the same between the memory cells 10x and 10y in each twin cell. Therefore, in the complementary readout type, different from the reference current readout type, the erased verification information for each address unit cannot be generated by reading the data from the n twin cells 12.

[0052] Therefore, in the complementary readout type, for each address (writing target unit), in order to generate the erased verification information indicating whether it is in the writable state, that is, whether all of the n twin cells 12 are in the erased state, additional memory cells are arranged.

[0053] FIG. 8 is a conceptual circuit diagram for explaining a first comparative example of the configuration for generating the erased verification information in the complementary readout type.

[0054] Referring to FIG. 8, in the first comparative example, corresponding to each address (writing target unit), in addition to n twin cells 12 for storing n-bit data, a memory cell 10v for storing the erase verification information (1 bit) of the address is arranged. Further, a sense amplifier SAv is arranged to read the stored data of the memory cell 10v. The data reading from the memory cell 10v is executed by the reference current reading type described in FIG. 1.

[0055] Specifically, the memory cell 10v is electrically connected to one (- terminal) of the input nodes of the sense amplifier SAv via a selector 11v. The selector 11v is turned on during the erase verification operation to confirm whether writing is possible before writing data to the corresponding n twin cells 12. Thereby, the sense amplifier SAv outputs read data RDTv indicating the stored data of the memory cell 10v based on the comparison of the cell current Icellv of the memory cell 10v and the reference current Iref similar to that in FIG. 1.

[0056] During the erase operation targeting the n twin cells 12, the memory cell 10v is commonly targeted for the erase operation together with the memory cells 10x and 10y of the n twin cells 12. Thereby, together with the memory cells 10x and 10y of the n twin cells 12, the stored data of the memory cell 10v also becomes "1".

[0057] In the data writing operation targeting the n twin cells 12, the memory cell 10v is also targeted for data writing in parallel. Thereby, as described in FIG. 3, in each twin cell 12, in addition to the stored data of either one of the memory cells 10x and 10y changing from "1" to "0", the stored data of the memory cell 10v also changes from "1" to "0".

[0058] Therefore, in the first comparative example of FIG. 8, the stored data of one memory cell 10v indicates the erase verification information. That is, if the stored data of the memory cell 10v is "1", it can be determined that all the corresponding n twin cells 12 are in the erased state and the address (writing target unit) is writable.

[0059] FIG. 9 shows a distribution diagram of cell current when the configuration of FIG. 8 is in the erased state. FIG. 9(a) shows the distribution of the cell current of the twin cell 12, while FIG. 9(b) shows the distribution of the cell current of the memory cell 10v that stores the erase verification information.

[0060] Referring to FIG. 9(a), in the erased state, the stored data of the memory cells 10x and 10y that make up each twin cell 12 are aligned to "1", and the memory cell currents Icellx and Icelly are distributed according to the distribution curve 201.

[0061] On the other hand, as shown in FIG. 9(b), in the erased state, since the stored data of the memory cell 10v is "1", the cell current Icellv of the memory cell 10v is distributed according to the distribution curve 201v when the stored data is "1". The distribution curve 201v is equivalent to the distribution curve 201 in FIG. 9(a).

[0062] FIG. 10 shows a distribution diagram of cell current when the configuration of FIG. 8 is in the written state. FIG. 10(a) shows the distribution of the cell current of the twin cell 12, while FIG. 10(b) shows the distribution of the cell current of the memory cell 10v that stores the erase verification information.

[0063] Referring to FIG. 10(a), in the written state, the stored data of the memory cells 10x and 10y that make up each twin cell 12 are either "0" and "1" one by one. Therefore, the memory cell currents Icellx and Icelly are distributed according to either the distribution curve 200 or the distribution curve 201.

[0064] On the other hand, as shown in FIG. 10(b), in the written state, since the stored data of the memory cell 10v is "0", the cell current Icellv of the memory cell 10v is distributed according to the distribution curve 200v when the stored data is "0". The distribution curve 200v is equivalent to the distribution curve 200 in FIG. 10(a).

[0065] From the comparison between FIGS. 9(b) and 10(b), by distinguishing the distribution curves 200v and 201v, the erase verification information can be obtained. That is, the erase verification information can be obtained by reading the stored data of the memory cell 10v through the comparison between the cell current Icellv of the memory cell 10v and the reference current Iref. That is, the read data RDTv generated by the sense amplifier SAv in FIG. 8 can be used as the erase verification information.

[0066] However, in the configuration of FIG. 8, the erase verification information is generated in the same reference current readout type as in FIG. 1. Therefore, similar to the description in FIG. 2, there is a problem with respect to the variation in the cell current of the memory cell 10v in the reliability of the erase verification information. Thereby, there is a concern that the erase verification information becomes a bottleneck regarding the reliability of the non-volatile semiconductor memory device (flash memory).

[0067] FIG. 11 shows a second comparative example of a configuration for generating erase verification information in a complementary readout type.

[0068] Referring to FIG. 11, in the second comparative example, in order to improve the reliability of the erase verification information, a plurality (for example, four) of memory cells 10v are connected in parallel, and 1-bit erase verification information is stored.

[0069] The four memory cells 10v are targets of the erase operation or the write operation in parallel. Therefore, when the n twin cells 12 at the corresponding address are in the erased state, the stored data of the four memory cells 10v are aligned to "1". On the other hand, when the n twin cells 12 at the corresponding address are in the written state, the stored data of the four memory cells 10v are aligned to "0".

[0070] In FIG. 11, since the cell current Icellv is the sum of the cell currents of four memory cells 10 connected in parallel, compared with the configuration of FIG. 8, the cell current Icellv flowing into the sense amplifier SA becomes four times. Therefore, the reference current Iref* flowing through the reference cell 15v is set to be approximately four times the reference current Iref of FIG. 8. For example, in the configuration of FIG. 11, by designing the transistor size of the reference cell 15v to be four times that of the reference cell 15v in FIG. 11, Iref* = 4×Iref can be realized.

[0071] FIG. 12 shows a distribution diagram of cell currents for explaining the difference in cell current Icellv with respect to the difference in the number of memory cells 10v.

[0072] FIG. 12(a) shows a distribution diagram of the cell current Icell in the first configuration example (FIG. 8) in which erase verification information is stored in one memory cell 10v. In the erased state, the cell current Icellv is distributed according to the distribution curve 201, while in the written state, the cell current Icellv is distributed according to the distribution curve 200.

[0073] Therefore, in the comparison between the reference current Iref set to separate the distribution curves 200 and 201 and the cell current Icellv, if there is an overlap in the distribution curves 200 and 201 due to manufacturing variations, degradation variations, etc., there is a possibility that the erase verification information may be misread.

[0074] On the other hand, FIG. 12(b) shows a distribution diagram of the cell current Icell in the second configuration example (FIG. 11) in which erase verification information is stored in four memory cells 10v. In the erased state, the cell current Icellv is distributed according to the distribution curve 201v of FIG. 12(a), while in the written state, the cell current Icellv is distributed according to the distribution curve 200v.

[0075] The distribution curves 200v and 201v represent the distribution of the sum of the cell currents of four cells. Therefore, under the distribution curves 200v and 201v, the difference in the cell current Icellv between the erased state and the written state is amplified compared to the difference in the cell current Icellv that follows the distribution curves 200 and 201 of a single cell current.

[0076] In the second comparative example, by enhancing the reliability of the erase verification information output from the four memory cells 10v, it is possible to prevent the erase verification information from becoming a bottleneck regarding the reliability of the non-volatile semiconductor memory device (flash memory).

[0077] However, the arrangement of the memory cells for generating the erase verification information is likely to cause an increase in size and cost because it increases the number of memory cell arrangements in the entire non-volatile semiconductor memory device.

[0078] FIG. 13 shows a conceptual diagram for explaining an example of the layout of the memory cells in the entire non-volatile semiconductor memory device in the second comparative example.

[0079] Referring to FIG. 13, as described above, in a complementary read type non-volatile semiconductor memory device in which n-bit data is stored for each address, for M addresses (M: an integer of 2 or more), (2 × n × M) memory cells 10x, 10y are arranged using the area 100 for data storage.

[0080] Furthermore, in the second comparative example, for each address, four memory cells 10v surrounded by a dotted line frame are additionally arranged to generate the erase verification information. In a complementary read type non-volatile semiconductor memory device, (4 × M) memory cells 10v are arranged using the area 101 for generating the erase verification information corresponding to the M addresses. As a result, for example, when n = 8, the number of memory cells additionally arranged in the area 110 for generating the erase verification information is 4 / (2 × 8) = 25% of the number of memory cells arranged in the area 100 for data storage.

[0081] As described above, in a complementary read type nonvolatile semiconductor memory device, if a memory cell for generating erase verification information for each write target unit (address) is additionally arranged, it is understood that problems occur in terms of size and cost.

[0082] <First Embodiment> In the first embodiment, a configuration for generating erase verification information will be described in a complementary read type nonvolatile semiconductor memory device without additionally arranging memory cells.

[0083] FIG. 15 is a conceptual circuit diagram for explaining a configuration for generating erase verification information in a complementary read type nonvolatile semiconductor memory device according to the first embodiment. Also in FIG. 15, a configuration for generating erase verification information corresponding to n twin cells 12 of one write target unit (address) is shown.

[0084] Furthermore, FIG. 14 shows a conceptual circuit diagram for explaining a configuration for generating erase verification information in a complementary read type nonvolatile semiconductor memory device according to a second comparative example for comparison with FIG. 15. In FIG. 14, in addition to the configuration for storing n-bit data, a sense amplifier SAv, a reference cell 15v, and four additionally arranged memory cells 10v are additionally arranged for generating erase verification information. Since the configuration of these additionally arranged elements is the same as that in FIG. 11, detailed description will not be repeated.

[0085] Referring to FIG. 15, in the complementary read type nonvolatile semiconductor memory device according to the first embodiment, the arrangement of the memory cells 10v in FIG. 14 is omitted, and one of the input nodes (- terminal) of the sense amplifier SAv that outputs erase verification information is connected to a power supply wiring PLs for supplying the power supply voltage Vpp2 of the sense amplifiers SA1 to SAn. The power supply wiring PLs is electrically connected to a power supply node 55 that supplies the power supply voltage Vpp2 via a resistance element 51 having an electrical resistance value R1.

[0086] As described below, during the erasure verification operation, a verification current Ivf, which is the sum of the currents flowing from the power supply line PLs to the n sense amplifiers SA1 to SAn, flows. Therefore, at the - terminal of the sense amplifier SAv and at the node Nr, a voltage Vvf that is lower than the power supply voltage Vpp2 by only the voltage drop generated by the verification current Ivf across the resistance element 51 is generated. That is, the voltage Vrf input to the sense amplifier SAv is represented by the following formula (1).

[0087] Vvf = Vpp2 - Ivf × R1 …(1) That is, the voltage Vvf corresponds to the voltage obtained by converting the verification current Ivf into a voltage using the electrical resistance value R1. The larger the verification current Ivf, the lower the voltage Vvf.

[0088] On the other hand, the other (+ terminal) of the input node of the sense amplifier SAv is connected to the node Nr which is connected to the reference cell 15v. The reference cell 15v is connected between the node Nr and the ground node that supplies the ground voltage. The node Nr is electrically connected to the power supply node 56 that supplies the power supply voltage Vpp2 via a resistance element 52 having an electrical resistance value R1. The reference cell 15v has a reference voltage Vrefn input to its gate and generates a reference current Irefn. As a result, at the node Nr, a voltage Vr that is lower than the power supply voltage Vpp2 by only the voltage drop generated by the reference current Irefn across the resistance element 52 is generated. Therefore, the voltage Vr input to the sense amplifier SAv is represented by the following formula (2).

[0089] Vr = Vpp2 - Irefn × R1 …(2) That is, the voltage Vr corresponds to the voltage obtained by converting the reference current Irefn into a voltage using the electrical resistance value R1. The larger the reference current Irefn, the lower the voltage Vr.

[0090] Sense amplifier SAv operates by receiving the power supply voltage Vpp1 from a power supply wiring independent of the power supply nodes 55 and 56, and outputs read data RDTv based on the high and low comparison of voltages Vvf and Vr. Since the sense amplifier SAv compares the verify current Ivf with the reference current Irefn through the comparison of voltages Vvf and Vr, the read data RDTv from the sense amplifier SAv corresponds to the erase verify information.

[0091] When Irefn > Ivf, the sense amplifier SAv outputs RDTv = "0" by making Vr < Vvf. On the other hand, when Ivf > Irefn, it outputs RDTv = "1" by making Vvf < Vr.

[0092] FIG. 16 shows a circuit diagram for explaining a configuration example of sense amplifiers SA1 to SAn. Since the configurations of sense amplifiers SA1 to SAn are the same, in FIG. 16, sense amplifiers SA1 to SAn are collectively denoted as sense amplifier SA.

[0093] Referring to FIG. 16, the sense amplifier SA includes P-type transistors 71 to 73, 79x, 79y, N-type transistors 74 to 76, inverters 81 to 83, and nodes Nx and Ny.

[0094] Node Nx corresponds to one input node (- terminal) of the sense amplifier SA, and node Ny corresponds to the other input node (+ terminal) of the sense amplifier SA. Similar to FIG. 3, node Nx is connected to the memory cell 10x via the selector 11x, while node Ny is connected to the memory cell 10y via the selector 11y.

[0095] Transistors 72 and 74 are connected in series between nodes N1 and N2 via node Nx. Further, the gates of transistors 72 and 74 are commonly connected to node Ny. On the other hand, transistors 73 and 75 are connected in series between nodes N1 and N2 via node Ny. Further, the gates of transistors 73 and 75 are commonly connected to node Nx. Thus, transistors 72 to 75 operate as a CMOS (Complementary Metal Oxide Semiconductor) operational amplifier that amplifies the voltage difference between nodes Nx and Ny.

[0096] Transistor 71 is connected between the power supply wiring PLs and node N1, and transistor 76 is connected between node N2 and the ground node. An enable signal SAE of the sense amplifier SA is input to the gate of transistor 76. An inverted signal of the enable signal SAE output from inverter 83 is input to the gate of transistor 71. Therefore, during the period when the enable signal SAE = “1”, transistors 71 and 76 are turned on to supply an operating current to the CMOS operational amplifier.

[0097] Transistor 79x is connected between the node supplying the power supply voltage Vpp2 and node Nx. Transistor 79y is connected between the node supplying the power supply voltage Vpp2 and node Ny. A precharge signal PCHGb set to “0” during the precharge period is input to the gates of the P-type transistors 79x and 79y. That is, transistors 79x and 79y operate as precharge switches for nodes Nx and Ny, respectively.

[0098] Inverter 81 outputs read data RDT with the voltage SAT of node Nx as an input. Inverter 82 outputs inverted read data RDTb complementary to the read data RDT with the voltage SAB of node Ny as an input.

[0099] FIG. 17 shows an operation waveform diagram of the sense amplifier SA shown in FIG. 15. First, the normal data readout from the twin cell 12 by the precharge period Ta, the sampling period Tb, and the sense period Tc will be described. The word line WLT connected to the gates of the memory cells 10x and 10y <n>and WLB <n>By changing from "0" to "1", the memory cells 10x and 10y are set to the data read state.

[0100] At time tr, when data reading from the twin cell 12 is started, a precharge period Ta is provided. During the precharge period Ta, the precharge signal PCHGb changes from "1" to "0", and the enable signal SAE is set to "0". Further, the selection signal SLb input to the selectors 11x and 11y changes from "1" to "0".

[0101] When the transistors 79x and 79y are turned on, cell currents of the memory cells 10x and 10y flow through the nodes Nx and Ny. On the other hand, since the enable signal SAE is "0", no operating current is supplied to the CMOS operational amplifier. As a result, the voltage SAT of the node Nx and the voltage SAB of the node Ny are precharged to a voltage level corresponding to "1" (the power supply voltage Vpp2). Conversely, the read data RDT and the inverted read data RDTb are set to "0".

[0102] Subsequently, during the sampling period Tb, the precharge signal PCHGb changes from "0" to "1".

[0103] By turning off the transistors 79x and 79y (precharge switches), the voltages SAT and SAB of the nodes Nx and Ny decrease due to discharge by the read currents Icellx and Icelly. On the other hand, also during the sampling period Tb, since the enable signal SAE is maintained at "0", no operating current is supplied to the CMOS operational amplifier. Therefore, during the sampling period Tb, the voltage difference between the nodes Nx and Ny (the difference between the voltages SAT and SAB) is not amplified.

[0104] As a result, a voltage difference corresponding to the current difference between the cell currents Icellx and Icelly occurs between the nodes Nx and Ny. In the example of FIG. 17, since Icellx < Icelly, the voltage drop rate of the voltage SAT (node Nx) is smaller than the voltage drop rate of the voltage SAB (node Ny), and as a result, SAT > SAB.

[0105] Subsequently, during the sense period Tc, the selection signal SLb changes from "0" to "1", and the nodes Nx and Ny are electrically disconnected from the memory cells 10x and 10y due to the off state of the selectors 11x and 11y. Further, the enable signal SAE changes from "0" to "1", and an operating current is supplied to the CMOS operational amplifier by the transistors 72 to 75.

[0106] Thereby, during the sense period Tc, the voltages SAT and SAB change so as to amplify the voltage difference between the nodes Nx and Ny generated during the sampling period Tb. In the example of FIG. 17 where the sense period Tc starts with the state of SAB < SAT, in the CMOS sense amplifier, the transistors 72 and 75 are turned on while the transistors 73 and 74 are turned off. As a result, the node Nx is electrically connected to the power supply line PLs, so that the voltage SAT rises to "1" (the power supply voltage Vpp2), while the ground voltage is transmitted to the node Ny, so that the voltage SAB drops to "0" (the ground voltage), and an "amplification operation" is executed. Due to the above amplification operation of the CMOS operational amplifier, a current IPLs corresponding to the operating current of the CMOS operational amplifier is generated in the power supply line PLs.

[0107] During the sense period Tc, read data RDT and inverted read data RDTb are generated based on the voltages SAT and SAB whose voltage difference has been amplified. In the example of FIG. 17, since Icell < Icelly, that is, the twin cell 12 is in the state of FIG. 3(a), the level of the voltage SAT ("1") is inverted, and the read data RDT = "0".

[0108] When the twin cell 12 is in the state of Fig. 3(b), since Icllx > Icelly, during the sampling period Tb, contrary to the example of Fig. 17, the voltage SAT decreases more than the voltage SAB (SAT < SAB). As a result, during the sense period Tc, in the CMOS sense amplifier, transistors 73 and 74 turn on while transistors 72 and 75 turn off. As a result, when the node Ny is electrically connected to the power supply wiring PLs, the voltage SAB rises to "1" (power supply voltage Vpp2), while the ground voltage is transmitted to the node Nx, so that the voltage SAT decreases to "0" (ground voltage), and the "amplification operation" is executed. Thereby, as shown in Fig. 3(b), the level of the voltage SAT ("0") is inverted, and the read data RDT = "1".

[0109] In this way, during the sense period Tc, for the nodes Nx and Ny corresponding to the input nodes of the sense amplifier SA, one of the nodes connected to the memory cell with the smaller cell current among the memory cells 10x and 10y constituting the twin cell 12 is set to "1", while the other node is set to "0", and a voltage difference occurs between the nodes Nx and Ny.

[0110] In the complementary read type non-volatile semiconductor memory device according to the first embodiment, during the erase verify operation, after performing the normal data read-like precharge period Ta, sampling period Tb, and sense period Tc on the twin cell 12, an erase verify period Td is further provided.

[0111] As shown in Fig. 17, during the erase verify period Td, from the state of the sense period Tc, the selection signal SLb changes from "1" to "0", and the selectors 11x, 11y are turned on again. Thereby, the nodes Nx and Ny are connected to the word line WLT <n>,WLTb <n>They are electrically connected to memory cells 10x and 10y in the data read state, respectively, in which "1" is input to the gate.

[0112] FIG. 18 shows a circuit diagram for explaining the current path during the erase verification period for the twin cell 12 in the write state. In FIG. 18, with respect to the circuit diagram of FIG. 16, the path of the current IPLs generated during the erase verification period Td is overwritten.

[0113] In the twin cell 12 in the write state, one of the memory cells 10x and 10y is in the write state and the other is in the erase state. In FIG. 18, similar to FIG. 3(a), among the twin cells 12, the memory cell 10x is in the write state (stored data "0") and the memory cell 10y is in the erase state (stored data "1").

[0114] Therefore, at the end of the sense period Tc, due to the amplification operation of the CMOS operational amplifier, a voltage difference is generated between nodes Nx and Ny, where the voltage SAT is "1" while the voltage SAB is "0". Therefore, in the CMOS operational amplifier, transistors 72 and 75 are turned on while transistors 73 and 74 are turned off, resulting in a state where a current path is formed between the power supply wiring PLs and node Nx.

[0115] From this state, when selectors 11x and 11y are turned on during the erase verification period Td, a current path is formed from the power supply wiring PLs to nodes Nx and memory cell 10x using the current path (transistor 72) in the CMOS sense amplifier. As a result, a current IPLs corresponding to the cell current of the memory cell 10x in the write state is generated in the power supply wiring PLs.

[0116] Conversely, when the memory cell 10x is in the erased state (stored data "1") and the memory cell 10y is in the written state (stored data "0"), as opposed to the example of FIG. 18, at the end of the sense period Tc, the voltage SAB is "1" while the voltage SAT is "0". Therefore, in the CMOS operational amplifier, transistors 73 and 74 are turned on while transistors 72, 75 are in the off state.

[0117] When the selectors 11x and 11y are turned on from this state, a current path is formed from the power supply wiring PLs to the node Ny and the memory cell 10y via the transistors 71 and 73. As a result, a current IPLs corresponding to the cell current of the memory cell 10y in the written state is generated in the power supply wiring PLs.

[0118] In this way, during the erase verification period Td, in each sense amplifier SA, a current IPLs corresponding to the cell current of the memory cell with the smaller cell current among the memory cells 10x and 10y constituting the twin cell 12 is generated in the power supply wiring PLs.

[0119] FIG. 19 is a circuit diagram for explaining the current path during the erase verification period for the twin cell in the erased state. Also in FIG. 19, the path of the current IPLs generated during the erase verification period Td is overwritten with respect to the circuit diagram of FIG. 16.

[0120] In the twin cell 12 in the erased state, both the memory cells 10x and 10y are maintained in the erased state (stored data "1"). Therefore, the cell currents of the memory cells 10x and 10y are equivalent to the cell currents in the erased state. However, during the sampling period Tb, a minute voltage difference occurs between the nodes Nx and Ny due to minute current differences caused by manufacturing variations or the influence of noise or the like. As a result, during the sense period Tc, one of the voltages SAT and SAB rises to "1" while the other drops to "0" due to the amplification of the minute voltage difference. However, it is indeterminate which of the voltages SAT and SAB rises to "1".

[0121] Thus, at the end of the sense period Tc, in the CMOS operational amplifier, one of the states where transistors 72 and 75 are on and the state where transistors 73 and 74 are on is formed.

[0122] Therefore, during the erase verification period Td, according to the minute difference in the cell currents of the memory cells 10x and 10y which are both in the erased state, one of the cell currents of the memory cells 10x and 10y, indicated by a dotted line in Fig. 19, will occur as the current IPLs in the power supply wiring PLs.

[0123] Fig. 20 is a conceptual circuit diagram for explaining the erase verification operation of the complementary read type non-volatile semiconductor memory device according to the first embodiment.

[0124] Referring to Fig. 20, in the erase verification operation of the non-volatile semiconductor memory device according to the first embodiment, the precharge period Ta, sampling period Tb, sense period Tc, and erase verification period Td of Fig. 17 are provided in order. As a result, during the erase verification period Td, since the above-described current IPLs are generated in the sense amplifiers SA1 to SAn, it is understood that a verification current Ivf obtained by summing the current IPLs in the n sense amplifiers SA is generated in the entire power supply wiring PLs.

[0125] Fig. 21 shows a distribution diagram of the verification current. Fig. 21(a) shows the distribution of the verification current generated during the erase verification operation for the twin cell 12 in the written state. As described with reference to Fig. 18, in the twin cell 12 in the written state, during the erase verification period Td, the cell current of one of the memory cells 10x and 10y which is in the written state (stored data "0") flows from the power supply wiring PLs to the sense amplifier SA as the current IPLs.

[0126] Therefore, since the verification current Ivf is the sum of the cell currents of n memory cells in the written state (stored data "0"), it is distributed according to the distribution curve 200vn of a current that is n times the cell current in the written state (stored data "0").

[0127] On the other hand, FIG. 21(b) shows the distribution of the verification current generated in the erase verification operation for the twin cell 12 in the erased state. As described with reference to FIG. 19, in the twin cell 12 in the erased state, during the erase verification period Td, the cell current of either one of the memory cells 10x and 10y, both of which are in the erased state, flows as the current IPLs from the power supply wiring PLs to the sense amplifier SA.

[0128] Therefore, since the verification current Ivf is the sum of the cell currents of the n memory cells in the erased state (stored data "1"), it is distributed according to the current distribution curve 201vn that is n times the cell current in the erased state (stored data "1").

[0129] As a result, the reference current Irefn can be set in the region where the distribution curves 200vn and 201vn do not overlap.

[0130] Referring to FIG. 20 again, the sense amplifier SAv equivalently compares the verification current Ivf with the reference current Irefn (FIG. 21) by comparing the voltage Vvf of the power supply wiring PLs with the voltage Vr of the node Nr.

[0131] As a result, when Ivf > Irefn, that is, in the state of FIG. 21(b), Vr > Vvf. Therefore, the sense amplifier SAv outputs RDTv = "1" as the erase verification information indicating that the n twin cells are in the erased state, that is, the address (writing target unit) corresponding to the n memory cells is writable.

[0132] On the contrary, when Ivf < Irefn, that is, in the state of FIG. 21(a), Vr < Vvf. Therefore, the sense amplifier SAv outputs RDTv = "0" as the erase verification information indicating that the n twin cells are in the written state, that is, the address (writing target unit) corresponding to the n memory cells is not writable.

[0133] Thus, according to the complementary readout type non-volatile semiconductor memory device according to the first embodiment, without performing the additional arrangement of the memory cells described in the comparative examples such as FIGS. 8 and 11, information (erase verification information) indicating whether all of the (2×n) memory cells included in the n twin memory cells belonging to a certain section (for example, a write target unit (address)) are in the erased state can be generated. As a result, it is possible to avoid the increase in size and cost due to the additional arrangement of the memory cells, and obtain the erase verification information for determining whether each write target unit (address) is writable.

[0134] Also, as described with reference to FIG. 21, the sum of the cell currents corresponding to the number (n) of twin cells belonging to the write target unit (address) is compared with the reference current Irefn. As a result, while the additional arrangement of the memory cell 10v is unnecessary, the erase verification information can be generated with the same read accuracy as in the case where n memory cells 10v are arranged in the second comparative example of FIG. 11.

[0135] In addition, as shown in FIG. 27, a modified example is also possible in which a constant voltage source 16 that outputs a voltage equivalent to Vr in FIG. 20 according to the design value of the reference current Irefn is arranged without actually generating the reference current Irefn. In this case, the sense amplifier SAv can generate the above-described erase verification information RDTv by comparing the voltage Vvf of the power supply wiring PLs with the voltage Vr from the constant voltage source 16. Thus, even in a configuration without providing a mechanism for actually generating the reference current Irefn, it is possible to generate the erase verification information RDTv based on the verification current Ivf flowing through the power supply wiring PLs.

[0136] In the first embodiment, the memory cell 10x corresponds to an example of the "first memory cell", the memory cell 10y corresponds to an example of the "second memory cell", the stored data "1" corresponds to an example of the "first level", and "0" corresponds to an example of the second level. Further, the sense amplifiers SA1 to SAn (sense amplifier SA) correspond to an example of the "first amplifier", the sense amplifier SAv corresponds to an example of the "second amplifier", and the power supply wiring PLs corresponds to an embodiment of the "first power supply wiring".

[0137] In addition, in FIG. 16, node Nx corresponds to an embodiment of the "first node", and node Ny corresponds to an embodiment of the "second node". Also, in the sense amplifier SA, an example of an amplification operation of generating a voltage difference obtained by amplifying a current difference between nodes Nx and Ny by a CMOS sense amplifier including transistors 72 to 75 is shown. However, it is also possible to perform the above-described amplification operation by a sense amplifier having a configuration different from that of the CMOS sense amplifier.

[0138] Furthermore, in FIGS. 15 and 20, the resistance element 51 corresponds to an embodiment of the "first resistance element", the resistance element 52 corresponds to an embodiment of the "second resistance element", the voltage Vvf corresponds to an embodiment of the "first voltage", and the voltage Vr corresponds to an embodiment of the "second voltage". Also, in FIG. 21, the distribution curve 201vn (FIG. 21(b)) corresponds to an embodiment of the "distribution curve of a current that is n times the first current", and the distribution curve 200vn (FIG. 21(a)) corresponds to an embodiment of the "distribution curve of a current that is n times the second current".

[0139] <Second Embodiment> In the second embodiment, a circuit configuration example for suppressing the influence of additional elements due to the erase verification operation on the normal data read operation of the sense amplifier SA will be described.

[0140] FIG. 22 is a conceptual circuit diagram for explaining a configuration for generating erase verification information in a complementary read type nonvolatile semiconductor memory device according to the second embodiment.

[0141] Referring to FIG. 22, in the second embodiment, a power supply wiring PLv used in the erase verify operation is arranged separately from the power supply wirings PLs of the sense amplifiers SA1 to SAn. The power supply wiring PLv is connected to the input node (- terminal) of the sense amplifier SAv similar to that in the first embodiment 1 (FIG. 15). The resistor element 51 and the power supply node 55 in FIG. 15 are also connected to the power supply wiring PLv. Further, in the sense amplifiers SA1 to SAn, NAND gates 91, 92, and P-type transistors 93, 94 are further arranged.

[0142] FIG. 23 is a circuit diagram for explaining the configuration of the sense amplifier shown in FIG. 22. Referring to FIG. 23, the sense amplifier SA according to the second embodiment is different from the configuration in the first embodiment shown in FIG. 16 in that NAND gates 91, 92 are arranged instead of inverters 81, 82, and P-type transistors 93, 94 are further arranged. The configurations of the other parts of FIG. 23 are the same as those in FIG. 16, so detailed descriptions will not be repeated.

[0143] The NAND gate 91 outputs the negative logical product (NAND) of the voltage SAT at the node Nx and the enable signal SAE as the read data RDT. Similarly, the NAND gate 92 outputs the negative logical product (NAND) of the voltage SAB at the node Ny and the enable signal SAE as the inverted read data RDTb.

[0144] Therefore, during the period when the enable signal SAE is "0", the read data RDT and the inverted read data RDTb are fixed at "1". During the period when the enable signal SAE is "1", the NAND gates 91 and 92 output the inverted levels of the voltages SAT and SAB as the read data RDT and the inverted read data RDTb, respectively, similar to the inverters 81, 82 in FIG. 15.

[0145] The transistor 93 is electrically connected between the power supply wiring PLv and the memory cell 10x without sandwiching the node Nx and the selector 11x. The output signal of the NAND gate 91, that is, the read data RDT, is input to the gate of the transistor 93.

[0146] Similarly, the transistor 94 is electrically connected between the power supply wiring PLv and the memory cell 10y without sandwiching the node Ny and the selector 11y therebetween. The output signal of the NAND gate 92, i.e., the inverted read data RDTb, is input to the gate of the transistor 94.

[0147] FIG. 24 shows an operation waveform diagram of the sense amplifier SA shown in FIG. 22. In the second embodiment, the operation of the sense amplifier SA in the precharge period Ta, the sampling period Tb, and the sense period Tc is the same as that in the second embodiment (FIG. 17) except that the read data RDT and the inverted read data RDTb are set to "1" in the precharge period Ta and the sampling period Tb.

[0148] That is, in the precharge period Ta, each of the nodes Nx and Ny is precharged by turning on the transistors 79x and 79y, so the voltages SAT and SAB are set to "1". In the second embodiment, since the enable signal SAE input to the NAND gates 91 and 92 is "0", the read data RDT and the inverted read data RDTb are "1". As a result, the transistors 93 and 94 are maintained in the off state.

[0149] Furthermore, in the sampling period Tb, a voltage difference corresponding to the current difference between the cell currents Icellx and Icelly is generated between the nodes Nx and Ny. In FIG. 24, an example of Icellx < Icelly is shown as in FIG. 17, so the voltage drop rate of the voltage SAT (node Nx) is smaller than the voltage drop rate of the voltage SAB (node Ny), and as a result, SAT > SAB. Also in the sampling period Tb, since the enable signal SAE is "0", the read data RDT and the inverted read data RDTb are "1". As a result, the transistors 93 and 94 are maintained in the off state.

[0150] During the sense period Tc, due to the off state of selectors 11x and 11y, memory cells 10x and 10y are electrically disconnected from nodes Nx and Ny. Then, by the amplification operation of the CMOS operational amplifier formed by transistors 72 to 75, the voltage difference between nodes Nx and Ny is amplified. As a result, in the example of FIG. 24 where the sense period Tc starts in the state of SAB < SAT, similar to FIG. 17, a voltage difference occurs between nodes Nx and Ny such that the voltage SAT rises to "1" while the voltage SAB drops to "0".

[0151] During the sense period Tc, since the enable signal SAE is "1", the output signals of NAND gates 91 and 92 become the inverted levels of voltages SAT and SAB. Then, transistors 93 and 94 are selectively turned on according to the output signals of NAND gates 91 and 92 that follow voltages SAT and SAB.

[0152] In the example of FIG. 24, since the read data RDT = "0" and the inverted read data RDTb = "1" are set, transistor 93 is turned on while transistor 94 is turned off. As a result, the power supply wiring PLv and the memory cell 10x are electrically connected, so a current IPLv equivalent to the cell current Icellx of the memory cell 10x is generated in the power supply wiring PLv.

[0153] During the erase verification period Td, similar to the first embodiment, the enable signal SAE is maintained at "1", while the select signal SLb, different from the first embodiment, is maintained at "1". As a result, the on state of transistor 93 is maintained, and a current IPLv similar to that in the sense period Tc continues to occur during the erase verification period Td.

[0154] FIG. 25 shows a circuit diagram for explaining the current path during the erase verification period for the twin cell 12 in the written state. In FIG. 25, with respect to the circuit diagram of FIG. 23, the path of the current IPLs generated during the erase verification period Td is overwritten.

[0155] Also in FIG. 25, similar to FIGS. 18 and 3(a), among the twin cells 12 in the write state, the memory cell 10x is in the write state (stored data "0") and the memory cell 10y is in the erase state (stored data "1").

[0156] At the end of the sense period Tc, since the voltage SAT is "1" while the voltage SAB is "0", the read data RDT = "0" and the inverted read data RDTb = "1" are set.

[0157] Therefore, during the sense period Tc and the erase verification period Td, while the transistor 94 is turned off, the transistor 93 is turned on, and a current IPLv corresponding to the cell current of the memory cell 10x in the write state is generated in the power supply line PLv.

[0158] In contrast to the example of FIG. 25, when the memory cell 10x is in the erase state (stored data "1") and the memory cell 10y is in the write state (stored data "0"), conversely, at the end of the sense period Tc, due to the amplification operation of the CMOS sense amplifier, a voltage difference is generated between the nodes Nx and Ny such that the voltage SAB is "1" while the voltage SAT is "0".

[0159] According to this voltage difference, the read data RDT = "1" and the inverted read data RDTb = "0" are set, and during the sense period Tc and the erase verification period Td, while the transistor 93 is turned off, the transistor 94 is turned on. As a result, a current IPLv corresponding to the cell current Icelly of the memory cell 10y in the write state is generated in the power supply line PLv.

[0160] Thus, also in the second embodiment, during the erase verification period Td, in each sense amplifier SA, a current IPLv corresponding to the cell current of the memory cell with the smaller cell current among the memory cells 10x and 10y constituting the twin cell 12 is generated in the power supply line PLs.

[0161] FIG. 26 is a circuit diagram for explaining a current path during an erase verification period for a twin cell in an erased state. Also in FIG. 26, with respect to the circuit diagram of FIG. 23, the path of the current IPLv generated during the erase verification period Td is overwritten.

[0162] In the erased twin cell 12, the cell currents of the memory cells 10x and 10y are both equivalent to the cell current in the erased state. However, during the sense period Tc, due to the amplification of the minute voltage difference between the two, while one of the voltages SAT and SAB rises to "1", the other drops to "0". Also in FIG. 26, which of the voltages SAT and SAB rises to "1" is indeterminate.

[0163] During the sense period Tc and the erase verification period Td, either one of the transistors 93 and 94 turns on. As a result, in response to the minute difference in the cell currents of the memory cells 10x and 10y, which are both in the erased state, one of the cell currents of the memory cells 10x and 10y, indicated by a dotted line in FIG. 26, occurs as the current IPLv in the power supply wiring PLv.

[0164] Thus, in the second embodiment, in each sense amplifier SA, a current IPLv similar to the current IPLs in the first embodiment occurs in the power supply wiring PLv. That is, in the second embodiment, the power supply wiring PLv corresponds to an example of the "first power supply wiring", and the power supply wiring PLs corresponds to an example of the "second power supply wiring". Also, in the configuration of FIG. 23, the transistor 93 corresponds to an example of the "first selection switch", and the transistor 94 corresponds to an example of the "second selection switch".

[0165] Referring again to FIG. 22, in the erase verify operation of the non-volatile semiconductor memory device according to the second embodiment, a precharge period Ta, a sampling period Tb, a sense period Tc, and an erase verify period Td of FIG. 24 are provided in this order. As a result, in the erase verify period Td, the above-described current IPLv is generated in the sense amplifiers SA1 to SAn, and thus, in the entire power supply wiring PLv, a verify current Ivf obtained by summing the currents IPLv in the n sense amplifiers SA is generated. As a result, also in the second embodiment, a verify current Ivf similar to that in the first embodiment can be generated.

[0166] As described above, also in the second embodiment, a verify current Ivf similar to that in the first embodiment is generated in a power supply wiring PLv provided separately from the power supply wiring PLs. Since the power supply wiring PLv is connected to the power supply node 55 via the resistance element 51 in the same manner as the power supply wiring PLs in the first embodiment, a voltage Vvf similar to that in the first embodiment can be generated and input to one (-terminal) of the input nodes of the sense amplifier SAv.

[0167] As a result, the sense amplifier SAv can output read data RDTv indicating erase verify information based on the comparison between the verify current Ivf and the reference current Irefn, similar to the first embodiment.

[0168] Specifically, also in the second embodiment, when Ivf > Irefn, the sense amplifier SAv outputs RDTv = "1" as erase verify information indicating that the n twin cells are in the erased state, that is, the address (writing target unit) corresponding to the n memory cells is writable.

[0169] On the other hand, also in the second embodiment, when Ivf < Irefn, RDTv = "0" is output as erase verify information indicating that the n twin cells are in the written state, that is, the address (writing target unit) corresponding to the n memory cells is not writable.

[0170] Thus, also in the complementary read type nonvolatile semiconductor memory device according to the second embodiment, it is possible to generate erase verification information without adding memory cells, and the same effects as those of the first embodiment can be achieved.

[0171] Furthermore, in the nonvolatile semiconductor memory device according to the second embodiment, unlike the first embodiment, an erase verification operation can be executed without connecting the resistance element 51 to the power supply wiring PLs of the sense amplifier SA. As a result, the resistance element 51 is not included in the current path in the sense amplifier SA during a normal data read operation (precharge period Ta, sampling period Tb, and sense period Tc).

[0172] This can prevent the read characteristics of the sense amplifier SA from changing due to the electrical resistance value R1 of the resistance element 51, and thus can prevent a decrease in the data read accuracy from the twin cell 12 by the sense amplifier SA. That is, when the erase verification operation according to the present disclosure is executed using a sense amplifier SA with stringent characteristics, the circuit configuration according to the second embodiment is suitable.

[0173] In FIGS. 23 to 26, similar to the first embodiment, an example in which a current IPLv corresponding to the cell current of the memory cell with the smaller cell current among the memory cells 10x and 10y constituting the twin cell 12 is generated in the power supply wiring PLs during the erase verification operation has been described. However, in the second embodiment in which the power supply wiring PLs for the amplification operation and the power supply wiring PLv for the erase verification operation are provided separately, the current IPLv during erase verification can be configured to correspond to the cell current of the memory cell with the larger cell current among the memory cells 10x and 10y.

[0174] FIG. 28 shows a circuit diagram for explaining the configuration of a sense amplifier in a complementary read type nonvolatile semiconductor memory device according to a modification of the second embodiment.

[0175] Comparing FIG. 28 with FIG. 23, in the sense amplifier SA according to the modification of the second embodiment, the connection destinations of the gates of the P-type transistors 93 and 94 are interchanged with those in FIG. 23. That is, the output signal of the NAND gate 92, i.e., the read data RDTb, is input to the gate of the transistor 93, while the output signal of the NAND gate 91, i.e., the read data RDT, is input to the gate of the transistor 94.

[0176] Regarding the sense amplifier SA shown in FIG. 28 as well, the operation waveforms of the sense amplifier SA during the precharge period Ta, the sampling period Tb, the sense period Tc, and the erase verify period Td are the same as those in FIG. 24. On the other hand, in the modification of FIG. 28, compared with the configuration of FIG. 23, in the erase verify period Td, the selection of which of the transistors 93 and 94 is turned on is opposite to that in the configuration of FIG. 23.

[0177] FIG. 29 shows a circuit diagram for explaining the current path during the erase verify period for the twin cell in the write state in FIG. 28.

[0178] Also in FIG. 29, at the end of the sense period Tc, similar to FIG. 25, the read data RDT = "0" and the inverted read data RDTb = "1" are set. However, since the connection destinations of the transistors 93 and 94 are different from those in FIG. 25, in FIG. 29, the transistor 94 is turned on while the transistor 93 is turned off. As a result, a current IPLv corresponding to the cell current of the memory cell 10y in the erase state, which is the larger current, is generated in the power supply wiring PLv, opposite to that in FIG. 25.

[0179] In addition, in the modification of the second embodiment, contrary to the example in FIG. 29, when the memory cell 10x is in the erased state (stored data "1") and the memory cell 10y is in the written state (stored data "0"), due to the amplification operation of the CMOS sense amplifier, a voltage difference is generated between the nodes Nx and Ny such that the voltage SAB is "1" while the voltage SAT is "0". As a result, in the erase verify period Td, the transistor 93 is On turned on while the transistor 94 is Off As a result, in the power supply wiring PLv, the cell current of the memory cell in the erased state, which has the larger current, 10x flows. Icellx It is understood that a current IPLv corresponding to this occurs.

[0180] Thus, in the modification of the second embodiment, during the erase verification period Td, a current IPLv corresponding to the cell current of the memory cell having the larger cell current among the memory cells 10x and 10y constituting the twin cell 12 is generated in the power supply wiring PLs.

[0181] Also, in the erase verification operation for the twin cell 12 in the erased state, depending on the minute difference in the cell currents of the memory cells 10x and 10y, both of which are in the erased state, the larger one of the cell currents of the memory cells 10x and 10y will occur as the current IPLv in the power supply wiring PLv.

[0182] Therefore, in the configuration of the second embodiment in which the power supply wirings PLs and PLv are separately arranged, regardless of which of the memory cells 10x and 10y constituting the twin cell 12, the memory cell having the larger cell current and the memory cell having the smaller cell current are connected to the power supply wiring PLv to generate the current IPLv, the erase verification operation can be executed. At this time, which of the memory cell having the larger cell current and the memory cell having the smaller cell current generates the current IPLv will be determined in advance by the connection destination of the gates of the transistors 93 and 94, as described with reference to FIGS. 23 and 28.

[0183] Note that in FIG. 22 according to the second embodiment as well, a modification in which the voltage Vr output from the same constant voltage source 16 as in FIG. 27 is input to the sense amplifier SAv can be applied. That is, in the present embodiment, in the sense amplifier SAv, as long as it is based on the verification current Ivf flowing through the power supply wiring PLs (first embodiment) or the power supply wiring PLv (second embodiment), the erase verification information RDTv may be generated without depending on the comparison with the reference current Irefn.

[0184] In addition, in the present embodiment, the memory cell to be complementarily read out has been described as a flash memory, but the present disclosure is not limited to the flash memory. Specifically, the present disclosure is commonly applicable to a complementary read type nonvolatile semiconductor memory device configured using a memory cell in which the cell current changes depending on whether the stored data is "1" or "0". Specifically, as long as the writing operation is performed by rewriting the stored data of one of the twin cells to the other of "0" and "1" from the erased state in which the stored data of each memory cell is aligned to either "0" or "1", the generation of the erase verification information indicating whether all the memory cells included in a certain section of twin cells are in the erased state can be commonly applied.

[0185] Regarding the plurality of embodiments described above, including combinations not mentioned in the specification, it is also confirmed that the configurations described in each embodiment can be appropriately combined within a range where no inconsistencies or contradictions occur, which has been planned since the initial filing.

[0186] As described above, the invention made by the present inventor has been specifically described based on the embodiments. However, it goes without saying that the present invention is not limited to the above embodiments and can be variously modified without departing from the gist thereof.

Description of Reference Numerals

[0187] 10, 10v, 10x, 10y memory cells, 11, 11v, 11x, 11y selectors, 12 twin cells, 15, 15v reference cells, 16 constant voltage source, 51, 52 resistance elements, 55, 56 power supply nodes, 100, 101 regions, 200, 200v, 200vn, 201, 201v, 201vn distribution curves (cell current), IPLs, IPLv currents (power supply lines), Icell, Icellv, Icellx, Icelly cell currents, Iref, Irefn, Iref* reference currents, Ivf verify current, PCHGb precharge signal, PLs, PLv power supply lines, RDT, RDT1~RDTn read data, RDTb inverted read data, RDTv read data (erase verify information), SA, SA1~SAn, SAv sense amplifiers, SAE enable signal, SLb selection signal, Ta precharge period, Tb sampling period, Tc sense period, Td erase verify period, Vpp1, Vpp2 power supply voltages, Vref, Vrefn, Vref* reference voltages.< / n> < / n> < / n> < / n>

Claims

1. Comprising a plurality of twin cells classified into a plurality of sections, Each of the plurality of twin cells, Including first and second memory cells in which the cell current passing through the data read state differs according to binary stored data, Each of the twin cells is in either an erased state in which the stored data is uniform or a written state in which the stored data is different, between the first and second memory cells, Each of the plurality of sections includes n (n: an integer of 2 or more) of the twin cells, n first amplifiers connected in parallel to the n twin cells, A second amplifier that generates erase verification information indicating whether all of the n twin cells are in the erased state, Further comprising a first power supply wiring, Each of the n first amplifiers forms a current path between one of the first and second memory cells, which is a predetermined one of the smaller and larger cell currents among the first and second memory cells in the data read state, and the first power supply wiring in the erase verification operation, The second amplifier generates the erase verification information based on the current flowing through the first power supply wiring in the erase verification operation, a non-volatile semiconductor memory device.

2. The second amplifier generates the erase verification information according to a comparison result between the current flowing through the first power supply wiring and a predetermined reference current, The stored data has a first level and a second level, The first and second memory cells of the twin cells in the erased state store the first level, whereas the first and second memory cells of the twin cells in the written state store one of the first level and the second level each, The reference current is set to a current value between a current distribution curve of n times the first current, which is the cell current when each of the first and second memory cells holds the first level, and a current distribution curve of n times the second current, which is the cell current when each of the first and second memory cells holds the second level, the non-volatile semiconductor memory device according to Claim 1.

3. The second amplifier generates the erase verification information based on a comparison result between a first voltage that changes depending on a voltage drop generated in a first resistance element connected between the first power supply wiring and a power supply node, and a second voltage that changes depending on a voltage drop generated in a second resistance element through which the reference current passes, the non-volatile semiconductor memory device according to Claim 2.

4. The non-volatile semiconductor memory device according to claim 1, wherein the second amplifier generates the erase verification information based on a first voltage that changes depending on a voltage drop generated in a first resistance element connected between the first power supply line and a power supply node.

5. The one memory cell is the memory cell having a smaller cell current among the first and second memory cells, Each of the n first amplifiers, includes a sense amplifier that executes an amplification operation of selectively connecting one of the first node and the second node to the first power supply line according to a comparison of magnitudes between a current flowing through the first node connected to the first memory cell and a current flowing through the second node connected to the second memory cell, In the erase verification operation, the first amplifier forms a current path between the one memory cell and the first power supply line using a current path formed in the sense amplifier according to a voltage difference generated between the first node and the second node by the amplification operation. The non-volatile semiconductor memory device according to claim 1.

6. A non-volatile semiconductor memory device, comprising: a plurality of twin cells classified into a plurality of sections, Each of the plurality of twin cells, includes first and second memory cells in which a cell current passing through in a data read state differs according to binary stored data, Each of the twin cells is in either an erase state in which the stored data is the same or a write state in which the stored data is different between the first and second memory cells, Each of the plurality of sections includes n (n: an integer of 2 or more) of the twin cells, The non-volatile semiconductor memory device, n first amplifiers connected in parallel to the n twin cells, a second amplifier that generates erase verification information indicating whether or not all of the n twin cells are in the erase state, and further includes a first power supply line, In the erase verification operation, each of the n first amplifiers forms a current path between one of the first and second memory cells having a smaller and a larger cell current, which are predetermined, among the first and second memory cells in the data read state and the first power supply line, In the erase verification operation, the second amplifier generates the erase verification information based on a current flowing through the first power supply line, The non-volatile semiconductor memory device, further includes a second power supply line provided separately from the first power supply line, The one memory cell is the memory cell with the smaller cell current or the memory cell with the larger cell current among the first and second memory cells, Each of the n first amplifiers is a sense amplifier that executes an amplification operation of selectively connecting one of the first node and the second node to the second power supply wiring according to a comparison of the magnitudes of the current flowing through the first node connected to the first memory cell and the current flowing through the second node connected to the second memory cell, a first selection switch electrically connected between the first power supply wiring and the first memory cell, and a second selection switch electrically connected between the first power supply wiring and the second memory cell, wherein the first selection switch and the second selection switch are selectively turned on so that an electrical connection is established between the one memory cell and the first power supply wiring according to the voltage difference generated between the first node and the second node by the amplification operation in the erase verification operation, and the non-volatile semiconductor memory device.

7. The non-volatile semiconductor memory device according to claim 5 or 6, wherein the sense amplifier is constituted by a CMOS sense amplifier.

8. Each of the plurality of sections corresponds to a data writing target unit, The non-volatile semiconductor memory device according to claim 1 or 6, wherein the erase verification information indicates whether the writing target unit is writable.

9. The plurality of sections are specified by an address, The non-volatile semiconductor memory device according to claim 8, wherein the number of bits of the data stored in the address is n.

10. The stored data has a first level and a second level, wherein the first and second memory cells of the twin cell in the erased state store the first level, while the first and second memory cells of the twin cell in the written state store one of the first level and the second level each, The non-volatile semiconductor memory device according to claim 1 or 6, wherein each of the first and second memory cells is constituted by a field effect transistor in which a threshold voltage when holding the stored data of the first level is lower than a threshold voltage when holding the stored data of the second level.

11. The non-volatile semiconductor memory device according to any one of claims 1 to 6, wherein the non-volatile semiconductor memory device is a flash memory.

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