Method for manufacturing a semiconductor device

Abstract

To provide a transistor in which shape defect is hard to occur, a transistor having excellent electric characteristics, and a semiconductor device having excellent electric characteristics.SOLUTION: A transistor 100 includes a semiconductor layer 108, a first insulating layer 110, a metal oxide layer 114, a functional layer 113, and a conductive layer 112. The first insulating layer is positioned on the semiconductor layer, the metal oxide layer is positioned on the first insulating layer, the functional layer is positioned on the metal oxide layer, the conductive layer is positioned on the functional layer, the semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have regions where the layers overlap with each other. In a channel length direction (dashed line A1-A2 direction) of the transistor, end parts of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are positioned inside from an end part of the semiconductor layer. In the functional layer, an etching rate in etchant having one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid or sulfuric acid is slower than the etching rate of the conductive layer.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] One aspect of the present invention relates to a semiconductor device. One aspect of the present invention relates to a display device. One aspect of the present invention relates to a method for manufacturing a semiconductor device or a display device.

[0002] Note that one aspect of the present invention is not limited to the above technical field. Examples of the technical field of one aspect of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof. A semiconductor device refers to all devices that can function by utilizing semiconductor characteristics.

Background Art

[0003] As a semiconductor material applicable to a transistor, an oxide semiconductor using a metal oxide has attracted attention. For example, in Patent Document 1, a semiconductor device is disclosed in which a plurality of oxide semiconductor layers are stacked, and among the plurality of oxide semiconductor layers, an oxide semiconductor layer serving as a channel contains indium and gallium, and the ratio of indium is made larger than the ratio of gallium, thereby increasing the field-effect mobility (sometimes simply referred to as mobility or μFE).

[0004] Since the metal oxide that can be used for the semiconductor layer can be formed by using a sputtering method or the like, it can be used for the semiconductor layer of a transistor constituting a large-sized display device. In addition, since a part of the production equipment for transistors using polycrystalline silicon or amorphous silicon can be improved and utilized, capital investment can be suppressed. Further, a transistor using a metal oxide has a higher field-effect mobility than when using amorphous silicon, so that a high-performance display device provided with a driving circuit can be realized.

[0005] In addition, in display devices, the screen size has a tendency to increase, and development has been carried out with a view to screen sizes of 60 inches or more in diagonal, and even 120 inches or more in diagonal. In addition, the resolution of the screen is also trending towards high definition, such as full high definition (pixel count 1920 × 1080, also referred to as "2K", etc.), ultra high definition (pixel count 3840 × 2160, also referred to as "4K", etc.), and super high definition (pixel count 7680 × 4320, also referred to as "8K", etc.).

[0006] The increase in screen size and high definition tend to increase the wiring resistance within the display unit. In Patent Document 2, in a liquid crystal display device using amorphous silicon transistors, a technique for forming a low-resistance wiring layer using copper (Cu) in order to suppress an increase in wiring resistance is disclosed.

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention aims to provide a transistor that is less likely to have a shape defect. Or, one aspect of the present invention aims to provide a transistor with good electrical characteristics. Or, one aspect of the present invention aims to provide a semiconductor device with good electrical characteristics. Or, one aspect of the present invention aims to provide a semiconductor device with stable electrical characteristics. Or, one aspect of the present invention aims to provide a highly reliable semiconductor device. Or, one aspect of the present invention aims to provide a highly reliable display device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one aspect of the present invention does not need to solve all of these problems. Note that other problems can be extracted from the descriptions in the specification, drawings, claims, etc.

Means for Solving the Problems

[0010] One aspect of the present invention has a transistor, the transistor having a semiconductor layer, a first insulating layer, a metal oxide layer, a functional layer, and a conductive layer. The first insulating layer is located on the semiconductor layer, the metal oxide layer is located on the first insulating layer, the functional layer is located on the metal oxide layer, the conductive layer is located on the functional layer, the semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have overlapping regions, and in the channel length direction of the transistor, the ends of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are located inside the ends of the semiconductor layer. The functional layer is a semiconductor device in which the etching rate in a certain etchant is slower than the etching rate of the conductive layer.

[0011] Also, one aspect of the present invention has a transistor, the transistor having a semiconductor layer, a first insulating layer, a metal oxide layer, a functional layer, and a conductive layer. The first insulating layer is located on the semiconductor layer, the metal oxide layer is located on the first insulating layer, the functional layer is located on the metal oxide layer, the conductive layer is located on the functional layer, the semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have overlapping regions, and in the channel length direction of the transistor, the ends of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are located inside the ends of the semiconductor layer. The functional layer is a semiconductor device in which the etching rate in an etchant having hydrogen peroxide is slower than the etching rate of the conductive layer.

[0012] Also, one aspect of the present invention has a transistor, the transistor having a semiconductor layer, a first insulating layer, a metal oxide layer, a functional layer, and a conductive layer. The first insulating layer is located on the semiconductor layer, the metal oxide layer is located on the first insulating layer, the functional layer is located on the metal oxide layer, the conductive layer is located on the functional layer, the semiconductor layer, the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer have overlapping regions, and in the channel length direction of the transistor, the ends of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are located inside the ends of the semiconductor layer. The functional layer has an etching rate in an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, or sulfuric acid that is slower than the etching rate of the conductive layer, and is a semiconductor device.

[0013] Also, in the semiconductor device described above, it is preferable that the upper surface shapes of the first insulating layer, the metal oxide layer, the functional layer, and the conductive layer are substantially the same.

[0014] Also, in the semiconductor device described above, it is preferable that the upper surface shapes of the first insulating layer, the metal oxide layer, and the functional layer are substantially the same, and the end of the conductive layer is located inside the end of the first insulating layer.

[0015] Also, in the semiconductor device described above, it is preferable that the upper surface shapes of the first insulating layer and the metal oxide layer are substantially the same, the upper surface shapes of the functional layer and the conductive layer are substantially the same, and the end of the conductive layer is located inside the end of the first insulating layer.

[0016] Also, in the semiconductor device described above, it is preferable that the upper surface shapes of the metal oxide layer, the functional layer, and the conductive layer are substantially the same, and the end of the conductive layer is located inside the end of the first insulating layer.

[0017] Also, in the semiconductor device described above, it is preferable that the upper surface shapes of the metal oxide layer and the functional layer are substantially the same, the end of the conductive layer is located inside the end of the metal oxide layer, and the end of the metal oxide layer is located inside the end of the first insulating layer.

[0018] Further, in the semiconductor device described above, it further has a second insulating layer. The semiconductor layer has a first region that does not overlap with the first insulating layer. The second insulating layer is in contact with the first region, and the second insulating layer preferably contains silicon, nitrogen, and hydrogen.

Advantages of the Invention

[0019] According to one aspect of the present invention, a transistor with less likely to have a shape defect can be provided. Or, a transistor with good electrical characteristics can be provided. Or, a semiconductor device with good electrical characteristics can be provided. Or, a semiconductor device with stable electrical characteristics can be provided. Or, a highly reliable semiconductor device can be provided. Or, a highly reliable display device can be provided.

[0020] Note that the description of these effects does not prevent the existence of other effects. Note that one aspect of the present invention does not necessarily have to have all of these effects. Note that other effects can be extracted from the descriptions in the specification, drawings, claims, etc.

Brief Description of the Drawings

[0021]

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Embodiments for Carrying Out the Invention

[0022] Hereinafter, embodiments will be described with reference to the drawings. However, the embodiments can be implemented in many different ways, and it is easily understood by those skilled in the art that the forms and details can be variously changed without departing from the spirit and its scope. Therefore, the present invention is not construed as being limited to the description content of the following embodiments.

[0023] Also, in each of the drawings described in this specification, the size of each component, the thickness of the layer, or the region may be exaggerated for clarity.

[0024] Also, the ordinal numbers "first", "second", "third", etc. used in this specification are attached to avoid confusion of components and are not numerically limiting.

[0025] Also, in this specification, terms indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, it is not limited to the terms described in the specification and can be appropriately rephrased according to the situation.

[0026] Also, in this specification and the like, the functions of the source and drain of a transistor may be interchanged when transistors with different polarities are employed or when the direction of current changes in a circuit operation. For this reason, the terms source and drain can be used interchangeably.

[0027] Note that in this specification and the like, the channel length direction of a transistor refers to one of the directions parallel to the straight line connecting the source region and the drain region at the shortest distance. That is, the channel length direction corresponds to one of the directions of the current flowing through the semiconductor layer when the transistor is in the on state. Also, the channel width direction refers to the direction orthogonal to the channel length direction. Note that depending on the structure and shape of the transistor, the channel length direction and the channel width direction may not be uniquely determined.

[0028] In addition, in this specification and the like, "electrically connected" includes cases where connection is made through "something having some electrical effect". Here, "something having some electrical effect" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets. For example, "something having some electrical effect" includes electrodes, wiring, switching elements such as transistors, resistance elements, inductors, capacitors, and other elements having various functions.

[0029] In addition, in this specification and the like, the term "film" and the term "layer" can be mutually interchanged. For example, the terms "conductive layer" and "insulating layer" may be mutually interchangeable with the terms "conductive film" and "insulating film" in some cases.

[0030] In addition, in this specification and the like, unless otherwise specified, the off-current refers to the drain current when the transistor is in the off state (also referred to as the non-conducting state or the cut-off state). The off state, unless otherwise specified, for an n-channel type transistor, is a state where the voltage V between the gate and the source gs is lower than the threshold voltage V th (for a p-channel type transistor, higher than V th ).

[0031] In this specification and the like, a display panel, which is an aspect of a display device, has a function of displaying (outputting) an image or the like on a display surface. Therefore, the display panel is an aspect of an output device.

[0032] In addition, in this specification and the like, something in which a connector such as an FPC (Flexible Printed Circuit) or a TCP (Tape Carrier Package) is attached to the substrate of the display panel, or something in which an IC is mounted on the substrate by a COG (Chip On Glass) method or the like may be referred to as a display panel module, a display module, or simply a display panel.

[0033] In addition, in this specification and the like, a touch panel, which is an aspect of a display device, has a function of displaying an image or the like on a display surface, and a function as a touch sensor that detects when a detection object such as a finger or a stylus touches, presses, or approaches the display surface. Therefore, the touch panel is an aspect of an input / output device.

[0034] The touch panel can also be referred to as, for example, a display panel (or display device) with a touch sensor, or a display panel (or display device) with a touch sensor function. The touch panel can also be configured to include a display panel and a touch sensor panel. Alternatively, it can be configured to have a function as a touch sensor inside or on the surface of the display panel.

[0035] Also, in this specification and the like, a substrate of a touch panel on which a connector or an IC is mounted may be referred to as a touch panel module, a display module, or simply a touch panel.

[0036] (Embodiment 1) In this embodiment, a semiconductor device, a display device, and a manufacturing method thereof according to an aspect of the present invention will be described.

[0037] One aspect of the present invention is a transistor having a semiconductor layer in which a channel is formed on a formation surface, a gate insulating layer (also referred to as a first insulating layer) on the semiconductor layer, a functional layer on the gate insulating layer, and a conductive layer (also referred to as a first conductive layer) that functions as a gate electrode on the functional layer. The semiconductor layer is preferably configured to include a metal oxide exhibiting semiconductor characteristics (hereinafter also referred to as an oxide semiconductor).

[0038] It is preferable to use a low-resistance material for the conductive layer. By using a low-resistance material for the conductive layer, the parasitic resistance can be reduced, and a transistor having a high on-current can be obtained, and a semiconductor device having a high on-current can be obtained. Further, in a large display device or a high-definition display device, by reducing the wiring resistance, signal delay can be suppressed, and high-speed driving becomes possible. As the conductive layer, copper, silver, gold, aluminum, or the like can be used. In particular, copper is preferable because of its excellent mass productivity.

[0039] When the end of the layer to be formed of the conductive layer is located inside the end of the conductive layer, that is, when so-called undercut occurs, the coverage of the layer formed later decreases, and defects such as step breaks and looseness occur in the layer. Shape defects such as undercut may cause problems such as variations in the electrical characteristics of the transistor.

[0040] In one aspect of the present invention, a functional layer is provided as the layer to be formed of the conductive layer, and the etching rate of the etchant used for processing the conductive layer is set to be approximately the same as or slower than that of the conductive layer. By adopting such a configuration, the occurrence of undercut can be suppressed, and a transistor with less likely shape defects can be obtained. Further, a transistor with good electrical characteristics can be obtained.

[0041] Further, it is preferable to use a material for the functional layer that has high adhesion to the conductive layer. By having high adhesion between the functional layer and the conductive layer, it is possible to suppress the etchant from entering between the functional layer and the conductive layer and generating voids when forming the functional layer and the conductive layer.

[0042] Hereinafter, more specific examples will be described with reference to the drawings.

[0043] <Configuration Example 1> FIG. 1(A) is a top view of the transistor 100, FIG. 1(B) corresponds to a cross-sectional view of the cut surface along the dashed line A1 - A2 shown in FIG. 1(A), and FIG. 1(C) corresponds to a cross-sectional view of the cut surface along the dashed line B1 - B2 shown in FIG. 1(A). In FIG. 1(A), a part of the components (such as the protective layer) of the transistor 100 is omitted in the illustration. Also, the direction of the dashed line A1 - A2 corresponds to the channel length direction, and the direction of the dashed line B1 - B2 corresponds to the channel width direction. Also, for the top view of the transistor, in the following drawings, as in FIG. 1(A), a part of the components will be omitted in the illustration.

[0044] The transistor 100 is provided on the substrate 102 and has an insulating layer 103, a semiconductor layer 108, an insulating layer 110, a metal oxide layer 114, a functional layer 113, a conductive layer 112, an insulating layer 116, an insulating layer 118, etc. The island-shaped semiconductor layer 108 is provided on the insulating layer 103. The insulating layer 110 is provided to cover a part of the upper surface of the insulating layer 103 and a part of the upper surface of the semiconductor layer 108. The metal oxide layer 114, the functional layer 113, and the conductive layer 112 are laminated in this order on the insulating layer 110 and have a portion that overlaps with the semiconductor layer 108.

[0045] The insulating layer 110, the metal oxide layer 114, the functional layer 113, and the conductive layer 112 are processed so that their upper surface shapes are substantially the same as each other.

[0046] In this specification, etc., "the upper surface shapes are substantially the same" means that at least a part of the contours overlap between the laminated layers. For example, it includes the case where the upper layer and the lower layer are processed by the same mask pattern or a part of them is processed by the same mask pattern. However, strictly speaking, the contours may not overlap exactly, and the end of the upper layer may be located inside the end of the lower layer or the end of the upper layer may be located outside the end of the lower layer. In this case, it is also said that "the upper surface shapes are substantially the same".

[0047] The insulating layer 116 is provided to cover the upper surface and the side surface of the conductive layer 112, the side surface of the functional layer 113, the side surface of the metal oxide layer 114, the side surface of the insulating layer 110, the upper surface and the side surface of the semiconductor layer 108, and the upper surface of the insulating layer 103. The insulating layer 118 is provided to cover the insulating layer 116. The insulating layer 116 and the insulating layer 118 function as a protective layer and can suppress the diffusion of impurity elements from the outside.

[0048] A part of the functional layer 113 and the conductive layer 112 functions as a gate electrode. A part of the insulating layer 110 functions as a gate insulating layer. The transistor 100 is a so-called top-gate type transistor in which a gate electrode is provided on the semiconductor layer 108.

[0049] Also, as shown in FIGS. 1(A) and 1(B), the transistor 100 may have a conductive layer 120a and a conductive layer 120b on the insulating layer 118. The conductive layer 120a and the conductive layer 120b function as a source electrode or a drain electrode. The conductive layer 120a and the conductive layer 120b are electrically connected to a region 108N, which will be described later, through an opening 141a or an opening 141b provided in the insulating layer 118 and the insulating layer 116, respectively.

[0050] The semiconductor layer 108 preferably contains a metal oxide.

[0051] For example, the semiconductor layer 108 preferably has indium, an element M (the element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium), and zinc. In particular, the element M is preferably one or more selected from aluminum, gallium, yttrium, or tin.

[0052] In particular, it is preferable to use an oxide containing indium, gallium, and zinc as the semiconductor layer 108.

[0053] The semiconductor layer 108 may have a stacked structure in which layers with different compositions, or layers with different crystallinities, or layers with different impurity concentrations are stacked.

[0054] As the conductive layer 112, one or more selected from copper, silver, gold, or aluminum can be used. In particular, copper is preferable because it has low resistance and excellent mass productivity.

[0055] The metal oxide layer 114 located between the insulating layer 110 and the functional layer 113 functions as a barrier film that prevents oxygen contained in the insulating layer 110 from diffusing to the conductive layer 112 side. Furthermore, the metal oxide layer 114 also functions as a barrier film that prevents hydrogen and water contained in the conductive layer 112 from diffusing to the insulating layer 110 side. For the metal oxide layer 114, for example, a material that is at least less permeable to oxygen and hydrogen than the insulating layer 110 can be used.

[0056] Even when a metal material that easily attracts oxygen, such as aluminum or copper, is used for the conductive layer 112, the metal oxide layer 114 can prevent oxygen from diffusing from the insulating layer 110 to the conductive layer 112. Also, even when the conductive layer 112 contains hydrogen, it can prevent hydrogen from diffusing from the conductive layer 112 through the insulating layer 110 to the semiconductor layer 108. As a result, the carrier density in the channel formation region of the semiconductor layer 108 can be made extremely low.

[0057] As the metal oxide layer 114, an insulating material or a conductive material can be used. When the metal oxide layer 114 has insulating properties, it functions as part of the gate insulating layer. On the other hand, when the metal oxide layer 114 has conductive properties, it functions as part of the gate electrode.

[0058] It is preferable to use an insulating material having a higher dielectric constant than silicon oxide as the metal oxide layer 114. In particular, using an aluminum oxide film, a hafnium oxide film, or a hafnium aluminate film, etc. is preferable because the driving voltage can be reduced.

[0059] As the metal oxide layer 114, for example, a conductive oxide such as indium oxide, indium tin oxide (ITO), or indium tin oxide containing silicon (ITSO) can also be used. In particular, a conductive oxide containing indium is preferable because of its high conductivity.

[0060] Further, as the metal oxide layer 114, it is preferable to use an oxide material containing one or more of the same elements as the semiconductor layer 108. In particular, it is preferable to use an oxide semiconductor material applicable to the semiconductor layer 108. At this time, as the metal oxide layer 114, it is preferable to apply a metal oxide film formed using the same sputtering target as the semiconductor layer 108 because the apparatus can be shared.

[0061] Alternatively, when a metal oxide material containing indium and gallium is used for both the semiconductor layer 108 and the metal oxide layer 114, it is preferable to use a material having a higher gallium composition (content ratio) than the semiconductor layer 108 because the blocking property against oxygen can be further enhanced. At this time, for the semiconductor layer 108, by using a material having a higher indium composition than the metal oxide layer 114, the field-effect mobility of the transistor 100 can be increased.

[0062] Also, the metal oxide layer 114 is preferably formed using a sputtering apparatus. For example, when forming an oxide film using a sputtering apparatus, oxygen can be suitably added to the insulating layer 110 and the semiconductor layer 108 by forming it in an atmosphere containing oxygen gas.

[0063] The functional layer 113 located between the metal oxide layer 114 and the conductive layer 112 is preferably made of a conductive material having oxidation resistance. By using a material having oxidation resistance, an increase in the resistance of the functional layer 113 can be suppressed.

[0064] Also, the etching rate of the metal oxide layer 114 and the functional layer 113 in the etchant used for processing the conductive layer 112 is preferably about the same as or slower than that of the conductive layer 112.

[0065] When the etching rates of the metal oxide layer 114 and the functional layer 113 are faster than that of the conductive layer 112, an undercut is likely to occur where the ends of the metal oxide layer 114 and the functional layer 113 are located more inward than the ends of the conductive layer 112. When an undercut occurs, the covering properties of the subsequently formed insulating layer 116 and insulating layer 118 deteriorate, and defects such as steps or low-density regions (also called looseness) occur in the insulating layer 116 and insulating layer 118.

[0066] In one aspect of the present invention, by configuring the etching rates of the metal oxide layer 114 and the functional layer 113 to be approximately the same as or slower than that of the conductive layer 112, the occurrence of undercuts can be suppressed, and a transistor with less likely shape defects can be obtained. Also, a transistor with good electrical characteristics can be obtained.

[0067] Also, the functional layer 113, the metal oxide layer 114, and the conductive layer 112 can be formed in the same process using the etchant used for processing the conductive layer 112. Furthermore, the upper surface shapes of the metal oxide layer 114, the functional layer 113, and the conductive layer 112 can be made to substantially coincide with each other.

[0068] The etching rate of the insulating layer 110 is preferably slower than those of the metal oxide layer 114, the functional layer 113, and the conductive layer 112. By configuring the etching rate of the insulating layer 110 to be slower than those of the metal oxide layer 114, the functional layer 113, and the conductive layer 112, the amount of etching of the insulating layer 110 can be reduced when the metal oxide layer 114, the functional layer 113, and the conductive layer 112 are formed.

[0069] Further, the functional layer 113 preferably has high adhesion to the metal oxide layer 114 and the conductive layer 112. For example, in a configuration where the conductive layer 112 is formed on the metal oxide layer 114, if the adhesion between these layers is low, when an etchant intrudes between the metal oxide layer 114 and the conductive layer 112 during the formation of the metal oxide layer 114 and the conductive layer 112, voids may occur between the metal oxide layer 114 and the conductive layer 112. In one aspect of the present invention, by providing the functional layer 113 between the metal oxide layer 114 and the conductive layer 112, the adhesion of the metal oxide layer 114, the functional layer 113, and the conductive layer 112 is enhanced, and the occurrence of voids between these layers can be suppressed, enabling a transistor with less likelihood of shape defects. Further, a transistor with good electrical characteristics can be obtained.

[0070] Further, the functional layer 113 preferably has a low emission amount of impurities having hydrogen. Examples of impurities having hydrogen include hydrogen and water. When impurities having hydrogen are emitted from the functional layer 113, when the hydrogen reaches the channel formation region of the semiconductor layer 108, it combines with oxygen in the channel formation region and desorbs as water, and oxygen deficiency (hereinafter, also referred to as V O ) may be formed in the channel formation region. Further, when oxygen deficiency (V O ) and hydrogen are present in the channel formation region, a state in which hydrogen enters oxygen deficiency (V O ) (hereinafter, also referred to as V O H) may be formed. V O H serves as a carrier generation source and may adversely affect the electrical characteristics and reliability of the transistor. By using the functional layer 113 with a low emission amount of impurities having hydrogen, good electrical characteristics and reliability can be obtained.

[0071] Further, the functional layer 113 preferably has a low emission amount of impurities containing oxygen. Examples of the impurities containing oxygen include oxygen, water, and the like. When impurities containing oxygen are emitted from the functional layer 113, if the oxygen reaches the conductive layer 112, the resistance of the conductive layer 112 may increase. By using the functional layer 113 with a low emission amount of impurities containing oxygen, it is possible to suppress an increase in the resistance of the conductive layer 112.

[0072] As the functional layer 113, a metal oxide can be used. For example, oxides containing indium such as indium oxide, indium tin oxide (ITO), and indium tin oxide containing silicon (ITSO) can be used. Since ITSO is difficult to crystallize due to containing silicon and has high flatness, the adhesion with the film formed on ITSO becomes high, which is particularly preferable. Further, metal oxides such as indium zinc oxide, zinc oxide, and zinc oxide containing gallium can be used.

[0073] Further, as the functional layer 113, an oxide having indium, element M (element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, or magnesium), and zinc can be used. In particular, it is preferable that element M is one or more selected from aluminum, gallium, yttrium, or tin. For example, in In-Ga-Zn oxide, it is preferable that the atomic ratio of In is larger than the atomic ratio of Ga because the conductivity increases. In particular, it is preferable that the atomic ratio of In, element M, and Zn in the functional layer 113 is In:M:Zn = 4:2:3 or in the vicinity thereof. Alternatively, it is preferable that the atomic ratio of In, M, and Zn is In:M:Zn = 5:1:6 or in the vicinity thereof. Further, as the composition of the semiconductor layer 108, the atomic ratios of In, element M, and Zn in the semiconductor layer 108 may be made substantially equal. That is, a material having an atomic ratio of In, element M, and Zn of In:M:Zn = 1:1:1 or in the vicinity thereof may be included.

[0074] Also, as the functional layer 113, a metal such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten, or an alloy mainly composed of this can be used.

[0075] It is preferable that the functional layer 113 uses a material different from the metal oxide layer 114 and the conductive layer 112. In this specification and the like, different materials refer to materials with different constituent elements or materials with the same constituent elements but different compositions. Even when the metal oxide layer 114 has low adhesion to the conductive layer 112, by providing a functional layer 113 having a material different from the metal oxide layer 114 between the metal oxide layer 114 and the conductive layer 112, the adhesion to the metal oxide layer 114 and the conductive layer 112 can be enhanced.

[0076] The functional layer 113 may have a structure in which two or more of the above-described materials are laminated.

[0077] The semiconductor layer 108 has a channel formation region that overlaps with the conductive layer 112 via the insulating layer 110. Further, the semiconductor layer 108 has a pair of regions 108N that sandwich the channel formation region. The region 108N is a region in the semiconductor layer 108 that does not overlap with either the conductive layer 112 or the insulating layer 110 and is a region in contact with the insulating layer 116.

[0078] The region 108N can also be referred to as a region having a lower resistance than the channel formation region, a region having a high carrier density, a region having a high oxygen defect density, a region having a high impurity concentration, or an n-type region.

[0079] Region 108N is a region containing impurity elements (hereinafter referred to as the first elements). Examples of the first elements include hydrogen, boron, carbon, nitrogen, fluorine, phosphorus, sulfur, arsenic, aluminum, magnesium, or noble gases. Representative examples of noble gases include helium, neon, argon, krypton, and xenon. In particular, it is preferable to contain boron, phosphorus, magnesium, or aluminum. Also, two or more of these elements may be contained.

[0080] It is preferable to use an oxide film for the insulating layer 103 and the insulating layer 110 in contact with the channel formation region of the semiconductor layer 108. For example, an oxide film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film can be used. Thereby, oxygen desorbed from the insulating layer 103 or the insulating layer 110 can be supplied to the channel formation region of the semiconductor layer 108 during heat treatment or the like in the manufacturing process of the transistor 100, and oxygen deficiency in the semiconductor layer 108 can be reduced. In FIGS. 1(B) and 1(C), the insulating layer 110 and the insulating layer 103 are shown in a single-layer structure, but they may each have a laminated structure of two or more layers.

[0081] Also, the insulating layer 103 preferably has a laminated structure of a nitride film and an oxide film on the nitride film. For example, silicon nitride, silicon oxynitride, aluminum nitride, aluminum oxynitride, etc. can be used as the nitride film. By providing a nitride film below the insulating layer 103, diffusion of impurities from the layer below the insulating layer 103 to the layer above the insulating layer 103 can be suppressed. At the same time, by providing an oxide film on the upper side of the insulating layer 103 in contact with the channel formation region, oxygen desorbed from the insulating layer 103 can be supplied to the channel formation region. As the insulating layer 103, for example, a laminated structure of a silicon nitride film and a silicon oxynitride film on the silicon nitride film can be used.

[0082] In this specification and the like, oxynitride refers to a substance having a higher oxygen content than nitrogen in its composition, and oxynitrides are included in oxides. Nitroxide refers to a substance having a higher nitrogen content than oxygen in its composition, and nitroxides are included in nitrides.

[0083] A part of the end of the insulating layer 110 is located on the semiconductor layer 108. The insulating layer 110 overlaps with the conductive layer 112 and has a region that functions as a gate insulating layer.

[0084] Here, it is preferable that the impurity concentration in the region 108N has a concentration gradient such that the closer it is to the insulating layer 116, the higher the concentration. Thereby, compared with the case where a uniform concentration is set throughout the region 108N, the total amount of the first element in the region 108N can be lowered, so that the amount of impurities that can diffuse into the channel formation region due to the influence of heat or the like during the manufacturing process can be kept low. Also, since the upper part of the region 108N has a lower resistance, the contact resistance with the conductive layer 120a (or the conductive layer 120b) can be more effectively reduced.

[0085] As will be described later, the process of adding the first impurity element to the region 108N can be performed using the insulating layer 110 as a mask. Thereby, the region 108N can be formed self-alignedly.

[0086] The region 108N has an impurity concentration of 1×10 19 atoms / cm 3 or more and 1×10 23 atoms / cm 3 or less, preferably 5×10 19 atoms / cm 3 or more and 5×10 22 atoms / cm 3 or less, and more preferably includes a region of 1×10 20 atoms / cm 3 or more and 1×10 22 atoms / cm 3 or less.

[0087] The concentration of impurities contained in the region 108N can be analyzed by, for example, secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), etc. When XPS analysis is used, the concentration distribution in the depth direction can be known by combining ion sputtering from the front side or rear side with XPS analysis.

[0088] In addition, in the region 108N, the first element is preferably present in an oxidized state. For example, it is preferable to use an element that is easily oxidized, such as boron, phosphorus, magnesium, aluminum, or silicon, as the first element. Since such an element that is easily oxidized can be stably present in an oxidized state by bonding with oxygen in the semiconductor layer 108, even if a high temperature (for example, 400° C. or higher, 600° C. or higher, or 800° C. or higher) is applied in a later process, desorption is suppressed. Furthermore, the first element removes oxygen from the semiconductor layer 108, and many oxygen vacancies are generated in the region 108N. These oxygen vacancies bond with hydrogen in the film to become a carrier supply source, and the region 108N becomes in an extremely low resistance state.

[0089] In addition, when a high-temperature process is performed in a later step, if a large amount of oxygen is supplied to region 108N from the outside or a film in the vicinity of region 108N, the resistance may increase. Therefore, when performing a high-temperature process, it is preferable to perform the process in a state where semiconductor layer 108 is covered with insulating layer 116 that has a high barrier property against oxygen.

[0090] The insulating layer 116 is provided in contact with a region 108N of the semiconductor layer 108.

[0091] The insulating layer 116 functions as a hydrogen supply source for the region 108N. For example, the insulating layer 116 is preferably a film that releases hydrogen when heated. By providing such an insulating layer 116 in contact with the region 108N and performing a heat treatment after the formation of the insulating layer 116, hydrogen can be supplied to the region 108N to reduce the resistance.

[0092] The insulating layer 116 is preferably a film formed using a gas containing a hydrogen element as a film-forming gas during film formation. Thereby, hydrogen can be effectively supplied to the region 108N even during the film formation of the insulating layer 116.

[0093] As the insulating layer 116, for example, an insulating film such as silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum nitride, or aluminum oxynitride can be used.

[0094] The region 108N is in a state containing a large amount of oxygen deficiency due to the addition of the first element as described above. Therefore, in addition to the hydrogen contained in the semiconductor layer 108, by further supplying hydrogen from the insulating layer 116, the carrier density can be increased more.

[0095] The insulating layer 118 functions as a protective layer for protecting the transistor 100. As the insulating layer 118, for example, an inorganic insulating material such as an oxide or a nitride can be used. More specific examples include inorganic insulating materials such as silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate. Also, the insulating layer 118 can be used as a planarization layer. In that case, an organic resin material can be used as the insulating layer 118.

[0096] Here, the case where the insulating layer 116 and the insulating layer 118 have a laminated structure as a protective layer is shown, but if the insulating layer 118 is not necessary, it may not be provided. Also, the insulating layer 118 may have a laminated structure of two or more layers.

[0097] Here, the semiconductor layer 108 and the oxygen deficiency that can be formed in the semiconductor layer 108 will be described.

[0098] Oxygen deficiencies formed in the channel formation region of the semiconductor layer 108 are a problem because they affect transistor characteristics. For example, when an oxygen deficiency is formed in the semiconductor layer 108, hydrogen binds to the oxygen deficiency and can become a carrier supply source. When a carrier supply source is generated in the channel formation region, fluctuations in the electrical characteristics of the transistor 100, typically a shift in the threshold voltage, occur. Therefore, in the channel formation region, it is preferable that there are fewer oxygen deficiencies.

[0099] Therefore, in one aspect of the present invention, the insulating films near the channel formation region of the semiconductor layer 108, specifically, the insulating layer 110 located above the channel formation region and the insulating layer 103 located below, are configured to include an oxide film. By moving oxygen from the insulating layer 103 and the insulating layer 110 to the channel formation region due to heat during the manufacturing process or the like, it becomes possible to reduce oxygen deficiencies in the channel formation region.

[0100] Further, the semiconductor layer 108 preferably has a region where the atomic ratio of In to the element M is greater than 1. The higher the In content, the more the field-effect mobility of the transistor can be improved.

[0101] Here, in the case of a metal oxide containing In, Ga, and Zn, the binding force between In and oxygen is weaker than the binding force between Ga and oxygen. Therefore, when the In content is high, oxygen deficiencies are likely to be formed in the metal oxide film. Further, even when the metal element represented by M is used instead of Ga, there is a similar tendency. When there are many oxygen deficiencies in the metal oxide film, the electrical characteristics of the transistor deteriorate and the reliability decreases.

[0102] However, in one aspect of the present invention, since an extremely large amount of oxygen can be supplied to the channel formation region of the semiconductor layer 108 containing a metal oxide, it becomes possible to use a metal oxide material with a high In content. As a result, a transistor having extremely high field-effect mobility, stable electrical characteristics, and high reliability can be realized.

[0103] For example, a metal oxide in which the atomic number ratio of In to element M is 1.5 or more, or 2 or more, or 3 or more, or 3.5 or more, or 4 or more can be preferably used.

[0104] In particular, it is preferable that the atomic number ratio of In, M, and Zn in the semiconductor layer 108 is In:M:Zn = 4:2:3 or in the vicinity thereof. Or, it is preferable that the atomic number ratio of In, M, and Zn is In:M:Zn = 5:1:6 or in the vicinity thereof. Further, as the composition of the semiconductor layer 108, the atomic number ratio of In, M, and Zn in the semiconductor layer 108 may be made substantially equal. That is, it may contain a material in which the atomic number ratio of In, M, and Zn is In:M:Zn = 1:1:1 or in the vicinity thereof.

[0105] For example, by using the above transistor with a high field-effect mobility in a gate driver that generates a gate signal, a display device with a narrow frame width (also referred to as a narrow frame) can be provided. Further, by using the above transistor with a high field-effect mobility in a source driver (particularly, a demultiplexer connected to the output terminal of the shift register included in the source driver), a display device with a small number of wirings connected to the display device can be provided.

[0106] Note that even if the semiconductor layer 108 has a region in which the atomic number ratio of In to element M is greater than 1, when the crystallinity of the semiconductor layer 108 is high, the field-effect mobility may be low. The crystallinity of the semiconductor layer 108 can be analyzed, for example, by using X-ray diffraction (XRD) or by using a transmission electron microscope (TEM).

[0107] Here, the channel formation region of the semiconductor layer 108 can have a low carrier density in the film by reducing the impurity concentration and the density of defect levels (reducing oxygen vacancies). A transistor using such a metal oxide film for the channel formation region of the semiconductor layer rarely has electrical characteristics (also called normally-on) in which the threshold voltage becomes negative. Further, a transistor using such a metal oxide film can obtain characteristics with an extremely small off-current.

[0108] When a highly crystalline metal oxide film is used for the semiconductor layer 108, damage during processing of the semiconductor layer 108 or during film formation of the insulating layer 110 can be suppressed, and a highly reliable transistor can be realized. On the other hand, by using a metal oxide film with a relatively low crystallinity for the semiconductor layer 108, electrical conductivity can be improved, and a transistor with a high field-effect mobility can be realized.

[0109] As the semiconductor layer 108, it is preferable to use a metal oxide film having a CAAC (c-axis aligned crystal) structure, a metal oxide film having an nc (nano crystal) structure, or a metal oxide film in which the CAAC structure and the nc structure are mixed, which will be described later.

[0110] Further, the semiconductor layer 108 may have a stacked structure of two or more layers.

[0111] For example, a semiconductor layer 108 in which two or more metal oxide films having different compositions are stacked can be used. For example, when an In-M-Zn oxide is used, among the films formed using a sputtering target in which the atomic number ratio of In, M, and Zn is In:M:Zn = 5:1:6, In:M:Zn = 4:2:3, In:M:Zn = 1:1:1, In:M:Zn = 2:2:1, In:M:Zn = 1:3:4, In:M:Zn = 1:3:2, or in the vicinity thereof, it is preferable to stack and use two or more of them.

[0112] In addition, a semiconductor layer 108 in which two or more metal oxide films having different crystallinities are laminated can be used. In that case, it is preferable that the same oxide target is used and the film formation conditions are made different so that they are continuously formed without being exposed to the atmosphere.

[0113] At this time, the semiconductor layer 108 can have a laminated structure of a metal oxide film having an nc structure and a metal oxide film having a CAAC structure. Alternatively, it may have a laminated structure of a metal oxide film having an nc structure and a metal oxide film having an nc structure. Regarding the functions of metal oxides or the material configurations that can be suitably used for each metal oxide film, the description of CAC (Cloud-Aligned Composite) described later can be incorporated.

[0114] For example, the oxygen flow rate ratio during the film formation of the first metal oxide film formed first is made smaller than the oxygen flow rate ratio during the film formation of the second metal oxide film formed later. Alternatively, the condition is such that no oxygen is passed during the film formation of the first metal oxide film. Thereby, oxygen can be effectively supplied during the film formation of the second metal oxide film. Further, the first metal oxide film can be a film having lower crystallinity and higher electrical conductivity than the second metal oxide film. On the other hand, by making the second metal oxide film provided on the upper part have higher crystallinity than the first metal oxide film, damage during the processing of the semiconductor layer 108 or during the film formation of the insulating layer 110 can be suppressed.

[0115] More specifically, the oxygen flow rate ratio during the film formation of the first metal oxide film is 0% or more and less than 50%, preferably 0% or more and 30% or less, more preferably 0% or more and 20% or less, and typically 10%. Also, the oxygen flow rate ratio during the film formation of the second metal oxide film is 50% or more and 100% or less, preferably 60% or more and 100% or less, more preferably 80% or more and 100% or less, still more preferably 90% or more and 100% or less, and typically 100%. In addition, the conditions such as pressure, temperature, and power during the film formation may be made different between the first metal oxide film and the second metal oxide film, but it is preferable to make the conditions other than the oxygen flow rate ratio the same because the time required for the film formation process can be shortened.

[0116] By adopting such a configuration, a transistor 100 with excellent electrical characteristics and high reliability can be realized.

[0117] Hereinafter, a configuration example of a transistor that is partially different from the above Configuration Example 1 will be described. Note that in the following, the description of the parts overlapping with the above Configuration Example 1 may be omitted. Also, in the drawings shown below, the parts having the same functions as those in the above Configuration Example 1 may have the same hatching pattern and may not be labeled.

[0118] <Configuration Example 2> FIG. 2(A) is a top view of the transistor 100A, FIG. 2(B) is a cross-sectional view of the transistor 100A in the channel length direction, and FIG. 2(C) is a cross-sectional view of the transistor 100A in the channel width direction.

[0119] The transistor 100A mainly differs from Configuration Example 1 in that it has a conductive layer 106 between the substrate 102 and the insulating layer 103. The conductive layer 106 has a region overlapping with the channel formation region of the semiconductor layer 108, the functional layer 113, and the conductive layer 112.

[0120] In the transistor 100A, the conductive layer 106 functions as a first gate electrode (also referred to as a bottom gate electrode), and the functional layer 113 and the conductive layer 112 function as a second gate electrode (also referred to as a top gate electrode). Also, a part of the insulating layer 103 functions as a first gate insulating layer, and a part of the insulating layer 110 functions as a second gate insulating layer.

[0121] The part of the semiconductor layer 108 that overlaps at least one of the functional layer 113, the conductive layer 112, and the conductive layer 106 functions as a channel formation region. Hereinafter, for the sake of simplicity of description, the part of the semiconductor layer 108 that overlaps with the functional layer 113 and the conductive layer 112 may be referred to as the channel formation region, but actually, a channel may be formed in the part (the part including the region 108N) that overlaps with the conductive layer 106 without overlapping with the functional layer 113 and the conductive layer 112.

[0122] Also, as shown in FIGS. 2(A) and 2(C), the conductive layer 106 may be electrically connected to the functional layer 113 and the conductive layer 112 through the metal oxide layer 114, the insulating layer 110, and the opening 142 provided in the insulating layer 103. Thereby, the same potential can be applied to the conductive layer 106, the functional layer 113, and the conductive layer 112.

[0123] The conductive layer 106 can be made of the same material as the conductive layer 112, the conductive layer 120a, or the conductive layer 120b. In particular, it is preferable to use a material containing copper for the conductive layer 106 because the wiring resistance can be reduced. Also, when a material containing a high melting point metal such as tungsten or molybdenum is used for the conductive layer 106, processing can be performed at a high temperature in a subsequent process.

[0124] Also, as shown in FIGS. 2(A) and 2(C), in the channel width direction, it is preferable that the functional layer 113, the conductive layer 112, and the conductive layer 106 protrude outside the end of the semiconductor layer 108. At this time, as shown in FIG. 2(C), the entire semiconductor layer 108 in the channel width direction is covered with the functional layer 113, the conductive layer 112, and the conductive layer 106 via the insulating layer 110 and the insulating layer 103.

[0125] With such a configuration, the semiconductor layer 108 can be electrically surrounded by the electric field generated by the pair of gate electrodes. At this time, in particular, it is preferable to apply the same potential to the conductive layer 106, the functional layer 113, and the conductive layer 112. Thereby, an electric field for inducing a channel in the semiconductor layer 108 can be effectively applied, so that the on-current of the transistor 100A can be increased. Therefore, it is also possible to miniaturize the transistor 100A.

[0126] Note that a configuration may be adopted in which the functional layer 113, the conductive layer 112, and the conductive layer 106 are not connected. At this time, a fixed potential may be applied to one of the pair of gate electrodes, and a signal for driving the transistor 100A may be applied to the other. At this time, the threshold voltage when driving the transistor 100A with the other electrode can also be controlled by the potential applied to one electrode.

[0127] The above is the description of Configuration Example 2.

[0128] <Configuration Example 3> FIG. 3(A) is a top view of the transistor 100B, FIG. 3(B) is a cross-sectional view of the transistor 100B in the channel length direction, and FIG. 3(C) is a cross-sectional view of the transistor 100B in the channel width direction.

[0129] The transistor 100B mainly differs from Configuration Example 1 in that the end of the conductive layer 112 is located inside the end of the insulating layer 110. In other words, the insulating layer 110 has a portion protruding outside the end of the conductive layer 112, at least on the semiconductor layer 108. Also, the upper surface shapes of the insulating layer 110, the metal oxide layer 114, and the functional layer 113 substantially coincide with each other.

[0130] As shown in FIGS. 3(B) and 3(C), the film thickness of the functional layer 113 in the region not overlapping with the conductive layer 112 may be thinner than the film thickness of the functional layer 113 in the region overlapping with the conductive layer 112.

[0131] The insulating layer 116 is provided to cover the upper surface and side surfaces of the conductive layer 112, the side surface of the functional layer 113, the side surface of the metal oxide layer 114, the side surface of the insulating layer 110, the upper surface and side surfaces of the semiconductor layer 108, and the upper surface of the insulating layer 103.

[0132] The above is the description of Configuration Example 3.

[0133] <Configuration Example 4> FIG. 4(A) is a top view of the transistor 100C, FIG. 4(B) is a cross-sectional view of the transistor 100C in the channel length direction, and FIG. 4(C) is a cross-sectional view of the transistor 100C in the channel width direction.

[0134] Transistor 100C is mainly different from Configuration Example 1 in that the ends of the conductive layer 112 and the functional layer 113 are located inside the ends of the insulating layer 110. In other words, the insulating layer 110 has a portion that protrudes outside the ends of the conductive layer 112 and the functional layer 113 at least on the semiconductor layer 108. Also, the upper surface shapes of the conductive layer 112 and the functional layer 113 generally coincide with each other. The upper surface shapes of the insulating layer 110 and the metal oxide layer 114 generally coincide with each other.

[0135] Note that as shown in FIGS. 4(B) and 4(C), the film thickness of the metal oxide layer 114 in the region where the metal oxide layer 114 does not overlap with the conductive layer 112 may be thinner than the film thickness of the metal oxide layer 114 in the region overlapping with the conductive layer 112 and the functional layer 113.

[0136] The semiconductor layer 108 has a pair of regions 108L sandwiching the channel formation region and a pair of regions 108N outside thereof. Region 108L is a region of the semiconductor layer 108 that overlaps with the insulating layer 110 and does not overlap with the conductive layer 112. Region 108L can be referred to as an offset region.

[0137] Region 108L can also be said to be a region having the same or lower resistance, the same or higher carrier density, the same or higher oxygen defect density, and the same or higher impurity concentration compared to the channel formation region.

[0138] Region 108L can also be said to be a region having the same or higher resistance, the same or lower carrier density, the same or lower oxygen defect density, and the same or lower impurity concentration compared to region 108N.

[0139] Note that the carrier density in region 108L does not have to be uniform, and may have a gradient such that the carrier density decreases from the region 108N side toward the channel formation region. For example, either one or both of the hydrogen concentration or the oxygen deficiency concentration in region 108L may have a gradient such that the concentration decreases from the region 108N side toward the channel formation region side.

[0140] A part of the end of the insulating layer 110 is located on the semiconductor layer 108. The insulating layer 110 has a region that overlaps with the conductive layer 112 and functions as a gate insulating layer, and a portion that does not overlap with the conductive layer 112 (i.e., the portion that overlaps with the region 108L).

[0141] The insulating layer 116 is provided to cover the upper surface and side surfaces of the conductive layer 112, the side surfaces of the functional layer 113, the side surfaces of the metal oxide layer 114, the side surfaces of the insulating layer 110, the upper surface and side surfaces of the semiconductor layer 108, and the upper surface of the insulating layer 103. Since the region 108L does not contact the insulating layer 116 due to the presence of the insulating layer 110 in between, less hydrogen is supplied to the region 108L than to the region 108N. Furthermore, since the impurity concentration is also smaller than that of the region 108N, the region 108L can be in a higher-resistance state than the region 108N.

[0142] As will be described later, since the region 108L can be formed self-alignedly, a photomask for forming the region 108L is not required, and the manufacturing cost can be reduced. Also, by forming the region 108L self-alignedly, there is no relative misalignment between the region 108L and the functional layer 113 and the conductive layer 112, so the widths of the region 108L in the semiconductor layer 108 can be made substantially the same.

[0143] A region 108L where the electric field of the gate is not applied (or is less likely to be applied than the channel formation region) can be stably formed without variation in a region in the semiconductor layer 108 that is not the low-resistance region 108N. As a result, the source-drain breakdown voltage of the transistor can be improved, and a highly reliable transistor can be realized. The width of the region 108L is 10 nm or more and 10 μm or less, preferably 30 nm or more and 5 μm or less, more preferably 50 nm or more and 1 μm or less. If the width of the region 108L in the channel length direction is long, the effective channel length may become long and the driving speed of the transistor may become slow. By setting the width as described above, a transistor with a high driving speed can be obtained.

[0144] In addition, when a conductive material is used for the metal oxide layer 114, since the gate electric field is applied to the semiconductor layer 108 in the region overlapping with the metal oxide layer 114, the region 108L is not formed.

[0145] The above is the description of Configuration Example 4.

[0146] <Configuration Example 5> FIG. 5(A) is a top view of the transistor 100D, FIG. 5(B) is a cross-sectional view of the transistor 100D in the channel length direction, and FIG. 5(C) is a cross-sectional view of the transistor 100D in the channel width direction.

[0147] The transistor 100D is mainly different from Configuration Example 1 in that the ends of the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are located inside the ends of the insulating layer 110. In other words, the insulating layer 110 has a portion that protrudes outside the ends of the conductive layer 112, the functional layer 113, and the metal oxide layer 114 at least on the semiconductor layer 108. Also, the upper surface shapes of the conductive layer 112, the functional layer 113, and the metal oxide layer 114 substantially coincide with each other.

[0148] The insulating layer 116 is provided to cover the upper surface and the side surface of the conductive layer 112, the side surface of the functional layer 113, the side surface of the metal oxide layer 114, the upper surface and the side surface of the insulating layer 110, the upper surface and the side surface of the semiconductor layer 108, and the upper surface of the insulating layer 103. The insulating layer 118 is provided to cover the insulating layer 116. An enlarged view of the region surrounded by the dashed-dotted line in FIG. 5(B) is shown in FIG. 6(A).

[0149] The semiconductor layer 108 has a pair of regions 108L sandwiching the channel formation region and a pair of regions 108N outside thereof. In a region in the semiconductor layer 108 that is not the low-resistance region 108N, a region 108L where the electric field of the gate is not applied (or is less likely to be applied than the channel formation region) can be formed stably and without variation. As a result, the source-drain breakdown voltage of the transistor can be improved, and a highly reliable transistor can be realized. Further, by providing the region 108L between the channel formation region and the low-resistance region 108N, the current density at the boundary between the channel formation region and the region 108N can be relaxed, heat generation at the boundary between the channel and the source or drain can be suppressed, and a highly reliable semiconductor device can be obtained.

[0150] When forming the conductive layer 112, the functional layer 113, and the metal oxide layer 114, a part of the insulating layer 110 that does not overlap with the conductive layer 112 may be etched, and the film thickness of the insulating layer 110 may become thinner. Specifically, as shown in FIG. 6(B), the film thickness of the insulating layer 110 in a region that does not overlap with the conductive layer 112 may be thinner than the film thickness of the insulating layer 110 in a region that overlaps with the conductive layer 112. In other words, the film thickness of the insulating layer 110 in a region that does not overlap with the channel formation region may be thinner than the film thickness of the insulating layer 110 in a region that overlaps with the channel formation region.

[0151] In FIGS. 5(B), 5(C), 6(A), and 6(B), the insulating layer 110 is shown as a single-layer structure, but it may have a laminated structure of two or more layers. FIG. 6(C) shows an example in which the insulating layer 110 has a two-layer structure of an insulating layer 110a and an insulating layer 110b on the insulating layer 110a. Since the insulating layer 110a and the insulating layer 110b can use insulating films of the same material, the interface between the insulating layer 110a and the insulating layer 110b may not be clearly confirmed. Therefore, in the present embodiment, the interface between the insulating layer 110a and the insulating layer 110b is illustrated by a broken line.

[0152] The insulating layer 110a in contact with the channel formation region of the semiconductor layer 108 preferably has a low defect density in the vicinity of the interface with the channel formation region and in the film. Further, the insulating layer 110a preferably has a low impurity concentration of hydrogen in the film. Also, it is preferable that the damage to the semiconductor layer 108 during the formation of the insulating layer 110a is small. By using a film with a low defect density and impurity concentration for the insulating layer 110a and using film formation conditions with small damage to the semiconductor layer 108, a transistor with good electrical characteristics can be obtained.

[0153] For example, when a film containing silicon is used as the insulating layer 110, the insulating layer 110a can be formed under film formation conditions where the ratio of the silicon-containing gas to the film formation gas used during film formation is low. By using film formation conditions where the ratio of the silicon-containing gas to the film formation gas is low, an insulating layer 110a with a low defect density and impurity concentration can be formed. Also, by lowering the film formation power during the formation of the insulating layer 110a, the damage to the semiconductor layer 108 can be reduced.

[0154] The insulating layer 110b in contact with the metal oxide layer 114 preferably has a structure such that the etching rate in the etchant used for the processing of the conductive layer 112 is about the same as or slower than that of the conductive layer 112.

[0155] The insulating layer 110b is preferably a denser film than the insulating layer 110a. The dense insulating layer 110b can be formed under film formation conditions with a slower film formation rate than the insulating layer 110a. Also, in the dense insulating layer 110b, the adsorption of water on its surface is suppressed. That is, by providing the insulating layer 110b on the upper surface of the insulating layer 110, the adsorption of water on the surface of the insulating layer 110 can be suppressed.

[0156] When water is adsorbed on the surface of the insulating layer 110, if the hydrogen in the adsorbed water reaches the channel formation region, carriers may be formed in the channel formation region, which may have an adverse effect on the electrical characteristics and reliability of the transistor. By providing the insulating layer 110b, on which water is less likely to be adsorbed, on the upper surface of the insulating layer 110, it is possible to suppress the formation of carriers in the channel formation region and obtain good electrical characteristics and reliability.

[0157] For the formation of the insulating layer 110b, film formation conditions with a slower film formation rate than those of the insulating layer 110a can be used. For example, when a film containing silicon is used as the insulating layer 110, the insulating layer 110b can be formed under conditions where the ratio of the silicon-containing gas to the film formation gas used during film formation is low. Further, compared with the insulating layer 110a, the insulating layer 110b can be made into an insulating layer on which water is less likely to be adsorbed by increasing the film formation power during film formation.

[0158] Preferably, the etching rate of the insulating layer 110b in a certain etchant is slower than that of the insulating layer 110a. Note that, compared with the insulating layer 110a, the film density of the insulating layer 110b may be higher. The difference in the film density between the insulating layer 110a and the insulating layer 110b can be evaluated, for example, by the density (luminance) of the TEM image.

[0159] When forming the conductive layer 112, the functional layer 113, and the metal oxide layer 114, the film thickness of the insulating layer 110b in the region that does not overlap with the conductive layer 112 may become thinner. As shown in FIG. 6(D), it is preferable that the insulating layer 110b remains in the region that does not overlap with the conductive layer 112. By adopting a configuration in which the insulating layer 110b remains in the region that does not overlap with the conductive layer 112, it is possible to suppress the adsorption of water on the insulating layer 110.

[0160] Preferably, the insulating layer 110b in the region that overlaps with the conductive layer 112 is formed to have a thickness such that the insulating layer 110b remains in the region that does not overlap with the conductive layer 112. The thickness of the insulating layer 110b in the region that overlaps with the conductive layer 112 is 1 nm or more and 50 nm or less, preferably 2 nm or more and 40 nm or less, and more preferably 3 nm or more and 30 nm or less.

[0161] FIG. 6(E) shows an example of a three-layer structure of the insulating layer 110 including the insulating layer 110a, the insulating layer 110b on the insulating layer 110a, and the insulating layer 110c between the insulating layer 110a and the insulating layer 110b. Since the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can use insulating films of the same material, there may be cases where the interfaces of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c cannot be clearly confirmed. Therefore, in the present embodiment, the interfaces of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c are illustrated by broken lines.

[0162] For forming the insulating layer 110c, film formation conditions with a higher film formation rate than those of the insulating layer 110a and the insulating layer 110b can be used. By using the insulating layer 110c with a high film formation rate, the laminated insulating layer 110 can be formed with high productivity.

[0163] For example, when a film containing silicon is used as the insulating layer 110, compared with the insulating layer 110a and the insulating layer 110b, the insulating layer 110c can use conditions where the ratio of the silicon-containing gas to the film formation gas used during film formation is high. Also, the insulating layer 110c can be made into an insulating layer with few impurities by increasing the power during film formation. Furthermore, the insulating layer 110c can be made into an insulating layer with few impurities by increasing the pressure during film formation.

[0164] It is preferable that the etching rate of the insulating layer 110c in one etchant is faster than that of the insulating layer 110a and the insulating layer 110b. Note that, compared with the insulating layer 110a and the insulating layer 110b, the film density of the insulating layer 110c may be lower. The difference in the film density of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be evaluated, for example, by the density (luminance) of a TEM image. Also, compared with the insulating layer 110a and the insulating layer 110b, the hydrogen concentration in the film of the insulating layer 110c may be higher. The difference in the hydrogen concentration of the insulating layer 110a, the insulating layer 110b, and the insulating layer 110c can be evaluated, for example, by secondary ion mass spectrometry.

[0165] When forming the conductive layer 112, the functional layer 113, and the metal oxide layer 114, the film thickness of the insulating layer 110b in the region that does not overlap with the conductive layer 112 may become thin. As shown in FIG. 6(F), it is preferable that the insulating layer 110b remains in the region that does not overlap with the conductive layer 112. By adopting a configuration in which the insulating layer 110b remains in the region that does not overlap with the conductive layer 112, adsorption of water to the insulating layer 110 can be suppressed.

[0166] Also, as shown in FIGS. 7(A), 7(B), and 7(C), the end portion of the conductive layer 112 may be located inside the end portions of the functional layer 113 and the metal oxide layer 114. FIG. 7(A) is a top view of the transistor 100E, FIG. 7(B) is a cross-sectional view of the transistor 100E in the channel length direction, and FIG. 7(C) is a cross-sectional view of the transistor 100E in the channel width direction.

[0167] The transistor 100E is mainly different from the configuration example 1 in that the end portions of the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are located inside the end portion of the insulating layer 110, and the end portion of the conductive layer 112 is located inside the end portions of the functional layer 113 and the metal oxide layer 114. In other words, the insulating layer 110 has a portion that protrudes outside the end portions of the conductive layer 112, the functional layer 113, and the metal oxide layer at least on the semiconductor layer 108. Further, the functional layer 113 and the metal oxide layer have portions that protrude outside the end portion of the conductive layer 112 at least on the insulating layer 110. Also, the upper surface shapes of the functional layer 113 and the metal oxide layer substantially coincide with each other.

[0168] By using a material for the etchant used for processing the conductive layer 112 in the conductive layer 112, the etching rate of which is faster than that of the metal oxide layer 114 and the functional layer 113, a configuration can be achieved in which the end portion of the conductive layer 112 is located inside the end portions of the functional layer 113 and the metal oxide layer 114.

[0169] The insulating layer 116 is provided to cover the upper surface and the side surfaces of the conductive layer 112, the upper surface and the side surfaces of the functional layer 113, the side surfaces of the metal oxide layer 114, the upper surface and the side surfaces of the insulating layer 110, the upper surface and the side surfaces of the semiconductor layer 108, and the upper surface of the insulating layer 103. The insulating layer 118 is provided to cover the insulating layer 116.

[0170] When forming the conductive layer 112, the functional layer 113, and the metal oxide layer 114, a part of the insulating layer 110 that does not overlap with the conductive layer 112 may be etched, and the film thickness of the insulating layer 110 may become thinner. An enlarged view of the region surrounded by the dashed-dotted line in FIG. 7(B) is shown in FIG. 8(A). As shown in FIG. 8(A), the film thickness of the insulating layer 110 in the region that does not overlap with the conductive layer 112 may be thinner than the film thickness of the insulating layer 110 in the region that overlaps with the conductive layer 112. In other words, the film thickness of the insulating layer 110 in the region that does not overlap with the channel formation region may be thinner than the film thickness of the insulating layer 110 in the region that overlaps with the channel formation region.

[0171] In FIGS. 7(B), 7(C), and 8(A), the insulating layer 110 is shown as a single-layer structure, but it may have a laminated structure of two or more layers. FIG. 8(B) shows an example in which the insulating layer 110 has a two-layer structure of the insulating layer 110a and the insulating layer 110b on the insulating layer 110a. FIG. 8(C) shows an example in which the insulating layer 110 has a three-layer structure of the insulating layer 110a, the insulating layer 110b on the insulating layer 110a, and the insulating layer 110c between the insulating layer 110a and the insulating layer 110b.

[0172] When forming the conductive layer 112, the functional layer 113, and the metal oxide layer 114, the film thickness of the insulating layer 110b in the region that does not overlap with the conductive layer 112 may become thinner. Also, as shown in FIGS. 8(B) and 8(C), it is preferable that the insulating layer 110b remains in the region that does not overlap with the conductive layer 112. By adopting a configuration in which the insulating layer 110b remains in the region that does not overlap with the conductive layer 112, it is possible to suppress the adsorption of water to the insulating layer 110.

[0173] Also, in the aforementioned transistors 100, 100A, 100B, and 100C, it is preferable that the insulating layer 110 has a laminated structure. By forming the insulating layer 110 into a two-layer structure including the insulating layer 110a and the insulating layer 110b on the insulating layer 110a, adsorption of water on the surface of the insulating layer 110 can be suppressed, and good electrical characteristics and reliability can be obtained. Furthermore, by forming the insulating layer 110 into a three-layer structure including the insulating layer 110a, the insulating layer 110b on the insulating layer 110a, and the insulating layer 110c between the insulating layer 110a and the insulating layer 110b, the laminated insulating layer 110 can be formed with high productivity.

[0174] The above is the description of Configuration Example 5.

[0175] <Fabrication Method Example 1> Hereinafter, a method for manufacturing a semiconductor device according to an aspect of the present invention will be described with reference to the drawings. Here, the transistor 100A illustrated in the above configuration example will be described as an example.

[0176] Note that thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed using a sputtering method, a chemical vapor deposition (CVD) method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like. Examples of the CVD method include a plasma enhanced CVD (PECVD) method and a thermal CVD method. Further, one example of the thermal CVD method is a metal organic CVD (MOCVD) method.

[0177] Also, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed using methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, and tools (equipment) such as a doctor knife, a slit coater, a roll coater, a curtain coater, and a knife coater.

[0178] In addition, when processing the thin film constituting the semiconductor device, it can be processed using a photolithography method or the like. In addition, the thin film may be processed by a nanoimprint method, a sandblasting method, a lift-off method, or the like. Further, an island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0179] Typically, there are the following two representative photolithography methods. One is a method in which a resist mask is formed on a thin film to be processed, the thin film is processed by etching or the like, and the resist mask is removed. The other is a method in which after forming a photosensitive thin film, exposure and development are performed to process the thin film into a desired shape.

[0180] In the photolithography method, as the light used for exposure, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or light obtained by mixing these can be used. In addition, ultraviolet light, KrF laser light, ArF laser light, or the like can also be used. Further, exposure may be performed by a liquid immersion exposure technique. In addition, as the light used for exposure, extreme ultraviolet (EUV) light or X-rays may be used. Further, instead of the light used for exposure, an electron beam can also be used. Using extreme ultraviolet light, X-rays, or an electron beam is preferable because extremely fine processing becomes possible. Note that when performing exposure by scanning a beam such as an electron beam, a photomask is not required.

[0181] For the etching of the thin film, a dry etching method, a wet etching method, a sandblasting method, or the like can be used.

[0182] Each of FIGS. 9 to 11 shows a cross section at each stage of the manufacturing process of the transistor 100A. In each figure, the cross sections in the channel length direction are arranged on the left side of the central broken line, and the cross sections in the channel width direction are arranged on the right side.

[0183] [Formation of Conductive Layer 106] A conductive film is formed on the substrate 102 and processed by etching to form a conductive layer 106 that functions as a first gate electrode.

[0184] 〔Formation of Insulating Layer 103〕 Subsequently, an insulating layer 103 is formed to cover the substrate 102 and the conductive layer 106 (Fig. 9(A)). The insulating layer 103 can be formed using methods such as PECVD method, ALD method, sputtering method, etc.

[0185] When the insulating layer 103 has a laminated structure, the insulating films that will form the insulating layer 103 are formed in order. For example, when the insulating layer 103 has a laminated structure of a nitride film and an oxide film on the nitride film, the nitride film and the oxide film are formed in this order.

[0186] Also, the nitride film included in the insulating layer 103 may have a laminated structure of two or more layers. For example, when the insulating layer 103 has a laminated structure of a first silicon nitride film, a second silicon nitride film on the first silicon nitride film, a third silicon nitride film on the second silicon nitride film, and a silicon oxynitride film on the third silicon nitride film, the first silicon nitride film, the second silicon nitride film, the third silicon nitride film, and the silicon oxynitride film are formed in this order.

[0187] When the insulating layer 103 has a laminated structure of a first silicon nitride film, a second silicon nitride film, a third silicon nitride film, and a silicon oxynitride film, it is preferable that the first silicon nitride film has a function of blocking impurities. By providing the first silicon nitride film, diffusion of impurities from the layer below the insulating layer 103 to the layer above the insulating layer 103 can be suppressed. It is preferable that the second silicon nitride film has low stress and high dielectric breakdown voltage. By providing the second silicon nitride film, an insulating layer 103 with low stress and high dielectric breakdown voltage can be obtained. It is preferable that the third silicon nitride film has little release of impurities containing hydrogen and has a function of blocking impurities containing hydrogen. By providing the third silicon nitride film, diffusion of hydrogen into the channel formation region can be suppressed. It is preferable that the silicon oxynitride film has a low defect density and little release of impurities containing hydrogen.

[0188] For example, the insulating layer 103 is formed by a plasma CVD method using a mixed gas of silane, nitrogen, and ammonia to form a first silicon nitride film having a function of blocking impurities. Next, a second silicon nitride film having low stress and high dielectric breakdown voltage is formed using a mixed gas with a higher ammonia flow rate than that of the first silicon nitride film. Next, a third silicon nitride film having little release of impurities containing hydrogen and having a function of blocking impurities containing hydrogen is formed using a mixed gas with a lower ammonia flow rate than that of the second silicon nitride film. Next, a silicon oxynitride film having a low defect density and little release of impurities containing hydrogen is formed using a mixed gas of silane and dinitrogen monoxide, and the insulating layer 103 can be formed. Also, by switching the film formation conditions in the same chamber, the first silicon nitride film, the second silicon nitride film, the third silicon nitride film, and the silicon oxynitride film can be continuously formed in a vacuum, and the insulating layer 103 can be formed with high productivity.

[0189] Alternatively, after forming the third silicon nitride film, a plasma treatment is performed in an oxygen-containing atmosphere to oxidize the surface of the third silicon nitride film, so that a silicon oxynitride film can be formed on the third silicon nitride film.

[0190] Compared with the first silicon nitride film and the third silicon nitride film, the second silicon nitride film may have a lower film density. The difference in the film density of the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be evaluated, for example, by the density (luminance) of the TEM image. Also, compared with the first silicon nitride film and the third silicon nitride film, the second silicon nitride film may have a higher hydrogen concentration in the film. The difference in the hydrogen concentration of the first silicon nitride film, the second silicon nitride film, and the third silicon nitride film can be evaluated, for example, by secondary ion mass spectrometry.

[0191] After forming the insulating layer 103, a process of supplying oxygen to the insulating layer 103 may be performed. For example, plasma treatment or heat treatment in an oxygen atmosphere can be performed. Alternatively, oxygen may be supplied to the insulating layer 103 by a plasma ion doping method or an ion implantation method. Note that heat treatment may not be performed after forming the insulating layer 103.

[0192] 〔Formation of Semiconductor Layer 108〕 Subsequently, a metal oxide film is formed on the insulating layer 103 and processed to form island-shaped semiconductor layers 108 (FIG. 9(B)).

[0193] The metal oxide film is preferably formed by a sputtering method using a metal oxide target.

[0194] Also, when forming the metal oxide film, oxygen gas and an inert gas (for example, helium gas, argon gas, xenon gas, etc.) may be mixed. Note that the higher the ratio of oxygen gas in the entire film-forming gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be enhanced, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film, and a transistor with a higher on-current can be obtained.

[0195] When the semiconductor layer 108 has a stacked structure, it is preferable to form films continuously in the same film formation chamber using the same sputtering target, because the interface can be made good. In particular, as the film formation conditions for each metal oxide film, conditions such as the pressure, temperature, and power during film formation may be varied, but it is preferable to set the conditions other than the oxygen flow rate ratio to be the same, because the time required for the film formation process can be shortened. Further, when laminating metal oxide films having different compositions, it is preferable to form films continuously without exposing them to the atmosphere.

[0196] It is preferable to set the film formation conditions so that the metal oxide film has a CAAC structure, an nc structure, or a metal oxide film in which the CAAC structure and the nc structure are mixed. Note that the film formation conditions for the metal oxide film to have a CAAC structure and the film formation conditions for the nc structure differ depending on the composition of the sputtering target used. Therefore, depending on the composition, in addition to the substrate temperature and the oxygen flow rate ratio, the pressure, the power, etc. may be appropriately set.

[0197] Further, as the film formation conditions for the metal oxide film, the substrate temperature may be set to be not lower than room temperature and not higher than 450°C, preferably not lower than room temperature and not higher than 300°C, more preferably not lower than room temperature and not higher than 200°C, and still more preferably not lower than room temperature and not higher than 140°C. For example, when a large glass substrate or a resin substrate is used for the substrate 102, it is preferable to set the substrate temperature to be lower than 140°C and not lower than room temperature, because the productivity is increased. Further, by forming the metal oxide film at room temperature or without heating, the crystallinity can be lowered.

[0198] Also, before forming the metal oxide film, it is preferable to perform a process for desorbing water, hydrogen, organic components, etc. adsorbed on the surface of the insulating layer 103, or a process for supplying oxygen into the insulating layer 103. For example, heat treatment can be performed at a temperature of 70°C or higher and 200°C or lower in a reduced-pressure atmosphere. Alternatively, plasma treatment in an atmosphere containing oxygen may be performed. Further, when plasma treatment is performed in an atmosphere containing nitrogen monoxide gas, the organic substances on the surface of the insulating layer 103 can be preferably removed. After such treatment, it is preferable to continuously form the metal oxide film without exposing the surface of the insulating layer 103 to the atmosphere.

[0199] For the processing of the metal oxide film, either one or both of the wet etching method and the dry etching method may be used. At this time, a part of the insulating layer 103 that does not overlap with the semiconductor layer 108 may be etched and become thinner.

[0200] After forming the metal oxide film or after processing the semiconductor layer 108, heat treatment may be performed to remove hydrogen or water in the metal oxide film or the semiconductor layer 108. The temperature of the heat treatment can typically be 150°C or higher and less than the strain point of the substrate, or 250°C or higher and 450°C or lower, or 300°C or higher and 450°C or lower. Note that after forming the metal oxide film or after processing the semiconductor layer 108, heat treatment may not be necessary. Further, the heat treatment may be performed at any stage as long as it is after forming the metal oxide film. Also, it may be combined with a subsequent heat treatment or a process where heat is applied.

[0201] The heat treatment can be performed in an atmosphere containing a noble gas or nitrogen. Alternatively, after heating in such an atmosphere, it may be heated in an atmosphere containing oxygen. As the atmosphere containing nitrogen or the atmosphere containing oxygen, ultra-dry air (CDA: Clean Dry Air) may be used. It is preferable that hydrogen, water, etc. are not contained in the atmosphere of the heat treatment. By using a gas highly purified to a dew point of -60°C or lower, preferably -100°C or lower, it is possible to prevent hydrogen, water, etc. from being incorporated into the semiconductor layer 108 as much as possible. The heat treatment can use an electric furnace, a rapid thermal annealing (RTA) apparatus, etc. By using an RTA apparatus, the heat treatment time can be shortened.

[0202] Note that it is preferable to form the insulating film 110f promptly after the formation of the semiconductor layer 108. When the surface of the semiconductor layer 108 is exposed, water may adsorb on the surface of the semiconductor layer 108. When water adsorbs on the surface of the semiconductor layer 108, hydrogen diffuses into the semiconductor layer 108 due to subsequent heat treatment or the like, and O VH may be formed. O Since VH can be a carrier generation source, it is preferable that the adsorbed water on the semiconductor layer 108 is less.

[0203] 〔Formation of Insulating Film 110f and Metal Oxide Film 114f〕 Subsequently, an insulating film 110f and a metal oxide film 114f are formed to cover the insulating layer 103 and the semiconductor layer 108.

[0204] The insulating film 110f is a film that will later become the insulating layer 110. As the insulating film 110f, for example, an oxide film such as a silicon oxide film or a silicon oxynitride film is preferably formed using a plasma chemical vapor deposition apparatus (PECVD apparatus, or simply referred to as a plasma CVD apparatus). Also, it may be formed using a PECVD method using microwaves.

[0205] When the insulating layer 110 has a laminated structure, insulating films that will form the insulating layer 110 are formed in order. For example, as shown in FIGS. 6(C), 6(D), and 8(B), when the insulating layer 110 has a two-layer structure of an insulating layer 110a and an insulating layer 110b, an insulating film that will form the insulating layer 110a and an insulating film that will form the insulating layer 110b are formed in this order.

[0206] For example, the insulating layer 110 is formed by a plasma CVD method using a mixed gas of silane and dinitrogen monoxide to form an insulating film that will be the insulating layer 110a. Next, an insulating film that will be the insulating layer 110b is formed under conditions where the pressure is lower and the power is higher than those of the insulating film that will be the insulating layer 110a, thereby forming the insulating layer 110. Also, by switching the film formation conditions in the same chamber, the insulating film that will be the insulating layer 110a and the insulating film that will be the insulating layer 110b can be continuously formed in a vacuum, and the insulating layer 110 can be formed with high productivity.

[0207] Also, as shown in FIGS. 6(E), 6(F), and 8(C), when the insulating layer 110 has a three-layer structure of an insulating layer 110a, an insulating layer 110c, and an insulating layer 110b, an insulating film that will be the insulating layer 110a, an insulating film that will be the insulating layer 110c, and an insulating film that will be the insulating layer 110b are formed in this order.

[0208] For example, the insulating layer 110 is formed by a plasma CVD method using a mixed gas of silane and dinitrogen monoxide to form an insulating film that will be the insulating layer 110a. Next, a mixed gas with a higher silane flow rate ratio to the dinitrogen monoxide flow rate than that of the insulating film that will be the insulating layer 110a is used, and an insulating film that will be the insulating layer 110c is formed under conditions where the power is high. Next, a mixed gas with a lower silane flow rate ratio to the dinitrogen monoxide flow rate than that of the insulating film that will be the insulating layer 110c is used, and an insulating film that will be the insulating layer 110b is formed under conditions where the pressure is low, thereby forming the insulating layer 110. Also, by switching the film formation conditions in the same chamber, the insulating film that will be the insulating layer 110a, the insulating film that will be the insulating layer 110c, and the insulating film that will be the insulating layer 110b can be continuously formed in a vacuum, and the insulating layer 110 can be formed with high productivity.

[0209] After forming the insulating film 110f, heat treatment may be performed to remove impurities in the insulating film 110f and adsorbed water on the surface of the insulating film 110f. The heat treatment can be carried out at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and noble gases. Note that heat treatment may not be necessary after forming the insulating film 110f. Also, the heat treatment may be performed at any stage as long as it is after the formation of the insulating film 110f. Further, it may be combined with a subsequent heat treatment or a process where heat is applied.

[0210] The metal oxide film 114f is a film that will later become the metal oxide layer 114. The metal oxide film 114f is preferably formed by sputtering, for example, in an atmosphere containing oxygen. Thereby, oxygen can be supplied to the insulating film 110f during the film formation of the metal oxide film 114f.

[0211] When the metal oxide film 114f is formed by sputtering using an oxide target containing the same metal oxide as in the case of the semiconductor layer 108 described above, the above method can be applied.

[0212] The metal oxide film 114f may be formed by a reactive sputtering method using oxygen as a film formation gas and a metal target. When aluminum is used for the metal target, an aluminum oxide film can be formed.

[0213] During the film formation of the metal oxide film 114f, the higher the ratio of the oxygen flow rate to the total flow rate of the film formation gas introduced into the film formation chamber of the film formation apparatus (oxygen flow rate ratio), or the higher the oxygen partial pressure in the film formation chamber, the more oxygen can be supplied into the insulating film 110f. The oxygen flow rate ratio or the oxygen partial pressure is, for example, 50% or more and 100% or less, preferably 65% or more and 100% or less, more preferably 80% or more and 100% or less, and even more preferably 90% or more and 100% or less. In particular, it is preferable to set the oxygen flow rate ratio to 100% and make the oxygen partial pressure as close to 100% as possible.

[0214] Thus, by forming the metal oxide film 114f by sputtering in an oxygen-containing atmosphere, oxygen can be supplied to the insulating film 110f and the desorption of oxygen from the insulating film 110f can be prevented during the film formation of the metal oxide film 114f. As a result, a very large amount of oxygen can be trapped in the insulating film 110f. Then, by subsequent heat treatment, a large amount of oxygen is supplied to the channel formation region of the semiconductor layer 108, oxygen vacancies in the channel formation region can be reduced, and a highly reliable transistor can be realized.

[0215] Further, as the film formation conditions of the metal oxide film 114f, the substrate temperature may be set to be equal to or higher than room temperature and equal to or lower than 450°C, preferably equal to or higher than room temperature and equal to or lower than 300°C, more preferably equal to or higher than room temperature and equal to or lower than 200°C, and even more preferably equal to or higher than room temperature and equal to or lower than 140°C. For example, when a large glass substrate or a resin substrate is used for the substrate 102, if the film formation temperature is set to be equal to or higher than room temperature and lower than 140°C, the productivity is high, which is preferable. Also, when the film formation temperature of the metal oxide film 114f is high, the crystallinity of the metal oxide film 114f becomes high, and the etching rate may become slow. When the film formation temperature of the metal oxide film 114f is low, the crystallinity of the metal oxide film 114f becomes low, and the etching rate may become fast. The film formation temperature of the metal oxide film 114f may be appropriately selected so as to obtain a desirable etching rate with respect to the etchant used when processing the metal oxide film 114f.

[0216] After the formation of the metal oxide film 114f, heat treatment may be performed to supply oxygen from the insulating film 110f to the semiconductor layer 108. The heat treatment can be performed at a temperature of 200°C or higher and 400°C or lower in an atmosphere containing one or more of nitrogen, oxygen, and noble gas. Note that heat treatment may not be performed after the formation of the metal oxide film 114f. Also, the heat treatment may be performed at any stage as long as it is after the film formation of the metal oxide film 114f. Further, it may be combined with a subsequent heat treatment or a step in which heat is applied.

[0217] Subsequently, by etching a part of the metal oxide film 114f, the insulating film 110f, and the insulating layer 103, an opening reaching the conductive layer 106 is formed (FIG. 9(C)). Thereby, the functional layer 113 and the conductive layer 112 to be formed later and the conductive layer 106 can be electrically connected through the opening.

[0218] 〔Formation of functional film 113f and conductive film 112f〕 Subsequently, a functional film 113f serving as the functional layer 113 and a conductive film 112f serving as the conductive layer 112 are formed on the metal oxide film 114f (FIG. 10(A)). The functional film 113f is preferably formed by a sputtering method using a sputtering target of a metal or an alloy. The conductive film 112f is preferably formed by a sputtering method using a sputtering target of a metal or an alloy.

[0219] 〔Formation of insulating layer 110, metal oxide layer 114, and conductive layer 112〕 Subsequently, a resist mask 115 is formed on the conductive film 112f. Thereafter, the conductive film 112f, the functional film 113f, and the metal oxide film 114f are removed in a region not covered by the resist mask 115 to form the conductive layer 112, the functional layer 113, and the metal oxide layer 114 (FIG. 10(B)).

[0220] For the formation of the conductive layer 112, the functional layer 113, and the metal oxide layer 114, a wet etching method can be preferably used. For the wet etching method, for example, an etchant containing hydrogen peroxide can be used. For example, an etchant containing one or more of phosphoric acid, acetic acid, nitric acid, hydrochloric acid, or sulfuric acid can be used. In particular, when a material containing copper is used for the conductive layer 112, an etchant containing phosphoric acid, acetic acid, and nitric acid can be preferably used.

[0221] In one aspect of the present invention, since the etching rates of the metal oxide layer 114 and the functional layer 113 are about the same as or slower than that of the conductive layer 112, the functional layer 113, the metal oxide layer 114, and the conductive layer 112 can be formed in the same process. Further, the upper surface shapes of the metal oxide layer 114, the functional layer 113, and the conductive layer 112 can be made to substantially coincide with each other. Also, since they can be formed in the same process, the process can be simplified and productivity can be increased.

[0222] When forming the conductive layer 112, the functional layer 113, and the metal oxide layer 114, the conductive layer 112 may recede from the functional layer 113 and the metal oxide layer 114. That is, the end of the conductive layer 112 is located inside the end of the metal oxide layer 114. Further, when the conductive layer 112 recedes from the functional layer 113 and the metal oxide layer 114, the film thickness of the functional layer 113 in the region where the conductive layer 112 does not overlap may be thinner than the film thickness of the functional layer 113 in the region where the conductive layer 112 overlaps (see FIGS. 3(A), 3(B), and 3(C)).

[0223] Also, when forming the conductive layer 112, the functional layer 113, and the metal oxide layer 114, the conductive layer 112 and the functional layer 113 may recede from the metal oxide layer 114. That is, the ends of the conductive layer 112 and the functional layer 113 are located inside the end of the metal oxide layer 114. Further, when the conductive layer 112 and the functional layer 113 recede from the metal oxide layer 114, the film thickness of the metal oxide layer 114 in the region where the conductive layer 112 does not overlap may be thinner than the film thickness of the metal oxide layer 114 in the region where the conductive layer 112 and the functional layer 113 overlap (see FIGS. 4(A), 4(B), and 4(C)).

[0224] Note that for forming the conductive layer 112, the functional layer 113, and the metal oxide layer 114, etching may be performed in at least two steps using different etching conditions or methods. For example, the conductive film 112f may be etched first, and then the functional film 113f and the metal oxide film 114f may be etched under different etching conditions.

[0225] Subsequently, in the region not covered by the resist mask 115, the insulating film 110f is removed to form the insulating layer 110 (FIG. 11(A)). For forming the insulating layer 110, either one or both of a wet etching method and a dry etching method can be used. Note that the insulating layer 110 may be formed with the resist mask 115 removed, but leaving the resist mask 115 can suppress a reduction in the film thickness of the conductive layer 112.

[0226] After forming the insulating layer 110, the resist mask 115 is removed.

[0227] [Formation of Insulating Layer 116 and Region 108N (Hydrogen Supply Process)] Subsequently, a process of supplying hydrogen is performed on the exposed region of the semiconductor layer 108. Here, hydrogen is supplied by forming an insulating layer 116 containing hydrogen in contact with the exposed region of the semiconductor layer 108 (FIG. 11(B)).

[0228] The insulating layer 116 is preferably formed by a plasma CVD method using a film-forming gas containing hydrogen. For example, a silicon nitride film is formed using a film-forming gas containing silane gas and ammonia gas. By using ammonia gas in addition to silane gas, a large amount of hydrogen can be contained in the film. Also, it becomes possible to supply hydrogen to the exposed portion of the semiconductor layer 108 even during film formation.

[0229] After forming the insulating layer 116, it is preferable to perform a heat treatment to supply a part of the hydrogen released from the insulating layer 116 to a part of the semiconductor layer 108. The heat treatment is preferably performed at a temperature of 150°C or higher and 450°C or lower, preferably 200°C or higher and 400°C or lower, in an atmosphere containing one or more of nitrogen, oxygen, and noble gas.

[0230] By supplying hydrogen in this way, a region 108N having extremely low resistance can be formed in the semiconductor layer 108.

[0231] Also, by the heat treatment, oxygen can be supplied from the insulating layer 110 to the channel formation region of the semiconductor layer 108.

[0232] 〔Formation of Insulating Layer 118〕 Subsequently, an insulating layer 118 is formed on the insulating layer 116 (Fig. 12(A)).

[0233] When the insulating layer 118 is formed by plasma CVD method, if the film formation temperature is too high, depending on the impurities contained in the region 108N etc., there is a risk that the impurities diffuse to the periphery including the channel formation region of the semiconductor layer 108. As a result, there is a risk that the resistance of the channel formation region decreases and the resistance of the region 108N increases. The film formation temperature of the insulating layer 116 or the insulating layer 118 is preferably, for example, 150°C or higher and 400°C or lower, more preferably 180°C or higher and 360°C or lower, still more preferably 200°C or higher and 250°C or lower. By forming the insulating layer 118 at a low temperature, good electrical characteristics can be imparted even to a transistor with a short channel length.

[0234] Also, a heat treatment may be performed after the formation of the insulating layer 118.

[0235] 〔Formation of Opening 141a and Opening 141b〕 Subsequently, after forming a mask by lithography at a desired position of the insulating layer 118, the insulating layer 118 and a part of the insulating layer 116 are etched to form an opening 141a and an opening 141b reaching the region 108N.

[0236] 〔Formation of Conductive Layer 120a and Conductive Layer 120b〕 Subsequently, a conductive film is formed on the insulating layer 118 so as to cover the opening 141a and the opening 141b, and the conductive film is processed into a desired shape to form a conductive layer 120a and a conductive layer 120b (Fig. 12(B)).

[0237] Through the above steps, the transistor 100A can be fabricated.

[0238] <Fabrication Method Example 2> Hereinafter, a method for manufacturing a semiconductor device according to an aspect of the present invention will be described with reference to the drawings. Here, the transistor 100D illustrated in the above configuration example will be described as an example. Note that descriptions of portions overlapping with the above will be omitted, and differences will be described.

[0239] FIGS. 13(A) and 13(B) show cross-sections at each stage of the manufacturing process of the transistor 100D. In each figure, cross-sections in the channel length direction are arranged on the left side of the central broken line, and cross-sections in the channel width direction are arranged on the right side.

[0240] Until the conductive film 112f is formed, it is the same as the manufacturing method shown in <Manufacturing Method Example 1>. Therefore, the manufacturing methods of the transistors according to FIGS. 9(A) to 9(C) and FIG. 10(A) can be referred to.

[0241] [Formation of Insulating Layer 110, Metal Oxide Layer 114, and Conductive Layer 112] Subsequently, the conductive film 112f, the functional film 113f, and the metal oxide film 114f are etched to form the conductive layer 112, the functional layer 113, and the metal oxide layer 114 (FIG. 13(A)).

[0242] At this time, the ends of the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are processed so as to be located inside the contour of the resist mask 115. It is preferable to use a wet etching method for the formation of the conductive layer 112, the functional layer 113, and the metal oxide layer 114. By adjusting the etching time, the width of the region 108L can be controlled.

[0243] Also, for the formation of the conductive layer 112, the functional layer 113, and the metal oxide layer 114, after etching the conductive film 112f, the functional film 113f, and the metal oxide film 114f using an anisotropic etching method, the side surfaces of the conductive film 112f, the functional film 113f, and the metal oxide film 114f may be etched using an isotropic etching method to retract the end faces (also referred to as side etching). Thereby, in a plan view, the conductive layer 112, the functional layer 113, and the metal oxide layer 114 whose ends are located inside the ends of the insulating layer 110 can be formed.

[0244] Subsequently, in the regions not covered by the resist mask 115, the insulating film 110f is removed to form the insulating layer 110 (FIG. 13(B)). Either one or both of the wet etching method and the dry etching method can be used to form the insulating layer 110.

[0245] After the formation of the insulating layer 110, the resist mask 115 is removed.

[0246] Note that the above description can be incorporated into the subsequent processes.

[0247] Through the above processes, the transistor 100D can be fabricated.

[0248] <Fabrication Method Example 3> Hereinafter, a method for fabricating a semiconductor device according to an aspect of the present invention will be described with reference to the drawings. Here, the transistor 100E exemplified in the above configuration example will be described as an example. Note that the description of the overlapping parts with the above will be omitted, and the different parts will be described.

[0249] FIGS. 14(A) and 14(B) show cross-sections at each stage of the manufacturing process of the transistor 100E. In each figure, cross-sections in the channel length direction are arranged on the left side of the central broken line, and cross-sections in the channel width direction are arranged on the right side.

[0250] Until the formation of the conductive film 112f, it is the same as the manufacturing method shown in <Fabrication Method Example 1>. Therefore, the manufacturing methods of the transistors according to FIGS. 9(A) to 9(C) and FIG. 10(A) can be referred to.

[0251] 〔Formation of Insulating Layer 110, Metal Oxide Layer 114, and Conductive Layer 112〕 Subsequently, the conductive film 112f, the functional film 113f, and the metal oxide film 114f are etched to form the conductive layer 112, the functional layer 113, and the metal oxide layer 114 (FIG. 14(A)).

[0252] At this time, the ends of the conductive layer 112, the functional layer 113, and the metal oxide layer 114 are processed so as to be located inside the contour of the resist mask 115. Further, by using a material with a slower etching rate for the conductive layer 112 than for the functional layer 113 and the metal oxide layer 114, the ends of the conductive layer 112 are located inside the ends of the functional layer 113 and the metal oxide layer 114. For the formation of the conductive layer 112, the functional layer 113, and the metal oxide layer 114, it is preferable to use a wet etching method. By adjusting the etching time, the width of the region 108L can be controlled.

[0253] Subsequently, in the region not covered by the resist mask 115, the insulating film 110f is removed to form the insulating layer 110 (FIG. 14(B)). For the formation of the insulating layer 110, either one or both of a wet etching method and a dry etching method can be used.

[0254] After the formation of the insulating layer 110, the resist mask 115 is removed.

[0255] Note that the above description can be incorporated in the subsequent processes.

[0256] Through the above processes, the transistor 100E can be fabricated.

[0257] <Components of the semiconductor device> Next, the components included in the semiconductor device of the present embodiment will be described in detail.

[0258] 〔Substrate〕 There are no major restrictions on the material of the substrate 102, etc., but at least it is necessary to have heat resistance enough to withstand subsequent heat treatment. For example, a single-crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium, an SOI substrate, a glass substrate, a ceramic substrate, a quartz substrate, a sapphire substrate, etc. may be used as the substrate 102. Also, those with semiconductor elements provided on these substrates may be used as the substrate 102.

[0259] Further, a flexible substrate may be used as the substrate 102, and transistors 100 and the like may be formed directly on the flexible substrate. Alternatively, a release layer may be provided between the substrate 102 and the transistors 100 and the like. The release layer can be used to separate from the substrate 102 after partially or fully completing a semiconductor device thereon and transfer it to another substrate. At that time, the transistors 100 and the like can be transferred to a substrate with poor heat resistance or a flexible substrate.

[0260] 〔Insulating layer 103〕 The insulating layer 103 can be formed by appropriately using a sputtering method, a CVD method, a vapor deposition method, a pulsed laser deposition (PLD) method, or the like. Further, as the insulating layer 103, for example, an oxide insulating film or a nitride insulating film can be formed as a single layer or a laminate. In order to improve the interface characteristics with the semiconductor layer 108, it is preferable that at least the region in the insulating layer 103 in contact with the semiconductor layer 108 is formed of an oxide insulating film. Also, it is preferable to use a film that releases oxygen by heating for the insulating layer 103.

[0261] As the insulating layer 103, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, gallium oxide, or Ga-Zn oxide may be used, and can be provided as a single layer or a laminate.

[0262] Also, when a film other than an oxide film such as a silicon nitride film is used on the side of the insulating layer 103 in contact with the semiconductor layer 108, it is preferable to perform a pretreatment such as oxygen plasma treatment on the surface in contact with the semiconductor layer 108 to oxidize the surface or the vicinity of the surface.

[0263] 〔Conductive film〕 As the conductive layer 106 and the conductive layer 112 that function as gate electrodes, the conductive layer 120a that functions as one of the source electrode or the drain electrode, and the conductive layer 120b that functions as the other of the source electrode or the drain electrode, they can be respectively formed using a metal element selected from chromium, copper, aluminum, gold, silver, zinc, molybdenum, tantalum, titanium, tungsten, manganese, nickel, iron, cobalt, or an alloy containing the above-mentioned metal elements as components, or an alloy combining the above-mentioned metal elements.

[0264] In addition, an oxide conductor or a metal oxide film such as indium-tin oxide, indium-tungsten oxide, indium-tungsten-zinc oxide, indium-titanium oxide, indium-titanium-tin oxide, indium-zinc oxide, indium-tin-silicon oxide, indium-gallium-zinc oxide can also be applied to the conductive layer 106, the conductive layer 112, the conductive layer 120a, and the conductive layer 120b.

[0265] Here, the oxide conductor (OC: Oxide Conductor) will be described. For example, when oxygen vacancies are formed in a metal oxide having semiconductor characteristics and hydrogen is added to the oxygen vacancies, donor levels are formed near the conduction band. As a result, the metal oxide becomes highly conductive and is converted into a conductor. The metal oxide converted into a conductor can be referred to as an oxide conductor.

[0266] In addition, as the conductive layer 106 etc., a laminated structure of a conductive film containing the above-mentioned oxide conductor (metal oxide) and a conductive film containing a metal or an alloy may be used. By using a conductive film containing a metal or an alloy, the wiring resistance can be reduced. At this time, it is preferable to apply a conductive film containing an oxide conductor on the side in contact with the insulating layer that functions as the gate insulating film.

[0267] In addition, among the above-described metal elements, it is preferable that the conductive layer 106, the conductive layer 112, the conductive layer 120a, and the conductive layer 120b have any one or more selected particularly from titanium, tungsten, tantalum, and molybdenum. In particular, it is preferable to use a tantalum nitride film. The tantalum nitride film has conductivity, has a high barrier property against copper, oxygen, or hydrogen, and emits little hydrogen from itself. Therefore, it can be suitably used as a conductive film in contact with the semiconductor layer 108 or a conductive film in the vicinity of the semiconductor layer 108.

[0268] 〔Insulating layer 110〕 The insulating layer 110 that functions as a gate insulating film of the transistor 100 or the like can be formed by a PECVD method, a sputtering method, or the like. As the insulating layer 110, an insulating layer containing one or more of a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, a hafnium oxide film, a yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film can be used. Note that the insulating layer 110 may have a two-layer stacked structure or a stacked structure of three or more layers.

[0269] In addition, the insulating layer 110 in contact with the semiconductor layer 108 is preferably an oxide insulating film, and more preferably has a region containing oxygen in excess of the stoichiometric composition. In other words, the insulating layer 110 is an insulating film capable of releasing oxygen. For example, oxygen can be supplied into the insulating layer 110 by forming the insulating layer 110 in an oxygen atmosphere, performing heat treatment, plasma treatment, or the like on the insulating layer 110 after film formation in an oxygen atmosphere, or forming an oxide film on the insulating layer 110 in an oxygen atmosphere.

[0270] In addition, as the insulating layer 110, materials such as hafnium oxide with a higher relative permittivity than silicon oxide or silicon oxynitride can also be used. Thereby, the film thickness of the insulating layer 110 can be increased to suppress leakage current due to tunneling current. In particular, crystalline hafnium oxide is preferable because it has a higher relative permittivity than amorphous hafnium oxide.

[0271] 〔Semiconductor layer〕 When the semiconductor layer 108 is an In-M-Zn oxide, the sputtering target used for forming the In-M-Zn oxide preferably has an atomic ratio of In to element M of 1 or more. Examples of the atomic ratio of the metal elements of such a sputtering target include In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, etc.

[0272] In addition, as the sputtering target, it is preferable to use a target containing polycrystalline oxide because it is easy to form the semiconductor layer 108 having crystallinity. Note that the atomic ratio of the semiconductor layer 108 to be formed includes a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the above sputtering target. For example, when the composition of the sputtering target used for the semiconductor layer 108 is In:Ga:Zn = 4:2:4.1 [atomic ratio], the composition of the semiconductor layer 108 to be formed may be in the vicinity of In:Ga:Zn = 4:2:3 [atomic ratio].

[0273] When the atomic ratio is described as In:Ga:Zn = 4:2:3 or in the vicinity thereof, when In is 4, it includes cases where Ga is 1 or more and 3 or less, and Zn is 2 or more and 4 or less. Also, when the atomic ratio is described as In:Ga:Zn = 5:1:6 or in the vicinity thereof, when In is 5, it includes cases where Ga is greater than 0.1 and 2 or less, and Zn is 5 or more and 7 or less. Further, when the atomic ratio is described as In:Ga:Zn = 1:1:1 or in the vicinity thereof, when In is 1, it includes cases where Ga is greater than 0.1 and 2 or less, and Zn is greater than 0.1 and 2 or less.

[0274] Further, the semiconductor layer 108 has an energy gap of 2 eV or more, preferably 2.5 eV or more. Thus, by using a metal oxide having an energy gap wider than that of silicon, the off-current of the transistor can be reduced.

[0275] Also, the semiconductor layer 108 preferably has a non-single crystal structure. The non-single crystal structure includes, for example, a CAAC structure, a polycrystalline structure, a microcrystalline structure, or an amorphous structure described later. In the non-single crystal structure, the amorphous structure has the highest density of defect levels, and the CAAC structure has the lowest density of defect levels.

[0276] Hereinafter, CAAC (c-axis aligned crystal) will be described. CAAC represents an example of a crystal structure.

[0277] The CAAC structure is one of the crystal structures such as a thin film having a plurality of nano-crystals (crystal regions with a maximum diameter of less than 10 nm). Each nano-crystal has a c-axis oriented in a specific direction, and the a-axis and b-axis have no orientation, and the nano-crystals are continuously connected without forming grain boundaries with each other. In particular, a thin film having a CAAC structure has the characteristic that the c-axis of each nano-crystal is likely to be oriented in the thickness direction of the thin film, the normal direction of the surface to be formed, or the normal direction of the surface of the thin film.

[0278] CAAC-OS (Oxide Semiconductor) is an oxide semiconductor with high crystallinity. On the other hand, since no clear crystal grain boundaries can be identified in CAAC-OS, it can be said that the decrease in electron mobility caused by the crystal grain boundaries is unlikely to occur. In addition, since the crystallinity of an oxide semiconductor can be decreased by the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are resistant to heat and have high reliability.

[0279] In crystallography, it is common to take a unit cell with a specific axis as the c-axis out of the three axes (crystal axes) that make up the unit cell: the a-axis, the b-axis, and the c-axis. In particular, in crystals with a layered structure, it is common to take the two axes parallel to the plane direction of the layers as the a-axis and the b-axis, and the axis that intersects the layers as the c-axis. A typical example of a crystal with such a layered structure is graphite, which is classified as a hexagonal crystal system, and the a-axis and b-axis of its unit cell are parallel to the cleavage plane, and the c-axis is perpendicular to the cleavage plane. For example, YbFe 2 O 4 InGaZnO with a type crystal structure 4 The crystals can be classified as hexagonal, with the a-axis and b-axis of the unit cell being parallel to the plane of the layers, and the c-axis being perpendicular to the layers (i.e., the a-axis and b-axis).

[0280] In an oxide semiconductor film having a microcrystalline structure (microcrystalline oxide semiconductor film), crystal parts may not be clearly identified in an image observed by TEM. The crystal parts included in a microcrystalline oxide semiconductor film often have a size of 1 nm to 100 nm, or 1 nm to 10 nm. In particular, an oxide semiconductor film having nanocrystals (nc), which are microcrystals having a size of 1 nm to 10 nm, or 1 nm to 3 nm, is called an nc-OS (nanocrystalline oxide semiconductor) film. In addition, in an image observed by TEM, for example, in an nc-OS film, crystal grain boundaries may not be clearly identified.

[0281] The nc-OS film has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Also, in the nc-OS film, no regularity is observed in the crystal orientation between different crystal parts. Therefore, no orientation is observed in the whole film. Accordingly, depending on the analysis method, the nc-OS film may not be distinguishable from an amorphous oxide semiconductor film. For example, when performing structural analysis on the nc-OS film using an XRD apparatus that uses X-rays having a diameter larger than that of the crystal part, in the analysis by the out-of-plane method, no peak indicating a crystal plane is detected. Also, when performing electron beam diffraction (also referred to as limited field of view electron beam diffraction) on the nc-OS film using an electron beam having a probe diameter larger than that of the crystal part (for example, 50 nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, when performing electron beam diffraction (also referred to as nano-beam electron beam diffraction) on the nc-OS film using an electron beam having a probe diameter close to or smaller than that of the crystal part (for example, 1 nm or more and 30 nm or less), a region with high luminance is observed so as to draw a circle (in a ring shape), and a plurality of spots may be observed within the region.

[0282] The nc-OS film has a lower density of defect levels than an amorphous oxide semiconductor film. However, in the nc-OS film, no regularity is observed in the crystal orientation between different crystal parts. Therefore, the nc-OS film has a higher density of defect levels than the CAAC-OS film. Accordingly, the nc-OS film may have a higher carrier density and a higher electron mobility than the CAAC-OS film. Therefore, a transistor using the nc-OS film may exhibit a high field-effect mobility.

[0283] The nc-OS film can be formed by reducing the oxygen flow rate ratio during film formation as compared with the CAAC-OS film. Also, the nc-OS film can be formed by lowering the substrate temperature during film formation as compared with the CAAC-OS film. For example, since the nc-OS film can be formed even in a state where the substrate temperature is relatively low (for example, a temperature of 130°C or lower) or in a state where the substrate is not heated, it is suitable for use when using a large glass substrate, a resin substrate, etc., and productivity can be improved.

[0284] An example of the crystal structure of a metal oxide will be described. Hereinafter, a metal oxide formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) will be described as an example. When the above target is used and the substrate temperature is 100°C or higher and 130°C or lower, the metal oxide formed by the sputtering method is likely to have either an nc (nano crystal) structure or a CAAC structure, or a structure in which these are mixed. On the other hand, when the substrate temperature is room temperature (R.T.), the metal oxide formed by the sputtering method is likely to have an nc crystal structure. Here, the room temperature (R.T.) mentioned here includes the temperature when the substrate is not heated.

[0285] <Configuration of Metal Oxide> Hereinafter, the configuration of CAC (Cloud-Aligned Composite)-OS that can be used in the transistor disclosed in one aspect of the present invention will be described.

[0286] In this specification and the like, there may be cases where CAAC (c-axis aligned crystal) and CAC (Cloud-Aligned Composite) are described. Note that CAAC represents an example of a crystal structure, and CAC represents an example of a function or a configuration of a material.

[0287] CAC-OS or CAC-metal oxide has a conductive function in part of the material and an insulating function in part of the material, and has a semiconductor function as a whole. When CAC-OS or CAC-metal oxide is used in the active layer of a transistor, the conductive function is the function of flowing electrons (or holes) serving as carriers, and the insulating function is the function of not flowing electrons serving as carriers. By causing the conductive function and the insulating function to act complementarily, respectively, a switching function (On / Off function) can be imparted to CAC-OS or CAC-metal oxide. In CAC-OS or CAC-metal oxide, by separating each function, both functions can be enhanced to the maximum extent.

[0288] Also, CAC-OS or CAC-metal oxide has a conductive region and an insulating region. The conductive region has the above-described conductive function, and the insulating region has the above-described insulating function. Also, in the material, the conductive region and the insulating region may be separated at the nanoparticle level. Also, the conductive region and the insulating region may be unevenly distributed in the material, respectively. Also, the conductive region may be observed to be blurred at the periphery and connected in a cloud shape.

[0289] Also, in CAC-OS or CAC-metal oxide, the conductive region and the insulating region may be dispersed in the material with sizes of 0.5 nm or more and 10 nm or less, preferably 0.5 nm or more and 3 nm or less, respectively.

[0290] In addition, CAC-OS or CAC-metal oxide is composed of components having different bandgaps. For example, CAC-OS or CAC-metal oxide is composed of a component having a wide bandgap due to an insulating region and a component having a narrow bandgap due to a conductive region. In such a configuration, when carriers flow, the carriers mainly flow in the component having the narrow bandgap. Further, the component having the narrow bandgap acts complementarily to the component having the wide bandgap, and carriers also flow in the component having the wide bandgap in conjunction with the component having the narrow bandgap. Therefore, when the above CAC-OS or CAC-metal oxide is used in the channel formation region of a transistor, a high current driving force, that is, a large on-current, and a high field-effect mobility can be obtained in the on-state of the transistor.

[0291] That is, CAC-OS or CAC-metal oxide can also be referred to as a matrix composite or a metal matrix composite.

[0292] The above is the description of the components.

[0293] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0294] (Embodiment 2) In this embodiment, an example of a display device having the transistor exemplified in the previous embodiment will be described.

[0295] <Configuration Example> FIG. 15(A) shows a top view of a display device 700. The display device 700 has a first substrate 701 and a second substrate 705 bonded together by a sealing material 712. In a region sealed by the first substrate 701, the second substrate 705, and the sealing material 712, a pixel portion 702, a source driver circuit portion 704, and a gate driver circuit portion 706 are provided on the first substrate 701. Further, a plurality of display elements are provided in the pixel portion 702.

[0296] In addition, an FPC terminal portion 708 to which an FPC 716 (FPC: Flexible printed circuit) is connected is provided in a portion of the first substrate 701 that does not overlap with the second substrate 705. Through the FPC 716, various signals and the like are supplied to each of the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 via the FPC terminal portion 708 and a signal line 710.

[0297] A plurality of gate driver circuit portions 706 may be provided. Further, the gate driver circuit portion 706 and the source driver circuit portion 704 may be separately formed on a semiconductor substrate or the like and may be in the form of packaged IC chips. The IC chips can be mounted on the first substrate 701 or the FPC 716.

[0298] The transistors included in the pixel portion 702, the source driver circuit portion 704, and the gate driver circuit portion 706 can be applied with the transistors of a semiconductor device according to an aspect of the present invention.

[0299] Examples of display elements provided in the pixel section 702 include liquid crystal elements and light emitting elements. As the liquid crystal element, a transmissive liquid crystal element, a reflective liquid crystal element, a transflective liquid crystal element, etc. can be used. Further, examples of the light emitting element include self-luminous light emitting elements such as an LED (Light Emitting Diode), an OLED (Organic LED), a QLED (Quantum-dot LED), and a semiconductor laser. Also, MEMS (Micro Electro Mechanical Systems) elements of a shutter method or an optical interference method, display elements to which a microcapsule method, an electrophoresis method, an electro-wetting method, or an electronic ink (registered trademark) method, etc. are applied can also be used.

[0300] The display device 700A shown in FIG. 15(B) is an example of a display device that can be used as a flexible display, in which a resin layer 743 having flexibility is applied instead of the first substrate 701.

[0301] The display device 700A has a pixel section 702 that is not rectangular but has an arcuate shape at its corners. Also, as shown in the region P1 in FIG. 15(B), the pixel section 702 and a cutout section in which a part of the resin layer 743 is cut out are provided. The pair of gate driver circuit sections 706 are provided on both sides with the pixel section 702 interposed therebetween. Also, the gate driver circuit section 706 is provided along an arcuate contour at the corners of the pixel section 702.

[0302] The resin layer 743 has a shape in which a portion where the FPC terminal section 708 is provided protrudes. Also, a part of the resin layer 743 including the FPC terminal section 708 can be folded back to the back side in the region P2 in FIG. 15(B). By folding back a part of the resin layer 743, the display device 700A can be mounted on an electronic device in a state where the FPC 716 is arranged to overlap the back side of the pixel section 702, and space saving of the electronic device can be achieved.

[0303] An IC 717 is mounted on an FPC 716 connected to the display device 700A. The IC 717 has a function as a source driver circuit, for example. At this time, the source driver circuit section 704 in the display device 700A can be configured to include at least one of a protection circuit, a buffer circuit, a demultiplexer circuit, and the like.

[0304] The display device 700B shown in FIG. 15(C) is a display device that can be suitably used for an electronic device having a large screen. The display device 700B can be suitably used for, for example, a television device, a monitor device, a personal computer (including a notebook type or a desktop type), a tablet terminal, digital signage, and the like.

[0305] The display device 700B has a plurality of source driver ICs 721 and a pair of gate driver circuit sections 722.

[0306] The plurality of source driver ICs 721 are each attached to an FPC 723. Also, one terminal of each of the plurality of FPCs 723 is connected to the first substrate 701, and the other terminal is connected to the printed circuit board 724. By bending the FPC 723, the printed circuit board 724 can be disposed on the back side of the pixel portion 702 and mounted on the electronic device, thereby saving space in the electronic device.

[0307] On the other hand, the gate driver circuit section 722 is formed on the first substrate 701. Thereby, an electronic device with a narrow bezel can be realized.

[0308] With such a configuration, a large and high-resolution display device can be realized. For example, a display device with a screen size of 30 inches or more, 40 inches or more, 50 inches or more, or 60 inches or more in diagonal can be realized. Also, a display device with an extremely high resolution such as 4K2K or 8K4K can be realized.

[0309] <Cross-sectional configuration example> Hereinafter, a configuration using a liquid crystal element as a display element and a configuration using an EL element will be described with reference to FIGS. 16 to 19. Note that FIGS. 16 to 18 are cross-sectional views taken along the dashed-dotted line Q-R shown in FIG. 15(A), respectively. FIG. 19 is a cross-sectional view taken along the dashed-dotted line S-T in the display device 700A shown in FIG. 15(B). FIGS. 16 and 17 show a configuration using a liquid crystal element as a display element, and FIGS. 18 and 19 show a configuration using an EL element.

[0310] 〔Explanation of Common Parts of Display Device〕 The display devices shown in FIGS. 16 to 19 include a routing wiring portion 711, a pixel portion 702, a source driver circuit portion 704, and an FPC terminal portion 708. The routing wiring portion 711 includes signal lines 710. The pixel portion 702 includes transistors 750 and capacitor elements 790. The source driver circuit portion 704 includes a transistor 752. FIG. 17 shows a case where the capacitor element 790 is not present.

[0311] As the transistors 750 and 752, the transistors exemplified in Embodiment 1 can be applied.

[0312] The transistors used in this embodiment have an oxide semiconductor film with high purity and suppressed formation of oxygen deficiency. The transistors can reduce the off-current. Therefore, the holding time of electrical signals such as image signals can be lengthened, and the writing interval of image signals and the like can also be set longer. Therefore, the frequency of the refresh operation can be reduced, and the effect of reducing power consumption is achieved.

[0313] In addition, since the transistor used in this embodiment can obtain a relatively high field-effect mobility, it can be driven at high speed. For example, by using such a transistor capable of high-speed driving in a display device, a switching transistor in a pixel portion and a driver transistor used in a driving circuit portion can be formed on the same substrate. That is, a configuration that does not apply a driving circuit formed of a silicon wafer or the like is also possible, and the number of components of the display device can be reduced. Also, in the pixel portion, by using a transistor capable of high-speed driving, a high-quality image can be provided.

[0314] The capacitor element 790 shown in FIGS. 16, 18, and 19 has a lower electrode formed by processing the same film as the first gate electrode of the transistor 750, and an upper electrode formed by processing the same metal oxide as the semiconductor layer. The upper electrode has a reduced resistance in the same manner as the source region and the drain region of the transistor 750. Also, a part of the insulating film that functions as the first gate insulating layer of the transistor 750 is provided between the lower electrode and the upper electrode. That is, the capacitor element 790 has a stacked structure in which an insulating film that functions as a dielectric film is sandwiched between a pair of electrodes. Further, a wiring obtained by processing the same film as the source electrode and the drain electrode of the transistor is connected to the upper electrode.

[0315] Also, a planarization insulating film 770 is provided on the transistor 750, the transistor 752, and the capacitor element 790.

[0316] Transistors of different structures may be used for the transistor 750 included in the pixel portion 702 and the transistor 752 included in the source driver circuit portion 704. For example, a configuration in which a top-gate type transistor is applied to one of them and a bottom-gate type transistor is applied to the other may be used. Note that the same applies to the gate driver circuit portion 706 as to the source driver circuit portion 704.

[0317] The signal line 710 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 750 and 752. At this time, it is preferable to use a low-resistance material such as a material containing copper element, because signal delay and the like due to wiring resistance are small, and display on a large screen becomes possible.

[0318] The FPC terminal portion 708 has a wiring 760, an anisotropic conductive film 780, and an FPC 716, a part of which functions as a connection electrode. The wiring 760 is electrically connected to the terminals of the FPC 716 via the anisotropic conductive film 780. Here, the wiring 760 is formed of the same conductive film as the source electrodes and drain electrodes of the transistors 750 and 752.

[0319] As the first substrate 701 and the second substrate 705, a flexible substrate such as a glass substrate or a plastic substrate can be used. When a flexible substrate is used for the first substrate 701, it is preferable to provide an insulating layer having a barrier property against water and hydrogen between the first substrate 701 and the transistors 750 and the like.

[0320] On the second substrate 705 side, a light-shielding film 738, a colored film 736, and an insulating film 734 in contact with these are provided.

[0321] 〔Configuration example of display device using liquid crystal element〕 The display device 700 shown in FIG. 16 has a liquid crystal element 775 and a spacer 778. The liquid crystal element 775 has a conductive layer 772, a conductive layer 774, and a liquid crystal layer 776 therebetween. The conductive layer 774 is provided on the second substrate 705 side and functions as a common electrode. The conductive layer 772 is electrically connected to the source electrode or drain electrode of the transistor 750. The conductive layer 772 is formed on the planarization insulating film 770 and functions as a pixel electrode.

[0322] For the conductive layer 772, a material that is transparent to visible light or a reflective material can be used. As the transparent material, for example, an oxide material containing indium, zinc, tin, etc. may be used. As the reflective material, for example, a material containing aluminum, silver, etc. may be used.

[0323] When a reflective material is used for the conductive layer 772, the display device 700 becomes a reflective liquid crystal display device. On the other hand, when a transparent material is used for the conductive layer 772, it becomes a transmissive liquid crystal display device. In the case of a reflective liquid crystal display device, a polarizing plate is provided on the viewing side. On the other hand, in the case of a transmissive liquid crystal display device, a pair of polarizing plates are provided so as to sandwich the liquid crystal element.

[0324] The display device 700 shown in FIG. 17 shows an example using a liquid crystal element 775 of the horizontal electric field type (for example, FFS mode). A conductive layer 774 that functions as a common electrode is provided on the conductive layer 772 via an insulating layer 773. The alignment state of the liquid crystal layer 776 can be controlled by the electric field generated between the conductive layer 772 and the conductive layer 774.

[0325] In FIG. 17, a holding capacitance can be formed by the laminated structure of the conductive layer 774, the insulating layer 773, and the conductive layer 772. Therefore, there is no need to provide a separate capacitance element, and the aperture ratio can be increased.

[0326] Although not shown in FIGS. 16 and 17, a configuration in which an alignment film in contact with the liquid crystal layer 776 may be provided. Also, optical members (optical substrates) such as polarizing members, retardation members, and anti-reflection members, and light sources such as backlights and side lights can be appropriately provided.

[0327] For the liquid crystal layer 776, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal (PDLC: Polymer Dispersed Liquid Crystal), a polymer network liquid crystal (PNLC: Polymer Network Liquid Crystal), a ferroelectric liquid crystal, an antiferroelectric liquid crystal, etc. can be used. Also, when adopting the horizontal electric field method, a liquid crystal showing a blue phase without using an alignment film may be used.

[0328] Also, as the mode of the liquid crystal element, a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, an IPS (In-Plane-Switching) mode, an FFS (Fringe Field Switching) mode, an ASM (Axially Symmetric aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, an ECB (Electrically Controlled Birefringence) mode, a guest-host mode, etc. can be used.

[0329] Also, a scattering-type liquid crystal element using polymer-dispersed liquid crystal, polymer network liquid crystal, etc. in the liquid crystal layer 776 can be used. At this time, it may be configured to perform black-and-white display without providing the color filter 736, or it may be configured to perform color display using the color filter 736.

[0330] Also, as a driving method of the liquid crystal element, a time-division display method (also called a field-sequential driving method) that performs color display based on a sequential addition color mixing method may be applied. In that case, a configuration without providing the color filter 736 can be adopted. When the time-division display method is used, for example, since it is not necessary to provide sub-pixels that exhibit each color of R (red), G (green), and B (blue), there are advantages such as improving the aperture ratio of the pixel and enhancing the fineness.

[0331] [Display device using a light-emitting element] The display device 700 shown in FIG. 18 has a light-emitting element 782. The light-emitting element 782 has a conductive layer 772, an EL layer 786, and a conductive film 788. The EL layer 786 has an organic compound or an inorganic compound such as a quantum dot.

[0332] Examples of materials that can be used for organic compounds include fluorescent materials or phosphorescent materials. Examples of materials that can be used for quantum dots include colloidal quantum dot materials, alloy-type quantum dot materials, core-shell-type quantum dot materials, core-type quantum dot materials, and the like.

[0333] In the display device 700 shown in FIG. 18, an insulating film 730 that covers a part of the conductive layer 772 is provided on the planarizing insulating film 770. Here, the light-emitting element 782 has a translucent conductive film 788 and is a top-emission type light-emitting element. Note that the light-emitting element 782 may have a bottom-emission structure that emits light toward the conductive layer 772 side, or a dual-emission structure that emits light toward both the conductive layer 772 side and the conductive film 788 side.

[0334] The colored film 736 is provided at a position overlapping with the light-emitting element 782, and the light-shielding film 738 is provided at positions overlapping with the insulating film 730, the wiring portion 711, and the source driver circuit portion 704. The colored film 736 and the light-shielding film 738 are covered with the insulating film 734. The space between the light-emitting element 782 and the insulating film 734 is filled with a sealing film 732. Note that in a case where the EL layer 786 is formed in an island shape for each pixel or in a stripe shape for each pixel column, that is, formed by painting, the colored film 736 may not be provided.

[0335] FIG. 19 shows a configuration of a display device that can be suitably applied to a flexible display. FIG. 19 is a cross-sectional view taken along the chain double-dashed line S-T in the display device 700A shown in FIG. 15(B).

[0336] The display device 700A shown in FIG. 19 has a structure in which a support substrate 745, an adhesive layer 742, a resin layer 743, and an insulating layer 744 are laminated instead of the first substrate 701 shown in FIG. 18. The transistor 750, the capacitor element 790, and the like are provided on the insulating layer 744 provided on the resin layer 743.

[0337] The support substrate 745 includes organic resin, glass, etc., and is a thin substrate having flexibility. The resin layer 743 is a layer containing an organic resin such as polyimide or acrylic. The insulating layer 744 includes an inorganic insulating film such as silicon oxide, silicon oxynitride, or silicon nitride. The resin layer 743 and the support substrate 745 are bonded together by an adhesive layer 742. The resin layer 743 is preferably thinner than the support substrate 745.

[0338] In addition, the display device 700 shown in FIG. 19 has a protective layer 740 instead of the substrate 705 shown in FIG. 18. The protective layer 740 is bonded to the sealing film 732. As the protective layer 740, a glass substrate, a resin film, or the like can be used. Further, as the protective layer 740, an optical member such as a polarizing plate or a diffusing plate, an input device such as a touch sensor panel, or a configuration in which two or more of these are laminated may be applied.

[0339] In addition, the EL layer 786 included in the light-emitting element 782 is provided in an island shape on the insulating film 730 and the conductive layer 772. By making the EL layer 786 different in emission color for each sub-pixel, color display can be realized without using the coloring film 736. Further, a protective layer 741 is provided to cover the light-emitting element 782. The protective layer 741 has a function of preventing impurities such as water from diffusing into the light-emitting element 782. The protective layer 741 is preferably an inorganic insulating film. More preferably, it has a laminated structure including one or more inorganic insulating films and one or more organic insulating films.

[0340] In addition, FIG. 19 shows a foldable region P2. In the region P2, there is a portion where no inorganic insulating film such as the support substrate 745 and the insulating layer 744 is provided in addition to the adhesive layer 742. Further, in the region P2, a resin layer 746 is provided to cover the wiring 760. By configuring the foldable region P2 to have as few inorganic insulating films as possible and laminating only a conductive layer containing a metal or an alloy and a layer containing an organic material, it is possible to prevent cracks from occurring when bent. Further, by not providing the support substrate 745 in the region P2, a part of the display device 700A can be bent with an extremely small radius of curvature.

[0341] 〔Configuration example of providing an input device to a display device〕 In addition, an input device may be provided to the display device shown in FIGS. 16 to 19. Examples of the input device include a touch sensor and the like.

[0342] For example, as the sensor method, various methods such as a capacitance method, a resistive film method, a surface acoustic wave method, an infrared method, an optical method, and a pressure sensitive method can be used. Or, two or more of these may be used in combination.

[0343] Note that the configuration of the touch panel includes a so-called in-cell type touch panel in which the input device is formed between a pair of substrates, a so-called on-cell type touch panel in which the input device is formed on the display device, or a so-called out-cell type touch panel that is used by being bonded to the display device.

[0344] The configuration examples illustrated in this embodiment, and the corresponding drawings, etc. can be implemented by appropriately combining at least a part of them with other configuration examples, or drawings, etc.

[0345] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification.

[0346] (Embodiment 3) In this embodiment, a display device having a semiconductor device according to an aspect of the present invention will be described with reference to FIG. 20.

[0347] The display device shown in FIG. 20(A) includes a pixel portion 502, a drive circuit portion 504, a protection circuit 506, and a terminal portion 507. Note that the protection circuit 506 may not be provided.

[0348] The transistor included in the pixel portion 502 or the drive circuit portion 504 can be applied with the transistor according to an aspect of the present invention. Also, the transistor according to an aspect of the present invention may be applied to the protection circuit 506.

[0349] The pixel section 502 has a plurality of pixel circuits 501 that drive a plurality of display elements arranged in X rows and Y columns (X and Y are each independently natural numbers of 2 or more).

[0350] The drive circuit section 504 has drive circuits such as a gate driver 504a that outputs a scan signal to the scan lines GL_1 to GL_X and a source driver 504b that supplies a data signal to the data lines DL_1 to DL_Y. The gate driver 504a may be configured to have at least a shift register. Also, the source driver 504b is configured using, for example, a plurality of analog switches. Further, the source driver 504b may be configured using a shift register or the like.

[0351] The terminal section 507 refers to a portion where terminals for inputting power, a control signal, an image signal, etc. from an external circuit to the display device are provided.

[0352] The protection circuit 506 is a circuit that makes a wiring to which it is connected and another wiring in a conductive state when a potential outside a certain range is applied to the wiring to which it is connected. The protection circuit 506 shown in FIG. 20(A) is connected to various wirings such as a scan line GL that is a wiring between the gate driver 504a and the pixel circuit 501 or a data line DL that is a wiring between the source driver 504b and the pixel circuit 501.

[0353] Also, the gate driver 504a and the source driver 504b may be provided on the same substrate as the pixel section 502, or a configuration may be adopted in which a gate driver circuit or a source driver circuit formed on a separate substrate (for example, a drive circuit substrate formed of a single crystal semiconductor film or a polycrystalline semiconductor film) is mounted on the substrate by COG or TAB (Tape Automated Bonding).

[0354] Also, the plurality of pixel circuits 501 shown in FIG. 20(A) can be configured as shown in FIGS. 20(B) and 20(C), for example.

[0355] The pixel circuit 501 shown in FIG. 20(B) includes a liquid crystal element 570, a transistor 550, and a capacitor element 560. Further, a data line DL_n, a scanning line GL_m, a potential supply line VL, etc. are connected to the pixel circuit 501.

[0356] One of the potentials of the pair of electrodes of the liquid crystal element 570 is appropriately set according to the specifications of the pixel circuit 501. The alignment state of the liquid crystal element 570 is set according to the data to be written. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal elements 570 included in each of the plurality of pixel circuits 501. Alternatively, different potentials may be applied to one of the pair of electrodes of the liquid crystal elements 570 in the pixel circuits 501 of each row.

[0357] Also, the pixel circuit 501 shown in FIG. 20(C) includes transistors 552 and 554, a capacitor element 562, and a light-emitting element 572. Further, a data line DL_n, a scanning line GL_m, a potential supply line VL_a, a potential supply line VL_b, etc. are connected to the pixel circuit 501.

[0358] Note that a high power supply potential VDD is applied to one of the potential supply line VL_a and the potential supply line VL_b, and a low power supply potential VSS is applied to the other. The current flowing through the light-emitting element 572 is controlled according to the potential applied to the gate of the transistor 554, thereby controlling the emission luminance from the light-emitting element 572.

[0359] The configuration examples illustrated in this embodiment, and the drawings etc. corresponding thereto, can be implemented by appropriately combining at least a part of them with other configuration examples, drawings, etc.

[0360] This embodiment can be implemented by appropriately combining at least a part of it with other embodiments described in this specification.

[0361] (Embodiment 4) Hereinafter, a pixel circuit including a memory for correcting the gradation displayed on a pixel and a display device having the same will be described. The transistor exemplified in Embodiment 1 can be applied to the transistor used in the pixel circuit exemplified below.

[0362] <Circuit Configuration> FIG. 21(A) shows a circuit diagram of a pixel circuit 400. The pixel circuit 400 includes a transistor M1, a transistor M2, a capacitor C1, and a circuit 401. Further, a wiring S1, a wiring S2, a wiring G1, and a wiring G2 are connected to the pixel circuit 400.

[0363] The gate of the transistor M1 is connected to the wiring G1, one of the source and the drain is connected to the wiring S1, and the other of the source and the drain is connected to one electrode of the capacitor C1. The gate of the transistor M2 is connected to the wiring G2, one of the source and the drain is connected to the wiring S2, and the other of the source and the drain is connected to the other electrode of the capacitor C1 and the circuit 401.

[0364] The circuit 401 is a circuit including at least one display element. Various elements can be used as the display element, but typically, a light-emitting element such as an organic EL element or an LED element, a liquid crystal element, or a MEMS (Micro Electro Mechanical Systems) element can be applied.

[0365] Let the node connecting the transistor M1 and the capacitor C1 be node N1, and the node connecting the transistor M2 and the circuit 401 be node N2.

[0366] The pixel circuit 400 can hold the potential of the node N1 by turning off the transistor M1. Further, the potential of the node N2 can be held by turning off the transistor M2. Further, with the transistor M2 turned off, by writing a predetermined potential to the node N1 via the transistor M1, the potential of the node N2 can be changed according to the displacement of the potential of the node N1 by capacitive coupling through the capacitor C1.

[0367] Here, one or both of the transistors M1 and M2 can be a transistor to which an oxide semiconductor exemplified in Embodiment 1 is applied. Therefore, due to an extremely low off-current, the potentials of the nodes N1 and N2 can be held for a long period. When the period for holding the potential of each node is short (specifically, when the frame frequency is 30 Hz or more, etc.), a transistor using a semiconductor such as silicon may be used.

[0368] <Example of driving method> Next, with reference to FIG. 21(B), an example of an operation method of the pixel circuit 400 will be described. FIG. 21(B) is a timing chart related to the operation of the pixel circuit 400. Here, for ease of explanation, various resistances such as wiring resistance, parasitic capacitances of transistors and wirings, and the influence of threshold voltages of transistors are not considered.

[0369] In the operation shown in FIG. 21(B), one frame period is divided into a period T1 and a period T2. The period T1 is a period for writing a potential to the node N2, and the period T2 is a period for writing a potential to the node N1.

[0370] 〔Period T1〕 In the period T1, potentials for turning on the transistors are applied to both the wiring G1 and the wiring G2. Also, a potential V ref which is a fixed potential is supplied to the wiring S1, and a first data potential V w is supplied to the wiring S2.

[0371] The potential V ref is applied to the node N1 from the wiring S1 through the transistor M1. Also, the first data potential V w is applied to the node N2 from the wiring S2 through the transistor M2. Therefore, a potential difference V w -V ref is held in the capacitor C1.

[0372] 〔Period T2〕 Subsequently, in period T2, a potential that turns on transistor M1 is applied to wiring G1, and a potential that turns off transistor M2 is applied to wiring G2. Also, a second data potential V data is supplied to wiring S1. A predetermined fixed potential may be applied to wiring S2, or it may be in a floating state.

[0373] At node N1, the second data potential V data is applied via transistor M1. At this time, due to capacitive coupling by capacitor C1, the potential of node N2 changes by potential dV according to the second data potential V data . That is, a potential obtained by adding the first data potential Vw and potential dV is input to circuit 401. Although FIG. 21(B) shows that potential dV is a positive value, it may be a negative value. That is, the second data potential V data may be lower than potential V ref .

[0374] Here, potential dV is generally determined by the capacitance value of capacitor C1 and the capacitance value of circuit 401. When the capacitance value of capacitor C1 is sufficiently larger than the capacitance value of circuit 401, potential dV becomes a potential close to the second data potential V data .

[0375] In this way, pixel circuit 400 can generate a potential to be supplied to circuit 401 including a display element by combining two types of data signals, so that gradation correction can be performed within pixel circuit 400.

[0376] Also, pixel circuit 400 can generate a potential exceeding the maximum potential that can be supplied to wiring S1 and wiring S2. For example, when a light-emitting element is used, high dynamic range (HDR) display or the like can be performed. Also, when a liquid crystal element is used, overdrive driving or the like can be realized.

[0377] <Application Example> [Example using a liquid crystal element] The pixel circuit 400LC shown in FIG. 21(C) has a circuit 401LC. The circuit 401LC has a liquid crystal element LC and a capacitor C2.

[0378] One electrode of the liquid crystal element LC is connected to the other electrode of the capacitor C1, the other of the source and drain of the transistor M2, and one electrode of the capacitor C2, and the other electrode is connected to a wiring to which a potential V com2 is applied. The capacitor C2 has its other electrode connected to a wiring to which a potential V com1 is applied.

[0379] The capacitor C2 functions as a holding capacitor. If the capacitor C2 is not necessary, it can be omitted.

[0380] Since the pixel circuit 400LC can supply a high voltage to the liquid crystal element LC, for example, high-speed display can be realized by overdrive driving, and a liquid crystal material with a high driving voltage can be applied. Also, by supplying a correction signal to the wiring S1 or the wiring S2, gradation can be corrected according to the use temperature, the deterioration state of the liquid crystal element LC, etc.

[0381] [Example using a light-emitting element] The pixel circuit 400EL shown in FIG. 21(D) has a circuit 401EL. The circuit 401EL has a light-emitting element EL, a transistor M3, and a capacitor C2.

[0382] The transistor M3 has its gate connected to one electrode of the capacitor C2, one of its source and drain connected to a wiring to which a potential V H is applied, and the other connected to one electrode of the light-emitting element EL, respectively. The capacitor C2 has its other electrode connected to a wiring to which a potential V com is applied. The light-emitting element EL has its other electrode connected to a wiring to which a potential V L is applied.

[0383] The transistor M3 has a function of controlling the current supplied to the light-emitting element EL. The capacitor C2 functions as a holding capacitor. If the capacitor C2 is not necessary, it can be omitted.

[0384] Here, a configuration in which the anode side of the light-emitting element EL is connected to the transistor M3 is shown, but the transistor M3 may be connected to the cathode side. At this time, the values of the potential V H and the potential V L can be appropriately changed.

[0385] By applying a high potential to the gate of the transistor M3, the pixel circuit 400EL can pass a large current through the light-emitting element EL, so that, for example, HDR display or the like can be realized. Also, by supplying a correction signal to the wiring S1 or the wiring S2, it is possible to correct variations in the electrical characteristics of the transistor M3 and the light-emitting element EL.

[0386] Note that the present invention is not limited to the circuits illustrated in FIGS. 21(C) and 21(D), and a configuration in which transistors, capacitors, or the like are additionally provided may be adopted.

[0387] This embodiment can be implemented in appropriate combination with at least some of the other embodiments described in this specification.

[0388] (Embodiment 5) In this embodiment, a display module that can be manufactured using one aspect of the present invention will be described.

[0389] The display module 6000 shown in FIG. 22(A) includes a display device 6006, a frame 6009, a printed circuit board 6010, and a battery 6011 to which an FPC 6005 is connected between an upper cover 6001 and a lower cover 6002.

[0390] For example, a display device manufactured using one aspect of the present invention can be used as the display device 6006. With the display device 6006, a display module with extremely low power consumption can be realized.

[0391] The upper cover 6001 and the lower cover 6002 can be appropriately changed in shape and dimensions according to the size of the display device 6006.

[0392] The display device 6006 may have a function as a touch panel.

[0393] The frame 6009 may have a protection function for the display device 6006, a function of blocking electromagnetic waves generated by the operation of the printed circuit board 6010, a function as a heat sink, etc.

[0394] The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting video signals and clock signals, a battery control circuit, etc.

[0395] FIG. 22(B) is a schematic cross-sectional view of the display module 6000 including an optical touch sensor.

[0396] The display module 6000 has a light emitting part 6015 and a light receiving part 6016 provided on the printed circuit board 6010. Also, it has a pair of light guide parts (light guide part 6017a, light guide part 6017b) in a region surrounded by the upper cover 6001 and the lower cover 6002.

[0397] The display device 6006 is provided overlapping the printed circuit board 6010 and the battery 6011 with the frame 6009 in between. The display device 6006 and the frame 6009 are fixed to the light guide part 6017a and the light guide part 6017b.

[0398] The light 6018 emitted from the light emitting part 6015 passes through the upper part of the display device 6006 by the light guide part 6017a, passes through the light guide part 6017b, and reaches the light receiving part 6016. For example, when the light 6018 is blocked by a detection object such as a finger or a stylus, a touch operation can be detected.

[0399] A plurality of light emitting parts 6015 are provided, for example, along two adjacent sides of the display device 6006. A plurality of light receiving parts 6016 are provided at positions facing the light emitting parts 6015. Thereby, information on the position where the touch operation is performed can be acquired.

[0400] The light emitting unit 6015 can use a light source such as an LED element, and in particular, it is preferable to use a light source that emits infrared rays. The light receiving unit 6016 can use a photoelectric element that receives the light emitted by the light emitting unit 6015 and converts it into an electrical signal. Preferably, a photodiode capable of receiving infrared rays can be used.

[0401] The light emitting unit 6015 and the light receiving unit 6016 can be arranged below the display device 6006 by the light guide parts 6017a and 6017b that transmit the light 6018, and it is possible to suppress external light from reaching the light receiving unit 6016 and causing the touch sensor to malfunction. In particular, when using a resin that absorbs visible light and transmits infrared rays, malfunction of the touch sensor can be more effectively suppressed.

[0402] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

[0403] (Embodiment 6) In this embodiment, an example of an electronic device to which the display device of one aspect of the present invention is applicable will be described.

[0404] The electronic device 6500 shown in Fig. 23(A) is a portable information terminal that can be used as a smartphone.

[0405] The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508, etc. The display unit 6502 has a touch panel function.

[0406] The display device of one aspect of the present invention can be applied to the display unit 6502.

[0407] Fig. 23(B) is a schematic cross-sectional view including the end portion on the microphone 6506 side of the housing 6501.

[0408] On the display surface side of the housing 6501, a protective member 6510 having translucency is provided, and a display panel 6511, an optical member 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0409] The display panel 6511, the optical member 6512, and the touch sensor panel 6513 are fixed to the protective member 6510 by an adhesive layer (not shown).

[0410] Also, in a region outside the display unit 6502, a part of the display panel 6511 is folded back. An FPC 6515 is connected to the folded-back portion. An IC 6516 is mounted on the FPC 6515. Also, the FPC 6515 is connected to a terminal provided on the printed circuit board 6517.

[0411] The flexible display panel according to one aspect of the present invention can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Also, since the display panel 6511 is extremely thin, it is possible to mount a large-capacity battery 6518 while suppressing the thickness of the electronic device. Also, by folding back a part of the display panel 6511 and arranging the connection portion with the FPC 6515 on the back side of the pixel portion, a narrow bezel electronic device can be realized.

[0412] This embodiment can be implemented in appropriate combination with other embodiments described in this specification, at least in part.

[0413] (Embodiment 7) In this embodiment, an electronic device including a display device manufactured using one aspect of the present invention will be described.

[0414] The electronic device exemplified below includes a display device according to one aspect of the present invention in the display unit. Therefore, it is an electronic device that realizes a high resolution. Also, it can be an electronic device that achieves both a high resolution and a large screen.

[0415] The display unit of the electronic device according to one aspect of the present invention can display videos having a resolution of, for example, full high vision, 4K2K, 8K4K, 16K8K, or higher.

[0416] Examples of the electronic device include not only electronic devices having a relatively large screen such as a television device, a notebook personal computer, a monitor device, a digital signage, a pachinko machine, and a game machine, but also a digital camera, a digital video camera, a digital photo frame, a mobile phone, a portable game machine, a portable information terminal, an audio reproduction device, and the like.

[0417] The electronic device to which one aspect of the present invention is applied can be incorporated along a flat or curved surface of an inner wall or outer wall of a house or building, an interior or exterior of an automobile, or the like.

[0418] FIG. 24(A) is a view showing the appearance of the camera 8000 with the finder 8100 attached.

[0419] The camera 8000 includes a housing 8001, a display unit 8002, operation buttons 8003, a shutter button 8004, and the like. A detachable lens 8006 is attached to the camera 8000.

[0420] Note that the lens 8006 and the housing of the camera 8000 may be integrated.

[0421] The camera 8000 can perform imaging by pressing the shutter button 8004 or touching the display unit 8002 that functions as a touch panel.

[0422] The housing 8001 has a mount having an electrode, and in addition to the finder 8100, a strobe device or the like can be connected.

[0423] The finder 8100 includes a housing 8101, a display unit 8102, buttons 8103, and the like.

[0424] The housing 8101 is attached to the camera 8000 by a mount that engages with the mount of the camera 8000. The viewfinder 8100 can display images and the like received from the camera 8000 on the display unit 8102.

[0425] The button 8103 has a function as a power button or the like.

[0426] The display device according to an aspect of the present invention can be applied to the display unit 8002 of the camera 8000 and the display unit 8102 of the viewfinder 8100. Note that the camera 8000 may have a built-in viewfinder.

[0427] FIG. 24(B) is a diagram showing the appearance of the head-mounted display 8200.

[0428] The head-mounted display 8200 includes a mounting portion 8201, a lens 8202, a main body 8203, a display unit 8204, a cable 8205, etc. A battery 8206 is built into the mounting portion 8201.

[0429] The cable 8205 supplies power from the battery 8206 to the main body 8203. The main body 8203 includes a wireless receiver or the like and can display the received video information on the display unit 8204. Further, the main body 8203 includes a camera and can use information on the movement of the user's eyeballs and eyelids as input means.

[0430] In addition, the mounting portion 8201 may be provided with a plurality of electrodes capable of detecting a current flowing along with the movement of the user's eyeballs at a position where it touches the user, and may have a function of recognizing the line of sight. Further, it may have a function of monitoring the user's pulse based on the current flowing through the electrodes. In addition, the mounting portion 8201 may include various sensors such as a temperature sensor, a pressure sensor, and an acceleration sensor, and may have a function of displaying the user's biological information on the display unit 8204 or a function of changing the video displayed on the display unit 8204 in accordance with the movement of the user's head.

[0431] The display device according to one aspect of the present invention can be applied to the display unit 8204.

[0432] FIGS. 24(C), 24(D) and 24(E) are diagrams showing the appearance of the head-mounted display 8300. The head-mounted display 8300 includes a housing 8301, a display unit 8302, a band-shaped fixture 8304, and a pair of lenses 8305.

[0433] The user can visually recognize the display of the display unit 8302 through the lenses 8305. It is preferable to arrange the display unit 8302 in a curved shape because the user can feel a high sense of immersion. In addition, by visually recognizing different images displayed in different regions of the display unit 8302 through the lenses 8305, three-dimensional display using parallax or the like can also be performed. Note that the configuration is not limited to providing one display unit 8302, and two display units 8302 may be provided, with one display unit arranged for each eye of the user.

[0434] The display device according to one aspect of the present invention can be applied to the display unit 8302. Since the display device having the semiconductor device according to one aspect of the present invention has extremely high definition, even when enlarged using the lenses 8305 as shown in FIG. 24(E), a more realistic image can be displayed without the user visually recognizing the pixels.

[0435] The electronic device shown in FIGS. 25(A) to 25(G) includes a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), connection terminals 9006, a sensor 9007 (including a function of measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, and the like.

[0436] The electronic devices shown in FIGS. 25(A) to 25(G) have various functions. For example, they can have functions such as displaying various information (still images, moving images, text images, etc.) on a display unit, a touch panel function, a function of displaying a calendar, date, or time, a function of controlling processing by various software (programs), a wireless communication function, a function of reading and processing programs or data recorded on a recording medium, and the like. Note that the functions of the electronic device are not limited to these, and it can have various functions. The electronic device may have a plurality of display units. Further, the electronic device may be provided with a camera or the like, and may have functions such as taking still images and moving images and storing them in a recording medium (external or built into the camera), and a function of displaying the taken images on the display unit.

[0437] Details of the electronic devices shown in FIGS. 25(A) to 25(G) will be described below.

[0438] FIG. 25(A) is a perspective view showing a television device 9100. The television device 9100 can incorporate a large screen, for example, a display unit 9001 of 50 inches or more, or 100 inches or more.

[0439] FIG. 25(B) is a perspective view showing a portable information terminal 9101. The portable information terminal 9101 can be used as, for example, a smartphone. Note that the portable information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, etc. Further, the portable information terminal 9101 can display character and image information on its plurality of surfaces. FIG. 25(B) shows an example in which three icons 9050 are displayed. Also, information 9051 indicated by a dashed rectangle can be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming calls such as e-mail, SNS, and telephone, titles of e-mail and SNS, sender names, dates, times, remaining battery levels, antenna reception strengths, and the like. Or, icons 9050 or the like may be displayed at the position where the information 9051 is displayed.

[0440] FIG. 25(C) is a perspective view showing the portable information terminal 9102. The portable information terminal 9102 has a function of displaying information on three or more sides of the display unit 9001. Here, an example is shown in which the information 9052, the information 9053, and the information 9054 are displayed on different sides respectively. For example, the user can also check the information 9053 displayed at a position where it can be observed from above the portable information terminal 9102 in a state where the portable information terminal 9102 is stored in the breast pocket of the clothing. The user can check the display without taking out the portable information terminal 9102 from the pocket, and can judge whether to receive a call, for example.

[0441] FIG. 25(D) is a perspective view showing the wristwatch-type portable information terminal 9200. The portable information terminal 9200 can be used as, for example, a smart watch. Further, the display surface of the display unit 9001 is provided in a curved shape, and display can be performed along the curved display surface. Further, the portable information terminal 9200 can also make a hands-free call by communicating with, for example, a wirelessly communicable headset. Further, the portable information terminal 9200 can also perform data transmission and charging mutually with other information terminals through the connection terminal 9006. Note that the charging operation may be performed by wireless power supply.

[0442] FIGS. 25(E), 25(F), and 25(G) are perspective views showing the foldable portable information terminal 9201. Further, FIG. 25(E) is a state in which the portable information terminal 9201 is unfolded, FIG. 25(G) is a folded state, and FIG. 25(F) is a perspective view of a state in the process of changing from one of FIGS. 25(E) and 25(G) to the other. The portable information terminal 9201 has excellent portability in the folded state, and excellent display comprehensibility due to a seamless wide display area in the unfolded state. The display unit 9001 included in the portable information terminal 9201 is supported by three housings 9000 connected by a hinge 9055. For example, the display unit 9001 can be bent with a curvature radius of 1 mm or more and 150 mm or less.

[0443] Fig. 26(A) shows an example of a television apparatus. In the television apparatus 7100, a display unit 7500 is incorporated in a housing 7101. Here, a configuration is shown in which the housing 7101 is supported by a stand 7103.

[0444] The operation of the television apparatus 7100 shown in Fig. 26(A) can be performed by operation switches provided in the housing 7101 or by a separate remote control operation unit 7111. Alternatively, a touch panel may be applied to the display unit 7500, and the television apparatus 7100 may be operated by touching it. The remote control operation unit 7111 may have a display unit in addition to operation buttons.

[0445] Note that the television apparatus 7100 may have a television broadcast receiver and a communication device for network connection.

[0446] Fig. 26(B) shows a notebook personal computer 7200. The notebook personal computer 7200 has a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, etc. A display unit 7500 is incorporated in the housing 7211.

[0447] Figs. 26(C) and 26(D) show an example of digital signage.

[0448] The digital signage 7300 shown in Fig. 26(C) has a housing 7301, a display unit 7500, a speaker 7303, etc. Further, it can have an LED lamp, operation keys (including a power switch or operation switches), connection terminals, various sensors, a microphone, etc.

[0449] Also, Fig. 26(D) shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7500 provided along the curved surface of the pillar 7401.

[0450] The larger the display unit 7500 is, the more information can be provided at one time, and since it is easy to catch people's eyes, for example, it has the effect of enhancing the advertising effect.

[0451] It is preferable to apply a touch panel to the display unit 7500 so that the user can operate it. As a result, it can be used not only for advertising purposes but also for purposes of providing information required by the user, such as route information, traffic information, and guidance information for commercial facilities.

[0452] Also, as shown in FIGS. 26(C) and 26(D), it is preferable that the digital signage 7300 or the digital signage 7400 can be linked by wireless communication with an information terminal 7311 such as a smartphone held by the user. For example, the information of the advertisement displayed on the display unit 7500 can be displayed on the screen of the information terminal 7311, and the display of the display unit 7500 can be switched by operating the information terminal 7311.

[0453] Also, a game using the information terminal 7311 as an operation means (controller) can be executed on the digital signage 7300 or the digital signage 7400. As a result, an unspecified number of users can participate in the game and enjoy it at the same time.

[0454] The display device according to one aspect of the present invention can be applied to the display unit 7500 in FIGS. 26(A) to 26(D).

[0455] Although the electronic device of the present embodiment is configured to have a display unit, one aspect of the present invention can also be applied to an electronic device that does not have a display unit.

[0456] This embodiment can be implemented in appropriate combination with at least a part of other embodiments described in this specification.

Example

[0457] In this example, as examples of materials that can be used for the conductive layer 112, the functional layer 113, the metal oxide layer 114, or the insulating layer 110, the etching rates of copper, titanium, molybdenum, ITSO, metal oxides, and silicon oxynitride were evaluated. For silicon oxynitride, three types of films with different film formation conditions (silicon oxynitride 1, silicon oxynitride 2, and silicon oxynitride 3) were evaluated.

[0458] For the evaluation, samples with various films formed on a glass substrate were used.

[0459] The copper film formation used in this example was performed by a sputtering method using a Cu target under the conditions of a pressure of 1.0 Pa and a power supply power of 15 kW (DC). The substrate temperature during film formation was 100°C. Argon gas was used as the film formation gas.

[0460] The titanium film formation used in this example was performed by a sputtering method using a Ti target under the conditions of a pressure of 0.3 Pa and a power supply power of 8 kW (DC). The substrate temperature during film formation was room temperature. Argon gas was used as the film formation gas.

[0461] The molybdenum film formation used in this example was performed by a sputtering method using a Mo target under the conditions of a pressure of 0.85 Pa and a power supply power of 35 kW (DC). The substrate temperature during film formation was 80°C. Argon gas was used as the film formation gas.

[0462] The ITSO film formation used in this example was performed by a sputtering method using an ITSO target (In 2 O 3 :SnO 2 :SiO 2 =85:10:5 [weight ratio]) under the conditions of a pressure of 0.15 Pa and a power supply power of 1 kW (DC). The substrate temperature during film formation was 80°C. Argon gas was used as the film formation gas.

[0463] The formation of the metal oxide film used in this example was carried out by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) under the conditions of a pressure of 0.6 Pa and a power supply power of 2.5 kW (alternating current). The substrate temperature during film formation was set to room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow ratio was set to 10%. Note that the film composition of the sample formed using a target with a composition of In:Ga:Zn = 4:2:4.1 [atomic ratio] is approximately In:Ga:Zn = 4:2:3 [atomic ratio].

[0464] The formation of the silicon oxynitride film 1 used in this example was carried out by a PECVD method using a mixed gas of silane gas with a flow rate of 24 sccm and dinitrogen monoxide gas with a flow rate of 18000 sccm under the conditions of a pressure of 200 Pa and a film formation power of 130 W. The substrate temperature during film formation was set to 350 °C. Note that the silicon oxynitride film 1 corresponds to the insulating layer 110a shown in Embodiment 1.

[0465] The formation of the silicon oxynitride film 2 used in this example was carried out by a PECVD method using a mixed gas of silane gas with a flow rate of 200 sccm and dinitrogen monoxide gas with a flow rate of 10000 sccm under the conditions of a pressure of 300 Pa and a film formation power of 750 W. The substrate temperature during film formation was set to 350 °C. Note that the silicon oxynitride film 2 corresponds to the insulating layer 110c shown in Embodiment 1.

[0466] The formation of the silicon oxynitride film 3 used in this example was carried out by a PECVD method using a mixed gas of silane gas with a flow rate of 20 sccm and dinitrogen monoxide gas with a flow rate of 3000 sccm under the conditions of a pressure of 40 Pa and a film formation power of 500 W. The substrate temperature during film formation was set to 350 °C. Note that the silicon oxynitride film 3 corresponds to the insulating layer 110b shown in Embodiment 1.

[0467] As the etchant, a chemical solution prepared by mixing two chemical solutions, Chemical Solution A and Chemical Solution B, at a volume ratio of 5:1 immediately before use was used. As Chemical Solution A, an aqueous solution of phosphoric acid (less than 5 wt%), hydrofluoric acid (less than 1 wt%), nitric acid (less than 10 wt%), and an additive (less than 22 wt%) was used. As Chemical Solution B, an aqueous solution of hydrogen peroxide (31 wt%) was used. The temperature of the etchant during etching was 30°C.

[0468] The etching rates of various films are shown in Table 1. In Table 1, "IGZO(4:2:3)" refers to the aforementioned metal oxide film, "SiON1" refers to the aforementioned silicon oxynitride film 1, "SiON2" refers to the aforementioned silicon oxynitride film 2, and "SiON3" refers to the aforementioned silicon oxynitride film 3.

[0469]

Table 1

[0470] As shown in Table 1, it was confirmed that the etching rates of titanium, molybdenum, ITSO, metal oxide, silicon oxynitride 1, silicon oxynitride 2, and silicon oxynitride 3 were slower than that of copper. Also, it was confirmed that the silicon oxynitride film 3 that can be used for the insulating layer 110b had a slower etching rate than the silicon oxynitride film 1 that can be used for the insulating layer 110a and the silicon oxynitride film 2 that can be used for the insulating layer 110c. It was confirmed that the silicon oxynitride film 2 that can be used for the insulating layer 110c had a faster etching rate than the silicon oxynitride film 1 that can be used for the insulating layer 110a and the silicon oxynitride film 3 that can be used for the insulating layer 110b.

Example

[0471] In this example, a sample (sample A) corresponding to the transistor 100B shown in FIG. 3 was fabricated, and the cross-sectional shape was evaluated.

[0472] <Fabrication of Sample> First, a tungsten film with a thickness of 100 nm was formed on a glass substrate by sputtering, and this was processed to obtain a first gate electrode.

[0473] Subsequently, a first silicon nitride film with a thickness of 50 nm, a second silicon nitride film with a thickness of 200 nm, a third silicon nitride film with a thickness of 50 nm, and a first silicon oxynitride film with a thickness of 3 nm were deposited in this order.

[0474] The deposition of the first silicon nitride film and the third silicon nitride film was each carried out by PECVD using a mixed gas of silane gas with a flow rate of 200 sccm, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 100 sccm, under the conditions of a pressure of 100 Pa and a film-forming power of 2000 W. The substrate temperature during film formation was 350 °C.

[0475] The deposition of the second silicon nitride film was carried out by PECVD using a mixed gas of silane gas with a flow rate of 290 sccm, nitrogen gas with a flow rate of 2000 sccm, and ammonia gas with a flow rate of 2000 sccm, under the conditions of a pressure of 200 Pa and a film-forming power of 3000 W. The substrate temperature during film formation was 350 °C.

[0476] The deposition of the first silicon oxynitride film was carried out by PECVD using a mixed gas of silane gas with a flow rate of 20 sccm and dinitrogen monoxide gas with a flow rate of 3000 sccm, under the conditions of a pressure of 40 Pa and a film-forming power of 3000 W. The substrate temperature during film formation was 350 °C.

[0477] Subsequently, a first metal oxide film with a thickness of 30 nm was deposited on the first gate insulating layer. The deposition of the first metal oxide film was carried out by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]), under the conditions of a pressure of 0.6 Pa and a power supply power of 2.5 kW. The substrate temperature during film formation was room temperature. A mixed gas of oxygen gas and argon gas was used as the film-forming gas, and the oxygen flow rate ratio was 10%.

[0478] Subsequently, after heat treatment at 370°C for 1 hour in a nitrogen atmosphere, heat treatment was performed at 370°C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 1:1). An oven device was used for the heat treatment.

[0479] Subsequently, the first metal oxide film was processed into an island shape to form the first metal oxide layer.

[0480] Subsequently, a second silicon oxynitride film with a thickness of 5 nm, a third silicon oxynitride film with a thickness of 130 nm, and a fourth silicon oxynitride film with a thickness of 5 nm were formed in this order as the second gate insulating layer.

[0481] The formation of the second silicon oxynitride film (film formation condition 1) was performed by PECVD using a mixed gas of silane gas with a flow rate of 24 sccm and dinitrogen monoxide gas with a flow rate of 18000 sccm under the conditions of a pressure of 200 Pa and a film formation power of 130 W. The substrate temperature during film formation was 350°C. The second silicon oxynitride film corresponds to the insulating layer 110a shown in Embodiment 1.

[0482] The formation of the third silicon oxynitride film (film formation condition 2) was performed by PECVD using a mixed gas of silane gas with a flow rate of 200 sccm and dinitrogen monoxide gas with a flow rate of 10000 sccm under the conditions of a pressure of 300 Pa and a film formation power of 750 W. The substrate temperature during film formation was 350°C. The third silicon oxynitride film corresponds to the insulating layer 110c shown in Embodiment 1.

[0483] The formation of the fourth silicon oxynitride film (film formation condition 3) was performed by PECVD using a mixed gas of silane gas with a flow rate of 20 sccm and dinitrogen monoxide gas with a flow rate of 3000 sccm under the conditions of a pressure of 40 Pa and a film formation power of 500 W. The substrate temperature during film formation was 350°C. The fourth silicon oxynitride film corresponds to the insulating layer 110b shown in Embodiment 1.

[0484] The film formation rates and etching rates of the second silicon oxynitride film (film formation condition 1), the third silicon oxynitride film (film formation condition 2), and the fourth silicon oxynitride film (film formation condition 3) are shown in Table 2. In Table 2, etching rate 1 indicates the etching rate in the etchant shown in Example 1, and etching rate 2 indicates the etching rate in 0.5 weight% hydrofluoric acid.

[0485]

Table 2

[0486] Subsequently, heat treatment was performed at 370 °C for 1 hour in a nitrogen atmosphere. An oven device was used for the heat treatment.

[0487] Subsequently, a second metal oxide film with a thickness of 20 nm was formed on the fourth silicon oxynitride film. The second metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) under the conditions of a pressure of 0.6 Pa and a power supply power of 2.5 kW. The substrate temperature during film formation was 200 °C. Oxygen gas (oxygen flow ratio 100%) was used as the film formation gas.

[0488] Subsequently, a 10-nm-thick ITSO film and a 100-nm-thick copper film were formed in this order on the second metal oxide film. The ITSO film and the copper film were formed by a sputtering method. The ITSO film was formed using an ITSO target (In 2 O 3 :SnO 2 :SiO 2 = 85:10:5 [weight ratio]). A Cu target was used for the formation of the copper film.

[0489] Subsequently, a resist mask was formed on the copper film, and the second metal oxide film, the ITSO film, and the copper film were processed to form a second metal oxide layer, an ITSO layer, and a copper layer. The processing used a wet etching method. Since the description of the etchant in Example 1 above can be referred to, a detailed description is omitted.

[0490] Subsequently, using the aforementioned resist mask as a mask, the second silicon oxynitride film was etched to form a second gate insulating layer. Dry etching was used for the processing. After that, the resist mask was removed.

[0491] Subsequently, as a protective layer covering the transistor, a fourth silicon nitride film with a thickness of 100 nm and a fifth silicon oxynitride film with a thickness of 300 nm were formed in this order. The fourth silicon nitride film and the fifth silicon oxynitride film were formed by plasma CVD, and the substrate temperature during film formation was 350 °C.

[0492] Sample A was obtained through the above steps.

[0493] <Cross-sectional Observation of the Sample> Next, sample A was thinned by a focused ion beam (FIB), and the cross-section of sample A was observed by STEM.

[0494] The STEM images of the cross-section of sample A are shown in FIGS. 27(A) and 27(B). FIG. 27(A) is a transmission electron image (TE image) at a magnification of 100,000 times. FIG. 27(B) is a Z contrast image (ZC image) at a magnification of 100,000 times of the same location as FIG. 27(A). In the Z contrast image, substances with a larger atomic number appear brighter. As shown in FIGS. 27(A) and 27(B), it was confirmed that no undercut occurred and the shape was good.

Example

[0495] In this example, a transistor (sample B1) corresponding to the transistor 100B shown in FIG. 3 was fabricated, and its electrical characteristics were evaluated. Also, a transistor (sample B2) without the conductive layer 106, which is the first gate electrode, in the transistor 100B was fabricated, and its electrical characteristics were evaluated in the same manner.

[0496] <Fabrication of the Sample> For the structure of the fabricated transistor, the transistor 100B illustrated in FIG. 3 can be adopted.

[0497] Up to the formation of the fourth silicon nitride film as the protective layer and the fifth silicon oxynitride film, the description of Example 2 above can be adopted, and thus the detailed description is omitted.

[0498] Subsequently, a part of the protective layer covering the transistor was opened, and a molybdenum film with a thickness of 100 nm was formed by sputtering. Then, it was processed to obtain source and drain electrodes. Thereafter, an acrylic resin film with a thickness of about 1.5 μm was formed as a planarization layer, and heat treatment was performed under the conditions of a nitrogen atmosphere, a temperature of 250 °C, and 1 hour.

[0499] Through the above steps, a transistor formed on a glass substrate was obtained.

[0500] <Id-Vg Characteristics of Transistor> Subsequently, the Id-Vg characteristics of the transistor fabricated above were measured.

[0501] As the measurement conditions for the Id-Vg characteristics of the transistor, the voltage applied to the first gate electrode (hereinafter also referred to as the gate voltage (Vg)) and the voltage applied to the second gate electrode (also referred to as Vbg) were applied in steps of 0.25 V from -15 V to +20 V. Also, the voltage applied to the source electrode (hereinafter also referred to as the source voltage (Vs)) was set to 0 V (common), and the voltage applied to the drain electrode (hereinafter also referred to as the drain voltage (Vd)) was set to 0.1 V and 5.1 V.

[0502] The Id-Vg characteristics of the transistor are shown in FIG. 28. In FIG. 28, sample B1 having the first gate electrode is shown in the upper part, and sample B2 not having the first gate electrode is shown in the lower part. Also, conditions where the channel length of the transistor is different are shown in the horizontal direction, and three types of transistors with a channel length of 2 μm, 3 μm, 6 μm and a channel width of 50 μm are shown. Further, in FIG. 28, the gate voltage (Vg) is shown on the horizontal axis, the drain current (Id) is shown on the left vertical axis, and the saturation mobility (μFE) at Vd = 5.1 V is shown on the right vertical axis. In FIG. 28, the horizontal axis is shown on a linear scale, the left end is Vg = -15 V, and the right end is Vg = 20 V. The left vertical axis is shown on a log scale, the lower end is Id = 1×10 -12 A, and the upper end is Id = 1×10 -2 A. The right vertical axis is shown on a linear scale, the lower end is μFE = 0 cm 2 / Vs, and the upper end is μFE = 100 cm 2 / Vs. In addition, the Id-Vg characteristics of 20 transistors were measured for each sample.

[0503] As shown in FIG. 28, good electrical characteristics were obtained for all samples.

Example

[0504] In this example, a sample (sample C) corresponding to the transistor 100E shown in FIG. 7 was fabricated, and the cross-sectional shape was evaluated.

[0505] <Fabrication of sample> First, a titanium film with a thickness of 30 nm and a copper film with a thickness of 100 nm were formed on a glass substrate in this order by sputtering, and this was processed to obtain the first gate electrode.

[0506] Subsequently, a first silicon nitride film with a thickness of 50 nm, a second silicon nitride film with a thickness of 200 nm, a third silicon nitride film with a thickness of 50 nm, and a first silicon oxynitride film with a thickness of 3 nm were formed in this order as the first gate insulating layer. The first gate insulating layer was formed by plasma CVD, and the substrate temperature during film formation was 350°C.

[0507] Subsequently, a first metal oxide film with a thickness of 30 nm was formed on the first gate insulating layer. The first metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) under the conditions of a pressure of 0.6 Pa and a power supply power of 2.5 kW. The substrate temperature during film formation was set at room temperature. A mixed gas of oxygen gas and argon gas was used as the film-forming gas, and the oxygen flow ratio was set at 10%.

[0508] Subsequently, after heat treatment at 370°C for 1 hour in a nitrogen atmosphere, heat treatment was performed at 370°C for 1 hour in an atmosphere of a mixed gas of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 1:1). An oven device was used for the heat treatment.

[0509] Subsequently, the first metal oxide film was processed into an island shape to form a first metal oxide layer.

[0510] Subsequently, a second silicon oxynitride film with a thickness of 5 nm, a third silicon oxynitride film with a thickness of 125 nm, and a fourth silicon oxynitride film with a thickness of 10 nm were formed in this order as the second gate insulating layer. The second gate insulating layer was formed by plasma CVD, and the substrate temperature during film formation was set at 350°C.

[0511] For the formation of the second silicon oxynitride film, the film-forming conditions 1 shown in Example 2 were used. For the formation of the third silicon oxynitride film, the film-forming conditions 2 were used. For the formation of the fourth silicon oxynitride film, the film-forming conditions 3 were used.

[0512] Subsequently, heat treatment was performed at 370°C for 1 hour in a nitrogen atmosphere. An oven device was used for the heat treatment.

[0513] Subsequently, a second metal oxide film with a thickness of 20 nm was formed on the fourth silicon oxynitride film. The second metal oxide film was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) under the conditions of a pressure of 0.6 Pa and a power supply power of 2.5 kW. The substrate temperature during film formation was 200 °C. Oxygen gas (oxygen flow ratio 100%) was used as the film formation gas.

[0514] Subsequently, a 10-nm-thick ITSO film and a 100-nm-thick copper film were formed in this order on the second metal oxide film. The ITSO film and the copper film were formed by sputtering. The ITSO film was formed using an ITSO target (In 2 O 3 :SnO 2 :SiO 2 = 85:10:5 [weight ratio]). A Cu target was used for the formation of the copper film.

[0515] Subsequently, a resist mask was formed on the copper film, and the second metal oxide film, the ITSO film, and the copper film were processed to form a second metal oxide layer, an ITSO layer, and a copper layer. The processing used a wet etching method. Since the description of the etchant in Example 1 above can be referred to, a detailed explanation is omitted.

[0516] Subsequently, using the aforementioned resist mask as a mask, the second silicon oxynitride film was etched to form a second gate insulating layer. The processing used a dry etching method. After that, the resist mask was removed.

[0517] Subsequently, as a protective layer covering the transistor, a 100-nm-thick fourth silicon nitride film and a 300-nm-thick fifth silicon oxynitride film were formed in this order. The fourth silicon nitride film and the fifth silicon oxynitride film were formed by plasma CVD, and the substrate temperature during film formation was 350 °C.

[0518] Sample C was obtained through the above steps.

[0519] <Cross-sectional Observation of the Sample> Next, sample C was thinned by a focused ion beam (FIB), and the cross-section of sample C was observed by STEM.

[0520] The STEM images of the cross-section of sample C are shown in FIGS. 29(A) and 29(B). FIG. 29(A) is a transmission electron image (TE image) at a magnification of 100,000 times. FIG. 29(B) is a Z-contrast image (ZC image) at a magnification of 100,000 times of the same location as FIG. 29(A). As shown in FIGS. 29(A) and 29(B), it was confirmed that no undercut occurred and the shape was good. Also, it was confirmed that the ends of the metal oxide layer, the ITSO layer, and the copper layer were located inside the end of the silicon oxynitride layer, and the end of the copper layer was located inside the ends of the ITSO layer and the copper layer. Further, it was confirmed that the width of the region corresponding to region 108L shown in FIG. 7(B) was about 200 nm.

Example

[0521] In this example, a transistor (sample D) corresponding to the transistor 100E shown in FIG. 7 was fabricated, and its electrical characteristics were evaluated.

[0522] <Fabrication of sample> The configuration of the fabricated transistor can refer to the transistor 100E illustrated in FIG. 7.

[0523] Up to the formation of the fourth silicon nitride film as the protective layer and the fifth silicon oxynitride film, the description of Example 4 above can be referred to, so detailed description is omitted.

[0524] Subsequently, a part of the protective layer covering the transistor was opened, and a titanium film with a thickness of 30 nm and a copper film with a thickness of 100 nm were formed in this order by sputtering, and then this was processed to obtain source electrodes and drain electrodes. Thereafter, an acrylic resin film with a thickness of about 1.5 μm was formed as a planarization layer, and heat treatment was performed under the conditions of a nitrogen atmosphere, a temperature of 250 ° C, and 1 hour.

[0525] A transistor formed on a glass substrate was obtained through the above steps.

[0526] <Id-Vg Characteristics of Transistor> Subsequently, the Id-Vg characteristics of the transistor fabricated above were measured.

[0527] As the measurement conditions for the Id-Vg characteristics of the transistor, the voltage applied to the first gate electrode (hereinafter also referred to as the gate voltage (Vg)) and the voltage applied to the second gate electrode (also referred to as Vbg) were applied in steps of 0.25 V from -15 V to +20 V. Also, the voltage applied to the source electrode (hereinafter also referred to as the source voltage (Vs)) was set to 0 V (common), and the voltage applied to the drain electrode (hereinafter also referred to as the drain voltage (Vd)) was set to 0.1 V and 5.1 V.

[0528] The Id-Vg characteristics of the transistor are shown in FIG. 30. In FIG. 30, the conditions where the channel length of the transistor is different are shown in the vertical direction, and four types of transistors with a channel length of 1.5 μm, 2 μm, 3 μm, 6 μm and a channel width of 50 μm are shown. In FIG. 30, the horizontal axis is shown on a linear scale, the left end is Vg = -15 V, and the right end is Vg = 20 V. The left vertical axis is shown on a logarithmic scale, and the lower end is Id = 1×10 -12 A, and the upper end is Id = 1×10 -2 A. The right vertical axis is shown on a linear scale, the lower end is μFE = 0 cm 2 / Vs, and the upper end is μFE = 100 cm 2 / Vs. Note that the Id-Vg characteristics of 20 transistors were measured for each sample.

[0529] As shown in FIG. 30, good electrical characteristics could be obtained even in transistors with a short channel length.

Example

[0530] In this example, samples (sample E1 and sample E2) with a laminated structure of an insulating film, a metal oxide film, a functional film, and a conductive film were fabricated, and the adsorbed water of the insulating film was evaluated. The cross-sectional structure of sample E1 is shown in Fig. 31(A), and the cross-sectional structure of sample E2 is shown in Fig. 31(B).

[0531] <Fabrication of Samples> First, on a glass substrate 200, as an insulating film 210, a first silicon oxynitride film 210A with a thickness of 5 nm, a second silicon oxynitride film 210B with a thickness of 130 nm, and a third silicon oxynitride film 210C were formed in this order. For the formation of the first silicon oxynitride film 210A, the film formation conditions 1 shown in Example 2 were used, for the formation of the second silicon oxynitride film 210B, the film formation conditions 2 were used, and for the formation of the third silicon oxynitride film 210C, the film formation conditions 3 were used. Also, for sample E1, the thickness of the third silicon oxynitride film 210C was 5 nm, and for sample E2, the thickness of the third silicon oxynitride film 210C was 10 nm.

[0532] Subsequently, a heat treatment was performed at 370°C for 1 hour in a nitrogen atmosphere. An oven device was used for the heat treatment.

[0533] Subsequently, a metal oxide film 214 with a thickness of 20 nm was formed on the third silicon oxynitride film 210C. The formation of the metal oxide film 214 was performed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) under the conditions of a pressure of 0.6 Pa and a power supply power of 2.5 kW. The substrate temperature during film formation was 200°C. Oxygen gas (oxygen flow ratio 100%) was used as the film formation gas.

[0534] Subsequently, an ITSO film 213 with a thickness of 10 nm and a copper film 212 with a thickness of 100 nm were formed in this order on the metal oxide film 214. The ITSO film 213 and the copper film 212 were formed by a sputtering method. The formation of the ITSO film 213 was performed using an ITSO target (In 2 O 3 :SnO 2 :SiO 2=85:10:5 [by weight]) was used. For the formation of the copper film 212, a Cu target was used.

[0535] Subsequently, the metal oxide film 214, the ITSO film 213, and the copper film 212 were removed by a wet etching method. For both sample E1 and sample E2, the etchant temperature during wet etching was set to 30 °C, and the etching time was set to 60 sec. Since the description of the etchant in Example 1 above can be referred to, detailed explanation is omitted.

[0536] Subsequently, the film thickness was measured. From the measurement results of the film thickness, it was confirmed that in sample E1, a part of the surface side of the third silicon oxynitride film 210C and the second silicon oxynitride film 210B was also removed by the above-described wet etching treatment, and the surface of the second silicon oxynitride film 210B was exposed. Similarly, it was confirmed that in sample E2, a part of the surface side of the third silicon oxynitride film 210C was removed, and the surface of the third silicon oxynitride film 210C was exposed.

[0537] Through the above steps, sample E1 and sample E2 were obtained.

[0538] <TDS analysis> Subsequently, using the temperature-programmed desorption gas analysis method (TDS: Thermal Desorption Spectrometry), the desorbed gas from sample E1 and sample E2 was evaluated. In the TDS measurement, the substrate temperature was raised from about 50 °C to about 550 °C at a heating rate such that the substrate temperature became 30 °C / min.

[0539] The TDS analysis results of sample E1 are shown in Fig. 32(A), and those of sample E2 are shown in Fig. 32(B). In Fig. 32(A) and Fig. 32(B), the horizontal axis represents the substrate temperature (Tsub), and the vertical axis represents the detection intensity (Intensity) of the mass-to-charge ratio 18 (M / z = 18). Note that the gas with a mass-to-charge ratio of 18 (M / z = 18) is mainly water (H 2 2O) molecules.

[0540] As shown in Fig. 32(A), in sample E1, a peak with a mass-to-charge ratio of 18 (M / z = 18) was observed near Tsub = 100°C. The peak observed near Tsub = 100°C is considered to be due to the adsorbed water on the sample surface. Since the surface of the second silicon oxynitride film 210B was exposed, it is considered that the water in the atmosphere was adsorbed on the surface of the second silicon oxynitride film 210B.

[0541] On the other hand, as shown in Fig. 32(B), in sample E2, the peak with a mass-to-charge ratio of 18 (M / z = 18) was very small. Although the surface of the third silicon oxynitride film 210C was exposed, since a film in which water is hardly adsorbed was used for the third silicon oxynitride film 210C, it is considered that the adsorption of water in the atmosphere was suppressed.

Example

[0542] In this example, the influence of impurities containing hydrogen on metal oxides was evaluated.

[0543] For the evaluation, a sample in which a metal oxide film with a thickness of 200 nm was formed on a glass substrate was used. As the metal oxide film, In-Ga-Zn oxide was used.

[0544] The film formation of the metal oxide film used in this example was performed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) under the conditions of a pressure of 0.4 Pa and a power supply power of 0.2 kW (DC). The substrate temperature during film formation was 350°C. As the film formation gas, a mixed gas of oxygen gas and argon gas was used, and the oxygen flow ratio was 33%. The film composition of the sample formed using a target with a composition of In:Ga:Zn = 4:2:4.1 [atomic ratio] is generally In:Ga:Zn = 4:2:3 [atomic ratio]. Immediately before the film formation of the metal oxide film, the glass substrate was heat-treated to remove the water adsorbed on the glass substrate. The heat treatment of the glass substrate was 350°C for 5 min in a vacuum atmosphere.

[0545] After forming the metal oxide film, the surface of the metal oxide film was exposed to a clean room atmosphere. The exposure time was about one week.

[0546] Subsequently, heat treatment of the sample was carried out. The heat treatment had 13 levels: no heat treatment, 250 °C for 10 min, 250 °C for 20 min, 250 °C for 30 min, 250 °C for 60 min, 300 °C for 10 min, 300 °C for 20 min, 300 °C for 30 min, 300 °C for 60 min, 350 °C for 10 min, 350 °C for 20 min, 350 °C for 30 min, and 350 °C for 60 min. The heat treatment was carried out in a vacuum atmosphere.

[0547] <Evaluation of hydrogen concentration> Using secondary ion mass spectrometry, the hydrogen concentration in the metal oxide film of the aforementioned sample was evaluated. For SIMS measurement, IMS-6f manufactured by CAMECA was used, and the primary ion species was Cs + with a primary acceleration voltage of 5.0 kV and a detection area of 30 μm in diameter. The detection limit (BG) was about 5×10 17 atoms / cm 3 .

[0548] The hydrogen concentration profiles of the samples without heat treatment (denoted as "none") and the samples heat-treated at 250 °C for 10 min, 20 min, 30 min, and 60 min are shown in Fig. 33(A). The hydrogen concentration profiles of the samples without heat treatment and the samples heat-treated at 300 °C for 10 min, 20 min, 30 min, and 60 min are shown in Fig. 33(B). The hydrogen concentration profiles of the samples without heat treatment and the samples heat-treated at 350 °C for 10 min, 20 min, 30 min, and 60 min are shown in Fig. 34(A).

[0549] In Fig. 33(A), Fig. 33(B), and Fig. 34(A), the horizontal axis represents the depth from the surface of the metal oxide film, and the vertical axis represents the hydrogen concentration.

[0550] As shown in Fig. 33(A), compared with the condition without heat treatment, the hydrogen concentration on the surface side of the metal oxide film was higher under the condition of 250 °C for 10 min. By exposing the surface of the metal oxide film to a clean room atmosphere, it is considered that water was adsorbed on the surface of the metal oxide film, and the hydrogen contained in the adsorbed water diffused into the metal oxide film by heat treatment. In addition, the longer the heat treatment at 250 °C, the higher the hydrogen concentration in the metal oxide film tended to be. It is considered that the increase in the heat treatment time increased the hydrogen diffusing into the metal oxide film.

[0551] As shown in Fig. 33(B), compared with the condition without heat treatment, the hydrogen concentration in the metal oxide film tended to be higher under any of the conditions of heat treatment at 300 °C. Also, no particular difference was observed depending on the heat treatment time.

[0552] As shown in Fig. 34(A), compared with the condition without heat treatment, the hydrogen concentration in the metal oxide film was higher under the condition of 350 °C for 10 min. Also, compared with the glass substrate side, the hydrogen concentration on the surface side of the metal oxide film tended to be lower. It is considered that the hydrogen once diffused into the metal oxide film desorbed from the surface side of the metal oxide by the heat treatment at 350 °C. In addition, the longer the heating time at 350 °C, the lower the hydrogen concentration in the metal oxide film, particularly the hydrogen concentration on the surface side of the metal oxide film. It is considered that the increase in the heat treatment time increased the hydrogen desorbing from the surface side of the metal oxide film.

[0553] <Evaluation of Carrier Density> For the sample under the condition of 250 °C for 10 min described above, the carrier density was evaluated.

[0554] In this example, the carrier density in the film thickness direction of the metal oxide film was evaluated. Specifically, film thickness measurement and resistance measurement were performed, and then the surface side was partially removed by etching to reduce the film thickness, and film thickness measurement and resistance measurement were performed again, which was repeated.

[0555] The carrier density was calculated from the resistivity obtained by resistance measurement. When calculating the carrier density, the mobility μ of the metal oxide was 16.50 cm2 / V·s, the charge of an electron q was taken as 1.602×10 -19 C.

[0556] The carrier density and hydrogen concentration in the metal oxide film are shown in Fig. 34(B). In Fig. 34(B), the horizontal axis represents the depth from the surface of the metal oxide film, and the vertical axis represents the carrier density and hydrogen concentration. Note that the hydrogen concentration shown in Fig. 34(B) is the same data as the hydrogen concentration shown in Fig. 33(A).

[0557] As shown in Fig. 34(B), since the hydrogen concentration and the carrier density in the film thickness direction in the metal oxide film are almost the same, it is considered that hydrogen in the metal oxide film generates carriers. Therefore, it was found that when using a metal oxide as the semiconductor layer, it is preferable to form the gate insulating layer promptly after forming the semiconductor layer.

Example

[0558] In this example, samples with different heat treatment conditions after forming the first metal oxide film were prepared and their electrical characteristics were evaluated. In this example, transistors (sample F1 to sample F4) corresponding to the transistor 100A shown in Fig. 2, and transistors (sample G1 to sample G4) corresponding to the transistor 100 shown in Fig. 1 were prepared.

[0559] <Fabrication of Samples> First, a tungsten film with a thickness of about 100 nm was formed on a glass substrate by sputtering, and this was processed to obtain a first gate electrode.

[0560] Subsequently, a first silicon nitride film with a thickness of 50 nm, a second silicon nitride film with a thickness of 200 nm, a third silicon nitride film with a thickness of 50 nm, and a first silicon oxynitride film with a thickness of 3 nm were formed in this order as the first gate insulating layer. The first gate insulating layer was formed by plasma CVD, and the substrate temperature during film formation was 350°C.

[0561] Subsequently, a first metal oxide film with a thickness of 30 nm was formed on the first gate insulating layer. The first metal oxide film was formed by sputtering using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) under the conditions of a pressure of 0.6 Pa and a power supply power of 2.5 kW. The substrate temperature during film formation was room temperature. A mixed gas of oxygen gas and argon gas was used as the film formation gas, and the oxygen flow ratio was set to 10%.

[0562] Subsequently, heat treatment was performed using an oven device. Samples F1 and G1 were heat-treated at 370°C for 1 hour in a nitrogen atmosphere and then heat-treated at 370°C for 1 hour in a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 1:1). Samples F2 and G2 were heat-treated at 370°C for 2 hours in a nitrogen atmosphere. Samples F3 and G3 were heat-treated at 370°C for 2 hours in a mixed gas atmosphere of nitrogen and oxygen (nitrogen gas flow rate: oxygen gas flow rate = 1:1). Samples F4 and G4 were heat-treated at 370°C for 2 hours in a CDA atmosphere.

[0563] Subsequently, the first metal oxide film was processed into an island shape to form a first metal oxide layer.

[0564] Subsequently, a second silicon oxynitride film with a thickness of 5 nm, a third silicon oxynitride film with a thickness of 125 nm, and a fourth silicon oxynitride film with a thickness of 10 nm were formed in this order as the second gate insulating layer. The second gate insulating layer was formed by plasma CVD, and the substrate temperature during film formation was 350°C.

[0565] For the formation of the second silicon oxynitride film, the film formation conditions 1 shown in Example 2 were used. For the formation of the third silicon oxynitride film, the film formation conditions 2 were used. For the formation of the fourth silicon oxynitride film, the film formation conditions 3 were used.

[0566] Subsequently, heat treatment was performed at 370°C for 1 hour in a nitrogen atmosphere. An oven device was used for the heat treatment.

[0567] Subsequently, a second metal oxide film with a thickness of 20 nm was formed on the fourth silicon oxynitride film. The second metal oxide film was formed by a sputtering method using an In-Ga-Zn oxide target (In:Ga:Zn = 4:2:4.1 [atomic ratio]) under the conditions of a pressure of 0.6 Pa and a power supply power of 2.5 kW. The substrate temperature during film formation was 200 °C. Oxygen gas (oxygen flow ratio 100%) was used as the film formation gas.

[0568] Subsequently, a molybdenum film with a thickness of 50 nm, an aluminum film with a thickness of 200 nm, and a titanium film with a thickness of 50 nm were formed in this order on the second metal oxide film. The molybdenum film, aluminum film, and titanium film were formed by a sputtering method.

[0569] The aluminum film used in this example was formed by a sputtering method using an Al target under the conditions of a pressure of 0.3 Pa and a power supply power of 10 kW (DC). The substrate temperature during film formation was 70 °C. Argon gas was used as the film formation gas. For the formation of the molybdenum film and titanium film, since the description of Example 1 above can be referred to, detailed description is omitted.

[0570] Subsequently, a resist mask was formed on the titanium film, and the second metal oxide film, molybdenum film, aluminum film, and titanium film were processed to form a second metal oxide layer, molybdenum layer, aluminum layer, and titanium layer. The processing used a wet etching method. Since the description of the etchant in Example 1 above can be referred to, detailed description is omitted.

[0571] Subsequently, using the above-mentioned resist mask as a mask, the second silicon oxynitride film was etched to form a second gate insulating layer. The processing used a dry etching method. After that, the resist mask was removed.

[0572] Subsequently, as a protective layer covering the transistor, a fourth silicon nitride film with a thickness of 100 nm and a third silicon oxynitride film with a thickness of 300 nm were formed in this order. The fourth silicon nitride film and the third silicon oxynitride film were formed by plasma CVD method, and the substrate temperature during film formation was set to 350 °C.

[0573] Subsequently, a part of the protective layer covering the transistor was opened, and a molybdenum film with a thickness of 100 nm was formed by sputtering method. Then, it was processed to obtain source electrodes and drain electrodes. Thereafter, an acrylic resin film with a thickness of about 1.5 μm was formed as a planarization layer, and heat treatment was performed under the conditions of a nitrogen atmosphere, a temperature of 250 °C, and 1 hour.

[0574] A transistor formed on a glass substrate was obtained through the above steps.

[0575] <Id-Vg characteristics of the transistor> Subsequently, the Id-Vg characteristics of the transistor fabricated above were measured.

[0576] As the measurement conditions for the Id-Vg characteristics of the transistor, the voltage applied to the first gate electrode (hereinafter also referred to as the gate voltage (Vg)) and the voltage applied to the second gate electrode (also referred to as Vbg) were applied in steps of 0.25 V from -15 V to +20 V. Also, the voltage applied to the source electrode (hereinafter also referred to as the source voltage (Vs)) was set to 0 V (common), and the voltage applied to the drain electrode (hereinafter also referred to as the drain voltage (Vd)) was set to 0.1 V and 5.1 V.

[0577] The Id-Vg characteristics of the transistors in samples F1 to F4 are shown in Fig. 35, and the Id-Vg characteristics of the transistors in samples G1 to G4 are shown in Fig. 36. In Figs. 35 and 36, the heat treatment conditions after the formation of the first metal oxide film are shown horizontally. Also, the conditions with different channel lengths of the transistors are shown vertically, and three types of transistors with a channel length of 2 μm, 3 μm, 6 μm and a channel width of 50 μm are shown. Further, in Figs. 35 and 36, the gate voltage (Vg) is shown on the horizontal axis, the drain current (Id) is shown on the left vertical axis, and the saturation mobility (μFE) at Vd = 5.1 V is shown on the right vertical axis. In Figs. 35 and 36, the horizontal axis is shown on a linear scale, the left end is Vg = -15 V, and the right end is Vg = 20 V. The left vertical axis is shown on a log scale, the lower end is Id = 1×10 -12 A, and the upper end is Id = 1×10 -2 A. The right vertical axis is shown on a linear scale, the lower end is μFE = 0 cm 2 / Vs, and the upper end is μFE = 100 cm 2 / Vs. Note that the Id-Vg characteristics of 20 transistors were measured for each sample.

[0578] As shown in Figs. 35 and 36, good electrical characteristics were obtained for all samples.

[0579] <Reliability of Transistor> Subsequently, the reliability of the transistors fabricated above was evaluated.

[0580] As a reliability evaluation, a gate bias stress test (GBT test) was conducted. In the GBT test, the substrate on which the transistor was formed was held at 60 °C, a voltage of 0.1 V was applied to the drain of the transistor, and a voltage of 20 V was applied to the gate, and this state was maintained for 1 hour. Here, the test environment was in the dark state.

[0581] The variation value (ΔVth) of the threshold voltage before and after the gate bias stress test was evaluated. For transistors with a channel length of 3 μm and a channel width of 50 μm, the variation values (ΔVth) of the threshold voltages of samples F1 to F4 are shown in Fig. 37(A), and the variation values (ΔVth) of the threshold voltages of samples G1 to G4 are shown in Fig. 37(B).

[0582] As shown in Figs. 37(A) and 37(B), it was confirmed that the variation in the threshold voltage of the fabricated transistors was extremely small.

[0583] From the above, it was confirmed that the transistor according to one aspect of the present invention has good electrical characteristics and high reliability.

Explanation of Reference Numerals

[0584] 100: Transistor, 100A: Transistor, 100B: Transistor, 100C: Transistor, 100D: Transistor, 100E: Transistor, 102: Substrate, 103: Insulating layer, 106: Conductive layer, 108: Semiconductor layer, 108L: Region, 108N: Region, 110: Insulating layer, 110a: Insulating layer, 110b: Insulating layer, 110c: Insulating layer, 110f: Insulating film, 112: Conductive layer, 112f: Conductive film, 113: Functional layer, 113f: Functional film, 114: Metal oxide layer, 114f: Metal oxide film, 115: Resist mask, 116: Insulating layer, 118: Insulating layer, 120a: Conductive layer, 120b: Conductive layer, 141a: Opening, 141b: Opening, 142: Opening, 200: Glass substrate, 210: Insulating film, 210A: Silicon oxynitride film, 210B: Silicon oxynitride film, 210C: Silicon oxynitride film, 212: Copper film, 213: ITSO film, 214: Metal oxide film

Claims

1. A method for manufacturing a semiconductor device having a transistor, comprising the steps of: forming a first conductive layer on a substrate; forming a first insulating film on the first conductive layer; forming a semiconductor layer containing indium, gallium, and zinc on the first insulating film; forming a second insulating film on the semiconductor layer; forming a first metal oxide film containing indium on the second insulating film at an oxygen flow rate of 65% or more and 100% or less; After forming the first metal oxide film, a heat treatment is performed; After the heat treatment, a second metal oxide film containing indium tin oxide is formed on the first metal oxide film; forming a conductive film containing copper on the second metal oxide film; forming a resist mask on the copper-containing conductive film; After forming the resist mask, the second insulating film, the first metal oxide film, the second metal oxide film, and the copper-containing conductive film are etched by a wet etching method to form an island-shaped insulating layer, a first metal oxide layer, a second metal oxide layer, and a second conductive layer containing copper; forming a third insulating film having an area located above the second conductive layer having copper after the etching; the semiconductor layer has a higher indium composition than the first metal oxide layer; the first metal oxide film and the second metal oxide film have an etching rate in one etchant that is slower than the conductive film containing copper; a third insulating film having a region in contact with a top surface of the semiconductor layer, a region in contact with a side surface of the island-shaped insulating layer, a region in contact with a side surface of the first metal oxide layer, a region in contact with a side surface of the second metal oxide layer, and a region in contact with a side surface and a top surface of the copper-containing conductive layer.

2. A method for manufacturing a semiconductor device having a transistor, comprising: forming a first conductive layer on a substrate; forming a first insulating film on the first conductive layer; forming a semiconductor layer containing indium, gallium, and zinc on the first insulating film; forming a second insulating film on the semiconductor layer; forming a first metal oxide film containing indium on the second insulating film at an oxygen flow rate of 65% or more and 100% or less; After forming the first metal oxide film, a heat treatment is performed; After the heat treatment, a second metal oxide film containing indium tin oxide is formed on the first metal oxide film; forming a conductive film containing copper on the second metal oxide film; forming a resist mask on the copper-containing conductive film; After forming the resist mask, the first metal oxide film, the second metal oxide film, and the copper-containing conductive film are etched by a wet etching method to form a first metal oxide layer, a second metal oxide layer, and a second conductive layer containing copper, which are located inside an outline of the resist mask in a cross-sectional view; forming an island-shaped insulating layer by etching the second insulating film using the resist mask after forming the first metal oxide layer, the second metal oxide layer, and the second conductive layer having copper; forming a third insulating film having a region located above the second conductive layer having copper after forming the island-shaped insulating layer; the semiconductor layer has a higher indium composition than the first metal oxide layer; the first metal oxide film and the second metal oxide film have an etching rate in one etchant that is slower than the conductive film containing copper; a third insulating film having a region in contact with a top surface of the semiconductor layer, a region in contact with a side surface and a top surface of the island-shaped insulating layer, a region in contact with a side surface of the first metal oxide layer, a region in contact with a side surface of the second metal oxide layer, and a region in contact with a side surface and a top surface of the copper-containing conductive layer.

3. A method for manufacturing a semiconductor device having a transistor, comprising: forming a first conductive layer on a substrate; forming a first insulating film on the first conductive layer; forming a semiconductor layer containing indium, gallium, and zinc on the first insulating film; forming a second insulating film on the semiconductor layer; forming a first metal oxide film containing indium on the second insulating film at an oxygen flow rate of 65% or more and 100% or less; After forming the first metal oxide film, a heat treatment is performed; After the heat treatment, a second metal oxide film containing indium tin oxide is formed on the first metal oxide film; forming a conductive film containing copper on the second metal oxide film; forming a resist mask on the copper-containing conductive film; After forming the resist mask, the first metal oxide film, the second metal oxide film, and the copper-containing conductive film are etched by a wet etching method to form a first metal oxide layer, a second metal oxide layer, and a second conductive layer containing copper, which are located inside an outline of the resist mask in a cross-sectional view; forming an island-shaped insulating layer by etching the second insulating film using the resist mask after forming the first metal oxide layer, the second metal oxide layer, and the second conductive layer having copper; forming a third insulating film having a region located above the second conductive layer having copper after forming the island-shaped insulating layer; the semiconductor layer has a higher indium composition than the first metal oxide layer; the conductive film containing copper has an etching rate in one etchant slower than the first metal oxide film and the second metal oxide film; a third insulating film having a region in contact with a top surface of the semiconductor layer, a region in contact with a side surface and a top surface of the island-shaped insulating layer, a region in contact with a side surface of the first metal oxide layer, a region in contact with a top surface of the second metal oxide layer, and a region in contact with a side surface and a top surface of the copper-containing conductive layer.

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