Semiconductor device

Abstract

To provide a semiconductor device with a novel structure, in which a storage content can be held even under no power supply situations, and writing is possible without limitation on the number of times.SOLUTION: A semiconductor device is formed of a material that can sufficiently reduce an off current of a transistor, for example, an oxide semiconductor material that is a wide-gap semiconductor. By the use of the semiconductor material that can sufficiently reduce the off current of the transistor, the information can be held for a long time. Moreover, timing of changing a potential of a signal line is delayed from timing of changing a potential of a writing word line. Thus, wrong data writing can be prevented.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The disclosed invention relates to a semiconductor device using a semiconductor element and a driving method thereof.

Background Art

[0002] Memory devices using semiconductor elements are roughly classified into volatile ones in which stored contents are lost when power supply is cut off and non-volatile ones in which stored contents are retained even when power supply is cut off.

[0003] As a typical example of a volatile memory device, there is DRAM (Dynamic Random Access Memory). DRAM stores information by selecting transistors constituting memory elements and accumulating charges in capacitors.

[0004] From the above principle, in DRAM, since the charges in the capacitors are lost when information is read out, a rewrite operation is required again every time information is read out. Also, in the transistors constituting the memory elements, due to leakage current (off-current) between the source and drain in the off state, etc., charges flow out or flow in even when the transistor is not selected, so the data holding period is short. For this reason, a rewrite operation (refresh operation) is required again at a predetermined cycle, and it is difficult to sufficiently reduce power consumption. Also, since the stored contents are lost when power supply is cut off, another memory device using a magnetic material or an optical material is required for long-term storage retention.

[0005] As another example of a volatile memory device, there is SRAM (Static Random Access ​​​​​​​​​​​​There is (a memory). SRAM uses circuits such as flip-flops to store the stored content. Since it does not require a refresh operation, it is advantageous over DRAM in this regard. However, because it uses circuits such as flip-flops, there is a problem that the unit price per storage capacity becomes high. Also, in terms of the stored content being lost when the power supply is cut off, there is no difference from DRAM.

[0006] A typical example of a non-volatile memory device is flash memory. Flash memory has a floating gate between the gate electrode and the channel formation region of a transistor, and stores data by holding charges in the floating gate. Therefore, the data retention period is extremely long (semi-permanent), and it has the advantage of not requiring the refresh operation necessary for volatile memory devices (see, for example, Patent Document 1). However, since the gate insulating layer constituting the memory element deteriorates due to the tunnel current generated during writing, there is a problem that the memory element stops functioning after a predetermined number of writes. In order to mitigate the influence of this problem, for example, a technique for equalizing the number of write operations of each memory element is adopted, but in order to realize this, complicated peripheral circuits are required. Therefore, even if such a technique is adopted, the fundamental lifetime problem is not solved. That is, flash memory is not suitable for applications where the information rewrite frequency is high.

[0007] Moreover, in order to inject charges into the floating gate or remove the charges, a high voltage is required, and a circuit for that is also required. Furthermore, for the injection of charges

[0008] or requires a relatively long time for removal, and it is not easy to speed up writing and erasing There is also such a problem.

Prior Art Documents

Patent Documents

[0009]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0010] In view of the above problems, in one aspect of the disclosed invention, a semiconductor device with a new structure is provided that can retain the stored content even in a situation where no power is supplied and has no limitation on the number of write operations. This is one of the objectives.

Means for Solving the Problems

[0011] In the disclosed invention, a semiconductor device is configured using a material that can sufficiently reduce the off-current of a transistor, for example, an oxide semiconductor material, which is a wide-gap semiconductor. By using a semiconductor material that can sufficiently reduce the off-current of the transistor, it is possible to retain information over a long period of time.

[0012] Also, the timing of the potential change of the signal line is delayed compared to the timing of the potential change of the write word line. This makes it possible to prevent data write errors.

[0013] One aspect of the present invention includes a write word line, a read word line, a bit line, a source line, a signal line, a memory cell array composed of a plurality of memory cells, a first drive circuit, and a second drive ​​​​It has a driving circuit, and one of the memory cells includes a first transistor having a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region, a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, and a capacitor element. The first channel formation region is configured to include a semiconductor material different from that of the second channel formation region. The first gate electrode, the second drain electrode, and one of the electrodes of the capacitor element are electrically connected to form a node for holding charge. The first driving circuit is electrically connected to the first drain electrode via a bit line and to the second source electrode via a signal line. The second driving circuit is electrically connected to the other electrode of the capacitor element via a read word line and to the second gate electrode via a write word line. The second driving circuit has a function of delaying the signal input to the signal line compared to the signal input to the write word line. It has a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region, a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, and a capacitor element. The first channel formation region is configured to include a semiconductor material different from that of the second channel formation region. The first gate electrode, the second drain electrode, and one of the electrodes of the capacitor element are electrically connected to form a node for holding charge. The first driving circuit is electrically connected to the first drain electrode via a bit line and to the second source electrode via a signal line. The second driving circuit is electrically connected to the other electrode of the capacitor element via a read word line and to the second gate electrode via a write word line. The second driving circuit has a function of delaying the signal input to the signal line compared to the signal input to the write word line. It has a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, and a capacitor element. The first channel formation region is configured to include a semiconductor material different from that of the second channel formation region. The first gate electrode, the second drain electrode, and one of the electrodes of the capacitor element are electrically connected to form a node for holding charge. The first driving circuit is electrically connected to the first drain electrode via a bit line and to the second source electrode via a signal line. The second driving circuit is electrically connected to the other electrode of the capacitor element via a read word line and to the second gate electrode via a write word line. The second driving circuit has a function of delaying the signal input to the signal line compared to the signal input to the write word line. It has a capacitor element. The first channel formation region is configured to include a semiconductor material different from that of the second channel formation region. The first gate electrode, the second drain electrode, and one of the electrodes of the capacitor element are electrically connected to form a node for holding charge. The first driving circuit is electrically connected to the first drain electrode via a bit line and to the second source electrode via a signal line. The second driving circuit is electrically connected to the other electrode of the capacitor element via a read word line and to the second gate electrode via a write word line. The second driving circuit has a function of delaying the signal input to the signal line compared to the signal input to the write word line. The first channel formation region is configured to include a semiconductor material different from that of the second channel formation region. The first gate electrode, the second drain electrode, and one of the electrodes of the capacitor element are electrically connected to form a node for holding charge. The first driving circuit is electrically connected to the first drain electrode via a bit line and to the second source electrode via a signal line. The second driving circuit is electrically connected to the other electrode of the capacitor element via a read word line and to the second gate electrode via a write word line. The second driving circuit has a function of delaying the signal input to the signal line compared to the signal input to the write word line. The first gate electrode, the second drain electrode, and one of the electrodes of the capacitor element are electrically connected to form a node for holding charge. The first driving circuit is electrically connected to the first drain electrode via a bit line and to the second source electrode via a signal line. The second driving circuit is electrically connected to the other electrode of the capacitor element via a read word line and to the second gate electrode via a write word line. The second driving circuit has a function of delaying the signal input to the signal line compared to the signal input to the write word line. The first driving circuit is electrically connected to the first drain electrode via a bit line and to the second source electrode via a signal line. The second driving circuit is electrically connected to the other electrode of the capacitor element via a read word line and to the second gate electrode via a write word line. The second driving circuit has a function of delaying the signal input to the signal line compared to the signal input to the write word line. The second driving circuit is electrically connected to the other electrode of the capacitor element via a read word line and to the second gate electrode via a write word line. The second driving circuit has a function of delaying the signal input to the signal line compared to the signal input to the write word line. The second driving circuit is electrically connected to the other electrode of the capacitor element via a read word line and to the second gate electrode via a write word line. The second driving circuit has a function of delaying the signal input to the signal line compared to the signal input to the write word line. The second driving circuit has a function of delaying the signal input to the signal line compared to the signal input to the write word line. It is a semiconductor device having a function of delaying the signal input to the signal line compared to the signal input to the write word line.

[0014] Also, one aspect of the present invention includes a write word line, a read word line, a bit line, a source line, a signal line, a memory cell array composed of a plurality of memory cells, a first driving circuit, a second driving circuit, and a delay circuit. One of the memory cells includes a first transistor having a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region, a second transistor having a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, and a capacitor element. The first channel formation region is configured to include a semiconductor material different from that of the second channel formation region. It has a second driving circuit and a delay circuit. One of the memory cells includes a first transistor having a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region, a second transistor having a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, and a capacitor element. The first channel formation region is configured to include a semiconductor material different from that of the second channel formation region. It has a delay circuit. One of the memory cells includes a first transistor having a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region, a second transistor having a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, and a capacitor element. The first channel formation region is configured to include a semiconductor material different from that of the second channel formation region. One of the memory cells includes a first transistor having a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region. It has a second transistor having a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, and a capacitor element. The first channel formation region is configured to include a semiconductor material different from that of the second channel formation region. It has a capacitor element. The first channel formation region is configured to include a semiconductor material different from that of the second channel formation region. The first channel formation region is configured to include a semiconductor material different from that of the second channel formation region. The second drain electrode, one of the electrodes of the capacitive element, is electrically connected to form a node for holding charges and the first drive circuit is electrically connected to the first drain electrode via a bit line, and is also electrically connected to the second source electrode via a signal line. The second drive circuit is electrically connected to the other electrode of the capacitive element via a read word line, and is also electrically connected to the second gate electrode via a write word line. The delay circuit is a semiconductor device electrically connected to the signal line. Further, one aspect of the present invention includes a write word line, a read word line, a bit line, a source line, a signal line, a memory cell array composed of a plurality of memory cells, a first drive circuit, and a second

[0015] drive circuit. One of the memory cells includes a first transistor including a first gate electrode, a first source electrode, a first drain electrode, and a first channel formation region, a second transistor including a second gate electrode, a second source electrode, a second drain electrode, and a second channel formation region, and a capacitive element. The first channel formation region is configured to include a semiconductor material different from that of the second channel formation region. The first gate electrode, the second drain electrode, and one of the electrodes of the capacitive element are electrically connected to form a node for holding charges. The first drive circuit is electrically connected to the first drain electrode via a bit line and is also electrically connected to the second source electrode via a signal line. The second drive circuit is electrically connected to the other electrode of the capacitive element via a read word line and is also electrically connected to the second gate electrode via a write word line. A first buffer circuit is connected to the signal line, a second buffer circuit is connected to the write word line, and the first buffer circuit is configured to form a node for holding charges. The first drive circuit is electrically connected to the first drain electrode via a bit line and is also electrically connected to the second source electrode via a signal line. The second drive circuit is electrically connected to the other electrode of the capacitive element via a read word line and is also electrically connected to the second gate electrode via a write word line. A first buffer circuit is connected to the signal line, a second buffer circuit is connected to the write word line, and the first buffer circuit is configured to form The channel length of the transistor that constitutes is greater than the channel length of the transistor that constitutes the second buffer circuit, and it is a semiconductor device.

[0016] Also, in the above configuration, it may be configured to have a potential conversion circuit that outputs a potential higher than the power supply potential to the second drive circuit.

[0017] Also, in the above configuration, between the bit line and the source line, the plurality of memory cells are connected in series.

[0018] Also, in the above configuration, a wiring line is electrically connected between the bit line and the plurality of memory cells connected in series.

[0019] Also, in the above configuration, it has a switch that controls the connection between the bit line and the signal line and the output terminal, a switch that controls the connection between the bit line and the signal line and the input terminal, and a wiring line, and the bit line and the signal line are electrically connected.

[0020] Also, in the above configuration, the second channel formation region of the second transistor is configured to include an oxide semiconductor.

[0021] Also, in the above configuration, the second drive circuit has a potential conversion circuit and a level shift circuit electrically connected to a write word line or a read word line.

[0022] Note that in the above, although a transistor may be configured using an oxide semiconductor, the disclosed invention is not limited to this. Materials that can achieve off-current characteristics equivalent to those of an oxide semiconductor, for example, wide-gap materials including silicon carbide (more specifically, for example, e ​​​​​​​​​Semiconductor materials with a bandgap Eg greater than 3 eV) may also be applied.

[0023] In addition, in this specification and the like, terms such as "upper" and "lower" do not limit the positional relationship of the components to be "directly above" or "directly below". For example, in the expression "gate electrode on the gate insulating layer ", those including other components between the gate insulating layer and the gate electrode are excluded from it.

[0024] Also, in this specification and the like, terms such as "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring", and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where a plurality of "electrodes" and "wires" are integrally formed.

[0025] Also, the functions of "source" and "drain" may be interchanged when transistors of different polarities are employed or when the direction of current changes in the circuit operation. Therefore, in this specification, the terms "source" and "drain" are assumed to be interchangeable.

[0026] In addition, in this specification and the like, "electrically connected" includes cases where they are connected through "something having some electrical action". Here, "something having some electrical action" is not particularly limited as long as it enables the transfer of electrical signals between the connection targets.

[0027] For example, "something having some electrical action" includes electrodes, wirings, switching elements such as transistors resistance elements, inductors, capacitors, and other various functions ​​It includes elements and the like.

Advantages of the Invention

[0028] Since a transistor using an oxide semiconductor has an extremely small off-current, using this makes it possible to retain the stored content for an extremely long period. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that the power consumption can be sufficiently reduced. Also, even when there is no power supply (however, it is desirable that the potential be fixed), it is possible to retain the stored content over a long period.

[0029] In addition, in the semiconductor device according to the disclosed invention, a high voltage is not required for writing information, and there is no problem of element degradation. For example, unlike a conventional non-volatile memory, since it is not necessary to inject electrons into the floating gate or extract electrons from the floating gate, problems such as degradation of the gate insulating layer do not occur at all. That is, in the semiconductor device according to the disclosed invention, there is no limit to the number of rewritable times, which is a problem in conventional non-volatile memories, and the reliability is dramatically improved. Furthermore, since information is written depending on the on-state and off-state of the transistor, high-speed operation can also be easily realized. Also, there is an advantage that an operation for erasing information is not required.

[0030] In addition, a transistor using a material other than an oxide semiconductor can operate at a sufficiently high speed. Therefore, by combining this with a transistor using an oxide semiconductor, the high-speed operation of the semiconductor device (for example, the information read operation) can be sufficiently ensured. ​​​​​​​​​In addition, transistors using materials other than oxide semiconductors can suitably realize various circuits (logic circuits, drive circuits, etc.) that require high-speed operation.

[0031] Thus, by integrating a transistor using a material other than an oxide semiconductor (more broadly, a transistor capable of sufficiently high-speed operation) and a transistor using an oxide semiconductor (more broadly, a transistor with a sufficiently small off-current), a semiconductor device having unprecedented characteristics can be realized.

Brief Description of the Drawings

[0032]

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Embodiments for Carrying Out the Invention

[0033] An example of an embodiment of the present invention will be described below with reference to the drawings. However, the present invention is not limited to the following description, and it will be easily understood by those skilled in the art that the form and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not

[0034] interpreted as being limited to the description of the embodiments shown below. In addition, the positions, sizes, ranges, etc. of each configuration shown in the drawings and the like may not represent the actual positions, sizes, ranges, etc. for the sake of simplicity of understanding. For this reason, the disclosed invention is not necessarily limited to the positions, sizes, ranges, etc. disclosed in the drawings and the like.

[0035] ​Note that the ordinal numbers such as "first", "second", "third", etc. in this specification and the like are attached to avoid confusion of components, and it is noted that they are not numerically limiting.

[0036] (Embodiment 1) In this embodiment, the circuit configuration and operation of a semiconductor device according to one aspect of the disclosed invention will be described with reference to FIGS. 1 to 3. Note that in the circuit diagram, the symbol "OS" may be attached to indicate that it is a transistor using an oxide semiconductor.

[0037] 〈Basic Circuit〉 First, the basic circuit configuration and its operation will be described with reference to FIG. 1. In the semiconductor device shown in FIG. 1 ( A-1), the first wiring (1st Line) is electrically connected to the drain electrode (or source electrode) of transistor 1 60, and the second wiring (2nd Line) is electrically connected to the source electrode (or drain electrode) of transistor 160. Also, the third wiring (3rd Line) is electrically connected to the source electrode (or drain electrode) of transistor 162, and the fourth wiring (4th Line) is electrically connected to the gate electrode of transistor 162. Then, the gate electrode of transistor 160 and the drain electrode (or source electrode) of transistor 162 are electrically connected to one of the electrodes of capacitor element 164, and the fifth wiring (5th Line) is electrically connected to the other electrode of capacitor element 164.

[0038] Here, for example, a transistor using an oxide semiconductor is applied to transistor 162. A transistor using an oxide semiconductor has the characteristic that the off-current is extremely small. ​​​​​is in this state. Therefore, by turning off the transistor 162, the potential of the gate electrode of the transistor 160 can be held for an extremely long time. And by having the capacitive element 164, the holding of the charge applied to the gate electrode of the transistor 160 becomes easy, and the reading of the held information also becomes easy.

[0039] Note that the transistor 160 is not particularly limited. From the viewpoint of improving the information reading speed, for example, a transistor with a high switching speed, such as a transistor using single-crystal silicon, is preferably applied.

[0040] Also, as shown in FIG. 1(B), it is also possible to adopt a configuration without providing the capacitive element 164.

[0041] In the semiconductor device shown in FIG. 1(A-1), by taking advantage of the feature that the potential of the gate electrode of the transistor 160 can be held, information can be written, held, and read as follows.

[0042] First, the writing and holding of information will be described. First, the potential of the fourth wiring is set to a potential at which the transistor 162 is turned on, and the transistor 162 is turned on. Thereby, the potential of the third wiring is applied to the gate electrode of the transistor 160 and the capacitive element 1 64. That is, a predetermined charge is applied to the gate electrode of the transistor 160 (writing). Here, two different charges for applying different potentials (hereinafter, the charge for applying a low potential is referred to as charge Q L , and the charge for applying a high potential is referred to as charge Q L H such that either one is applied) Do so. Note that charges that apply three or more different potentials may be applied to improve the storage capacity. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 is in the off state, and the transistor 162 is turned off, so that the charge applied to the gate electrode of the transistor 160 is retained (held). Since the off-current of the transistor 162 is extremely small, the charge on the gate electrode of the transistor 160 is retained for a long time.

[0043]

[0044] Next, the reading of information will be described. When a predetermined potential (constant potential) is applied to the second wiring and an appropriate potential (reading potential) is applied to the fifth wiring, the first wiring takes on different potentials according to the amount of charge held on the gate electrode of the transistor 160. Generally, when the transistor 160 is an n-channel type, the apparent threshold value V when Q is applied to the gate electrode of the transistor 160 is lower than the apparent threshold value V when Q is applied to the gate electrode of the transistor 160. Here, the apparent threshold value refers to the potential of the fifth wiring required to turn the transistor 160 "on". Therefore, by setting the potential of the fifth wiring to a potential V between V and V, the charge applied to the gate electrode of the transistor 160 can be discriminated. For example, in writing, when Q is applied, if the potential of the fifth wiring becomes V (>V), the transistor 160 will be in the "on state". H th_H L th_L th_H th_L 0 H 0 (>V th_H )L is given If so, even if the potential of the fifth wiring is V 0 (< V th_L ), transistor 16 0 remains in the "off state". Therefore, by looking at the potential of the first wiring, the information being held can be read.

[0045] When memory cells are arranged and used in an array, it is necessary to be able to read only the information of a desired memory cell. Thus, when reading the information of a predetermined memory cell and not reading the information of other memory cells, if the transistors 160 are connected in parallel between the respective memory cells , a potential should be applied to the fifth wiring of the memory cell that is not the target of reading such that the transistor 160 becomes in the "off state" regardless of the state of the gate electrode, that is, a potential smaller than V . Also, if the transistors 160 are connected in series between the respective memory cells , a potential should be applied to the fifth wiring of the memory cell that is not the target of reading such that the transistor 160 becomes in the "on state" regardless of the state of the gate electrode, that is, a potential larger than V . th_H should be applied to the fifth wiring. Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the writing and holding of the above information. That is, the potential of the fourth wiring is set to a potential at which the transistor 162 becomes in the on state, and the transistor 162 is turned on. As a result, the potential of the third wiring (the potential related to the new information) is applied to the gate electrode of the transistor 160 and the capacitor element 164. Then, the potential of the fourth wiring is set to a potential at which the transistor 162 becomes in the off state th_L .

[0046] Next, the rewriting of information will be described. The rewriting of information is performed in the same manner as the writing and holding of the above information. That is, the potential of the fourth wiring is set to a potential at which the transistor 162 becomes in the on state, and the transistor 162 is turned on. As a result, the potential of the third wiring (the potential related to the new information) is applied to the gate electrode of the transistor 160 and the capacitor element 164. Then, the potential of the fourth wiring is set to a potential at which the transistor 162 becomes in the off state (new information related potential) is applied to the gate electrode of the transistor 160 and the capacitor element 164. After that, the potential of the fourth wiring is set to a potential at which the transistor 162 becomes in the off state is applied.​​ By turning off the transistor 162, the gate voltage of the transistor 160 becomes a state in which charges related to new information are applied.

[0047] In this way, the semiconductor device according to the disclosed invention can directly rewrite information by writing information again. Therefore, it is not necessary to extract charges from the floating gate using a high voltage required in a flash memory or the like, and it is possible to suppress a decrease in the operation speed caused by the erasing operation. That is, high-speed operation of the semiconductor device is realized. Note that the drain electrode (or source electrode) of the transistor 162 is electrically connected to the gate electrode of the transistor 160, thereby acting equivalently to the floating gate of a floating gate type transistor used as a non-volatile memory element. Hereinafter, in some cases, the portion where the drain electrode (or source electrode) of the transistor 162 and the gate electrode of the transistor 160 are electrically connected is called the node FG. When the transistor 162 is off, the node FG can be regarded as being embedded in an insulator, and charges are held in the node FG. Since the off-current of the transistor 162 using an oxide semiconductor is 1 / 100,000 or less of that of a transistor formed of a silicon semiconductor or the like, it is possible to ignore the disappearance of the charges accumulated in the node FG due to the leakage of the transistor 162. That is, it is possible to realize a non-volatile storage device capable of holding information without power supply by using the transistor 162 using an oxide semiconductor.

[0048] Note that the drain electrode (or source electrode) of the transistor 162 is electrically connected to the gate electrode of the transistor 160, thereby acting equivalently to the floating gate of a floating gate type transistor used as a non-volatile memory element. Hereinafter, in some cases, the portion where the drain electrode (or source electrode) of the transistor 162 and the gate electrode of the transistor 160 are electrically connected is called the node FG. When the transistor 162 is off, the node FG can be regarded as being embedded in an insulator, and charges are held in the node FG. Since the off-current of the transistor 162 using an oxide semiconductor is 1 / 100,000 or less of that of a transistor formed of a silicon semiconductor or the like, it is possible to ignore the disappearance of the charges accumulated in the node FG due to the leakage of the transistor 162. That is, it is possible to realize a non-volatile storage device capable of holding information without power supply by using the transistor 162 using an oxide semiconductor. Hereinafter, in some cases, the portion where the drain electrode (or source electrode) of the transistor 162 and the gate electrode of the transistor 160 are electrically connected is called the node FG. When the transistor 162 is off, the node FG can be regarded as being embedded in an insulator, and charges are held in the node FG. Since the off-current of the transistor 162 using an oxide semiconductor is 1 / 100,000 or less of that of a transistor formed of a silicon semiconductor or the like, it is possible to ignore the disappearance of the charges accumulated in the node FG due to the leakage of the transistor 162. That is, it is possible to realize a non-volatile storage device capable of holding information without power supply by using the transistor 162 using an oxide semiconductor. When the transistor 162 is off, the node FG can be regarded as being embedded in an insulator, and charges are held in the node FG. Since the off-current of the transistor 162 using an oxide semiconductor is 1 / 100,000 or less of that of a transistor formed of a silicon semiconductor or the like, it is possible to ignore the disappearance of the charges accumulated in the node FG due to the leakage of the transistor 162. That is, it is possible to realize a non-volatile storage device capable of holding information without power supply by using the transistor 162 using an oxide semiconductor. Since the off-current of the transistor 162 using an oxide semiconductor is 1 / 100,000 or less of that of a transistor formed of a silicon semiconductor or the like, it is possible to ignore the disappearance of the charges accumulated in the node FG due to the leakage of the transistor 162. That is, it is possible to realize a non-volatile storage device capable of holding information without power supply by using the transistor 162 using an oxide semiconductor. That is, it is possible to realize a non-volatile storage device capable of holding information without power supply by using the transistor 162 using an oxide semiconductor.

[0049] ​​​​​​​​For example, when the off-current of the transistor 162 at room temperature (25 °C) is 10 zA (1 zA (zepto ampere) is 1 × 10 -21 A) or less and the capacitance value of the capacitor element 164 is about 10 fF in some cases, data retention for at least 10 4 seconds or more is possible. Note that it goes without saying that the retention time varies depending on the transistor characteristics and capacitance value.

[0050] Further, in the semiconductor device of the disclosed invention, there is no problem of deterioration of the gate insulating film (tunnel insulating film) pointed out in the conventional floating gate type transistor That is, the problem of deterioration of the gate insulating film when injecting electrons into the floating gate, which has been a conventional problem, can be solved. This means that there is no theoretical limit on the number of write operations. Also, the high voltage that was necessary for writing and erasing in the conventional floating gate type transistor is not required. The semiconductor device shown in FIG. 1(A-1) can be considered as shown in FIG. 1(A-2) with elements such as transistors constituting the semiconductor device including resistors and capacitors. That is, in FIG. 1(A-2), it is considered that the transistor 160 and the capacitor element 164 are each configured to include a resistor and a capacitor. R1 and C1 are the resistance value and capacitance value of the capacitor element 164, respectively, and the resistance value R1 corresponds to the resistance value due to the insulating layer constituting the capacitor element 164. Also, R2 and C2 are the resistance value and capacitance value of the transistor 160, respectively, and the resistance value R2 corresponds to the resistance value due to the gate insulating layer when the transistor 160 is in the on state, and the capacitance value C2 is the so-called gate capacitance (between the gate electrode and

[0051] the semiconductor device shown in FIG. 1(A-1) can be considered as shown in FIG. 1(A-2) with elements such as transistors constituting the semiconductor device including resistors and capacitors. That is, in FIG. 1(A-2), it is considered that the transistor 160 and the capacitor element 164 are each configured to include a resistor and a capacitor. R1 and C1 are the resistance value and capacitance value of the capacitor element 164, respectively, and the resistance value R1 corresponds to the resistance value due to the insulating layer constituting the capacitor element 164. Also, R2 and C2 are the resistance value and capacitance value of the transistor 160, respectively, and the resistance value R2 corresponds to the resistance value due to the gate insulating layer when the transistor 160 is in the on state, and the capacitance value C2 is the so-called gate capacitance (between the gate electrode and the semiconductor device shown in FIG. 1(A-1) can be considered as shown in FIG. 1(A-2) with elements such as transistors constituting the semiconductor device including resistors and capacitors. That is, in FIG. 1(A-2), it is considered that the transistor 160 and the capacitor element 164 are each configured to include a resistor and a capacitor. R1 and C1 are the resistance value and capacitance value of the capacitor element 164, respectively, and the resistance value R1 corresponds to the resistance value due to the insulating layer constituting the capacitor element 164. Also, R2 and C2 are the resistance value and capacitance value of the transistor 160, respectively, and the resistance value R2 corresponds to the resistance value due to the gate insulating layer when the transistor 160 is in the on state, and the capacitance value C2 is the so-called gate capacitance (between the gate electrode and the semiconductor device shown in FIG. 1(A-1) can be considered as shown in FIG. 1(A-2) with elements such as transistors constituting the semiconductor device including resistors and capacitors. the semiconductor device shown in FIG. 1(A-1) can be considered as shown in FIG. 1(A-2) with elements such as transistors constituting the semiconductor device including resistors and capacitors. It corresponds to the capacitance value of the capacitance formed between the source electrode and the drain electrode, and the capacitance formed between the gate electrode and the channel formation region).

[0052] When the transistor 162 is in the off state, if the resistance value between the source electrode and the drain electrode (also called the effective resistance) is ROS, then when the gate leakage current of the transistor 162 is sufficiently small and the conditions are met, when R1 and R2 satisfy R1≥ROS (R1 is greater than or equal to ROS) and R2≥ROS (R2 is greater than or equal to ROS), the charge holding period (which can also be called the information holding period) will mainly be determined by the off - current of the transistor 162. Conversely, when these conditions are not met, even if the off - current of the transistor 162 is sufficiently small, it becomes difficult to ensure a sufficient holding period. This is because of leakage currents other than the off - current of the transistor 162 (for example, the leakage current that occurs between the source electrode and the gate electrode in the transistor 160, etc.). Therefore, it can be said that the semiconductor device disclosed in this embodiment preferably satisfies the relationship of R1≥ROS (R1 is greater than or equal to ROS) and R2≥ROS (R2 is greater than or equal to ROS).

[0053] is large.

[0054] On the other hand, it is desirable that C1 and C2 satisfy the relationship of C1≥C2 (C1 is greater than or equal to C2). By increasing C1, when controlling the potential of the node FG by the fifth wiring, the potential of the fifth wiring can be efficiently applied to the node FG, and the potential difference between the potentials applied to the fifth wiring (for example, the potential during reading and the potential during non - reading) can be kept low. This is because it can be achieved.

[0055] In this way, by satisfying the above relationships, it is possible to realize a more suitable semiconductor device. Note that R1 and R2 are controlled by the gate insulating layer of the transistor 160 and the insulating layer of the capacitor element 164. The same applies to C1 and C2. Therefore, it is desirable to appropriately set the material, thickness, etc. of the gate insulating layer so as to satisfy the above relationships. In the semiconductor device shown in this embodiment, the node FG functions equivalently to the floating gate of a floating gate type transistor such as a flash memory, but the node FG of this embodiment has characteristics essentially different from those of the floating gate of a flash memory or the like. In a flash memory, since the potential applied to the control gate is high, it is necessary to maintain a certain distance between cells so that the potential does not affect the floating gates of adjacent cells. This is one of the factors that hinder the high integration of semiconductor devices. And this factor is due to the fundamental principle of flash memory of generating tunnel current by applying a high electric field.

[0056] In the semiconductor device shown in this embodiment, the node FG functions equivalently to the floating gate of a floating gate type transistor such as a flash memory, but the node FG of this embodiment has characteristics essentially different from those of the floating gate of a flash memory or the like. In a flash memory, since the potential applied to the control gate is high, it is necessary to maintain a certain distance between cells so that the potential does not affect the floating gates of adjacent cells. This is one of the factors that hinder the high integration of semiconductor devices. And this factor is due to the fundamental principle of flash memory of generating tunnel current by applying a high electric field. In a flash memory, since the potential applied to the control gate is high, it is necessary to maintain a certain distance between cells so that the potential does not affect the floating gates of adjacent cells. This is one of the factors that hinder the high integration of semiconductor devices. And this factor is due to the fundamental principle of flash memory of generating tunnel current by applying a high electric field. On the other hand, the semiconductor device according to this embodiment operates by the switching of a transistor using an oxide semiconductor and does not use the principle of charge injection by tunnel current as described above. That is, a high electric field for injecting charges like in a flash memory is not required. As a result, it is not necessary to consider the influence of the high electric field by the control gate on adjacent cells, and high integration becomes easier.

[0057] In a flash memory, since the potential applied to the control gate is high, it is necessary to maintain a certain distance between cells so that the potential does not affect the floating gates of adjacent cells. This is one of the factors that hinder the high integration of semiconductor devices. And this factor is due to the fundamental principle of flash memory of generating tunnel current by applying a high electric field. In a flash memory, since the potential applied to the control gate is high, it is necessary to maintain a certain distance between cells so that the potential does not affect the floating gates of adjacent cells. This is one of the factors that hinder the high integration of semiconductor devices. And this factor is due to the fundamental principle of flash memory of generating tunnel current by applying a high electric field. In a flash memory, since the potential applied to the control gate is high, it is necessary to maintain a certain distance between cells so that the potential does not affect the floating gates of adjacent cells. This is one of the factors that hinder the high integration of semiconductor devices. And this factor is due to the fundamental principle of flash memory of generating tunnel current by applying a high electric field. In a flash memory, since the potential applied to the control gate is high, it is necessary to maintain a certain distance between cells so that the potential does not affect the floating gates of adjacent cells. This is one of the factors that hinder the high integration of semiconductor devices. And this factor is due to the fundamental principle of flash memory of generating tunnel current by applying a high electric field. On the other hand, the semiconductor device according to this embodiment operates by the switching of a transistor using an oxide semiconductor and does not use the principle of charge injection by tunnel current as described above. That is, a high electric field for injecting charges like in a flash memory is not required. As a result, it is not necessary to consider the influence of the high electric field by the control gate on adjacent cells, and high integration becomes easier.

[0058] On the other hand, the semiconductor device according to this embodiment operates by the switching of a transistor using an oxide semiconductor and does not use the principle of charge injection by tunnel current as described above. That is, a high electric field for injecting charges like in a flash memory is not required. As a result, it is not necessary to consider the influence of the high electric field by the control gate on adjacent cells, and high integration becomes easier. On the other hand, the semiconductor device according to this embodiment operates by the switching of a transistor using an oxide semiconductor and does not use the principle of charge injection by tunnel current as described above. That is, a high electric field for injecting charges like in a flash memory is not required. As a result, it is not necessary to consider the influence of the high electric field by the control gate on adjacent cells, and high integration becomes easier. On the other hand, the semiconductor device according to this embodiment operates by the switching of a transistor using an oxide semiconductor and does not use the principle of charge injection by tunnel current as described above. That is, a high electric field for injecting charges like in a flash memory is not required. As a result, it is not necessary to consider the influence of the high electric field by the control gate on adjacent cells, and high integration becomes easier. On the other hand, the semiconductor device according to this embodiment operates by the switching of a transistor using an oxide semiconductor and does not use the principle of charge injection by tunnel current as described above. That is, a high electric field for injecting charges like in a flash memory is not required. As a result, it is not necessary to consider the influence of the high electric field by the control gate on adjacent cells, and high integration becomes easier. On the other hand, the semiconductor device according to this embodiment operates by the switching of a transistor using an oxide semiconductor and does not use the principle of charge injection by tunnel current as described above. That is, a high electric field for injecting charges like in a flash memory is not required. As a result, it is not necessary to consider the influence of the high electric field by the control gate on adjacent cells, and high integration becomes easier.

[0059] Also, the fact that a high electric field is not required and large peripheral circuits (such as a booster circuit) are not required is an advantage over flash memory. For example, the maximum value of the voltage applied to the memory cell according to this embodiment (the difference between the maximum and minimum of the potentials simultaneously applied to each terminal of the memory cell) can be 5 V or less, preferably 3 V or less, when writing information in two levels (1 bit) in one memory cell. Furthermore, when making the relative dielectric constant εr1 of the insulating layer constituting the capacitive element 164 different from the relative dielectric constant εr2 of the gate insulating layer constituting the transistor 160, it is easy to realize 2·S2≧S1 (2·S2 is equal to or greater than S1), preferably S2≧S1 (S2 is equal to or greater than S1), while satisfying C1≧C2 (C1 is equal to or greater than C2) for the area S1 of the capacitive element 164 and the area S2 of the region having the gate capacitance in the transistor 160. Specifically, for example, in the insulating layer constituting the capacitive element 164, a film made of a high-k material such as hafnium oxide, or a laminate structure of a film made of a high-k material such as hafnium oxide and a film made of an oxide semiconductor is adopted to make εr1 10 or more, preferably 15 or more, and in the gate insulating layer constituting the transistor 160, silicon oxide is adopted to make 3≦εr2≦4 (εr2 is 3 or more and 4 or less). By using such a configuration in combination, further higher integration of the semiconductor device according to the disclosed invention is possible. Note that, in order to increase the storage capacity of the semiconductor device, in addition to higher integration, a technique of multi-valuing can be adopted.

[0060]

[0061]

[0062] It is also possible. For example, the configuration may be such that information of three or more levels is written into one of the memory cells. In this case, the storage capacity can be increased as compared with the case where information of two levels (1 bit) is written. For example, as described above, the charge Q that applies a low potential L and the charge Q that applies a high potential H In addition to by applying a charge Q that applies another potential to the gate electrode of the transistor 160, multi-valuing can be achieved. In this case, even if a circuit configuration of relatively large scale (for example, 15F 2 ~50 F 2 etc.: F is the minimum processing dimension) is adopted, a sufficient storage capacity can be ensured.

[0063] <Application Example 1> Next, a more specific circuit configuration and operation applying the circuit shown in FIG. 1 will be described with reference to FIGS. 2 and 3.

[0064] FIG. 2(A) is an example of a circuit diagram of a semiconductor device having (m × n) memory cells 170. The configuration of the memory cell 170 in FIG. 2 is the same as that in FIG. 1(A-1). That is, as shown in FIG. 2 (B), the first wiring in FIG. 1(A-1) corresponds to the bit line BL in FIG. 2(B), the second wiring in FIG. 1(A-1) corresponds to the source line SL in FIG. 2(B), the third wiring in FIG. 1(A-1) corresponds to the signal line S in FIG. 2(B), and the fourth wiring in FIG. 1(A-1) corresponds to the write word line WWL in FIG. 2(B), and the fifth wiring in FIG. 1(A-1) corresponds to the read word line RWL in FIG. 2(B). However, in FIG. 2(A), only the memory cells 170(1,1) to (1,n) in the first row are directly connected to the bit line BL, and the memory cells 170(m,1) to (m,n) in the m-th row is directly connected to the source line SL only. The memory cells 170 in other rows are electrically connected to the bit line BL and the source line SL via other memory cells 170 in the same column.

[0065] The semiconductor device shown in FIG. 2 includes m write word lines WWL (where m is an integer of 2 or more), m read word lines RWL, n source lines SL (where n is an integer of 2 or more), n bit lines BL, n signal lines S, and a memory cell array in which memory cells 170 are arranged in a matrix of m (rows) × n (columns) vertically and horizontally, a first drive circuit 190 connected to the n bit lines BL and the n signal lines S, and a second drive circuit 192 connected to the m write word lines WWL and the m read word lines RWL. The first drive circuit 190 and the second drive circuit 192 are connected by wiring WRITE and wiring READ. .

[0066] In addition, an address selection signal line A is connected to the second drive circuit 192. The address selection signal line A is a wiring that transmits a signal for selecting an address in the row direction of the memory cell.

[0067] The first drive circuit 190 and the second drive circuit 192 shown in FIG. 2(A) will be described with reference to FIG. 23. The first drive circuit 190 and the second drive circuit 192 are connected by wiring WRITE and wiring READ.

[0068] The first drive circuit 190 is composed of a read circuit 211, a control circuit 212, a delay circuit 213, and a buffer circuit 214. The input terminal IN is connected to the signal line S via the control circuit 212, the delay circuit 213, and the buffer circuit 214. Also, the bit The read circuit 211 connected to the line BL is connected to the output terminal OUT.

[0069] The second drive circuit 192 is composed of a decoder circuit 221, a control circuit 222, buffer circuits 22 3 and 224. The address selection signal line A is connected to the decoder circuit 221. Also, the decoder circuit 221 is connected to the control circuit 222, and the control circuit 222 is connected to the write word line WWL via the buffer circuit 223 and is connected to the read word line RWL via the buffer circuit 224.

[0070] The writing, holding, and reading of data are basically the same as in the case of FIG. 1. That is, the specific writing operation is as follows. Here, as an example, referring to FIGS. 2(B) and 23, the case where either the potential V1 (a potential lower than the power supply potential VDD) or the reference potential GND is applied to the node FG will be described, but the relationship of the potential applied to the node FG is not limited to this. Also, the data held when the potential V1 is applied to the node FG is defined as data "1", and the data held when the reference potential GND is applied to the node FG is defined as data " 0". 0".

[0071] First, for data writing, the potential of the read word line RWL connected to the memory cell 170 to be written is set to GND, and the potential of the write word line WWL is set to V2 (a potential higher than V1, for example, VDD) to select the memory cell 170 to be written.

[0072] When writing data "0" to the memory cell 170, GND is applied to the signal line S, and the memo When writing data "1" to the memory cell 170, V2 is applied to the signal line S. Here Since the potential of the write word line WWL is set to V2, it is possible to apply V1 to the node FG.

[0073] Data retention is achieved by setting the potential of the read word line RWL and the potential of the write word line WWL to GND.

[0074] When the potential of the read word line RWL is fixed to GND, the potential of the node FG is fixed to the potential at the time of writing. That is, when V1 which is data "1" is applied to the node FG , the potential of the node FG becomes V1, and when GND which is data "0" is applied to the node FG , the potential of the node FG becomes GND.

[0075] Since GND is applied to the write word line WWL, regardless of whether data "1" or data "0" is written, the transistor 162 is in the off state. Since the off-current of the transistor 162 is extremely small, the charge of the gate electrode of the transistor 160 is retained for a long time.

[0076] Data reading is performed by setting the potential of the read word line RWL connected to the memory cell 170 to be read and the potential of the write word line WWL to GND, and also setting the potential of the read word line RWL connected to the memory cell 170 that is not the target of reading to V2, and setting the potential of the write word line WWL to GND.

[0077] By setting the potential of the read word line RWL connected to the memory cell 170 to be read to GND ​​​​​Then, when data "1", which is V1, is applied to node FG of memory cell 170 to be read, transistor 160 turns on. On the other hand, if GND, which is data "0", is applied to node FG, transistor 160 turns off. Also, when the potential of read word line RWL connected to memory cell 170 that is not the read target is set to V2 and the potential of write word line WWL is set to GND, when data "1" is written in memory cell 170 that is not the read target, and when data "0" is written, transistor 160 turns on in either case.

[0078] That is, by the above-described read operation, when data "1" is written in memory cell 170 to be read, transistor 160 turns on and the potential of bit line BL decreases. Also, when data "0" is written, transistor 160 turns off and the potential of bit line BL at the start of reading is maintained or increases. Note that when the above-described configuration is adopted, the potential of read word line RWL and the potential of write word line WWL in the data holding operation and the data reading operation are GND. That is, when data "1" is written in all memory cells 170 in the target column, transistor 160 turns on and the source line SL and the bit line BL conduct regardless of whether it is holding or reading.

[0079] For this reason, there is a problem of increased power consumption. In order to sufficiently suppress the power consumption caused by such a situation, memory cell 1 is written, transistor 160 turns on and the potential of bit line BL decreases. Also, when data "0" is written, transistor 160 turns off and the potential of bit line BL at the start of reading is maintained or increases. That is, by the above-described read operation, when data "1" is written in memory cell 170 to be read, transistor 160 turns on and the potential of bit line BL

[0080] Note that when the above-described configuration is adopted, the potential of read word line RWL and the potential of write word line WWL in the data holding operation and the data reading operation are GND. That is, when data "1" is written in all memory cells 170 in the target column, transistor 160 turns on and the source line SL and the bit line BL conduct regardless of whether it is holding or reading. For this reason, there is a problem of increased power consumption. In order to sufficiently suppress the power consumption caused by such a situation, memory cell 1 is written, transistor 160 turns on and the source line SL and the bit line BL conduct regardless of whether it is holding or reading. For this reason, there is a problem of increased power consumption. In order to sufficiently suppress the power consumption caused by such a situation, memory cell 1 is written, transistor 160 turns on and the source line SL and the bit line BL conduct regardless of whether it is holding or reading. It is advisable to provide a selection transistor between 70 and the source line SL or the bit line BL. Also during operations other than the read operation, the potentials of the source line SL and the bit line BL may be made equal.

[0081] Fig. 3 shows an example of a timing chart related to a more detailed operation of the semiconductor device according to Fig. 2(A). Names such as READ and A in the timing chart indicate the wirings to which the potentials shown in the timing chart are applied. When there are multiple wirings having the same function, they are distinguished by attaching _1, _2, etc. to the end of the wiring name. Here, for simplicity of explanation, a semiconductor device in which memory cells 170 are arranged in 2 (rows) × 2 (columns) will be described as an example, but the disclosed invention is not limited to this. However, the disclosed invention is not limited to this.

[0082] The timing chart shown in Fig. 3 shows the case where data "1" is written to all memory cells (write 1), then all the written data is read out (read 1), and next, data "1" is written to the memory cells in the first row and the first column and the memory cells in the second row and the second column, and at the same time, data "0" is written to the memory cells in the first row and the second column and the memory cells in the second row and the first column (write 2), and then all the written data is read out (read 2), and shows the potential relationship of each wiring.

[0083] In write 1, WRITE is set to a high potential and READ is set to a low potential so that writing to the memory cells can be performed. The second drive circuit 192 outputs row selection signals corresponding to the potentials of A_1 and A_2 to RWL and WWL. Here, it is assumed that the first row is selected when A_1 is at a high potential and the second row is selected when A_2 is at a high potential. Also, the selection ​​​​​​​​​​​The WWL of the selected row becomes a high potential, and the RWL becomes a low potential regardless of selection or non - selection. .

[0084] In Write 1, in order to write data "1" to all memory cells, S_1 and S_2 are set to high potential in accordance with the timing of row selection. Note that the signal input period of S_1 and S_2 should be longer than the signal input period of WWL. Or, the signal input of S_1 and S _2 is delayed compared to the signal input of WWL. If the signal input period of S_1 and S_2 is short, or the signal input of S_1 and S_2 is earlier than the signal input of WWL, there is a possibility that the writing to the memory cell is insufficient. To achieve this operation, for example, a delay circuit 213 can be connected to S_1 or S_2 to delay the signal input of S_1 or S_2 compared to the signal input of WWL. Or, the size (e.g., channel length) of the transistors constituting the buffer circuit 214 connected to S_1 or S_2 can be made larger than the size (e.g., channel length) of the transistors constituting the buffer circuit 223 connected to WWL to reduce the driving ability and delay the signal input of S_1 and S_2 compared to the signal input of WWL. Or, the size (e.g., channel width) of the transistors constituting the buffer circuit 214 connected to S_1 or S_2 can be made smaller than the size (e.g., channel width) of the transistors constituting the buffer circuit 2 23 connected to WWL to reduce the driving ability and delay the signal input of S_1 and S_2 compared to the signal input of WWL . Note that the potentials of BL_1 and BL_2 do not cause major problems during writing (they can be high potential or low potential). . . . . . . . . .

[0087] In the first read operation, the WRITE is set to a low potential and the READ is set to a high potential so that the memory cell can be read. The second drive circuit 192 outputs row selection signals to RWL and WWL according to A_1 and A_2. Here, when A_1 is at a high potential, the first row is selected, and when A_2 is at a high potential, the second row is selected. Also, the RWL of the selected row becomes a low potential, the RWL of the unselected row becomes a high potential, and the WWL becomes a low potential regardless of selection or non-selection.

[0086] Due to the above operation, potentials corresponding to the data held in the memory cells of the selected row are applied to BL_1 and BL_2. Note that the potentials of S_1 and S_2 do not pose a problem during reading.

[0087] The potential relationships of the respective wirings in the second write operation are the same as those in the first write operation. However, in order to write data "1" to the memory cells in the first row and first column and the second row and second column, and at the same time write data "0" to the memory cells in the first row and second column and the second row and first column, S_1 and S_2 are set to a low potential or a high potential in accordance with the timing of row selection.

[0088] The potential relationships of the respective wirings in the second read operation are the same as those in the first read operation. It can be seen that potentials corresponding to the data held in the memory cells of the selected row are applied to BL_1 and BL_2.

[0089] In addition, in the above write operation, in order to delay the signal input to the signal line S compared to the signal input to the write word line WWL, for example, a delay circuit shown in FIG. 4 is It may be provided in circuit 190 and connected to signal line S. Connecting the delay circuit and signal line S can delay the change in the potential of signal line S from the change in the potential of write word line WWL and can suppress write errors to memory cell 170.

[0090] Next, the delay circuit 213 provided in the first drive circuit 190 shown in FIG. 23 will be described with reference to FIGS. 4( A), (B), (C), (D) and FIG. 22.

[0091] As the delay circuit 213, a circuit in which an even number of inverters shown in FIG. 4(A) are connected in series can be used. Also, as shown in FIG. 4(B), a configuration in which a capacitive element is added to the serially connected even number of inverters, or as shown in FIG. 4(C), a configuration in which a resistor is added to the serially connected even number of inverters may be used. Furthermore, as shown in FIG. 4(D), a configuration in which a resistor and a capacitive element are added to the serially connected even number of inverter circuits may be used. .

[0092] Alternatively, in the above-described write operation, in order to delay the signal input to signal line S from the signal input to write word line WWL, in the buffer circuits provided in the first drive circuit 190 and the second drive circuit 192, the size (e.g., channel length) of the transistors of the buffer circuit 214 included in the first drive circuit 190 may be made larger than the size of the transistors of the buffer circuit 223 included in the second drive circuit 192. Or, the size (e.g., channel width) of the transistors of the buffer circuit 214 included in the first drive circuit 190 may be made larger than the size (e.g., For example, it may be made smaller than the channel width. Also in this case, the change in the potential of the signal line S can be delayed more than the change in the potential of the write word line WWL, and write errors to the memory cell 170 can be suppressed. The change in the potential of the signal line S can be delayed more than the change in the potential of the write word line WWL, and write errors to the memory cell 170 can be suppressed.

[0093] Next, the read circuit 211 provided in the second drive circuit 192 shown in FIG. 23 will be described with reference to FIG. 22.

[0094] FIG. 22(A) shows an outline of the read circuit. The read circuit includes a transistor and a sense amplifier circuit.

[0095] At the time of reading, the terminal A is connected to the bit line BL to which the memory cell performing the reading is connected. Also, a bias potential Vbias is applied to the gate electrode of the transistor, and the potential of the terminal A is controlled. The bias potential Vbias is applied to the gate electrode of the transistor, and the potential of the terminal A is controlled.

[0096] The memory cell 170 exhibits different resistance values according to the data stored therein. Specifically, when the transistor 160 of the selected memory cell 170 is in the on state, it is in a low resistance state, and when the transistor 160 of the selected memory cell 170 is in the off state, it is in a high resistance state. When the transistor 160 of the selected memory cell 170 is in the on state, it is in a low resistance state. When the transistor 160 of the selected memory cell 170 is in the off state, it is in a high resistance state.

[0097] When the memory cell is in the high resistance state, the potential of the terminal A becomes higher than the reference potential Vref, and the sense amplifier circuit outputs a potential (data "0") corresponding to the potential of the terminal A. On the other hand, when the memory cell is in the low resistance state, the potential of the terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit outputs a potential (data "1") corresponding to the potential of the terminal A. When the memory cell is in the high resistance state, the potential of the terminal A becomes higher than the reference potential Vref, and the sense amplifier circuit outputs a potential (data "0") corresponding to the potential of the terminal A. On the other hand, when the memory cell is in the low resistance state, the potential of the terminal A becomes lower than the reference potential Vref, and the sense amplifier circuit outputs a potential (data "1") corresponding to the potential of the terminal A.

[0098] In this way, by using the read circuit, data can be read from the memory cell. ​​​​​​Note that the read circuit of this embodiment is just an example, and other known circuits may be used instead. Also, the read circuit may have a precharge circuit. Instead of the reference potential Vref, it may be configured such that a reference bit line is connected.

[0099] Fig. 22(B) shows a differential sense amplifier which is an example of a sense amplifier circuit. The differential sense amplifier has input terminals Vin(+) and Vin(-) and an output terminal Vout, and amplifies the difference between Vin( + ) and Vin(-). If Vin(+) > Vin(-), Vout is generally a High output, and if Vin(+) < Vin(-), Vout is generally a Low output and becomes so.

[0100] Fig. 22(C) shows a latch-type sense amplifier which is an example of a sense amplifier circuit. The latch-type sense amplifier has input / output terminals V1 and V2 and input terminals for control signals Sp and Sn. First, with signal Sp set to High and signal Sn set to Low, the power supply potential (Vdd) is cut off. Then, the potentials for comparison are applied to V1 and V2. After that, with signal Sp set to Low and signal S n set to High, when the power supply potential (Vdd) is supplied, if the potentials for comparison V1in and V2 in are in the relationship V1in > V2in, the output of V1 is High and the output of V2 is Low and if they are in the relationship V1in < V2in, the output of V1 is Low and the output of V2 is Hig h and becomes so. Using such a relationship, the difference between V1in and V2in can be amplified.

[0101] <Application Example 2> Next, a circuit configuration different from the circuit configuration shown in Fig. 2 will be described with reference to Fig. 5.

[0102] FIG. 5(A) is an example of a circuit diagram of a semiconductor device having (m×n) memory cells 170. Since the configuration of the memory cell 170 in FIG. 5(A) is the same as that in FIG. 2(B), detailed description thereof is omitted.

[0103] The semiconductor device shown in FIG. 5(A) includes m (m is an integer of 2 or more) write word lines WWL, m read word lines RWL, n (n is an integer of 2 or more) source lines SL, n bit lines BL, n signal lines S, a memory cell array in which the memory cells 170 are arranged in a matrix of m (rows) × n (columns), a potential conversion circuit 180, a first drive circuit 190 connected to the n bit lines BL and the n signal lines S, and a second drive circuit 192 connected to the m write word lines WWL and the m read word lines RWL. Here, the potential conversion circuit 180 is connected to the second drive circuit 192 by a wiring VHL, and outputs a potential higher than the power supply potential VDD (high potential: VH) to the second drive circuit 192. In the present embodiment, the wirings WRITE and READ are connected to the potential conversion circuit 180 respectively, so as to convert the potential in accordance with the output of the first drive circuit 190. However, the disclosed invention is not limited thereto. The potential conversion circuit 180, the first drive circuit 190, and the second drive circuit 192 may be configured not to be connected by the wirings WRITE and READ. In addition, an address selection signal line A is connected to the second drive circuit 192. The address selection signal line A is a wiring that transmits a signal for selecting an address in the row direction of the memory cell.

[0104]

[0105] Regarding the first drive circuit 190 and the second drive circuit 192 shown in FIG. 5(A), reference will be made to FIG. 24 for explanation. The first drive circuit 190 and the second drive circuit 192 are connected by wiring WRITE and wiring READ. Also, the wiring WRITE and the wiring READ are each connected to the potential conversion circuit 180.

[0106] The first drive circuit 190 is composed of a read circuit 211, a control circuit 212, a delay circuit 213 , and a buffer circuit 214. The input terminal IN is connected to the signal line S via the control circuit 212, the delay circuit 213, and the buffer circuit 214. Also, the read circuit 211 connected to the bit line BL is connected to the output terminal OUT.

[0107] The second drive circuit 192 is composed of a decoder circuit 221, a control circuit 222, a buffer circuit 22 3, a buffer circuit 224, and a level shift circuit 225. The address selection signal line A is connected to the decoder circuit 221. Also, the decoder circuit 221 is connected to the control circuit 222, and the control circuit 222 is connected to the write word line WWL via the level shift circuit 225 and the buffer circuit 223. Also, the control circuit 22 2 is connected to the read word line RWL via the buffer circuit 224. Note that the read circuit 211 may be referred to FIG. 22, and the delay circuit 213 may be referred to FIG. 4 . Here, GND or VH is output to the write word line WWL.

[0108] The writing, holding, and reading of data are the same as in the case of FIG. 2. However, in this configuration , when writing, the potential of the write word line WWL is set to a potential higher than the power supply potential​ can be set as (VH). Therefore, a sufficiently high potential can be applied to the node FG, enabling data retention for a longer period. Also, the discrimination ability of the data is improved.

[0109] As an example of the potential conversion circuit 180, an example of a boosting circuit that performs four-stage boosting is shown in FIG. 6. In FIG. 6, the input terminal (here, the source terminal or the drain terminal that is connected to the gate terminal) of the first transistor 1300 is supplied with the power supply potential VDD. The output terminal (here, the source terminal or the drain terminal that is not connected to the gate terminal) of the first transistor 1300 is connected to the input terminal of the second transistor 1310 and one terminal of the first capacitor element 1350. Similarly, the output terminal of the second transistor 1310 is connected to the input terminal of the third transistor 1320 and one terminal of the second capacitor element 1360. Since the following is the same, detailed description is omitted, but it can also be said that one terminal of the nth capacitor element is connected to the output terminal of the nth transistor (n: natural number). In FIG. 6, a transistor 1390 connected to the power supply VDD is connected to the output terminal of the final-stage transistor, but this configuration is not limited thereto. For example, a configuration in which a capacitor connected to the ground potential GND is further added may also be used. In FIG. 6, the output of the fifth transistor 1340 becomes the output VH of the boosting circuit.

[0110] Furthermore, the clock signal CP_CLK is input to the other terminal of the second capacitor element 1360 and the other terminal of the fourth capacitor element 1380. Also, the other To the terminal and the other terminal of the third capacitor element 1370, a clock signal CP_CLKB obtained by inverting the clock signal CP_CLK is input. That is, it can be said that the clock signal CP_CLK is input to the other terminal of the 2k-th capacitor element, and the inverted clock signal CP_CLKB is input to the other terminal of the (2k - 1)-th capacitor element (k is a natural number). Of course, the clock signal CP_CLK and the inverted clock signal CP_CLKB can be used interchangeably. When the clock signal CP_CLK is Low, that is, when the inverted clock signal CP_CLKB is High, the second capacitor element 1360 and the fourth capacitor element 1380 are charged, and the potentials of the nodes N1 and N3 that capacitively couple with the inverted clock signal CP_CLKB are pulled up by a predetermined voltage (a voltage corresponding to the potential difference between the High and Low of the clock signal CP_CLK). On the other hand, the potentials of the nodes N2 and N4 that capacitively couple with the clock signal CP_CLK are pulled down by a predetermined voltage. As a result, charges move through the second transistor 1310 and the fourth transistor 1330, and the potentials of the nodes N2 and N4 are pulled up to a predetermined value. Next, when the clock signal CP_CLK becomes High and the inverted clock signal becomes Low, the potentials of the nodes N2 and N4 are further pulled up. On the other hand, the potentials of the nodes N1 and N3 are pulled down by a predetermined voltage. As a result, charges move through the first transistor 1300, the third transistor 1320, and the fifth transistor 1340, and the potentials of the nodes N2 and N4 are pulled up to a predetermined value.

[0111] When the clock signal CP_CLK is Low, that is, when the inverted clock signal CP_CLKB is High, the second capacitor element 1360 and the fourth capacitor element 1380 are charged, and the potentials of the nodes N1 and N3 that capacitively couple with the inverted clock signal CP_CLKB are pulled up by a predetermined voltage (a voltage corresponding to the potential difference between the High and Low of the clock signal CP_CLK). On the other hand, the potentials of the nodes N2 and N4 that capacitively couple with the clock signal CP_CLK are pulled down by a predetermined voltage. As a result, charges move through the second transistor 1310 and the fourth transistor 1330, and the potentials of the nodes N2 and N4 are pulled up to a predetermined value. Next, when the clock signal CP_CLK becomes High and the inverted clock signal becomes Low, the potentials of the nodes N2 and N4 are further pulled up. On the other hand, the potentials of the nodes N1 and N3 are pulled down by a predetermined voltage. As a result, charges move through the first transistor 1300, the third transistor 1320, and the fifth transistor 1340, and the potentials of the nodes N2 and N4 are pulled up to a predetermined value. On the other hand, the potentials of the nodes N2 and N4 that capacitively couple with the clock signal CP_CLK are pulled down by a predetermined voltage. As a result, charges move through the second transistor 1310 and the fourth transistor 1330, and the potentials of the nodes N2 and N4 are pulled up to a predetermined value.

[0112] As a result, charges move through the second transistor 1310 and the fourth transistor 1330, and the potentials of the nodes N2 and N4 are pulled up to a predetermined value. Next, when the clock signal CP_CLK becomes High and the inverted clock signal becomes Low, the potentials of the nodes N2 and N4 are further pulled up. On the other hand, the potentials of the nodes N1 and N3 are pulled down by a predetermined voltage.

[0113] Next, when the clock signal CP_CLK becomes High and the inverted clock signal becomes Low, the potentials of the nodes N2 and N4 are further pulled up. On the other hand, the potentials of the nodes N1 and N3 are pulled down by a predetermined voltage. As a result, charges move through the first transistor 1300, the third transistor 1320, and the fifth transistor 1340, and the potentials of the nodes N2 and N4 are pulled up to a predetermined value. On the other hand, the potentials of the nodes N1 and N3 are pulled down by a predetermined voltage.

[0114] As a result, charges move through the first transistor 1300, the third transistor 1320, and the fifth transistor 1340, and the potentials of the nodes N2 and N4 are pulled up to a predetermined value. ​Charge transfers through the resistor 1340, resulting in nodes N1, N3, and N4. The potential of 5 is raised to a predetermined potential. The potential at V N5 =V N4(CP_CLK=High) >V N3(CP_CLK=Lo w) >V N2(CP_CLK=High) >V N1(CP_CLK=Low) >Vdd and The boost circuit configuration is limited to four-stage boosting. The number of stages of the boost circuit can be changed as appropriate.

[0115] Note that a transistor used in the boost circuit includes an oxide semiconductor having good off-state current characteristics. By using transistors, the voltage holding time of each node can be increased.

[0116] Next, the level shift circuit 225 (level shifter) provided in the second driving circuit 192 will be described. I will explain it below.

[0117] 7 and 8 show examples of boost level shift circuit diagrams. The configuration of the level shifter shown in FIG. The source terminal of the first p-type transistor 1200 and the source terminal of the third p-type transistor 1201 are as follows: The source terminals of the transistor 1230 are both electrically connected to a power supply that provides a potential VH. The drain terminal of the first p-type transistor 1200 is connected to the drain terminal of the second p-type transistor 1210. and the drain terminal of the third p-type transistor 1230 is electrically connected to the source terminal of The source terminal of the fourth p-type transistor 1240 is electrically connected to the source terminal of the second p-type transistor The drain terminal of the transistor 1210 is connected to the drain terminal of a first n-type transistor 1220. and a fourth p-type transistor 1230 electrically connected to the gate terminal of the third p-type transistor 1230. The drain terminal of the n - transistor 1240 is electrically connected to the drain terminal of the second n - type transistor 1250 and the gate terminal of the first p - type transistor 1200. Also, the source terminal of the first n - type transistor 1220 and the source terminal of the second n - type transistor 1250 are both given GND(=0[V]).

[0118] In FIG. 7, the input signal (I) is input to the gate terminal of the second p - type transistor 1210 and the gate terminal of the first n - type transistor 1220, and the inverted signal (IB) of the input signal is input to the gate terminal of the fourth p - type transistor 1240 and the gate terminal of the second n - type transistor 1250. The output signal (O) is taken out from the drain terminal of the fourth p - type transistor 1240. Also, the inverted signal (OB) of the output signal can be taken out from the drain terminal of the second p - type transistor 1210.

[0119] The basic operation of the level shifter shown in FIG. 7 will be described. When High is input to the input signal (I), since the first n - type transistor 1220 becomes conductive, the potential GND is input to the gate terminal of the third p - type transistor 1230, the third p - type transistor 1230 becomes conductive, and Low is output to the inverted signal (OB) of the output signal. At this time, the potential is GND. On the other hand, since the inverted input signal (IB) is Low at this time, the fourth p - type transistor 1240 becomes conductive and the second n - type transistor 1250 becomes non - conductive. Here, since both the third p - type transistor 1230 and the fourth p - type transistor 12 40 become conductive, High is output to the output signal (O), and the potential at this time is VH. ​

[0120] When the potential of the input signal (I) is Low, the transistors of the level shifter shown in FIG. 7 operate in the reverse manner as described above and a Low is output from the output signal (O). At this time, the potential becomes GND and so on.

[0121] In this way, an output signal (O) with the amplitude converted with respect to the input signal can be obtained That is, the level shifter shown in FIG. 7 can convert the potential difference between High and Low of the input signal (I) into the potential difference between High and Low of the output signal (O).

[0122] FIG. 8 shows an example of a level shift circuit diagram for boosting different from FIG. 7. The configuration of the level shifter shown in FIG. 8 is as follows. The source terminals of the first p-type transistor 1260 and the second p type transistor 1280 are both electrically connected to a power supply that supplies the potential VH to them. The drain terminal of the first n-type transistor 1270 is electrically connected to the drain terminal of the first p-type transistor 1 260 and the gate terminal of the second p-type transistor 1280, and the drain terminal of the second n-type transistor 1290 is electrically connected to the drain terminal of the second p-type transistor 12 80 and the gate terminal of the first p-type transistor 1260. Also, GND (= 0 [V]) is supplied to both the source terminal of the first n-type transistor 1270 and the source terminal of the second n-type transistor 12 90. In FIG. 8, the input signal (I) is input to the gate terminal of the first n-type transistor 1270 and the inverted signal (IB) of the input signal is input to the gate terminal of the second n-type transistor 1290

[0123] ​​​​is input. The output signal (O) is taken from the drain terminal of the second n-type transistor 1290. Also, an inverted signal (OB) of the output signal can be taken from the drain terminal of the first n-type transistor 1270.

[0124] The basic operation of the level shifter shown in FIG. 8 will be described. When a High is input to the input signal (I), since the first n-type transistor 1270 is turned on, a potential GND is input to the gate terminal of the second p-type transistor 1280, and when the second p-type transistor 1280 is turned on, a Low is output to the inverted signal (OB) of the output signal, and the potential at this time becomes GND. On the other hand, since the inverted input signal (IB) is Low at this time, the second n-type transistor 1290 is turned off. Here, since the second p-type transistor 1280 is turned on, a High is output to the output signal (O), and the potential at this time becomes VH.

[0125] When the potential of the input signal (I) is Low, the transistors of the level shifter shown in FIG. 8 operate in the reverse of the above, a Low is output from the output signal (O), and the potential at this time becomes GND.

[0126] In this way, an output signal (O) with an amplitude converted with respect to the input signal can be obtained. That is, the level shifter shown in FIG. 8 can convert the potential difference between High and Low of the input signal (I) into the potential difference between High and Low of the output signal (O).

[0127] The potential converted to a high potential by the potential conversion circuit 180 shown in FIG. 6 is used by the boost level shifters shown in FIGS. 7 and 8 included in the second drive circuit 192, from the write word line WWL to each​​​ It is output to the memory cell 170. Further, the potential converted to a high potential by the potential conversion circuit 180 is output from the signal line S to each memory cell 170 using the boost level shifter included in the first drive circuit 190. It may be configured as follows.

[0128] As described above, the configurations, methods, etc. shown in this embodiment can be appropriately combined and used with the configurations, methods, etc. shown in other embodiments.

[0129] (Embodiment 2) In this embodiment, the configuration of a semiconductor device according to an aspect of the disclosed invention and a method for manufacturing the same will be described with reference to FIGS. 9 to 13.

[0130] <Cross-sectional configuration and planar configuration of semiconductor device> FIG. 9 shows an example of the configuration of a semiconductor device. FIG. 9(A) shows a cross-section of the semiconductor device, and FIG. 9(B) shows a plan view of the semiconductor device. Here, FIG. 9(A) corresponds to the cross-sections at A1 - A2 and B1 - B2 in FIG. 9(B). The semiconductor device shown in FIGS. 9(A) and 9(B) has a transistor 160 using a first semiconductor material at the lower part and a transistor 162 using a second semiconductor material at the upper part. Here, it is desirable that the first semiconductor material and the second semiconductor material are different materials. For example, the first semiconductor material can be a semiconductor material other than an oxide semiconductor (such as silicon), and the second semiconductor material can be an oxide semiconductor. A transistor using a material other than an oxide semiconductor is easy to operate at high speed. On the other hand, a transistor using an oxide semiconductor can hold charges for a long time due to its characteristics.

[0131] ​​​​​​​​​​​​It should be noted that the above transistors are all n-channel transistors. However, it goes without saying that a p-channel transistor can be used. The technical essence of the invention is to develop a semiconductor device that can sufficiently reduce the off-state current, such as an oxide semiconductor, to retain data. The advantage of this is that the transistor 162 is made of a semiconductor material that can be reduced to The specific configuration of the semiconductor device, such as the materials used in the device and the structure of the semiconductor device, is shown here. There is no need to limit it to anything.

[0132] The transistor 160 in FIG. 9 is formed on a substrate 100 including a semiconductor material (e.g., silicon). 00 and a channel forming region 116 provided so as to sandwich the channel forming region 116. A metal compound region 124 in contact with the impurity region 120 and a channel A gate insulating layer 108 is provided on the gate forming region 116, and In the figure, the source electrode and the drain electrode are not explicitly shown. In some cases, the transistor does not have a gate electrode, but for convenience, this state is also referred to as a transistor. In this case, the source region and the drain region are not shown in order to explain the connection relationship of the transistor. The drain region may be referred to as the source electrode or the drain electrode. In the above, the description of the source electrode may include the source region.

[0133] In addition, an element isolation insulating layer 106 is provided on the substrate 100 so as to surround the transistor 160. An insulating layer 128 and an insulating layer 130 are provided to cover the transistor 160. In order to achieve high integration, a transistor 160 is provided as shown in FIG. It is desirable to adopt a configuration without a sidewall insulating layer. On the other hand, when emphasizing the characteristics of the transistor 160 a sidewall insulating layer may be provided on the side surface of the gate electrode 110, and an impurity region 120 including regions with different impurity concentrations may be provided.

[0134] The transistor 162 in FIG. 9 includes a source electrode or a drain electrode 142a provided on the insulating layer 130, and a source electrode or a drain electrode 142b, and an oxide semiconductor layer 144 electrically connected to the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b, a gate insulating layer 146 covering the source electrode or the drain electrode 142a, the source electrode or the drain electrode 142b, and the oxide semiconductor layer 144, and a gate electrode 148a provided so as to overlap the oxide semiconductor layer 144 on the gate insulating layer 146, an insulating layer 143a in a region overlapping the gate electrode 148a between the source electrode or the drain electrode 142a and the oxide semiconductor layer 144, and an insulating layer 143b in a region overlapping the gate electrode 148a between the source electrode or the drain electrode 142b and the oxide semiconductor layer 144. In order to reduce the capacitance between the source electrode or the drain electrode and the gate electrode, it is desirable to provide the insulating layers 143a and 143b, but it is also possible to adopt a configuration without providing the insulating layers 143a and 143b. Note that in order to reduce the capacitance between the source electrode or the drain electrode and the gate electrode, it is desirable to provide the insulating layers 143a and 143b, but it is also possible to adopt a configuration without providing the insulating layers 143a and 143b.

[0135] Here, the oxide semiconductor layer 144 is desirably highly purified by sufficiently removing impurities such as hydrogen and by supplying sufficient oxygen. Specifically, for example, the hydrogen concentration in the oxide semiconductor layer 144 is 5×10 19 atoms / cm 3 ​​​​​​​​​​​​​ Hereinafter, preferably 5×10 18 atoms / cm 3 Hereinafter, more preferably 5×10 17 a toms / cm 3 shall be as follows. The hydrogen concentration in the above-described oxide semiconductor layer 144 is measured by secondary ion mass spectrometry (SIMS). In this way, in the oxide semiconductor layer 144 in which the hydrogen concentration is sufficiently reduced to high purity and the defect levels in the energy gap caused by oxygen deficiency are reduced by sufficient supply of oxygen, the carrier concentration is less than 1×10 / cm and preferably less than 1×10 / cm and more preferably less than 1.45×10 12 / cm 3 . For example, the off-current (here, the value per unit channel width (1 μm)) at room temperature (25°C) is 100 zA (1 zA (zeptoampere) is 1×10 A) or less, preferably 10 zA or less. In this way, by using an i-type (intrinsic) or substantially i-type oxide semiconductor, a transistor 162 with extremely excellent off-current characteristics can be obtained. 11 / cm 3 10 3 / cm 3 . That is, for the transistor 162 in FIG. 9, in order to suppress the leakage generated between elements due to miniaturization, an oxide semiconductor layer 144 processed into an island shape is used, but a configuration that is not processed into an island shape may also be adopted. When the oxide semiconductor layer is not processed into an island shape, contamination of the oxide semiconductor layer 144 due to etching during processing can be prevented. A) or less, preferably 10 zA or less. In this way, by using an i-type (intrinsic) or substantially i-type oxide semiconductor, a transistor 162 with extremely excellent off-current characteristics can be obtained. -21 A) or less, preferably 10 zA or less. In this way, by using an i-type (intrinsic) or substantially i-type oxide semiconductor, a transistor 162 with extremely excellent off-current characteristics can be obtained.

[0136]

[0137] ​​​​​​​The capacitive element 164 in FIG. 9 is composed of a source electrode or a drain electrode 142a, an oxide semiconductor layer 144, a gate insulating layer 146, and an electrode 148b. That is, the source electrode or the drain electrode 142a functions as one electrode of the capacitive element 164, and the electrode 1 48b functions as the other electrode of the capacitive element 164.

[0138] In the capacitive element 164 of FIG. 9, by laminating the oxide semiconductor layer 144 and the gate insulating layer 146, sufficient insulation between the source electrode or the drain electrode 142a and the electrode 148b can be ensured. Of course, in order to ensure sufficient capacitance, a capacitive element 164 having a configuration without the oxide semiconductor layer 144 may be adopted. Also, a capacitive element 164 having a configuration with an insulating layer formed in the same manner as the insulating layer 143a may be adopted. Furthermore, when capacitance is not required, it is also possible to adopt a configuration in which the capacitive element 164 is not provided. In addition, in the transistor 162 and the capacitive element 164, the ends of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are preferably tapered. By tapering the ends of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b, the coverage of the oxide semiconductor layer 144 can be improved and step discontinuities can be prevented. Here, the taper angle is, for example, 3 0° or more and 60° or less. Note that the taper angle refers to the inclination angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) when observed from a direction perpendicular to the cross-section (a plane perpendicular to the surface of the substrate). In addition, in the transistor 162 and the capacitive element 164, the ends of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b are preferably tapered. By tapering the ends of the source electrode or the drain electrode 142a and the source electrode or the drain electrode 142b, the coverage of the oxide semiconductor layer 144 can be improved and step discontinuities can be prevented. Here, the taper angle is, for example, 3

[0139] 0° or more and 60° or less. Note that the taper angle refers to the inclination angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) when observed from a direction perpendicular to the cross-section (a plane perpendicular to the surface of the substrate). 0° or more and 60° or less. Note that the taper angle refers to the inclination angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) when observed from a direction perpendicular to the cross-section (a plane perpendicular to the surface of the substrate). 0° or more and 60° or less. Note that the taper angle refers to the inclination angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) when observed from a direction perpendicular to the cross-section (a plane perpendicular to the surface of the substrate). 0° or more and 60° or less. Note that the taper angle refers to the inclination angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) when observed from a direction perpendicular to the cross-section (a plane perpendicular to the surface of the substrate). 0° or more and 60° or less. Note that the taper angle refers to the inclination angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) when observed from a direction perpendicular to the cross-section (a plane perpendicular to the surface of the substrate). 0° or more and 60° or less. Note that the taper angle refers to the inclination angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) when observed from a direction perpendicular to the cross-section (a plane perpendicular to the surface of the substrate). 0° or more and 60° or less. Note that the taper angle refers to the inclination angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) when observed from a direction perpendicular to the cross-section (a plane perpendicular to the surface of the substrate). 0° or more and 60° or less. Note that the taper angle refers to the inclination angle formed by the side surface and the bottom surface of a layer having a tapered shape (for example, the source electrode or the drain electrode 142a) when observed from a direction perpendicular to the cross-section (a plane perpendicular to the surface of the substrate).

[0140] In this embodiment, the transistor 162 and the capacitor 164 are the same as the transistor 160. By adopting such a planar layout, For example, if the minimum processing dimension is F and the area occupied by the memory cell is 15 F 2 ~25F 2 It is possible to make the following:

[0141] An insulating layer 150 is provided over the transistor 162 and the capacitor 164. An insulating layer 152 is provided on the edge layer 150. The gate insulating layer 146 and the insulating layer An electrode 154 is provided in an opening formed in the insulating layer 152, etc. On the top of the electrode 154, a wiring 156 is formed to connect to the electrode 154. The source electrode or drain electrode 142b is connected to the wiring 156. For example, the present invention is not limited to this. The wiring 156 may be directly connected to the source electrode or the metal compound region 124. may be in contact with the drain electrode 142b.

[0142] <Method for Manufacturing Semiconductor Device> Next, an example of a method for manufacturing the above semiconductor device will be described. A method for fabricating the transistor 160 will be described with reference to FIGS. 10 and 11. A method for manufacturing the transistor 162 and the capacitor 164 will be described with reference to FIGS. Please refer to the following for explanation.

[0143] <Method of manufacturing the lower transistor> First, a substrate 100 containing a semiconductor material is prepared (see FIG. 10(A)). The substrate 100 may be a single crystal semiconductor substrate such as silicon or silicon carbide, or a polycrystalline semiconductor substrate. The substrates can be used for semiconductor devices such as silicon germanium, compound semiconductor substrates, and SOI substrates. In this embodiment, a single crystal silicon substrate is used as the substrate 100 containing a semiconductor material. In general, an "SOI substrate" is a substrate that has silicon on an insulating surface. The term "substrate" refers to a substrate having a semiconductor layer formed thereon. In this specification, however, the term "substrate" refers to a substrate having a silicon layer formed on an insulating surface. The term "substrate" is used to include a substrate having a semiconductor layer made of a material other than silicon. The semiconductor layer of the "SOI substrate" is not limited to a silicon semiconductor layer. The substrate is a structure in which a semiconductor layer is provided on an insulating substrate such as a glass substrate via an insulating layer. This includes the following:

[0144] In particular, when a single crystal semiconductor substrate such as silicon is used as the substrate 100 containing a semiconductor material, In this case, it is preferable because the read operation of the semiconductor device can be performed at a high speed.

[0145] A protective layer 102 is formed on the substrate 100 to serve as a mask for forming an element isolation insulating layer. (See FIG. 10A.) The protective layer 102 is made of, for example, silicon oxide or silicon nitride. For example, an insulating layer made of silicon oxynitride or the like can be used. In order to control the threshold voltage of a transistor, impurities that give n-type conductivity are used. The substrate 100 may be doped with an impurity element that imparts p-type conductivity or an impurity element that imparts p-type conductivity. In the case of silicon, impurities that give n-type conductivity are, for example, phosphorus or arsenic. In addition, examples of impurities that impart p-type conductivity include boron and aluminum. For example, nium, gallium, etc. can be used.

[0146] Next, using the above protective layer 102 as a mask, etching is performed to remove a part of the substrate 100 in the region not covered by the protective layer 102 (the exposed region). As a result, a semiconductor region 104 separated from other semiconductor regions is formed (see FIG. 10(B)). For this etching, dry etching is preferably used, but wet etching may also be used. The etching gas and etching liquid can be appropriately selected according to the material to be etched. Next, an insulating layer is formed so as to cover the semiconductor region 104, and the insulating layer in the region overlapping the semiconductor region 104 is selectively removed to form an element isolation insulating layer 106 (see FIG. 10(C)). The insulating layer is formed using silicon oxide, silicon nitride, silicon oxynitride, or the like. As a method for removing the insulating layer, there are polishing processes such as CMP (chemical mechanical polishing) and etching processes, and any of them may be used. Note that after the formation of the semiconductor region 104 or after the formation of the element isolation insulating layer 106, the above protective layer 102 is removed. Next, an insulating layer is formed on the surface of the semiconductor region 104, and a layer containing a conductive material is formed on the insulating layer. The insulating layer will be the subsequent gate insulating layer and can be formed, for example, by heat treatment (thermal oxidation treatment, thermal nitridation treatment, etc.) on the surface of the semiconductor region 104. Instead of heat treatment, high-density plasma treatment may be applied. High-density plasma treatment uses, for example, noble gases such as helium (He), argon (Ar), krypton (Kr), xenon (Xe), oxygen, nitrogen oxide

[0147]

[0148]

[0149] ​​​​​​​​​​​​​​can be carried out using a mixed gas such as ammonia, nitrogen, and hydrogen. Of course, an insulating layer may be formed using a CVD method, a sputtering method, or the like. The insulating layer may be silicon oxide , silicon oxynitride, silicon nitride, hafnium oxide, aluminum oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSi x O y (x>0, y>0)), hafnium silicate (HfSi with nitrogen added x O y N z (x>0, y>0, z>0)) , hafnium aluminate with nitrogen added (HfAl x O y N z (x>0, y>0, z >0)), etc., and it is desirable to form a single-layer structure or a laminated structure. The thickness of the insulating layer is , for example, 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less can be achieved.

[0150] The layer containing the conductive material can be formed using a metal material such as aluminum, copper, titanium, tantalum, tungsten, etc. Further, a layer containing a conductive material may be formed using a semiconductor material such as polycrystalline silicon. The forming method is not particularly limited, and various film-forming methods such as an evaporation method, a CVD method, a sputtering method, and a spin coating method can be used. In this embodiment form, an example of forming a layer containing a conductive material using a metal material is shown as follows.

[0151] Thereafter, the insulating layer and the layer containing the conductive material are selectively etched to form the gate insulating layer 108 and the gate electrode 110 (see Fig. 10(C)).

[0152] Next, phosphorus (P), arsenic (As), or the like is added to the semiconductor region 104 to form the channel formation region 116 and the impurity region 120 (see Fig. 10(D)). Here, phosphorus or arsenic is added to form an n-type transistor. However, in the case of forming a p-type transistor, impurity elements such as boron (B) or aluminum (Al) may be added. Here, the concentration of the added impurity can be set as appropriate. However, when the semiconductor element is highly miniaturized, it is desirable to increase the concentration.

[0153] Note that a sidewall insulating layer may be formed around the gate electrode 110 to form impurity regions added with different concentrations of impurity elements.

[0154] Next, a metal layer 122 is formed so as to cover the gate electrode 110, the impurity region 120, etc. (see Fig. 11(A)). The metal layer 122 can be formed using various film formation methods such as vacuum evaporation, sputtering, and spin coating. The metal layer 122 is preferably formed using a metal material that reacts with the semiconductor material constituting the semiconductor region 104 to become a low- resistance metal compound. Examples of such a metal material include titanium, tantalum, tungsten, nickel, cobalt, platinum, etc.

[0155] Next, heat treatment is performed to react the metal layer 122 with the semiconductor material. As a result, a metal compound region 124 in contact with the impurity region 120 is formed (see Fig. 11(A)). Note that when polycrystalline silicon or the like is used as the gate electrode 110, a metal compound region is also formed in the portion of the gate electrode 110 in contact with the metal layer 122.

[0156] ​As the above heat treatment, for example, heat treatment by irradiation with a flash lamp can be used. Of course, other heat treatment methods may be used, but in order to improve the controllability of the chemical reaction related to the formation of the metal compound, it is desirable to use a method that can achieve heat treatment for a very short time. The above metal compound region is formed by the reaction between the metal material and the semiconductor material, and is a region with sufficiently enhanced conductivity. By forming the metal compound region, the electrical resistance can be sufficiently reduced and the element characteristics can be improved. After forming the metal compound region 124, the metal layer 122 is removed.

[0157] Next, an insulating layer 128 and an insulating layer 130 are formed so as to cover each component formed by the above-described process (see Fig. 11(B)). The insulating layer 128 and the insulating layer 130 can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, or aluminum oxide. In particular, by using a material with a low dielectric constant (low-k) for the insulating layer 128 and the insulating layer 130, it is possible to sufficiently reduce the capacitance caused by the overlap of various electrodes and wirings, which is preferable. Note that a porous insulating layer using these materials may be applied to the insulating layer 128 and the insulating layer 130. In a porous insulating layer, the dielectric constant is lower than that of a dense insulating layer, so it is possible to further reduce the capacitance caused by electrodes and wirings. In addition, the insulating layer 128 and the insulating layer 130 can also be formed using an organic insulating material such as polyimide or acrylic. Here, a laminated structure of the insulating layer 128 and the insulating layer 130 is shown, but one aspect of the disclosed invention is not limited to this. It may be a single layer or a laminated structure of three or more layers.

[0158] ​​​ As described above, a transistor 160 using a substrate 100 including a semiconductor material is formed (see Fig. 11(B)). Such a transistor 160 is characterized by being capable of high-speed operation. Therefore, by using this transistor as a read transistor, information can be read out at high speed.

[0159] Thereafter, as a process before forming the transistor 162 and the capacitor element 164, a CMP process is performed on the insulating layer 128 and the insulating layer 130 to expose the upper surface of the gate electrode 110 (see Fig. 11( C)). As a process for exposing the upper surface of the gate electrode 110, in addition to the CMP process, etching processing or the like can also be applied. However, in order to improve the characteristics of the transistor 162, it is desirable to make the surfaces of the insulating layer 128 and the insulating layer 130 as flat as possible. .

[0160] Note that before and after each of the above steps, processes for forming electrodes, wirings, semiconductor layers, insulating layers, etc. may be further included. For example, as a wiring structure, a multilayer wiring structure formed by laminating an insulating layer and a conductive layer can be adopted to realize a highly integrated semiconductor device. For example, it is also possible to adopt a multilayer wiring structure formed by laminating an insulating layer and a conductive layer as a wiring structure to realize a highly integrated semiconductor device.

[0161] <Method for fabricating upper transistor> Next, a conductive layer is formed on the gate electrode 110, the insulating layer 128, the insulating layer 130, etc., and the conductive layer is selectively etched to form a source electrode or drain electrode 142a, a source electrode or drain electrode 142b (see Fig. 12(A)).

[0162] The conductive layer can be formed by a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. It can be formed by... Also, as the material of the conductive layer, elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum, tungsten, or alloys having the above-described elements as components can be used. Any one of manganese, magnesium, zirconium, beryllium, neodymium, scandium, or a material obtained by combining a plurality of these can also be used.

[0163] The conductive layer may have a single-layer structure or a laminated structure of two or more layers. For example, a single-layer structure of a titanium film or a titanium nitride film, a single-layer structure of an aluminum film containing silicon, a two-layer structure in which a titanium film is laminated on an aluminum film, a two-layer structure in which a titanium film is laminated on a titanium nitride film, a three-layer structure in which a titanium film, an aluminum film, and a titanium film are laminated, etc. can be mentioned. In addition, when the conductive layer has a single-layer structure of a titanium film or a titanium nitride film, there is an advantage that it is easy to process into the source electrode or drain electrode 142a having a tapered shape, and the source electrode or drain electrode 142 b. Further, the conductive layer may be formed using a conductive metal oxide. Examples of the conductive metal oxide include indium oxide (In O ), tin oxide (SnO ), zinc oxide (ZnO), indium tin oxide alloy (In

[0164] O -SnO 2 3 2 ), indium zinc oxide alloy (In O 2 3 -ZnO), or a material obtained by adding silicon or silicon oxide to these metal oxide materials can be used. 2 (sometimes abbreviated as ITO), indium zinc oxide alloy (In O 2 3 -ZnO), or a material obtained by adding silicon or silicon oxide to these metal oxide materials can be used.

[0165] ​​​​​​ Etching of the conductive layer is preferably performed so that the ends of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b to be formed have a tapered shape. Here, the taper angle is preferably, for example, 30° or more and 60° or less. By etching the ends of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b so as to have a tapered shape, the coverage of the gate insulating layer 146 formed later can be improved, and step discontinuities can be prevented.

[0166] The channel length (L) of the upper transistor is determined by the distance between the lower ends of the source electrode or drain electrode 142a and the source electrode or drain electrode 142b. When forming a mask for exposure used to form a transistor with a channel length (L) of less than 25 nm, it is desirable to use extreme ultraviolet light with a short wavelength of several nm to several tens of nm. Exposure with extreme ultraviolet light has high resolution and a large depth of focus. Therefore, it is also possible to set the channel length (L) of the transistor formed later to be 10 nm or more and 1 000 nm (1 μm) or less, and it is possible to increase the operating speed of the circuit. Also, by miniaturization, it is possible to reduce the power consumption of the semiconductor device.

[0167] Note that an insulating layer that functions as a base may be provided on the insulating layer 128 and the insulating layer 130. The insulating layer can be formed using a method such as PVD or CVD.

[0168] Next, an insulating layer 143a is formed on the source electrode or drain electrode 142a, and a source electrode or ​​​​An insulating layer 143b is formed on each of the drain electrodes 142b (see Fig. 12(B)). . After forming the insulating layer 143a and the insulating layer 143b to cover the source electrode or the drain electrodes 142a and the source electrode or the drain electrode 142b, the insulating layer can be formed by selectively etching the insulating layer . Also, the insulating layer 143a and the insulating layer 143b are formed so as to overlap a part of the gate electrode formed later. By providing such an insulating layer , it is possible to reduce the capacitance between the gate electrode and the source electrode or the drain electrode .

[0169] The insulating layer 143a and the insulating layer 143b can be formed using a material containing an inorganic insulating material such as silicon oxide, silicon oxynitride, silicon nitride, aluminum oxide, etc. In particular, by using a material with a low dielectric constant (low-k) for the insulating layer 143a and the insulating layer 143b , it becomes possible to sufficiently reduce the capacitance between the gate electrode and the source electrode or the drain electrode , which is preferable. Note that a porous insulating layer using these materials may be applied to the insulating layer 143a and the insulating layer 143b. In a porous insulating layer, the dielectric constant is lower than that of a dense insulating layer , so it is possible to further reduce the capacitance between the gate electrode and the source electrode or the drain electrode .

[0170] In terms of reducing the capacitance between the gate electrode and the source electrode or the drain electrode , it is preferable to form the insulating layer 143a and the insulating layer 143b, but it is also possible to adopt a configuration without providing the insulating layer .

[0171] Next, the source electrode or the drain electrode 142a and the source electrode or the drain electrode 1 After forming an oxide semiconductor layer so as to cover 42b, the oxide semiconductor layer is selectively etched to form an oxide semiconductor layer 144 (see FIG. 12(C)).

[0172] The oxide semiconductor layer may be formed using a quaternary metal oxide such as In-Sn-Ga-Zn-O, or a ternary metal oxide such as In-Ga-Zn-O, In-Sn-Zn-O, In-Al-Zn- O, Sn-Ga-Zn-O, Al-Ga-Zn-O, Sn-Al-Zn-O, or a binary metal oxide such as In-Zn-O, In-Ga-O, Sn-Zn-O, Al -Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, or a unary metal oxide such as In-O, Sn-O, Zn-O. Among these, an In-Ga-Zn-O-based oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high field-effect mobility. Therefore, it is suitable as a semiconductor material used in semiconductor devices.

[0173] Among them, an In-Ga-Zn-O-based oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high field-effect mobility. Therefore, it is suitable as a semiconductor material used in semiconductor devices. Among them, an In-Ga-Zn-O-based oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high field-effect mobility. Therefore, it is suitable as a semiconductor material used in semiconductor devices. Among them, an In-Ga-Zn-O-based oxide semiconductor material has a sufficiently high resistance in the absence of an electric field and can sufficiently reduce the off-current, and also has a high field-effect mobility. Therefore, it is suitable as a semiconductor material used in semiconductor devices.

[0174] Typical examples of In-Ga-Zn-O-based oxide semiconductor materials include those represented by InGaO 3 (ZnO) m (m > 0, m: non-natural number). Also, there are oxide semiconductor materials represented as InMO nMO 3 (ZnO) m (m > 0, m: non-natural number) by using M instead of Ga. Here, M represents one metal element or a plurality of metal elements selected from gallium (Ga), aluminum (Al), iron (Fe), nickel (Ni), manganese (Mn), cobalt (Co), etc. For example, as M, Ga, Ga and Al, Ga and Fe, G (Ni), manganese (Mn), cobalt (Co), etc. For example, as M, Ga, Ga and Al, Ga and Fe, G (Ni), manganese (Mn), cobalt (Co), etc. For example, as M, Ga, Ga and Al, Ga and Fe, G It is possible to apply a, Ni, Ga and Mn, Ga and Co, etc. Note that the above The above composition is derived from the crystal structure, and it should be noted that this is only an example.

[0175] As a target for producing the oxide semiconductor layer by sputtering, those having a composition ratio of In:Ga:Zn = 1:x:y (x is 0 or more, y is 0.5 or more and 5 or less) are preferably used. For example, In is suitable. For example, In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:2 [mole ratio] composition ratio, such as a metal oxide target, can be used. Also, In 2 O 3 :Ga 2 O 3 :ZnO = 1:1:1 [mole ratio] composition ratio of a metal oxide target, or I n 2 O 3 :Ga 2 O 3 :ZnO = 1:1:4 [mole ratio] composition ratio of a metal oxide target, or In 2 O 3 :Ga 2 O 3 :ZnO = 1:0:2 [mole ratio] composition ratio of a metal oxide target can also be used.

[0176] In this embodiment, the oxide semiconductor layer having an amorphous structure is formed by a sputtering method using an In-Ga-Zn-O-based metal oxide target.

[0177] The relative density of the metal oxide in the metal oxide target is 80% or more, preferably 95% or more, more preferably 99.9% or more. Using a metal oxide target with a high relative density​ As a result, it is possible to form an oxide semiconductor layer with a dense structure.

[0178] The formation atmosphere of the oxide semiconductor layer is preferably a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a mixed atmosphere of a noble gas (typically argon) and oxygen. Specifically, for example, it is preferable to use a high-purity gas atmosphere in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of 1 ppm or less (desirably 10 ppb or less). or less. Specifically, for example, it is preferable to use a high-purity gas atmosphere in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of 1 ppm or less (desirably 10 ppb or less). Specifically, for example, it is preferable to use a high-purity gas atmosphere in which impurities such as hydrogen, water, hydroxyl groups, and hydrides are removed to a concentration of 1 ppm or less (desirably 10 ppb or less). .

[0179] When forming the oxide semiconductor layer, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 400°C. Alternatively, the temperature of the object to be processed during the formation of the oxide semiconductor layer may be room temperature (25°C ± 10°C). Then, while removing moisture in the processing chamber, a sputtering gas from which hydrogen, water, etc. have been removed is introduced, and the oxide semiconductor layer is formed using the above target. By forming the oxide semiconductor layer while heating the object to be processed, impurities contained in the oxide semiconductor layer can be reduced. Also, damage due to sputtering can be reduced. To remove moisture in the processing chamber, it is preferable to use an adsorption-type vacuum pump. For example, a cryopump, an ion pump, a titanium sublimation pump, etc. can be used. Also, a turbo molecular pump with a cold trap added may be used. By evacuating using a cryopump or the like, hydrogen, water, etc. can be removed from the processing chamber, so that the impurity concentration in the oxide semiconductor layer can be reduced. When forming the oxide semiconductor layer, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 400°C. When forming the oxide semiconductor layer, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 400°C. When forming the oxide semiconductor layer, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 400°C. When forming the oxide semiconductor layer, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 400°C. When forming the oxide semiconductor layer, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 400°C. When forming the oxide semiconductor layer, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 400°C. When forming the oxide semiconductor layer, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 400°C. When forming the oxide semiconductor layer, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 400°C. When forming the oxide semiconductor layer, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 400°C. When forming the oxide semiconductor layer, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 400°C. When forming the oxide semiconductor layer, for example, the object to be processed is held in a processing chamber maintained in a reduced-pressure state, and the object to be processed is heated so that the temperature of the object to be processed is 100°C or higher and lower than 550°C, preferably 200°C or higher and lower than 400°C.

[0180] As the formation conditions of the oxide semiconductor layer, for example, the distance between the object to be processed and the target is 17 0 mm, the pressure is 0.4 Pa, the direct current (DC) power is 0.5 kW, the atmosphere is an oxygen (oxygen 100 %) atmosphere, or an argon (argon 100%) atmosphere, or a mixed atmosphere of oxygen and argon, and the like can be applied. In addition, when using a pulsed direct current (DC) power supply it is preferable because it can reduce the powdery substances (also referred to as particles, dust) generated during film formation and the film thickness distribution becomes uniform. The thickness of the oxide semiconductor layer is 1 nm or more and 50 nm or less, preferably 1 nm or more and 30 nm or less, more preferably 1 nm or more and 10 nm or less. By using an oxide semiconductor layer of such a thickness, it is possible to suppress the short-channel effect associated with miniaturization. However, since the appropriate thickness varies depending on the oxide semiconductor material to be applied and the use of the semiconductor device, etc., the thickness can also be selected according to the material and use, etc. used.

[0181] Before forming the oxide semiconductor layer by sputtering, it is preferable to perform reverse sputtering to generate plasma by introducing argon gas and remove the deposits on the formation surface (for example, the surface of the insulating layer 130). Here, reverse sputtering means a method of modifying the surface by colliding ions with the processing surface, which is the opposite of colliding ions with the sputter target in normal sputtering. As a method of colliding ions with the processing surface there is a method of applying a high-frequency voltage to the processing surface side under an argon atmosphere to generate plasma near the object to be processed. Note that an atmosphere such as nitrogen, helium, or oxygen may be applied instead of the argon atmosphere.

[0182] ​​​​​​​​Thereafter, it is desirable to perform a heat treatment (first heat treatment) on the oxide semiconductor layer. This removes excess hydrogen (including water and hydroxyl groups) in the oxide semiconductor layer by the first heat treatment, arranges the structure of the oxide semiconductor layer, and can reduce the defect levels in the energy gap . The temperature of the first heat treatment is, for example, 300°C or higher and less than 550°C, or 400°C or higher and 50 0°C or lower.

[0183] The heat treatment can be performed, for example, by introducing the object to be treated into an electric furnace using a resistance heating element or the like, in a nitrogen atmosphere, at 450°C for 1 hour. During this time, the oxide semiconductor layer is not exposed to the atmosphere so as to prevent the mixing of water and hydrogen.

[0184] The heat treatment apparatus is not limited to an electric furnace, and an apparatus that heats the object to be treated by heat conduction from a medium such as heated gas or heat radiation may also be used. For example, an RTA (Rapid Thermal Anneal ) apparatus such as an LRTA (Lamp Ra pid Thermal Anneal) apparatus or a GRTA (Gas Rapid The ) apparatus can be used. The LRTA apparatus is an apparatus that heats the object to be treated by the radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps , xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps . The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas. As the gas, noble gases such as argon or inert gases such as nitrogen that do not react with the object to be treated by heat treatment are used. For example, as the first heat treatment, the object to be treated is introduced into a heated inert gas atmosphere and heated for several minutes

[0185] After heat treatment, GRTA treatment may be performed to take out the object to be processed from the inert gas atmosphere. . When GRTA treatment is used, high-temperature heat treatment can be performed in a short time. Also, it can be applied even under temperature conditions exceeding the heat resistance temperature of the object to be processed. During the treatment, the inert gas may be switched to a gas containing oxygen. By performing the first heat treatment in an atmosphere containing oxygen, it is possible to reduce the defect levels in the energy gap caused by oxygen deficiency. .

[0186] Note that as the inert gas atmosphere, an atmosphere mainly composed of nitrogen or a noble gas (helium, neon, argon, etc.) without containing water, hydrogen, etc. is preferably applied. For example, the purity of nitrogen or noble gases such as helium, neon, and argon introduced into the heat treatment apparatus is 6N (99.9999%) or more, preferably 7N (99.99999%) or more ( that is, the impurity concentration is 1 ppm or less, preferably 0.1 ppm or less).

[0187] In any case, by reducing impurities by the first heat treatment and forming an oxide semiconductor layer that is i-type (intrinsic semiconductor) or extremely close to i-type, a transistor with extremely excellent characteristics can be realized.

[0188] By the way, since the above heat treatment (the first heat treatment) has the effect of removing hydrogen, water, etc., this heat treatment can also be called a dehydration treatment, a dehydrogenation treatment, etc. The dehydration treatment and the dehydrogenation treatment can also be performed at timings such as after the formation of the oxide semiconductor layer, after the formation of the gate insulating layer, and after the formation of the gate electrode. Also, such dehydration treatment and dehydrogenation treatment may be performed not only once but also multiple times.

[0189] The oxide semiconductor layer may be etched either before or after the heat treatment. From the viewpoint of miniaturization of elements, it is preferable to use dry etching. However, wet etching may also be used. The etching temperature can be appropriately selected according to the material to be etched. When this does not pose a problem, the oxide semiconductor layer does not need to be processed into an island shape.

[0190] Next, a gate insulating layer 146 is formed in contact with the oxide semiconductor layer 144, and then a gate insulating A gate electrode 148a is formed on the layer 146 in a region overlapping with the oxide semiconductor layer 144. Then, an electrode 148b is formed in a region overlapping with the source or drain electrode 142a (FIG. 12(D)).

[0191] The gate insulating layer 146 can be formed by using a CVD method, a sputtering method, or the like. The gate insulating layer 146 may be made of silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, or the like. tantalum oxide, hafnium oxide, yttrium oxide, gallium oxide, hafnium silicon Cate (HfSi x O y (x>0, y>0)), nitrogen-doped hafnium silicate (HfSi x O y N z (x>0, y>0, z>0)), nitrogen doped hafnium aluminium minate (HfAl x O y N z (x>0, y>0, z>0) The gate insulating layer 146 may have a single layer structure or a stacked layer structure. Good. Also, its thickness is not particularly limited, but when miniaturizing the semiconductor device, it is desirable to make it thin in order to ensure the operation of the transistor. For example, when using silicon oxide, it can be made 1 nm or more and 100 nm or less, preferably 10 nm or more and 50 nm or less. As described above, when the gate insulating layer is made thin, gate leakage caused by the tunneling effect or the like becomes a problem. To solve the problem of gate leakage, it is preferable to use a high-k material such as hafnium oxide, tantalum oxide, yttrium oxide, hafnium silicate (HfSi O (x>0

[0192] , y>0)), hafnium silicate with nitrogen added (HfSi O N x O y (x>0 , y>0, z>0)), hafnium aluminate with nitrogen added (HfAl x O y N z (x>0, y>0, z>0)), etc. for the gate insulating layer 146. By using a high-k material for the gate insulating layer 146, it becomes possible to increase the film thickness in order to suppress gate leakage while ensuring electrical characteristics. Note that a laminated structure of a film containing a high-k material and a film containing any of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, etc. may be used. x O y N z ( x>0, y>0, z>0)), etc. It is good to use. By using a high-k material for the gate insulating layer 146, while ensuring electrical characteristics, it becomes possible to increase the film thickness to suppress gate leakage. In addition, a laminated structure of a film containing a high-k material and a film containing any of silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, aluminum oxide, etc. may be used. After forming the gate insulating layer 146, it is desirable to perform a second heat treatment in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200°C or more and 450°C or less, preferably 25 0°C or more and 350°C or less. For example, heat treatment can be performed at 250°C for 1 hour in a nitrogen atmosphere. After the formation of the gate insulating layer 146, it is desirable to perform a second heat treatment in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200 °C or higher and 450 °C or lower, preferably 25 0 °C or higher and 350 °C or lower. For example, heat treatment can be performed at 250 °C for 1 hour in a nitrogen atmosphere.

[0193] After forming the gate insulating layer 146, it is desirable to perform a second heat treatment in an inert gas atmosphere or an oxygen atmosphere. The temperature of the heat treatment is 200 °C or higher and 450 °C or lower, preferably 25 0 °C or higher and 350 °C or lower. For example, heat treatment can be performed at 250 °C for 1 hour in a nitrogen atmosphere. 0 °C or higher and 350 °C or lower. For example, heat treatment can be performed at 250 °C for 1 hour in a nitrogen atmosphere. is sufficient. By performing the second heat treatment, variations in the electrical characteristics of the transistor can be reduced. This can be achieved. Further, when the gate insulating layer 146 contains oxygen, oxygen can be supplied to the oxide semiconductor layer 144 to compensate for the oxygen deficiency in the oxide semiconductor layer 144 and form an oxide semiconductor layer 144 that is of the i-type (intrinsic semiconductor) or is as close as possible to the i-type.

[0194] Note that in this embodiment, the second heat treatment is performed after the formation of the gate insulating layer 146. However, the timing of the second heat treatment is not limited to this. For example, the second heat treatment may be performed after the formation of the gate electrode. Also, the second heat treatment may be performed following the first heat treatment, or the second heat treatment may be combined with the first heat treatment, or the first heat treatment may be combined with the second heat treatment.

[0195] As described above, by applying at least one of the first heat treatment and the second heat treatment, the oxide semiconductor layer 144 can be purified to a high purity such that it contains as few impurities as possible other than its main components.

[0196] The gate electrode 148a and the electrode 148b can be formed by forming a conductive layer on the gate insulating layer 146 and then selectively etching the conductive layer. The conductive layer that becomes the gate electrode 148a and the electrode 148b can be formed using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method. Details are the same as in the case of the source electrode or the drain electrode 142a, etc., and these descriptions can be referred to.

[0197] Next, an insulating layer 15 is formed on the gate insulating layer 146, the gate electrode 148a, and the electrode 148b. ​​​​​0 and an insulating layer 152 are formed (see Fig. 13(A)). The insulating layer 150 and the insulating layer 15 2 can be formed using a PVD method, a CVD method, or the like. In addition, inorganic insulating materials such as silicon oxide, acid silicon nitride, silicon nitride, hafnium oxide, and aluminum oxide are included and can be formed using a material.

[0198] Note that for the insulating layer 150 and the insulating layer 152, it is desirable to use a material with a low dielectric constant or a structure with a low dielectric constant (such as a porous structure). By lowering the dielectric constant of the insulating layer 150 and the insulating layer 152, the capacitance generated between wirings, electrodes, etc. can be reduced, and the operation speed can be increased for this reason.

[0199] Note that in this embodiment, the insulating layer 150 and the insulating layer 152 have a laminated structure, but one aspect of the disclosed invention is not limited to this. It may be a single layer or a laminated structure of three or more layers as well. In addition, a configuration without an insulating layer is also possible.

[0200] Note that it is desirable to form the insulating layer 152 so that its surface is flat. By forming the insulating layer 152 so that the surface is flat, even when the semiconductor device is miniaturized, etc., electrodes, wirings, etc. can be suitably formed on the insulating layer 152 for this reason. Note that the flattening of the insulating layer 152 can be performed using a method such as CMP (chemical mechanical polishing) can be done.

[0201] Next, an opening reaching the source electrode or the drain electrode 142b is formed in the gate insulating layer 146, the insulating layer 150, and the insulating layer 152 (see Fig. 13(B)). The formation of the opening is performed by selective etching using a mask or the like.

[0202] Thereafter, an electrode 154 is formed in the opening, and a wiring 15 in contact with the electrode 154 is formed on the insulating layer 152. 6 is formed (see FIG. 13(C)).

[0203] The electrode 154 is formed by forming a conductive layer in an area including the opening using, for example, a PVD method or a CVD method. Then, a part of the conductive layer is removed by a method such as etching or CMP. It can be formed by:

[0204] More specifically, for example, a thin titanium film is formed by PVD in the area including the opening, and then CV After forming a thin titanium nitride film by the D method, a tungsten film is formed to fill the opening. Here, the titanium film formed by the PVD method is The oxide film (such as the natural oxide film) on the formation surface is reduced, and the lower electrode (here, the source electrode or It has a function of reducing the contact resistance with the drain electrode 142b. The titanium nitride film has a barrier function that suppresses the diffusion of conductive materials. After forming a barrier film made of titanium nitride or the like, a copper film may be formed by plating.

[0205] When forming an electrode by removing a part of the conductive layer, the surface is made flat. For example, a thin titanium film or titanium nitride film is formed in the area including the opening. If a tungsten film is then formed to fill the opening, the subsequent CMP process By this process, unnecessary tungsten, titanium, titanium nitride, etc. are removed and the surface In this way, the flatness of the surface including the electrode 154 can be improved. As a result, good electrodes, wiring, insulating layers, semiconductor layers, etc. can be formed in the subsequent steps. becomes possible.

[0206] The wiring 156 is formed by forming a conductive layer using a PVD method such as a sputtering method or a CVD method such as a plasma CVD method and then patterning the conductive layer. In addition, as the material of the conductive layer, elements selected from aluminum, chromium, copper, tantalum, titanium, molybdenum tungsten, or alloys containing the above-described elements as components can be used. Materials containing any one of manganese, magnesium, zirconium, beryllium, neodymium, scandium or a combination of a plurality of these may be used. Details are the same as those of the source electrode or the drain electrode 142a or the like.

[0207] As described above, the transistor 162 using the highly purified oxide semiconductor layer 144 and the capacitor element 164 are completed (see FIG. 13(C)).

[0208] In the transistor 162 shown in this embodiment, since the oxide semiconductor layer 144 is highly purified its hydrogen concentration is 5×10 19 atoms / cm 3 or less, desirably 5× 10 18 atoms / cm 3 or less, more desirably 5×10 17 atoms / cm 3 or less. In addition, the carrier density of the oxide semiconductor layer 144 is sufficiently smaller than the carrier density (about 1×10 / cm 14 / cm 3 in a general silicon wafer) (for example, less than 1 ×10 12 / cm 3 , more preferably less than 1.45×10 10 / cm 3 ). Then, the off-current of the transistor 162 also becomes sufficiently small. For example, the transistor 16 The off-current of 2 at room temperature (25 °C) (here, the value per unit channel width (1 μm)) is 100 zA (1 zA (zeptoampere) is 1 × 10 -21 A) or less, desirably 10 zA or less.

[0209] By using the highly purified and crystallized oxide semiconductor layer 144 in this way, it becomes easy to sufficiently reduce the off-current of the transistor. And by using such a transistor, a semiconductor device capable of retaining the stored content for an extremely long time can be obtained.

[0210] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with those shown in other embodiments.

[0211] (Embodiment 3) In this embodiment, a semiconductor device having a configuration different from that in FIGS. 2 and 5 will be described with reference to FIGS. 25 to 27.

[0212] FIG. 25(A) is an example of a circuit diagram of a semiconductor device having (m × n) memory cells 170. Since the configuration of the memory cell 170 in FIG. 25(A) is the same as that in FIG. 2(B), a detailed description thereof will be omitted.

[0213] The semiconductor device shown in FIG. 25(A) has substantially the same configuration as the semiconductor device shown in FIG. 2(A). The difference between the semiconductor device shown in FIG. 2(A) and the semiconductor device shown in FIG. 25(A) lies in whether or not a wiring 195 electrically connected to the bit line BL is provided. That is, in FIG. 25( The semiconductor device shown in (A) has a wiring 195 electrically connected to a bit line BL. The said wiring 195 has a function of keeping the potential of the bit line applied to the memory cell at an appropriate value. In a configuration where a large number of memory cells are connected in series as in the disclosed invention, reading information may become difficult due to voltage drops in the memory cells.

[0214] For example, taking a configuration in which 64 memory cells are connected in series as a unit, the wiring 195 is connected to each unit so that an appropriate potential is applied to each unit. Thereby, even in a configuration having a large number of memory cells, information can be read suitably. Note that the number of memory cells included in each unit is not limited to 64. It can be set as appropriate within a range that does not affect the read operation, such as 32, 128, etc.

[0215] FIG. 26 shows an example of the configuration of the semiconductor device shown in FIG. 25. FIG. 26(A) shows a cross section of the semiconductor device, and FIG. 26(B) shows a plan view of the semiconductor device. Here, FIG. 26(A) corresponds to the cross section taken along C1 - C2 and D1 - D2 in FIG. 26(B). A characteristic point in the configuration shown in FIG. 26 is that, in addition to the wiring 156b electrically connected to the source electrode or drain electrode 142a, it has a wiring 156a. The said wiring 156a corresponds to the wiring 195 electrically connected to the bit line BL in FIG. 25. Note that, although not explicitly shown in FIG. 26(B), the wiring 156a and the wiring 156b exist in a form extending in the vertical direction of FIG. 26(B) parallel to each other.

[0216] The operation of the above semiconductor device is the same as that in the case of FIG. 2(A). For details, refer to the previous embodiment Refer to the corresponding description of the form.

[0217] Even when adopting the configurations of FIGS. 2(A) and 5(A), similar effects can be obtained by using the signal line S instead of the above wiring. In this case, for example, as shown in FIG. 27, after electrically connecting the bit line BL and the signal line S, a switch 231 for controlling the connection between the bit line BL and the signal line S and the output terminal OUT, and a switch 232 for controlling the connection between the bit line BL and the signal line S and the input terminal IN, and a wiring SW can be adopted. In this case, by using the signal supplied to the wiring SW, the switch 231 can be turned on during reading, and the switch 232 can be turned on during writing. Note that the signal supplied to the wiring SW is generated by the signal generation circuit 233 based on the signals from the wirings WRITE and READ. When adopting such a configuration, since it is not necessary to provide the wiring 195 shown in FIG. 25, it is possible to further increase the integration degree of the semiconductor device while maintaining a suitable reading operation. After electrically connecting the bit line BL and the signal line S, a switch 231 for controlling the connection between the bit line BL and the signal line S and the output terminal OUT, and a switch 232 for controlling the connection between the bit line BL and the signal line S and the input terminal IN, and a wiring SW can be adopted. After electrically connecting the bit line BL and the signal line S, a switch 231 for controlling the connection between the bit line BL and the signal line S and the output terminal OUT, and a switch 232 for controlling the connection between the bit line BL and the signal line S and the input terminal IN, and a wiring SW can be adopted. After electrically connecting the bit line BL and the signal line S, a switch 231 for controlling the connection between the bit line BL and the signal line S and the output terminal OUT, and a switch 232 for controlling the connection between the bit line BL and the signal line S and the input terminal IN, and a wiring SW can be adopted. In this case, by using the signal supplied to the wiring SW, the switch 231 can be turned on during reading, and the switch 232 can be turned on during writing. Note that the signal supplied to the wiring SW is generated by the signal generation circuit 233 based on the signals from the wirings WRITE and READ. When adopting such a configuration, since it is not necessary to provide the wiring 195 shown in FIG. 25, it is possible to further increase the integration degree of the semiconductor device while maintaining a suitable reading operation. In this case, by using the signal supplied to the wiring SW, the switch 231 can be turned on during reading, and the switch 232 can be turned on during writing. In this case, by using the signal supplied to the wiring SW, the switch 231 can be turned on during reading, and the switch 232 can be turned on during writing. Note that the signal supplied to the wiring SW is generated by the signal generation circuit 233 based on the signals from the wirings WRITE and READ. When adopting such a configuration, since it is not necessary to provide the wiring 195 shown in FIG. 25, it is possible to further increase the integration degree of the semiconductor device while maintaining a suitable reading operation. In this case, by using the signal supplied to the wiring SW, the switch 231 can be turned on during reading, and the switch 232 can be turned on during writing. Note that the signal supplied to the wiring SW is generated by the signal generation circuit 233 based on the signals from the wirings WRITE and READ. When adopting such a configuration, since it is not necessary to provide the wiring 195 shown in FIG. 25, it is possible to further increase the integration degree of the semiconductor device while maintaining a suitable reading operation. In this case, since it is not necessary to provide the wiring 195 shown in FIG. 25, it is possible to further increase the integration degree of the semiconductor device while maintaining a suitable reading operation. In this case, since it is not necessary to provide the wiring 195 shown in FIG. 25, it is possible to further increase the integration degree of the semiconductor device while maintaining a suitable reading operation.

[0218] In addition, other configurations in FIG. 27 are the same as those in FIG. 23. For details, refer to the description of FIG. 23. In addition, other configurations in FIG. 27 are the same as those in FIG. 23. For details, refer to the description of FIG. 23.

[0219] The configuration shown in this embodiment is a modification of the semiconductor device shown in FIG. 2(A), but it can also be a modification of the semiconductor device shown in FIG. 5(A). The configuration shown in this embodiment is a modification of the semiconductor device shown in FIG. 2(A), but it can also be a modification of the semiconductor device shown in FIG. 5(A).

[0220] As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments. As described above, the configurations, methods, etc. shown in this embodiment can be used in appropriate combination with the configurations, methods, etc. shown in other embodiments.

[0221] (Embodiment 4) In this embodiment, when applying the semiconductor device described in the above embodiment to an electronic device, it will be described with reference to FIG. 14. In this embodiment, when applying the above semiconductor device to an electronic device such as a computer, a mobile phone (also referred to as a cellular phone or a mobile phone device), a portable information terminal (including a portable game machine, an audio playback device, etc.), a digital camera, a digital video camera, an electronic paper, a television device (also referred to as a TV or a television receiver), etc., it will be described. FIG. 14(A) shows a notebook personal computer, which is composed of a housing 701, a housing 702, a display unit 703, a keyboard 704, etc. At least one of the housing 701 and the housing 702 is provided with the semiconductor device shown in the previous embodiment. Therefore, a notebook personal computer with high-speed information writing and reading, long-term memory retention, and sufficiently reduced power consumption is realized.

[0222] FIG. 14(B) shows a portable information terminal (PDA). The main body 711 is provided with a display unit 713, an external interface 715, operation buttons 714, etc. It also includes a stylus 712 for operating the portable information terminal. Inside the main body 711, the semiconductor device shown in the previous embodiment is provided. Therefore, a portable information terminal with high-speed information writing and reading, long-term memory retention, and sufficiently reduced power consumption is realized.

[0223]

[0224] FIG. 14(C) shows an electronic book 720 equipped with an electronic paper, which is composed of two housings, a housing 721 and a housing 723. The housing 721 and the housing 723 are respectively provided with a display unit 7 ​​​​​​​​​​​​ 25 and a display unit 727 are provided. The housing 721 and the housing 723 are connected by a shaft portion 737 and can perform an opening / closing operation around the shaft portion 737. Further, the housing 7 21 is provided with a power supply 731, operation keys 733, a speaker 735, etc. At least one of the housing 721 and the housing 723 is provided with the semiconductor device shown in the previous embodiment. Therefore, an electronic book in which information can be written and read at high speed, long-term memory retention is possible, and power consumption is sufficiently reduced is realized.

[0225] FIG. 14(D) shows a mobile phone, which is composed of two housings, a housing 740 and a housing 741. Furthermore, the housing 740 and the housing 741 can be slid and changed from the state of being unfolded as shown in FIG. 14(D) to a state of overlapping each other, enabling miniaturization suitable for carrying. Also, the housing 741 is provided with a display panel 742, a speaker 743, a microphone 744, operation keys 745, a pointing device 746, a camera lens 747, an external connection terminal 74 8, etc. The housing 740 is provided with a solar cell 749 for charging the mobile phone , an external memory slot 750, etc. The antenna is built in the housing 741. At least one of the housing 740 and the housing 741 is provided with the semiconductor device shown in the previous embodiment. Therefore, a mobile phone in which information can be written and read at high speed, long-term memory retention is possible, and power consumption is sufficiently reduced is realized.

[0226] FIG. 14(E) shows a digital camera, which is composed of a main body 761, a display unit 767, an eyepiece portion 763, an operation switch 764, a display unit 765, a battery 766, etc. The main body Inside 761, the semiconductor device shown in the previous embodiment is provided. Therefore, writing and reading of information are fast, long-term memory retention is possible, and a digital camera with sufficiently reduced power consumption is realized.

[0227] FIG. 14(F) shows a television device 770, which is composed of a housing 771, a display unit 773, a stand 775, etc. The operation of the television device 770 can be performed by switches provided in the housing 771 or a remote control operation unit 780. In the housing 771 and the remote control operation unit 780, the semiconductor device shown in the previous embodiment is mounted. Therefore, writing and reading of information are fast, long-term memory retention is possible, and a television device with sufficiently reduced power consumption is realized.

[0228] As described above, in the electronic device shown in this embodiment, the semiconductor device according to the previous embodiment is mounted Thereby, an electronic device with reduced power consumption is realized.

Example

[0229] In this example, the results of obtaining the off-current of a transistor using a highly purified oxide semiconductor will be described.

[0230] First, considering that the off-current of a transistor using a highly purified oxide semiconductor is sufficiently small, a transistor with a channel width W of 1 m, which is sufficiently large, was prepared and the off-current was measured. The results of measuring the off-current of a transistor with a channel width W of 1 m are shown in FIG. 15. In FIG. 15, the horizontal axis is the gate voltage VG, and the vertical axis is the drain current ID. When the drain voltage VD is +1 V or +10 V, in the range where the gate voltage VG is from -5 V to -20 V ​ The off-current of the transistor is found to be 1×10 -12 A or less, which is the detection limit. Also, the off-current of the transistor (here, the value per unit channel width (1 μm)) is found to be 1 aA / μm (1×10 -18 A / μm) or less.

[0231] Next, the results of more accurately obtaining the off-current of the transistor using the highly purified oxide semiconductor will be described. As described above, the off-current of the transistor using the highly purified oxide semiconductor is found to be 1×10 A or less, which is the detection limit of the measuring instrument. -12 Therefore, the results of fabricating a device for characteristic evaluation and obtaining a more accurate off-current value (a value below the detection limit of the measuring instrument in the above measurement) will be described. First, the device for characteristic evaluation used in the current measurement method will be described with reference to FIG. 16.

[0232] First, the device for characteristic evaluation used in the current measurement method will be described with reference to FIG. 16.

[0233] In the device for characteristic evaluation shown in FIG. 16, three measurement systems 800 are connected in parallel. The measurement system 80 0 includes a capacitor element 802, transistors 804, 805, 806 , and a transistor 808. Transistors 804, 805, 806 and transistor 808 are applied with transistors using the highly purified oxide semiconductor.

[0234] In the measurement system 800, one of the source terminal and the drain terminal of the transistor 804, one of the terminals of the capacitor element 802, and one of the source terminal and the drain terminal of the transistor 805 are connected to a power supply (the power supply that supplies V2). Also, the source ​​the other of the source and drain terminals of the transistor 808 One of the terminals of the capacitor 802, the other terminal of the capacitor 802, and the gate terminal of the transistor 805 are connected to each other. The other of the source terminal and the drain terminal of the transistor 808 is connected to One of the source terminal and the drain terminal of the transistor 806 and the gate of the transistor 806 The output terminal of the transistor 805 is connected to a power supply (the power supply that provides V1). the other of the source and drain terminals of the transistor 806 The other terminal is connected and serves as an output terminal.

[0235] The gate terminal of the transistor 804 is connected to a resistor R1, R2, and R3. A potential Vext_b2 for controlling the state of the transistor 808 is supplied to the gate terminal of the transistor 808. A potential Vext_b1 is supplied to control the on and off states of the transistor 808. Moreover, the potential Vout is output from the output terminal.

[0236] Next, a current measuring method using the above-mentioned characteristic evaluation element will be described.

[0237] First, an overview of the initialization period during which a potential difference is applied to measure the off-state current will be given. In the initialization period, a gate terminal of the transistor 808 is connected to the transistor 808. A potential Vext_b1 is input to set the source terminal of the transistor 804 in the ON state. A node connected to the other of the input or drain terminals of the transistor 808 (i.e., the source one of the terminal and the drain terminal of the capacitance element 802, the other terminal of the capacitance element 802, and the transistor 80 A potential V1 is applied to node A, which is the node connected to the gate terminal of transistor 5. Here, The potential V1 is, for example, a high potential. Also, a potential at which the transistor 804 is turned off is applied to Vext_b2, and the transistor 804 is kept in the off state. After that, a potential Vext_b1 for turning off the transistor 808 is input to the gate terminal of the transistor 808 to turn off the transistor 808. After the transistor 808 is turned off, the potential V1 is set to a low potential. Here too, the transistor 804 is kept in the off state. Also, the potential V2 is set to the same potential as V1. Thus, the initialization period ends. In the state where the initialization period has ended, a potential difference occurs between the node A and one of the source terminal and the drain terminal of the transistor 804, and a potential difference also occurs between the node A and the other of the source terminal and the drain terminal of the transistor 808. Therefore, a small amount of charge flows through the transistors 804 and 808. That is, an off-current is generated.

[0238] Next, an outline of the measurement period of the off-current will be described. During the measurement period, the potential of one of the source terminal or the drain terminal of the transistor 804 (that is, V2), and the potential of the other of the source terminal or the drain terminal of the transistor 808 (that is, V1) are fixed at a low potential. On the other hand, during the measurement period, the potential of the above node A is not fixed (in a floating state). As a result, charge flows through the transistor 804, and the amount of charge held in the node A varies with the passage of time. Then, as the amount of charge held in the node A varies, the potential of the node A varies. That is, the output potential Vout of the output terminal also varies.

[0239]

[0240] ​​​​​​​​​​​​​​​​Details of the relationship between each potential during the initialization period for applying the potential difference and the subsequent measurement period (timing chart) are shown in Fig. 17. shown in Fig. 17.

[0241] During the initialization period, first, the potential Vext_b2 is set to a potential (high potential) such that the transistor 804 is in the on state. As a result, the potential of node A becomes V2, that is, a low potential ( VSS). Note that it is not essential to apply a low potential (VSS) to node A. After that VSS). Then, the potential Vext_b2 is set to a potential (low potential) such that the transistor 804 is in the off state, and the transistor 804 is turned off. Next, the potential Vext_b1 is set to a potential (high potential) such that the transistor 808 is in the on state. As a result, the potential of node A becomes V1, that is, a high potential (VDD). Then, Vext_b1 is set to a potential such that the transistor 808 is in the off state. As a result, node A becomes in a floating state, and the initialization period ends. transistor 808 is in the on state. As a result, the potential of node A becomes V1, that is, a high potential (VDD). Then, Vext_b1 is set to a potential such that the transistor 808 is in the off state. As a result, node A becomes in a floating state, and the initialization period ends. transistor 808 is in the off state. As a result, node A becomes in a floating state, and the initialization period ends. transistor 808 is in the off state. As a result, node A becomes in a floating state, and the initialization period ends.

[0242] During the subsequent measurement period, the potentials V1 and V2 are set to potentials such that charge flows into or out of node A. Here, the potentials V1 and V 2 are set to a low potential (VSS). However, at the timing of measuring the output potential Vout, since it is necessary to operate the output circuit, V1 is temporarily set to a high potential (VDD). However, the period during which V1 is set to a high potential (VDD) is set to a short period that does not affect the measurement. However, the period during which V1 is set to a high potential (VDD) is set to a short period that does not affect the measurement. However, the period during which V1 is set to a high potential (VDD) is set to a short period that does not affect the measurement.

[0243] When the potential difference is applied as described above and the measurement period starts, the amount of charge held in node A varies with the passage of time, and accordingly, the potential of node A varies. This is because the transistor When the potential difference is applied as described above and the measurement period starts, the amount of charge held in node A varies with the passage of time, and accordingly, the potential of node A varies. This is because the transistor Since it means that the potential of the gate terminal of the switch 805 fluctuates, the output potential Vout of the output terminal will also change over time.

[0244] A method for calculating the off-current from the obtained output potential Vout will be described below.

[0245] Prior to calculating the off-current, the relationship between the potential V A of node A and the output potential Vout is obtained and set. Thereby, the potential V A of node A can be obtained from the output potential Vout. From the above relationship, the potential V A of node A can be expressed as a function of the output potential Vout as follows:

[0246]

Equation

[0247] Also, the charge Q A of node A is expressed as follows using the potential V A of node A, the capacitance C A connected to node A, and a constant (const). Here, the capacitance C connected to node A is the sum of the capacitance of the capacitor element 802 and other capacitances. A

[0248]

Equation

[0249] The current I A of node A is the time derivative of the charge flowing into (or out of) node A, so the current I of node A is expressed as follows: A

[0250] ​​​

Number

[0251] In this way, the current I of node A can be obtained from the capacitance C connected to node A A and the output potential Vout of the output terminal. of node A. A It can be obtained.

[0252] By the method shown above, the leakage current (off-current) flowing between the source and drain of the transistor in the off state can be measured. It can be measured.

[0253] In this embodiment, transistors 804, 805, 806, and 808 were fabricated using a highly purified oxide semiconductor with a channel length L = 10 μm and a channel width W = 50 μm. Also, in each parallel measurement system 800, the capacitance values of the capacitive elements 802 were set to 100 fF, 1 pF, and 3 pF. were fabricated. Also, in each parallel measurement system 800, the capacitance values of the capacitive elements 802 were set to 100 fF, 1 pF, and 3 pF. In addition, in the measurement according to this embodiment, VDD = 5 V and VSS = 0 V. Also, during the measurement period, the potential V1 was set to VSS as a principle, and Vout was measured as VDD for a period of 100 msec every 10 to 300 sec. Also, the Δt used for calculating the current I flowing through the element was set to approximately 30000 sec. were set to 100 fF, 1 pF, and 3 pF.

[0254] Note that in the measurement according to this embodiment, VDD = 5 V and VSS = 0 V. Also, during the measurement period, the potential V1 was set to VSS as a principle, and Vout was measured as VDD for a period of 100 msec every 10 to 300 sec. Also, the Δt used for calculating the current I flowing through the element was set to approximately 30000 sec. In addition, in the measurement according to this embodiment, VDD = 5 V and VSS = 0 V. Also, during the measurement period, the potential V1 was set to VSS as a principle, and Vout was measured as VDD for a period of 100 msec every 10 to 300 sec. Also, the Δt used for calculating the current I flowing through the element was set to approximately 30000 sec. In addition, in the measurement according to this embodiment, VDD = 5 V and VSS = 0 V. Also, during the measurement period, the potential V1 was set to VSS as a principle, and Vout was measured as VDD for a period of 100 msec every 10 to 300 sec. Also, the Δt used for calculating the current I flowing through the element was set to approximately 30000 sec. In addition, in the measurement according to this embodiment, VDD = 5 V and VSS = 0 V. Also, during the measurement period, the potential V1 was set to VSS as a principle, and Vout was measured as VDD for a period of 100 msec every 10 to 300 sec. Also, the Δt used for calculating the current I flowing through the element was set to approximately 30000 sec.

[0255] Fig. 18 shows the relationship between the elapsed time Time related to the above current measurement and the output potential Vout. From Fig. 18, it can be confirmed that the potential is changing as time elapses.

[0256] Fig. 19 shows the off-current at room temperature (25 °C) calculated by the above current measurement. Note that Fig. 19 shows the relationship between the source-drain voltage V and the off-current I. Fig. From 19, it was found that the off-current was about 40 zA / μm under the condition that the source-drain voltage was 4 V. Also, it was found that the off-current was 10 zA / μm or less under the condition that the source-drain voltage was 3.1 V. Note that 1 zA represents 10 A. -21 A.

[0257] Furthermore, the off-current in the temperature environment of 85 °C calculated by the above current measurement is shown in FIG. 20. FIG. 20 shows the relationship between the source-drain voltage V and the off current I in the temperature environment of 85 °C. From FIG. 20, it was found that the off-current was 100 zA / μm or less under the condition that the source-drain voltage was 3.1 V.

[0258] As described above, in the transistor using the highly purified oxide semiconductor according to this embodiment, it was confirmed that the off-current was sufficiently small.

Example

[0259] The rewritable number of times of the memory cell according to one aspect of the disclosed invention was investigated. In this example, the investigation results will be described with reference to FIG. 21.

[0260] The semiconductor device used in the investigation was a semiconductor device having the circuit configuration shown in FIG. 1(A-1). Here, an oxide semiconductor was used for the transistor corresponding to transistor 162. As the capacitor element corresponding to capacitor element 16 4, one having a capacitance value of 0.33 pF was used.

[0261] The investigation was conducted by comparing the initial memory window width with the memory window width after retaining and writing information a predetermined number of times. The retention of information in the memory cell Holding and information writing are performed by applying either 0V or 5V to the wiring corresponding to the third wiring in FIG. 1(A-1), and applying either 0V or 5V to the wiring corresponding to the fourth wiring. When the potential of the wiring corresponding to the fourth wiring is 0V, the transistor corresponding to transistor 162 (writing transistor) is in the off state, and the potential applied to node FG is held. When the potential of the wiring corresponding to the fourth wiring is 5V, the transistor corresponding to transistor 162 is in the on state, so the potential of the wiring corresponding to the third wiring is applied to node FG. Also, it is performed by applying either 0V or 5V to the wiring corresponding to the fourth wiring and applying either 0V or 5V to the wiring corresponding to the fourth wiring. When the potential of the wiring corresponding to the fourth wiring is 0V, the transistor corresponding to transistor 162 (writing transistor) is in the off state, and the potential applied to node FG is held. When the potential of the wiring corresponding to the fourth wiring is 5V, the transistor corresponding to transistor 162 is in the on state, so the potential of the wiring corresponding to the third wiring is applied to node FG. When the potential of the wiring corresponding to the fourth wiring is 0V, the transistor corresponding to transistor 162 (writing transistor) is in the off state, and the potential applied to node FG is held. or the transistor corresponding to transistor 162 (writing transistor) is in the off state, and the potential applied to node FG is held. When the potential of the wiring corresponding to the fourth wiring is 5V, the transistor corresponding to transistor 162 is in the on state, so the potential of the wiring corresponding to the third wiring is applied to node FG. When the potential of the wiring corresponding to the fourth wiring is 5V, the transistor corresponding to transistor 162 is in the on state, so the potential of the wiring corresponding to the third wiring is applied to node FG. When the potential of the wiring corresponding to the fourth wiring is 5V, the transistor corresponding to transistor 162 is in the on state, so the potential of the wiring corresponding to the third wiring is applied to node FG. The potential of the wiring corresponding to the third wiring is applied to node FG.

[0262] The memory window width is one of the indexes indicating the characteristics of the memory device. Here, the shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to transistor 160 (reading transistor) between different memory states is meant. Different memory states refer to the state where 0V is applied to node FG (hereinafter referred to as the Low state) and the state where 5V is applied to node FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. The memory window width is one of the indexes indicating the characteristics of the memory device. Here, the shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to transistor 160 (reading transistor) between different memory states is meant. Different memory states refer to the state where 0V is applied to node FG (hereinafter referred to as the Low state) and the state where 5V is applied to node FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. The memory window width is one of the indexes indicating the characteristics of the memory device. Here, the shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to transistor 160 (reading transistor) between different memory states is meant. Different memory states refer to the state where 0V is applied to node FG (hereinafter referred to as the Low state) and the state where 5V is applied to node FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. The memory window width is one of the indexes indicating the characteristics of the memory device. Here, the shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to transistor 160 (reading transistor) between different memory states is meant. Different memory states refer to the state where 0V is applied to node FG (hereinafter referred to as the Low state) and the state where 5V is applied to node FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. The memory window width is one of the indexes indicating the characteristics of the memory device. Here, the shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to transistor 160 (reading transistor) between different memory states is meant. Different memory states refer to the state where 0V is applied to node FG (hereinafter referred to as the Low state) and the state where 5V is applied to node FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. The memory window width is one of the indexes indicating the characteristics of the memory device. Here, the shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to transistor 160 (reading transistor) between different memory states is meant. Different memory states refer to the state where 0V is applied to node FG (hereinafter referred to as the Low state) and the state where 5V is applied to node FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state. The memory window width is one of the indexes indicating the characteristics of the memory device. Here, the shift amount ΔVcg of the curve (Vcg-Id curve) showing the relationship between the potential Vcg of the wiring corresponding to the fifth wiring and the drain current Id of the transistor corresponding to transistor 160 (reading transistor) between different memory states is meant. Different memory states refer to the state where 0V is applied to node FG (hereinafter referred to as the Low state) and the state where 5V is applied to node FG (hereinafter referred to as the High state). That is, the memory window width can be confirmed by sweeping the potential Vcg in the Low state and the High state.

[0263] FIG. 21(A) shows the investigation results of the memory window width in the initial state and after performing 1×10 9 write operations. In FIG. 21(A), the horizontal axis indicates V cg (V), and the vertical axis indicates Id (A). cg (V), and the vertical axis indicates Id (A).

[0264] As shown in FIG. 21(A), after performing 1×10 9Before and after performing the loop writing, there is almost no change in the Vcg-Id curve of the write in the High state and the Vcg-Id curve of the write in the Low state. Also, there is almost no change in the shift amount (ΔVcg) between the Vcg-Id curve of the write in the High state and the Vcg-Id curve of the write in the Low state before and after 1×10 times of writing. Fig. 21(B) shows the relationship between the potential of the wiring corresponding to the fifth wiring necessary to turn on the transistor 160 in the write in the High state or the write in the Low state and the number of rewrite times. In Fig. 21(B), the horizontal axis represents the number of rewrite times, and the vertical axis represents the potential of the wiring corresponding to the fifth wiring, that is, the apparent threshold value V 9 of the transistor 160. is shown.

[0265] Note that the threshold value can generally be calculated by the tangent method. Specifically, for a curve with the horizontal axis as the gate voltage Vg and the vertical axis as the square root value of the drain current Id, a tangent line is obtained at the point where the slope of the curve is maximum. The intersection of the tangent line and the horizontal axis (the value of the gate voltage Vg) is taken as the threshold value. In Fig. 21(B), the apparent threshold value V is also calculated by the tangent method. Table 1 shows the memory window width calculated from Fig. 21(B). Note that the memory window width is obtained by calculating the difference between the apparent threshold value V of the transistor 160 in the write in the High state and the apparent threshold value V th of the transistor 160 in the write in the Low state. is shown.

[0266]

[0267] th is calculated.

[0267] Table 1 shows the memory window width calculated from Fig. 21(B). Note that the memory window width is obtained by calculating the difference between the apparent threshold value V of the transistor 160 in the write in the High state and the apparent threshold value V th_ H of the transistor 160 in the write in the Low state and th_L is obtained.

[0268]

Table 1

[0269] From Table 1, the memory cell of this embodiment has a change amount of the memory window width within 2%, specifically 1.68%, before and after performing 1×10 9 times of writing. Therefore, it is shown that the semiconductor device does not deteriorate at least before and after 1×10 times of writing. at least 9 times of writing.

[0270] Fig. 21(C) shows the relationship between the number of rewrites and the mutual conductance (gm) of the memory cell. In Fig. 21(C), the horizontal axis represents the number of rewrites, and the vertical axis represents the mutual conductance (g m) value.

[0271] When the mutual conductance (gm) of the memory cell decreases, effects such as difficulty in distinguishing between the written state and the erased state appear. However, as shown in Fig. 21(C), it can be seen that there is almost no change in the gm value even after performing 10 times of rewrites in the memory cell of this embodiment. Therefore, it can be said that the semiconductor device according to this embodiment is a semiconductor device with extremely high reliability that does not deteriorate even after 10 times of rewrites. 9 times of rewrites. Therefore, the semiconductor device according to this embodiment is a semiconductor device with extremely high reliability that does not deteriorate even after 10 9 times of rewrites. As described above, the memory cell according to one aspect of the disclosed invention has characteristics that do not change even after repeating retention and writing a large number of times, such as 10

[0272] times, and has extremely high rewrite resistance. That is, according to one aspect of the disclosed invention, it can be said that an extremely reliable memory cell and an extremely reliable semiconductor device equipped with the same are realized. 0 9 times, and has extremely high rewrite resistance. That is, according to one aspect of the disclosed invention, it can be said that an extremely reliable memory cell and an extremely reliable semiconductor device equipped with the same are realized. As described above, according to one aspect of the disclosed invention, an extremely reliable memory cell and an extremely reliable semiconductor device equipped with the same are realized. reliable semiconductor device are realized.

Explanation of Signs

[0273] 100 Substrate 102 Protection layer 104 Semiconductor region 106 Element isolation insulating layer 108 Gate insulating layer 110 Gate electrode 116 Channel formation region 120 Impurity region 122 Metal layer 124 Metal compound region 128 Insulating layer 130 Insulating layer 142a Source electrode or drain electrode 142b Source electrode or drain electrode 143a Insulating layer 143b Insulating layer 144 Oxide semiconductor layer 146 Gate insulating layer 148a Gate electrode 148b Electrode 150 Insulating layer 152 Insulating layer 154 Electrode 156 Wiring 156a Wiring 156b Wiring 160 Transistor 162 Transistor 164 Capacitor element 170 Memory cell 180 Potential conversion circuit 190 First drive circuit 192 Second drive circuit 195 Wiring 211 Read circuit 212 Control circuit 213 Delay circuit 214 Buffer circuit 221 Decoder circuit 222 Control circuit 223 Buffer circuit 224 Buffer circuit 225 Level shift circuit 231 Switch 232 Switch 233 Signal generation circuit 701 Housing 702 Housing 703 Display unit 704 Keyboard 711 Main body 712 Stylus 713 Display unit 714 Operation button 715 External interface 720 E-book 721 Housing 723 Housing 725 Display unit 727 Display unit 731 Power supply 733 Operation key 735 Speaker 737 Shaft part 740 Housing 741 Housing 742 Display panel 743 Speaker 744 Microphone 745 Operation key 746 Pointing device 747 Camera lens 748 External connection terminal 749 Solar cell 750 External memory slot 761 Main body 763 Eyepiece 764 Operation switch 765 Display unit 766 Battery 767 Display unit 770 Television set 771 Housing 773 Display unit 775 Stand 780 Remote control operation unit 800 Measurement system 802 Capacitive element 804 Transistor 805 Transistor 806 Transistor 808 Transistor 1200 p-Type Transistor 1210 p-Type Transistor 1220 n-Type Transistor 1230 p-Type Transistor 1240 p-Type Transistor 1250 n-Type Transistor 1260 p-Type Transistor 1270 n-Type Transistor 1280 p-Type Transistor 1290 n-Type Transistor 1300 Transistor 1310 Transistor 1320 Transistor 1330 Transistor 1340 Transistor 1350 Capacitor Element 1360 Capacitor Element 1370 Capacitor Element 1380 Capacitor Element 1390 Transistor

Claims

1. A semiconductor device comprising a first transistor, a second transistor, and a capacitance element, a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other; a channel formation region of the first transistor having silicon; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second conductive layer having a region located above the first insulating layer and a region in contact with an upper surface of the first conductive layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one electrode of the capacitor; a third conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitor; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer; a third insulating layer having a region located above the second insulating layer and a region located above the oxide semiconductor layer; a fourth conductive layer having a region located above the third insulating layer and functioning as a gate electrode of the second transistor; a fourth insulating layer having a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the fourth conductive layer; the third conductive layer has a region that does not overlap the second insulating layer and overlaps the third insulating layer in a cross-sectional view of the second transistor in a channel length direction; the fourth conductive layer has a region overlapping the second insulating layer and a region overlapping the third insulating layer in a cross-sectional view of the second transistor in a channel length direction; the third conductive layer and the fourth conductive layer have the same material; a channel formation region of the first transistor does not overlap with the fourth conductive layer.

2. A semiconductor device comprising a first transistor, a second transistor, and a capacitance element, a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other; a channel formation region of the first transistor having silicon; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second conductive layer having a region located above the first insulating layer and a region in contact with an upper surface of the first conductive layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one electrode of the capacitor; a third conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitor; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer; a third insulating layer having a region located above the second insulating layer and a region located above the oxide semiconductor layer; a fourth conductive layer having a region located above the third insulating layer and functioning as a gate electrode of the second transistor; a fourth insulating layer having a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the fourth conductive layer; the third conductive layer has a region that does not overlap the second insulating layer and overlaps the third insulating layer in a cross-sectional view of the second transistor in a channel length direction; the fourth conductive layer has a region overlapping the second insulating layer and a region overlapping the third insulating layer in a cross-sectional view of the second transistor in a channel length direction; the third conductive layer and the fourth conductive layer have the same material; a channel formation region of the first transistor does not overlap with the fourth conductive layer; The third conductive layer has a region overlapping with the first conductive layer.

3. A semiconductor device comprising a first transistor, a second transistor, and a capacitance element, a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other; a channel formation region of the first transistor having silicon; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second conductive layer having a region located above the first insulating layer and a region in contact with an upper surface of the first conductive layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one electrode of the capacitor; a third conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitor; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer; a third insulating layer having a region located above the second insulating layer and a region located above the oxide semiconductor layer; a fourth conductive layer having a region located above the third insulating layer and functioning as a gate electrode of the second transistor; a fourth insulating layer having a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the fourth conductive layer; the third conductive layer has a region that does not overlap the second insulating layer and overlaps the third insulating layer in a cross-sectional view of the second transistor in a channel length direction; the fourth conductive layer has a region overlapping the second insulating layer and a region overlapping the third insulating layer in a cross-sectional view of the second transistor in a channel length direction; the third conductive layer and the fourth conductive layer have the same material; a channel formation region of the first transistor does not overlap with the fourth conductive layer; the first insulating layer comprises silicon nitride; The fourth insulating layer comprises silicon oxide.

4. A semiconductor device comprising a first transistor, a second transistor, and a capacitance element, a gate electrode of the first transistor, one of a source electrode and a drain electrode of the second transistor, and one electrode of the capacitance element are electrically connected to each other; a channel formation region of the first transistor having silicon; a first conductive layer having a region located above a channel formation region of the first transistor and functioning as a gate electrode of the first transistor; a first insulating layer having a region in contact with a side surface of the first conductive layer; a second conductive layer having a region located above the first insulating layer and a region in contact with an upper surface of the first conductive layer, and having a function as one of a source electrode and a drain electrode of the second transistor and a function as one electrode of the capacitor; a third conductive layer having a region overlapping with the second conductive layer and functioning as the other electrode of the capacitor; an oxide semiconductor layer having a region located above the first insulating layer and including a channel formation region of the second transistor; a second insulating layer having a region in contact with an upper surface of the second conductive layer; a third insulating layer having a region located above the second insulating layer and a region located above the oxide semiconductor layer; a fourth conductive layer having a region located above the third insulating layer and functioning as a gate electrode of the second transistor; a fourth insulating layer having a region in contact with an upper surface of the third conductive layer and a region in contact with an upper surface of the fourth conductive layer; the third conductive layer has a region that does not overlap the second insulating layer and overlaps the third insulating layer in a cross-sectional view of the second transistor in a channel length direction; the fourth conductive layer has a region overlapping the second insulating layer and a region overlapping the third insulating layer in a cross-sectional view of the second transistor in a channel length direction; the third conductive layer and the fourth conductive layer have the same material; a channel formation region of the first transistor does not overlap with the fourth conductive layer; the third conductive layer has an area overlapping the first conductive layer, the first insulating layer comprises silicon nitride; The fourth insulating layer comprises silicon oxide.

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