Electronic component

Abstract

To provide electronic components that reduce delamination between inductor elements and capacitor elements and also reduce delamination between inductor elements and insulating layers.SOLUTION: An electronic component 1 has a capacitor element 7, an inductor element 2, and an interlayer insulating layer 62. The interlayer insulating layer has a first main surface 62a, a second main surface 62b, and via holes 610. The capacitor element is disposed on the second main surface side of the interlayer insulating layer and has a first electrode layer 71, a second electrode layer 72, and a dielectric layer 74. The inductor element is disposed on the first main surface side of the interlayer insulating layer and further has an inductor wiring including an inductor portion 210 disposed on the first main surface and a via portion 211 that connects the inductor portion and the second electrode layer through the via hole. The inductor wiring has an adhesion layer 201, a conducting layer 202 formed in contact with the adhesion layer, and a metal layer 203 formed in contact with the conducting layer. The adhesion layer continuously comes into contact with the first main surface, the inner surface of the via hole, and the second electrode layer.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present disclosure relates to electronic components.

Background Art

[0002] Conventionally, as an electronic component, there is one described in Japanese Patent Application Laid-Open No. 10-51257 (Patent Document 1). This electronic component has an inductor wiring, a capacitor electrode electrically connected to the inductor wiring, and an insulating layer disposed between the inductor wiring and the capacitor electrode. The inductor wiring and the capacitor electrode are connected by a via portion penetrating through a via hole of the insulating layer.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] By the way, in the conventional electronic component as described above, the adhesion between the inductor wiring and the capacitor electrode is not sufficient, and there is a risk that the inductor wiring and the capacitor electrode may peel off. Also, the adhesion between the inductor wiring and the insulating layer is not sufficient, and there is a risk that the inductor wiring and the insulating layer may peel off.

[0005] Therefore, an object of the present disclosure is to provide an electronic component capable of reducing peeling between an inductor element and a capacitor element and reducing peeling between the inductor element and an insulating layer.

Means for Solving the Problems

[0006] To solve the above problems, an electronic component according to one aspect of the present disclosure is a capacitor element, and an inductor element electrically connected to the capacitor element, and The interlayer insulating layer disposed between the capacitor element and the inductor element and comprises the interlayer insulating layer has a first main surface, a second main surface, and via holes penetrating the first main surface and the second main surface, the capacitor element is disposed on the second main surface side of the interlayer insulating layer, and further has a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first electrode layer and the second electrode layer, the inductor element is disposed on the first main surface side of the interlayer insulating layer, and further has an inductor wiring including an inductor portion disposed on the first main surface and a via portion penetrating the via hole to connect the inductor portion and the second electrode layer, the inductor wiring has an adhesion layer, a conduction layer formed in contact with the adhesion layer, and a metal layer formed in contact with the conduction layer, the adhesion layer is in continuous contact with the first main surface, the inner surface of the via hole, and the second electrode layer.

[0007] According to the above aspect, since the adhesion layer is in continuous contact with the first main surface of the interlayer insulating layer, the inner surface of the via hole of the interlayer insulating layer, and the second electrode layer, the adhesion between the inductor wiring and the second electrode layer can be improved, and the adhesion between the inductor wiring and the interlayer insulating layer can be improved. Therefore, the peeling between the inductor element and the capacitor element can be reduced, and the peeling between the inductor element and the interlayer insulating layer can be reduced.

Advantages of the Invention

[0008] According to the electronic component which is one aspect of the present disclosure, the peeling between the inductor element and the capacitor element can be reduced, and the peeling between the inductor element and the insulating layer can be reduced.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

Figure 3

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 4E

Figure 4F

Figure 4G

Figure 4H

Figure 4I

Figure 4J

Figure 5

Mode for Carrying Out the Invention

[0010] Hereinafter, an electronic component which is one aspect of the present disclosure will be described in detail with reference to the illustrated embodiments. Note that the drawings include some schematic ones and may not reflect actual dimensions and ratios.

[0011] <First Embodiment> [Outline Configuration] FIG. 1 is a plan view showing the first embodiment of the electronic component. FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1. FIG. 3 is an equivalent circuit diagram of the first embodiment of the electronic component. As shown in FIGS. 1, 2, and 3, the electronic component 1 includes a capacitor element 7, an inductor element 2, and an interlayer insulating layer 62.

[0012] The interlayer insulating layer 62 is disposed between the capacitor element 7 and the inductor element 2. The interlayer insulating layer 62 has a first main surface 62a and a second main surface 62b facing each other. The interlayer insulating layer 62 has a via hole 620 penetrating through the first main surface 62a and the second main surface 62b.

[0013] The capacitor element 7 is disposed on the second main surface 62b side of the interlayer insulating layer 62. The capacitor element 7 has a first electrode layer 71, a second electrode layer 72, and a dielectric layer 74. The dielectric layer 74 is disposed between the first electrode layer 71 and the second electrode layer 72.

[0014] The inductor element 2 is disposed on the first main surface 62a side of the interlayer insulating layer 62. The inductor element 2 has an insulator 60 and an inductor wiring 21 disposed within the insulator 60. The inductor wiring 21 includes an inductor portion 210 disposed on the first main surface 62a of the interlayer insulating layer 62 and a via portion 211 that penetrates through the via hole 620 of the interlayer insulating layer 62 to connect the inductor portion 210 and the second electrode layer 72. The boundary surface between the inductor portion 210 and the via portion 211 is located on the same plane as the first main surface 62a of the interlayer insulating layer 62. The boundary surface is shown by a two-dot chain line in FIG. 2. Since the inductor portion 210 and the via portion 211 are integrally and continuously provided, it is difficult to actually distinguish the boundary surface. Note that the boundary surface may be formed so as to be distinguishable.

[0015] The inductor wiring 21 has an adhesion layer 201, a conduction layer 202 formed to contact the adhesion layer 201, and a metal layer 203 formed to contact the conduction layer 202. The adhesion layer 201 is made of a metal having adhesiveness and conductivity, and the adhesiveness with a member in contact with the adhesion layer 201 is improved. The conduction layer 202 is made of a metal having conductivity, enabling the supply of charges from the outside, and is used, for example, as a plating seed layer. The metal layer 203 is made of a metal having conductivity and is, for example, a plating layer.

[0016] The adhesion layer 201 extends continuously from the first main surface 62a of the interlayer insulating layer 62, the inner surface of the via hole 620 of the interlayer insulating layer 62, and the second electrode layer 72. The adhesion layer 201 is in continuous contact with the first main surface 62a of the interlayer insulating layer 62, the inner surface of the via hole 620 of the interlayer insulating layer 62, and the second electrode layer 72. Here, "continuous contact" means that the portions of the adhesion layer 201 in direct contact with the first main surface 62a, the inner surface of the via hole 620, and the second electrode layer 72 are formed in a state where they are electrically conductive to each other without interruption.

[0017] According to the above configuration, since the adhesion layer 201 is in continuous contact with the first main surface 62a of the interlayer insulating layer 62, the inner surface of the via hole 620 of the interlayer insulating layer 62, and the second electrode layer 72, the adhesion between the inductor wiring 21 and the second electrode layer 72 can be improved, and the adhesion between the inductor wiring 21 and the interlayer insulating layer 62 can be improved. Therefore, the peeling between the inductor element 2 and the capacitor element 7 can be reduced, and the peeling between the inductor element 2 and the interlayer insulating layer 62 can be reduced.

[0018] Here, when an adhesion layer is not provided on the inductor wiring, in order to improve the adhesion between the inductor wiring and the interlayer insulating layer, for example, the first main surface of the interlayer insulating layer may be roughened by a roughening process or the like to increase the contact area between the first main surface of the interlayer insulating layer and the inductor wiring. However, there is a problem that the rough shape of the first main surface of the interlayer insulating layer is transferred to the contact surface between the inductor wiring and the interlayer insulating layer, the contact surface of the inductor wiring becomes rough, and the high-frequency characteristics of the inductor wiring deteriorate. On the other hand, in the present embodiment, the adhesion between the inductor wiring and the interlayer insulating layer can be improved without roughening the contact surface between the inductor wiring and the interlayer insulating layer.

[0019] [Preferred form] (Electronic component 1) The electronic component 1 is mounted on an electronic device such as a personal computer, a DVD player, a digital camera, a TV, a mobile phone, or car electronics. The electronic component 1 includes a capacitor element 7, a protective layer 61, an interlayer insulating layer 62, an inductor element 2, a first external terminal 41, and a second external terminal 42.

[0020] In the figure, the thickness direction of the electronic component 1 is defined as the Z direction, with the forward Z direction being the upper side and the reverse Z direction being the lower side. In the plane orthogonal to the Z direction of the electronic component 1, the longitudinal direction of the electronic component 1, which is the direction in which the first external terminal 41 and the second external terminal 42 are arranged, is defined as the X direction, and the width direction of the electronic component 1, which is the direction orthogonal to the longitudinal direction, is defined as the Y direction.

[0021] The first end 21a of the inductor wiring 21 of the inductor element 2 is connected to the first external terminal 41. The second end 21b of the inductor wiring 21 of the inductor element 2 is connected to the second external terminal 42. The first end of the capacitor element 7 is connected to the first end 21a of the inductor wiring 21. The second end of the capacitor element 7 is connected to the second end 21b of the inductor wiring 21. In this way, the inductor element 2 and the capacitor element 7 are connected in parallel to form an LC resonance circuit.

[0022] (Capacitor element 7) The capacitor element 7 includes a first electrode layer 71, a second electrode layer 72, a dielectric layer 74, and a connection conductor layer 75.

[0023] The first electrode layer 71 extends in a direction parallel to the second main surface 62b of the interlayer insulating layer 62. The first electrode layer 71 is provided on the substrate 5. The substrate 5 has a first main surface 5a and a second main surface 5b that face each other. The substrate 5 is, for example, a semiconductor substrate containing silicon elements. The first electrode layer 71 is a high-conductivity doped region formed by doping the substrate 5 with impurities. In this embodiment, the entire substrate 5 is used as the doped region, but a part of the substrate 5 may be used as the doped region. In this case, by not using the portion of the substrate 5 that is exposed outside the electronic component 1 as the doped region, the insulation of the electronic component 1 can be maintained.

[0024] Here, when forming the first electrode layer 71, which is a doped region, by doping the substrate 5 with impurities, for example, group III or group V impurities are doped into the silicon substrate 5 at 1×10 16 / cm 3By doping at the above concentrations, the electrical resistivity of the substrate 5 can be lowered, and the doped region can be used as a conductor. Preferably, the electrical resistivity of the substrate 5 is 1 Ω·cm or less. According to this, by lowering the electrical resistivity of the substrate 5, it can be used as a ground or as an electrode layer of a capacitor.

[0025] Note that the first electrode layer 71 may be a thin film of a metal material separate from the substrate 5. That is, for example, the first electrode layer 71 of the thin film may be formed on the substrate 5 using chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering, or the like. In this case, the dielectric layer 74 is formed on the first electrode layer 71 of the thin film, and the second electrode layer 72 is formed on the dielectric layer 74.

[0026] The second electrode layer 72 extends in a direction parallel to the second main surface 62b of the interlayer insulating layer 62 and faces the first electrode layer 71 in a direction (upward direction) perpendicular to the second main surface 62b. The second electrode layer 72 is formed along the first electrode layer 71. The second electrode layer 72 is a thin film of a metal material. The second electrode layer 72 is formed, for example, using chemical vapor deposition, atomic layer deposition, or sputtering.

[0027] The second electrode layer 72 has an adhesion layer 701 and a metal layer 703 formed so as to be in contact with the adhesion layer 701. The adhesion layer 701 contacts the upper surface of the dielectric layer 74. The adhesion layer 701 is made of a metal having adhesiveness and conductivity, and is preferably a titanium layer (Ti layer), which can improve the adhesiveness with the dielectric layer 74. The metal layer 703 is made of a metal having conductivity, and is preferably an aluminum layer (Al layer). It is preferable that the ratio of the thickness of the metal layer 703 to the thickness of the adhesion layer 701 is 7 to 15 so that sufficient adhesiveness is obtained and the thickness of the second electrode layer 72 can be suppressed. The thickness of the adhesion layer 701 is, for example, 0.1 μm, and the thickness of the metal layer 703 is, for example, 1 μm.

[0028] The dielectric layer 74 is located between the first electrode layer 71 and the second electrode layer 72. The dielectric layer 74 is formed along the first electrode layer 71. The dielectric layer 74 is a thin film of a dielectric material. The dielectric layer 74 is formed, for example, using a chemical vapor deposition method or an atomic layer deposition method. The dielectric layer 74 is, for example, SiO2 and is formed by thermal oxidation or the like. The thickness of the dielectric layer 74 is, for example, 0.9 μm.

[0029] The connection conductor layer 75 is in the same layer as the second electrode layer 72 and is disposed on the upper surface of the dielectric layer 74. A part of the connection conductor layer 75 penetrates through the via hole 740 of the dielectric layer 74 and is connected to the first electrode layer 71. Similar to the second electrode layer 72, the connection conductor layer 75 has an adhesion layer 701 and a metal layer 703 formed in contact with the adhesion layer 701. The adhesion layer 701 contacts the upper surface of the dielectric layer 74, the inner surface of the via hole 740 of the dielectric layer 74, and the first electrode layer 71.

[0030] The first electrode layer 71 is connected to the connection conductor layer 75, and the connection conductor layer 75 is connected to the first end 21a of the inductor wiring 21. Thereby, the first electrode layer 71 is electrically connected to the first end 21a of the inductor wiring 21 and is electrically connected to the first external terminal 41.

[0031] The second electrode layer 72 is connected to the second end 21b of the inductor wiring 21. Thereby, the second electrode layer 72 is electrically connected to the second end 21b of the inductor wiring 21 and is electrically connected to the second external terminal 42. Therefore, by applying a voltage between the first external terminal 41 and the second external terminal 42, a capacitance can be formed between the first electrode layer 71 and the second electrode layer 72.

[0032] Note that the first electrode layer 71 may be directly connected to the first end 21a of the inductor wiring 21 without passing through the connection conductor layer 75. At this time, the first end 21a of the inductor wiring 21 penetrates through the via hole 740 of the dielectric layer 74 and is connected to the first electrode layer 71.

[0033] (Protection layer 61) The protective layer 61 is provided on the first electrode layer 71 (the first main surface 5a of the substrate 5) so as to cover the second electrode layer 72, the dielectric layer 74, and the connection conductor layer 75. The protective layer 61 is, for example, a single layer of SiN, SiO2, BPSG, or a laminated structure thereof. The protective layer 61 protects the dielectric layer 74 from moisture.

[0034] (Interlayer insulating layer 62) The interlayer insulating layer 62 is provided on the protective layer 61. The interlayer insulating layer 62 is, for example, an organic insulating material made of an epoxy-based, phenol-based, liquid crystal polymer-based, polyimide-based, acrylic-based material, or a mixture containing them. The interlayer insulating layer 62 is preferably, for example, 10 to 50 μm so that the thickness of the electronic component 1 can be suppressed while maintaining the insulation between the second electrode layer 72 of the capacitor element 7 and the inductor wiring 21. Note that the protective layer 61 may be omitted, and in this case, the interlayer insulating layer 62 is provided on the first electrode layer 71 (the first main surface 5a of the substrate 5) so as to cover the second electrode layer 72, the dielectric layer 74, and the connection conductor layer 75.

[0035] (Inductor element 2) The inductor element 2 includes an insulator 60 and an inductor wiring 21 disposed within the insulator 60.

[0036] The insulator 60 is, for example, an organic insulating material made of an epoxy-based, phenol-based, liquid crystal polymer-based, polyimide-based, acrylic-based material, or a mixture containing them. Note that the insulator 60 may be composed of a magnetic layer, and the magnetic layer includes magnetic powder and a resin containing the magnetic powder. The resin is, for example, an organic insulating material made of an epoxy-based, phenol-based, liquid crystal polymer-based, polyimide-based, acrylic-based material, or a mixture containing them. The magnetic powder is, for example, an FeSi-based alloy such as FeSiCr, an FeCo-based alloy, an Fe-based alloy such as NiFe, or an amorphous alloy thereof. Therefore, compared with a magnetic layer made of ferrite, the DC superposition characteristics can be improved by the magnetic powder, and the magnetic powder is insulated from each other by the resin, so the loss (iron loss) at high frequencies is reduced. The magnetic layer may be a case where it does not contain an organic resin, such as a sintered body of ferrite or magnetic powder.

[0037] The inductor wiring 21 is a wiring that extends in a spiral shape along the first main surface 62a of the interlayer insulating layer 62. The number of turns of the inductor wiring 21 preferably exceeds one turn. Thereby, the inductance can be improved. The inductor wiring 21 is wound in a spiral shape, for example, in a clockwise direction from the first end 21a which is the outer peripheral end toward the second end 21b which is the inner peripheral end when viewed from the Z direction. The inductor wiring 21 includes an inductor portion 210 and a via portion 211. The inductor portion 210 is a wound portion disposed on the first main surface 62a and wound in a spiral shape. The via portion 211 penetrates through the via hole 620 of the interlayer insulating layer 62 and the via hole 610 of the protective layer 61. Specifically, the via portion 211 of the first end 21a of the inductor wiring 21 is connected to the connection conductor layer 75, and the via portion 211 of the second end 21b of the inductor wiring 21 is connected to the second electrode layer 72.

[0038] The inductor wiring 21 has an adhesion layer 201, a conduction layer 202 formed to be in contact with the adhesion layer 201, and a metal layer 203 formed to be in contact with the conduction layer 202. The adhesion layer 201 extends continuously on the first main surface 62a of the interlayer insulating layer 62, the inner surface of the via hole 620 of the interlayer insulating layer 62, and the second electrode layer 72. The adhesion layer 201 is in continuous contact with the first main surface 62a of the interlayer insulating layer 62, the inner surface of the via hole 620 of the interlayer insulating layer 62, and the second electrode layer 72. Specifically, the inductor portion 210 has the adhesion layer 201, the conduction layer 202, and the metal layer 203, and the via portion 211 has the adhesion layer 201, the conduction layer 202, and the metal layer 203.

[0039] The adhesion layer 201 is preferably a titanium layer (Ti layer). The thickness of the adhesion layer 201 is, for example, 0.35 μm.

[0040] The conductive layer 202 is, for example, a layer made of Au, Pt, Pd, Ag, Cu, Al, Co, Cr, Zn, Ni, Ti, W, Fe, Sn, In, or a compound thereof. The conductive layer 202 is preferably a seed layer. The thickness of the conductive layer 202 is, for example, desirably 2 μm or less, and is not particularly limited as long as it can supply electric charges and sufficiently functions as a seed layer for electrolytic plating. The conductive layer 202 is formed on the adhesion layer 201, for example, using sputtering or the like.

[0041] The metal layer 203 is, for example, a layer made of Au, Pt, Pd, Ag, Cu, Al, Co, Cr, Zn, Ni, Ti, W, Fe, Sn, In, or a compound thereof. The thickness of the metal layer 203 is, for example, 30 μm. The metal layer 203 is preferably a copper layer (Cu layer). The metal layer 203 is preferably a plating layer. The metal layer 203 is formed on the conductive layer 202, for example, by supplying electric charges to the conductive layer 202 and performing electrolytic plating.

[0042] (The first external terminal 41 and the second external terminal 42) The first external terminal 41 is disposed on the upper surface of the insulator 60. The first external terminal 41 includes a main body portion 410 and a via portion 411. The main body portion 410 is a flat plate portion disposed on the upper surface of the insulator 60. The via portion 411 penetrates through the via hole 600 of the insulator 60 and is connected to the first end 21a of the inductor wiring 21. The boundary surface between the main body portion 410 and the via portion 411 is located on the same plane as the upper surface of the insulator 60. The boundary surface is indicated by a two-dot chain line in FIG. 2. Since the main body portion 410 and the via portion 411 are integrally and continuously provided, it is difficult to actually distinguish the boundary surface. Note that the boundary surface may be formed so as to be distinguishable.

[0043] The first external terminal 41 has an adhesion layer 401, a conduction layer 402 formed to contact the adhesion layer 401, and a metal layer 403 formed to contact the conduction layer 402. The adhesion layer 401 extends continuously on the upper surface of the insulator 60, the inner surface of the via hole 600 of the insulator 60, and the metal layer 203 of the inductor wiring 21. The adhesion layer 401 is in continuous contact with the upper surface of the insulator 60, the inner surface of the via hole 600 of the insulator 60, and the metal layer 203 of the inductor wiring 21. Specifically speaking, the main body portion 410 has the adhesion layer 401, the conduction layer 402, and the metal layer 403, and the via portion 411 has the adhesion layer 401, the conduction layer 402, and the metal layer 403. The materials of the adhesion layer 401, the conduction layer 402, and the metal layer 403 of the first external terminal 41 are the same as the materials of the adhesion layer 201, the conduction layer 202, and the metal layer 203 of the inductor wiring 21, respectively.

[0044] The second external terminal 42 is disposed on the upper surface of the insulator 60. The second external terminal 42 includes a main body portion 420 and a via portion 421, similar to the first external terminal 41. The main body portion 420 is a flat plate portion disposed on the upper surface of the insulator 60. The via portion 421 penetrates the via hole 600 of the insulator 60 and is connected to the second end 21b of the inductor wiring 21. The boundary surface between the main body portion 420 and the via portion 421 is located on the same plane as the upper surface of the insulator 60. The boundary surface is indicated by a two-dot chain line in FIG. 2.

[0045] The second external terminal 42 has an adhesion layer 401, a conduction layer 402 formed to contact the adhesion layer 401, and a metal layer 403 formed to contact the conduction layer 402. The adhesion layer 401 extends continuously on the upper surface of the insulator 60, the inner surface of the via hole 600 of the insulator 60, and the metal layer 203 of the inductor wiring 21. The adhesion layer 401 is in continuous contact with the upper surface of the insulator 60, the inner surface of the via hole 600 of the insulator 60, and the metal layer 203 of the inductor wiring 21. Specifically speaking, the main body portion 420 has the adhesion layer 401, the conduction layer 402, and the metal layer 403, and the via portion 421 has the adhesion layer 401, the conduction layer 402, and the metal layer 403. The materials of the adhesion layer 401, the conduction layer 402, and the metal layer 403 of the second external terminal 42 are the same as the materials of the adhesion layer 401, the conduction layer 402, and the metal layer 403 of the first external terminal 41, respectively.

[0046] (Contact of Inductor Wiring 21, Interlayer Insulation Layer 62, and Second Electrode Layer 72) The adhesion layer 201 of the inductor wiring 21 is in continuous contact with the first main surface 62a of the interlayer insulation layer 62, the inner surface of the via hole 620 of the interlayer insulation layer 62, and the second electrode layer 72. According to this, the adhesion between the inductor wiring 21 and the second electrode layer 72 can be improved, and the adhesion between the inductor wiring 21 and the interlayer insulation layer 62 can be improved. Therefore, the peeling between the inductor element 2 and the capacitor element 7 can be reduced, and the peeling between the inductor element 2 and the interlayer insulation layer 62 can be reduced.

[0047] Preferably, the adhesion layer 201 of the inductor wiring 21 is a Ti layer. Also, the second electrode layer 72 includes an Al layer that contacts the adhesion layer 201. That is, the metal layer 703 of the second electrode layer 72 is an Al layer.

[0048] According to the above configuration, since the second electrode layer 72 includes an Al layer, the processing accuracy of the second electrode layer 72 is high and the variation in the characteristics of the second electrode layer 72 is small. Also, since the adhesion layer 201 is a Ti layer, the adhesion between the Ti layer of the adhesion layer 201 and the Al layer of the second electrode layer 72 can be improved, the adhesion between the Ti layer of the adhesion layer 201 and the conduction layer 202 can be improved, and the adhesion between the Ti layer of the adhesion layer 201 and the interlayer insulation layer 62 can be improved.

[0049] Also, since the adhesion layer 201 is a Ti layer, the hillock of the Al layer of the second electrode layer 72 can be prevented by the Ti layer of the adhesion layer 201. Here, a hillock refers to a defect in which hemispherical protrusions grow on a metal. Hillocks are likely to occur in Al, but by forming a Ti layer on the Al layer, hillocks can be suppressed.

[0050] Preferably, the metal layer 203 is a Cu layer. According to the above configuration, the conductivity of the metal layer 203 becomes high and the Q value can be increased. Although the Cu layer (metal layer 203) and the Al layer (second electrode layer 72) are likely to peel off when in direct contact, by providing a Ti layer (adhesion layer 201) between the Cu layer and the Al layer, the peeling between the Cu layer and the Al layer can be suppressed via the Ti layer.

[0051] Preferably, the ratio of the thickness of the metal layer 203 of the inductor portion 210 to the thickness of the second electrode layer 72 is 15 or more and 70 or less. Here, the thickness refers to the size in the direction (Z direction) orthogonal to the first main surface 62a of the interlayer insulating layer 62. As a method for measuring the thickness, for example, an SEM image of a cross section including the Z direction of the electronic component 1 is acquired, the thicknesses at five locations are measured from the SEM image, and the average value of the thicknesses at the five locations is calculated. The thickness of the metal layer 203 is preferably 30 ± 5 μm, and the thickness of the second electrode layer 72 is preferably 1 ± 0.5 μm.

[0052] According to the above configuration, since the ratio is 15 or more, the thickness of the second electrode layer 72 is reduced, the patterning accuracy of the second electrode layer 72 is improved, the variation in capacitance is reduced, and on the other hand, the thickness of the metal layer 203 of the inductor portion 210 is increased, so that the DC resistance of the metal layer 203 of the inductor portion 210 can be reduced and the Q value can be increased. On the contrary, if the thickness of the second electrode layer 72 is thicker than necessary, the patterning accuracy of the second electrode layer 72 deteriorates, the variation in capacitance increases, and on the other hand, if the thickness of the metal layer 203 of the inductor portion 210 is thinner than necessary, the DC resistance of the metal layer 203 of the inductor portion 210 increases and the Q value decreases.

[0053] Since the ratio is 70 or less, the thickness of the second electrode layer 72 is increased, the coverage rate of the dielectric layer 74 is increased, and the capacitor characteristics can be improved. On the other hand, the thickness of the metal layer 203 of the inductor portion 210 is reduced, for example, the variation in the thickness of the Cu plating is reduced, and the variation in characteristics can be reduced. On the contrary, if the thickness of the second electrode layer 72 is thinner than necessary, the coverage rate of the dielectric layer 74 decreases, the capacitor characteristics deteriorate, and on the other hand, if the metal layer 203 of the inductor portion 210 is thicker than necessary, for example, the variation in the thickness of the Cu plating increases and the characteristic variation increases.

[0054] Note that the contact between the inductor wiring 21 and the connection conductor layer 75 is the same as the contact between the inductor wiring 21 and the second electrode layer 72. That is, at the first end 21a of the inductor wiring 21, the adhesion layer 201 of the inductor wiring 21 is in continuous contact with the first main surface 62a of the interlayer insulating layer 62, the inner surface of the via hole 620 of the interlayer insulating layer 62, and the connection conductor layer 75. According to this, the adhesion between the inductor wiring 21 and the connection conductor layer 75 can be improved, and the adhesion between the inductor wiring 21 and the connection conductor layer 75 can be improved.

[0055] [Manufacturing method] Next, the manufacturing method of the electronic component 1 will be described.

[0056] As shown in FIG. 4A, a substrate 5 having first and second main surfaces 5a and 5b facing each other and containing silicon elements is prepared. Ions are implanted into the substrate 5 to obtain a high-conductivity substrate. Thereby, the substrate 5 is used as the first electrode layer 71 of the capacitor element 7.

[0057] As shown in FIG. 4B, a dielectric layer 74 is formed on the first main surface 5a of the substrate 5. As shown in FIG. 4C, the dielectric layer 74 is etched into a predetermined pattern using a photolithography process.

[0058] As shown in FIG. 4D, a resist 80 is patterned on the first main surface 5a of the substrate 5 and the dielectric layer 74. As shown in FIG. 4E, an adhesion layer 701 and a metal layer 703 are deposited on the dielectric layer 74 to form the second electrode layer 72 and the connection conductor layer 75, and the resist 80 is removed.

[0059] As shown in FIG. 4F, a protective layer 61 is provided on the first main surface 5a of the substrate 5 so as to cover the second electrode layer 72, the dielectric layer 74, and the connection conductor layer 75, and an interlayer insulating layer 62 is provided on the protective layer 61. Using a photolithography process, via holes V (via holes 610, 620) for exposing the second electrode layer 72 and the connection conductor layer 75 are provided in the protective layer 61 and the interlayer insulating layer 62.

[0060] As shown in FIG. 4G, an adhesion layer 201 is formed by sputtering on the first main surface 62a of the interlayer insulating layer 62, the inner surface of the via hole V, the exposed surface of the second electrode layer 72, and the exposed surface of the connection conductor layer 75. A conduction layer 202 is formed by sputtering on the adhesion layer 201. Thereafter, a resist (not shown) is provided on the conduction layer 202, and using the conduction layer 202 as a seed layer, a metal layer 203 is formed on the conduction layer 202 by electrolytic plating. Thereafter, the resist is removed, and the adhesion layer 201 and the conduction layer 202 covered with the resist are removed, and an inductor wiring 21 is formed on the interlayer insulating layer 62 as shown in FIG. 4H. The inductor wiring 21 includes an inductor portion 210 disposed on the first main surface 62a of the interlayer insulating layer 62 and via portions 211 that penetrate the via holes V and are connected to the second electrode layer 72 and the connection conductor layer 75, respectively.

[0061] As shown in FIG. 4I, an insulator 60 is provided on the first main surface 62a of the interlayer insulating layer 62 so as to cover the inductor wiring 21. Using a photolithography method, via holes 600 are formed in the insulator 60 so that the first end 21a and the second end 21b of the inductor wiring 21 are exposed.

[0062] As shown in FIG. 4J, similar to the inductor wiring 21 (adhesion layer 201, conduction layer 202, and metal layer 203), first external terminals 41 and second external terminals 42 each composed of an adhesion layer 401, a conduction layer 402, and a metal layer 403 are provided on the upper surface of the insulator 60 and in the via holes 600. The first external terminal 41 is connected to the first end 21a of the inductor wiring 21, and the second external terminal 42 is connected to the second end 21b of the inductor wiring 21. Thereby, the electronic component 1 shown in FIG. 2 is manufactured.

[0063] <Second Embodiment> FIG. 5 is a cross-sectional view showing a second embodiment of the electronic component. FIG. 5 is a cross-section including the central axis of the via portion. The second embodiment differs from the first embodiment in the configuration of the via portion of the inductor wiring. This different configuration will be described below. Other configurations are the same as those of the first embodiment, and the same reference numerals as those of the first embodiment are given and the description thereof is omitted.

[0064] As shown in FIG. 5, the via portion 211A of the inductor wiring 21A of the second embodiment has a first contact surface 211a that contacts the second electrode layer 72 and a second contact surface 211b that contacts the inductor portion 210. The second contact surface 211b is located on the same plane as the first main surface 62a of the interlayer insulating layer 62. The second contact surface 211b is the boundary surface between the inductor portion 210 and the via portion 211A. As described in the first embodiment, since the inductor portion 210 and the via portion 211 are provided continuously and integrally, it is difficult to actually distinguish the second contact surface 211b (boundary surface). Note that the second contact surface 211b may be formed so as to be distinguishable.

[0065] The first contact surface 211a and the second contact surface 211b are circular when viewed from the Z direction, but may be elliptical or polygonal. The first diameter d1 of the first contact surface 211a is smaller than the second diameter d2 of the second contact surface 211b. Here, the first diameter d1 of the first contact surface 211a refers to the equivalent diameter of the circle of the first contact surface 211a when viewed from the Z direction, and the second diameter d2 of the second contact surface 211b refers to the equivalent diameter of the circle of the second contact surface 211b when viewed from the Z direction.

[0066] According to the above configuration, in a cross section including the central axis of the via portion 211A, for example, the side surface 211c of the via portion 211A can be formed in a tapered shape so that the width of the via portion 211A becomes as small as the first contact surface 211a. Thereby, the contact area between the via portion 211A and the via holes 610 and 620 can be increased, and the adhesion between the inductor wiring 21A and the interlayer insulating layer 62 can be further improved.

[0067] In addition, since the side surface 211c of the via portion 211A can be formed in a tapered shape, the inner surfaces of the via holes 610 and 620 can also be formed in a tapered shape. Thereby, when manufacturing the inductor wiring 21A, when the adhesion layer 201 is vapor-deposited on the inner surfaces of the via holes 610 and 620 from the wider side of the openings of the via holes 610 and 620, the adhesion layer 201 easily reaches the narrower side of the openings of the via holes 610 and 620, the covering property of the adhesion layer 201 with respect to the inner surfaces of the via holes 610 and 620 is improved, and the adhesion is further improved.

[0068] As shown in FIG. 5, preferably, in a cross-section including the central axis of the via portion 211A, the side surface 211c of the via portion 211A has a tapered shape such that the width of the via portion 211A becomes smaller as it is closer to the first contact surface 211a. Here, the width of the via portion 211A refers to the size in the direction orthogonal to the central axis of the via portion 211A. Specifically, the width of the via portion 211A is the size in the X direction in FIG. 5. In a cross-section including the central axis of the via portion 211A, the side surface 211c of the via portion 211A is formed linearly, but it may also be formed in a curved shape.

[0069] According to the above configuration, since the side surface 211c of the via portion 211A is formed in a tapered shape, the contact area between the via portion 211A and the via holes 610 and 620 can be increased. Thereby, the adhesion between the inductor wiring 21A and the interlayer insulating layer 62 can be further improved.

[0070] Also, since the side surface 211c of the via portion 211A is formed in a tapered shape, the inner surfaces of the via holes 610 and 620 will also be formed in a tapered shape. Thereby, when manufacturing the inductor wiring 21A, when the adhesion layer 201 is vapor-deposited on the inner surfaces of the via holes 610 and 620 from the wider side of the openings of the via holes 610 and 620, the adhesion layer 201 can easily reach the narrower side of the openings of the via holes 610 and 620, the coverage of the adhesion layer 201 on the inner surfaces of the via holes 610 and 620 is improved, and the adhesion is further improved.

[0071] Here, a method of forming the side surface 211c of the via portion 211A into a tapered shape will be described. Compared with the manufacturing method of the first embodiment, the difference lies in the step of providing the via holes V (via holes 610 and 620) in the protective layer 61 and the interlayer insulating layer 62 shown in FIG. 4F.

[0072] As shown in FIG. 4F, when exposing the protective layer 61 and the interlayer insulating layer 62 by a photolithography process, the position of the exposure focus is controlled to make the shape of the via holes V (via holes 610, 620) a tapered shape. Specifically speaking, when the protective layer 61 and the interlayer insulating layer 62 are negative type, the position of the exposure focus is shifted toward the substrate 5 side. On the other hand, when the protective layer 61 and the interlayer insulating layer 62 are positive type, the position of the exposure focus is shifted toward the first main surface 62a side of the interlayer insulating layer 62. In this way, the side surface 211c is formed in a tapered shape.

[0073] In addition, in FIG. 5, the via portion 211 on the second end 21b side of the inductor wiring 21 has been described. However, the same may apply to the via portion 211 on the first end 21a side of the inductor wiring 21.

[0074] Note that the present disclosure is not limited to the above-described embodiments, and design changes are possible without departing from the gist of the present disclosure. For example, the respective feature points of the first and second embodiments may be combined in various ways.

[0075] In the above embodiment, there is at least one inductor wiring of the inductor element, and a plurality of inductor wirings may be stacked in the Z direction and connected in series or in parallel. Further, the inductor wiring (inductor portion) of the inductor element is what imparts inductance to the inductor element by generating magnetic flux when current flows through it, and there is no particular limitation on its structure, shape, material, etc. In particular, it is not limited to a straight line or a curve (spiral = two-dimensional curve) extending on a plane as in the embodiment, and various known wiring shapes such as meander wiring can be used.

[0076] In the above embodiment, there are at least two electrode layers of the capacitor element, and any structure may be used as long as it can store charge between the two electrode layers through the dielectric portion by applying a voltage to the two electrode layers, and there is no particular limitation on its structure, shape, material, etc. In particular, it is not limited to a plate shape as in the embodiment, and various electrode shapes such as meander shapes can be used.

[0077] In the above-described embodiment, there is one capacitor element and one inductor element, respectively. However, at least one of the capacitor element or the inductor element may be plural. According to this, the characteristics of the electronic component can be adjusted.

[0078] The present disclosure includes the following aspects. <1> A capacitor element, An inductor element electrically connected to the capacitor element, And an interlayer insulating layer disposed between the capacitor element and the inductor element Comprising The interlayer insulating layer has a first main surface, a second main surface, and a via hole penetrating the first main surface and the second main surface, The capacitor element is disposed on the second main surface side of the interlayer insulating layer, and further has a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first electrode layer and the second electrode layer, The inductor element is disposed on the first main surface side of the interlayer insulating layer, and further includes an inductor portion disposed on the first main surface and a via portion that penetrates the via hole and connects the inductor portion and the second electrode layer, and has an inductor wiring, The inductor wiring has an adhesion layer, a conduction layer laminated on the adhesion layer, and a metal layer laminated on the conduction layer, The adhesion layer is an electronic component that continuously contacts the first main surface, the inner surface of the via hole, and the second electrode layer. <2> The adhesion layer is a titanium layer, and the second electrode layer includes an aluminum layer that contacts the adhesion layer. The electronic component according to <1>. <3> The metal layer is a copper layer. The electronic component according to <1> or <2>. <4> The ratio of the thickness of the metal layer of the inductor portion in the direction orthogonal to the first main surface to the thickness of the second electrode layer in the direction orthogonal to the first main surface is 15 or more and 70 or less. The electronic component according to any one of <1> to <3>. <5> The via portion has a first contact surface that contacts the second electrode layer and a second contact surface that contacts the inductor portion. The electronic component according to any one of <1> to <4>, wherein a first diameter d1 of the first contact surface is smaller than a second diameter d2 of the second contact surface. <6> The via portion has a first contact surface that contacts the second electrode layer and a second contact surface that contacts the inductor portion. The electronic component according to any one of <1> to <5>, wherein, in a cross section including a central axis of the via portion, a side surface of the via portion has a tapered shape such that a width of the via portion becomes smaller toward the first contact surface.

Explanation of Reference Numerals

[0079] 1 Electronic component 2 Inductor element 5 Substrate 7 Capacitor element 21, 21A Inductor wiring 21a First end 21b Second end 201 Adhesive layer 202 Conductive layer 203 Metal layer 210 Inductor portion 211, 211A Via portion 211a First contact surface 211b Second contact surface 211c Side surface 41, 42 First and second external terminals 401 Adhesive layer 402 Conductive layer 403 Metal layer 410, 420 Body portion 411, 421 Via portion 60 Insulator 600 Via hole 61 Protective layer 610 Via hole 62 Interlayer insulating layer 62a First main surface 62b Second main surface 620 Via hole 71 and 72, the first and second electrode layers 701, adhesion layer 703, metal layer 74, dielectric layer 740, via hole 75, connection conductor layer 80, resist d1, first diameter d2, second diameter

Claims

1. A capacitor element, an inductor element electrically connected to the capacitor element, and an interlayer insulating layer disposed between the capacitor element and the inductor element are provided, the interlayer insulating layer has a first main surface, a second main surface, and via holes penetrating the first main surface and the second main surface, the capacitor element is disposed on the second main surface side of the interlayer insulating layer, and further has a first electrode layer, a second electrode layer, and a dielectric layer disposed between the first electrode layer and the second electrode layer, the inductor element is disposed on the first main surface side of the interlayer insulating layer, and further has an inductor portion disposed on the first main surface and a via portion penetrating the via hole to connect the inductor portion and the second electrode layer, and has an inductor wiring, the inductor wiring has an adhesion layer, a conduction layer formed to contact the adhesion layer, and a metal layer formed to contact the conduction layer, the adhesion layer is continuously in contact with the first main surface, the inner surface of the via hole, and the second electrode layer, a protective layer is provided on the first electrode layer so as to cover the second electrode layer and the dielectric layer, the interlayer insulating layer is made of an organic insulating material composed of an epoxy-based, phenol-based, liquid crystal polymer-based, polyimide-based, acrylic-based material or a mixture containing them, the protective layer is an electronic component composed of a single layer of SiN, SiO2, BPSG or a laminated structure thereof.

2. The electronic component according to claim 1, wherein the adhesion layer is a titanium layer, the second electrode layer includes an aluminum layer in contact with the adhesion layer, and the metal layer is a copper layer.

3. The electronic component according to claim 1 or 2, wherein the ratio of the thickness of the metal layer of the inductor portion in the direction orthogonal to the first main surface to the thickness of the second electrode layer in the direction orthogonal to the first main surface is 15 or more and 70 or less.

4. The via portion has a first contact surface in contact with the second electrode layer and a second contact surface in contact with the inductor portion, The electronic component according to claim 1, wherein a first diameter d1 of the first contact surface is smaller than a second diameter d2 of the second contact surface.

5. The via portion has a first contact surface in contact with the second electrode layer and a second contact surface in contact with the inductor portion, In a cross section including the central axis of the via portion, the side surface of the via portion has a tapered shape such that the width of the via portion becomes smaller toward the first contact surface. The electronic component according to claim 1.

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