Control Circuit of Step-Down Converter, Step-Down Converter, and Electronic Device

Abstract

To provide a step-down converter capable of stabilizing a switching frequency.SOLUTION: A bottom detection circuit 210 asserts a turning-on signal TURN_ON when an output voltage VOUT of a step-down converter 100 is under a bottom level VBOTTOM. A on-time generation circuit 220 is configured to measure an on-time TON=α x VOUT / VIN with an assert of a turn-on signal TURN_ON as a trigger. α is a controllable coefficient. An an-time correction circuit 240 decreases the coefficient α when a switching period TSW of a control logic 230 is longer than a reference period TREF and increases the coefficient α when the switching period TSW of the control logic 230 is shorter than the reference period TREF.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present disclosure relates to a step-down DC / DC converter (switching regulator).

Background Art

[0002] Various electronic devices such as smartphones, consumer devices such as tablet computers, in-vehicle devices, OA devices, and industrial devices are equipped with circuit components that require a power supply voltage lower than or higher than the battery voltage or the external power supply voltage. In order to supply an appropriate power supply voltage to such circuit components, a buck converter (Buck converter) or a boost converter is used.

[0003] As a control method of the buck converter, the COT (Constant On-Time) method is known. In the COT method, when the output voltage V OUT drops to a certain threshold value V TH , the high-side transistor is turned on, and the high-side transistor is kept on for a certain on-time T ON . When the on-time T ON ends, the low-side transistor is turned on. After that, when the output voltage V OUT drops to the threshold value V TH , the high-side transistor is turned on again. By repeating this operation, the output voltage V OUT can be stabilized within a voltage range near the threshold voltage V TH .

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] In the COT method, in order to keep the switching frequency constant, the on-time T ON is controlled according to the input voltage V IN and the output voltage V OUT . Specifically, when the target value of the switching frequency is f REF , T ON =V OUT / V IN ×1 / f REF …(1) By doing so, the switching frequency f can be stabilized.

[0006] The control based on Equation (1) assumes that there is no loss in the high-side transistor, low-side transistor, or inductor. However, in reality, the high-side transistor and low-side transistor have on-resistance, and the inductor also includes an equivalent series resistance ESR. These resistance components cause Equation (1) not to hold, resulting in an error in the switching frequency f.

[0007] The present disclosure has been made in such a situation, and one of the exemplary purposes of one aspect thereof is to provide a step-down converter with a stabilized switching frequency.

Means for Solving the Problem

[0008] One aspect of the present disclosure relates to a control circuit of a step-down converter. The control circuit includes a bottom detection circuit that asserts a turn-on signal when the output voltage of the step-down converter falls below a bottom level, and a second timer circuit that measures the on-time T ON triggered by the assertion of the turn-on signal. When the input voltage of the step-down converter is V IN , the output voltage is V OUT , and the controllable coefficient is α, an on-time generation circuit configured such that T ON =α·V OUT / V IN , and from the assertion of the turn-on signal to the on-time T ONDuring this period, the control logic turns on the high-side transistor and then turns on the low-side transistor until the turn-on signal is asserted next, and when the switching period of the control logic is longer than the reference period, the coefficient α is decreased, and when the switching period of the control logic is shorter than the reference period, the coefficient α is increased. An on-time correction circuit is provided.

[0009] In addition, any combination of the above components, and those obtained by mutually substituting components and expressions among methods, apparatuses, systems, etc. are also effective as aspects of the present invention.

Effects of the Invention

[0010] According to an aspect of the present disclosure, the switching frequency of the buck converter can be stabilized.

Brief Description of the Drawings

[0011]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Best Mode for Carrying Out the Invention

[0012] (Overview of Embodiment) The overview of some exemplary embodiments of the present disclosure will be described. This overview simplifies and describes some concepts of one or more embodiments for the purpose of providing a basic understanding of the embodiments as a prelude to the detailed description to follow, and does not limit the scope of the invention or the disclosure. This overview is not an all-inclusive overview of all possible embodiments, nor is it intended to identify the important elements of all embodiments or to delineate the scope of some or all aspects. For convenience, "one embodiment" may be used to refer to one embodiment (example or variation) or a plurality of embodiments (examples or variations) disclosed herein.

[0013] A control circuit according to one embodiment controls a buck converter. The control circuit includes a bottom detection circuit that asserts a turn-on signal when the output voltage of the buck converter falls below a bottom level, and a second timer circuit that measures an on-time T ON triggered by the assertion of the turn-on signal. When the input voltage of the buck converter is V IN and the output voltage is V OUT and a controllable coefficient is α, an on-time generation circuit configured such that T ON = α·V OUT / V IN a control logic that turns on the high-side transistor during the period from the assertion of the turn-on signal to the on-time T ON and then turns on the low-side transistor until the turn-on signal is asserted again, and an on-time correction circuit that decreases the coefficient α when the switching period of the control logic is longer than a reference period and increases the coefficient α when the switching period of the control logic is shorter than the reference period.

[0014] The switching period T SW of the control logic is the reference period T REFWhen it is longer, by decreasing the coefficient α, the on-time T ON becomes shorter, and as a result, the switching period T SW becomes shorter, and it can approach the reference period T REF . Conversely, when the switching period T SW of the control logic is shorter than the reference period T REF , by increasing the coefficient α, the on-time T ON becomes longer, and as a result, the switching period T SW becomes longer, and it can approach the reference period T REF . By performing this feedback control, regardless of the magnitude of the on-resistance of the high-side transistor or the low-side transistor, the switching period of the control logic can be made closer to the reference period, and the switching frequency, which is the reciprocal of the switching period, can be stabilized. This configuration has the advantage that a feedback system involving complex phase compensation, such as a PLL (Phase Locked Loop) circuit or an FLL (Frequency Locked Loop) circuit, is not required.

[0015] In one embodiment, the on-time correction circuit may include a first timer circuit that receives a switching control signal having the switching period of the control logic and starts measuring the reference period triggered by a specific edge of the switching control signal. The first timer circuit may generate a down signal when the next said specific edge of the switching control signal occurs before the measurement of the reference period is completed, and may generate an up signal when the measurement of the reference period is completed before the next specific edge of the switching control signal occurs. The on-time correction circuit may change the coefficient α based on the up signal and the down signal. According to this configuration, the on-time can be adjusted in synchronization with the switching control signal.

[0016] In one embodiment, the specific edge may be an edge corresponding to the turn-on of the high-side transistor. Thereby, at the timing of starting the measurement of the on-time, the on-time to be measured can be updated.

[0017] In one embodiment, the on-time correction circuit may include a ramp signal generation circuit that has a slope and generates a ramp signal that is reset in response to a specific edge of the switching control signal, and a comparison circuit that generates a down signal when the ramp signal is reset before reaching a reference value corresponding to a reference period and generates an up signal when the ramp signal reaches the reference value before resetting.

[0018] In one embodiment, the on-time correction circuit may include an adjustment signal generation circuit that generates an adjustment signal that increases and decreases according to the up signal and the down signal, and the coefficient α may be controlled according to the adjustment signal.

[0019] In one embodiment, the adjustment signal generation circuit may include an up-down counter that counts up according to the up signal and counts down according to the down signal.

[0020] In one embodiment, the adjustment signal generation circuit may include a charge pump circuit that receives the up signal and the down signal.

[0021] In one embodiment, the on-time generation circuit includes a capacitor, a current source that supplies a current Ia = β·V proportional to the input voltage V to the capacitor, and a comparator that compares the voltage of the capacitor with a threshold voltage V proportional to the output voltage V. The on-time T is represented by the following formula (2). IN to the capacitor, and a comparator that compares the voltage of the capacitor with a threshold voltage V proportional to the output voltage V. The on-time T is represented by the following formula (2). IN to the capacitor, and a comparator that compares the voltage of the capacitor with a threshold voltage V proportional to the output voltage V. The on-time T is represented by the following formula (2). OUT to the capacitor, and a comparator that compares the voltage of the capacitor with a threshold voltage V proportional to the output voltage V. The on-time T is represented by the following formula (2). TH to the capacitor, and a comparator that compares the voltage of the capacitor with a threshold voltage V proportional to the output voltage V. The on-time T is represented by the following formula (2). ON is represented by the following formula (2). T ON = C·V TH / Ia = C·V TH / (β·V IN ) …(2) V TH = g·V OUT If we set T ON = C·g·V OUT / (β·V IN ) …(3) That is, when α = C·g / β, the output voltage VOUT is proportional to the input voltage V IN and inversely proportional to the on-time T ON can be generated.

[0022] In one embodiment, the on-time correction circuit may vary the proportionality constant β.

[0023] In one embodiment, the current source includes a resistor R and generates a current Ib = V IN that is proportional to the input voltage V and inversely proportional to the resistor R, IN / R, and may include a voltage-current conversion circuit and a current amplification circuit that amplifies the current Ib by a gain γ to generate a current Ia.

[0024] In one embodiment, the resistor R is a variable resistor, and the on-time correction circuit may vary the resistance value of the resistor R.

[0025] In one embodiment, the gain γ of the current amplification circuit is variable, and the on-time correction circuit may vary the gain γ.

[0026] In one embodiment, the on-time generation circuit may include a threshold voltage generation circuit that generates a threshold voltage obtained by multiplying the output voltage V OUT by a gain g. The on-time correction circuit may vary the gain g.

[0027] In one embodiment, the threshold voltage generation circuit may include a filter that smoothes the switching voltage generated at the connection node of the high-side transistor and the low-side transistor.

[0028] In one embodiment, the control circuit may be integrally integrated on a single semiconductor substrate. "Integral integration" includes cases where all of the circuit components are formed on the semiconductor substrate and cases where the main circuit components are integrally integrated, and some resistors, capacitors, etc. may be provided outside the semiconductor substrate for adjusting circuit constants. By integrating the circuit on one chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

[0029] (Embodiment) Hereinafter, the present disclosure will be described with reference to the drawings based on preferred embodiments. The same or equivalent components, members, and processes shown in each drawing are denoted by the same reference numerals, and redundant descriptions will be omitted as appropriate. Further, the embodiments are illustrative rather than limiting the invention or the disclosure, and not all features and combinations thereof described in the embodiments are necessarily essential to the invention or the disclosure.

[0030] In this specification, the state where "member A is connected to member B" includes not only the case where member A and member B are physically directly connected, but also the case where member A and member B are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.

[0031] Similarly, the state where "member C is connected between member A and member B" includes not only the case where member A and member C, or member B and member C are directly connected, but also the case where they are indirectly connected via other members that do not substantially affect their electrical connection state or impair the functions and effects achieved by their combination.

[0032] FIG. 1 is a block diagram of a step-down converter 100 according to an embodiment. The step-down converter 100 receives a DC input voltage V on an input line 102 and supplies an output voltage V having a voltage level lower than the input voltage V to a load connected to an output line 104. The step-down converter 100 is of a constant voltage output type that stabilizes the output voltage V at a target level V. IN IN OUT OUT OUT(REF)

[0033] ​​​​​The step-down converter 100 includes a control IC 200 and its main circuit 110. The step-down converter 100 is of the synchronous rectification type, and the main circuit 110 includes an inductor L1, an output capacitor C1, resistors R1, R2, a high-side transistor M1, and a low-side transistor M2.

[0034] The control IC 200 controls the step-down converter 100 (main circuit 110) and stabilizes the output voltage V OUT at its target level V OUT(REF) .

[0035] The control IC 200 is a functional IC (Integrated Circuit) integrated on a single semiconductor substrate and includes an input pin (also referred to as a terminal) VIN, a switching pin SW, a ground pin GND, and a feedback pin FB. The input pin VIN is connected to the input line 102 and supplied with the input voltage V IN . The external inductor L1 is connected to the switching pin SW, and the ground pin PGND is grounded. The feedback signal V OUT based on the output voltage V FB of the step-down converter 100 is input to the feedback pin FB. For example, the feedback signal V FB is a voltage signal obtained by dividing the output voltage V OUT by the resistors R1 and R2.

[0036] In addition to the high-side transistor M1 and the low-side transistor M2 which are part of the main circuit 110, the control IC 200 includes a bottom detection circuit 210, an on-time generation circuit 220, a control logic 230, an on-time correction circuit 240, and a driver circuit 202.

[0037] The high-side transistor M1 is connected between the input pin VIN and the switching pin SW, and the low-side transistor M2 is connected between the switching pin SW and the ground pin PGND.

[0038] The high-side transistor M1 and the low-side transistor M2 may be discrete elements provided outside the control IC200. Also, the high-side transistor M1 and the low-side transistor M2 may be IGBTs (Insulated Gate Bipolar Transistors) or bipolar transistors.

[0039] The high-side transistor M1 may be of the N-type (i.e., N-channel or NPN-type), in which case a bootstrap circuit is added.

[0040] The bottom detection circuit 210 turns on the turn-on signal TURN_ON (e.g., high) when the output voltage V OUT of the step-down converter 100 falls below the bottom level V BOTTOM . The bottom detection circuit 210 receives a feedback signal V OUT indicating the output voltage V FB and a reference voltage V REF . The bottom detection circuit 210 is configured to assert the turn-on signal TURN_ON when the feedback signal V FB drops to the bottom level V REF based on the reference voltage V BOTTOM .

[0041] The configuration of the bottom detection circuit 210 is not particularly limited. For example, the reference voltage V REF may be used directly as the bottom level V BOTTOM . In this case, the bottom detection circuit 210 may include a voltage comparator that compares the feedback signal V FB with the reference voltage V REF .

[0042] Alternatively, the bottom detection circuit 210 may be composed of an error amplifier and a voltage comparator. The error amplifier in the previous stage amplifies the error between the feedback signal V FB and the reference voltage V REF to generate the bottom level V BOTTOM . The voltage comparator in the subsequent stage compares the feedback signal VFB may be compared with the bottom level V generated by the error amplifier. BOTTOM

[0043] The on-time generation circuit 220 includes a second timer circuit 222 that measures the on-time T ON triggered by the assertion of the turn-on signal TURN_ON. The second timer circuit 222 receives signals indicating the input voltage V IN and the output voltage V OUT and the on-time T measured by the second timer circuit 222 ON is represented by Equation (4) using a controllable coefficient α. T ON = α·V OUT / V IN …(4) Outputs an on-time ONTIME indicating the elapse of the on-time T. The on-time ONTIME may be a pulse signal that goes high during the on-time T ON or a signal indicating the end of the on-time T. As will be described later, α is variable according to the adjustment signal ADJ generated by the on-time correction circuit 240. ON ON

[0044] The control logic 230 sets the on-state where the high-side transistor M1 is on and the low-side transistor M2 is off from the assertion of the turn-on signal TURN_ON until the on-time T ON elapses, and then sets the off-state where the high-side transistor M1 is off and the low-side transistor M2 is on until the turn-on signal TURN_ON is asserted again. The control logic 230 generates a switching control signal SW_CTRL indicating the on-state and the off-state. The driver circuit 202 drives the high-side transistor M1 and the low-side transistor M2 according to the switching control signal SW_CTRL.

[0045] The on-time correction circuit 240 receives the switching period T of the control logic 230 SWA signal indicating this is input. For example, a switching control signal SW_CTRL may be input to the on-time correction circuit 240, or the gate signal of the high-side transistor M1 or the gate signal of the low-side transistor M2 may be input.

[0046] The on-time correction circuit 240 is based on the switching period T SW being longer than the reference period T REF to decrease the coefficient α and act on the on-time generation circuit 220 so that the switching period T SW of the control logic 230 is shorter than the reference period T REF to increase the coefficient α. The on-time correction circuit 240 generates an adjustment signal ADJ for controlling the coefficient α.

[0047] The above is the configuration of the buck converter 100. Subsequently, its operation will be described.

[0048] FIG. 2 is a waveform diagram for explaining the basic operation of the buck converter 100 in FIG. 1. In FIG. 2, the output voltage V OUT , turn-on signal TURN_ON, on-time ONTIME, switching control signal SW_CTRL, states of the high-side transistor M1 and the low-side transistor M2 are shown.

[0049] When the output voltage V OUT drops to the bottom level V BOTTOM , the turn-on signal TURN_ON is asserted and the switching control signal SW_CTRL becomes the on level (here high). As a result, the high-side transistor M1 turns on and the low-side transistor M2 turns off. Also, triggered by the assertion of the turn-on signal TURN_ON, the measurement of the on-time T ON starts. When the on-time T ON elapses, the on-time ONTIME is asserted and the switching control signal SW_CTRL becomes the off level (here low). As a result, the high-side transistor M1 turns off and the low-side transistor M2 turns on. By repeating this operation, the output voltage V OUTis stabilized within a voltage range determined according to the bottom level V BOTTOM and is stabilized within a voltage range determined according to the bottom level V

[0050] Next, the feedback control of the switching frequency will be described. FIG. 3 is a diagram for explaining the feedback control of the switching frequency.

[0051] In each switching cycle, the switching period T SWi (i = 1, 2,...) is compared with the reference period T REF and is compared with the reference period T

[0052] In the first switching cycle 1, T SW1 < T REF and therefore α increases in the next cycle. As a result, the on-time T ON2 in the second switching cycle becomes longer, and as a result, the switching period T SW2 also becomes longer than the period T SW1 of the previous cycle.

[0053] Also in the second switching cycle, T SW2 < T REF and therefore α further increases in the next cycle. As a result, the on-time T ON3 in the third switching cycle becomes even longer, and as a result, the switching period T SW3 also becomes longer than the period T SW2 of the previous cycle.

[0054] Also in the third switching cycle, T SW2 < T REF and therefore α further increases in the next cycle. As a result, the on-time T ON4 in the fourth switching cycle becomes even longer, and as a result, the switching period T SW4 also becomes longer than the period T SW3 of the previous cycle.

[0055] In the fourth switching cycle, T SW4 > T REFTherefore, α is decreased in the next cycle. As a result, the on-time T ON5 is the on-time T of the previous cycle ON4 As a result, the switching period T SW5 is the period of the previous cycle T SW4 It will be shorter.

[0056] By repeating this operation, the switching period T SW is the reference period T REF It can be stabilized to.

[0057] The operation of the step-down converter 100 has been described above.

[0058] Switching period T SW is the reference period T REF By decreasing the coefficient α when the on-time T ON As a result, the switching period T SW becomes longer, and the reference period T REF Conversely, the switching period T SW is the reference period T REF When the on-time T ON becomes longer, and the switching period T SW becomes longer, and the reference period T REF By performing this feedback control, the switching period T SW The reference period T REF and the switching period T SW The switching frequency f SW This configuration has the advantage that it does not require a feedback system with complex phase compensation, such as a PLL (Phase Locked Loop) circuit or an FLL (Frequency Locked Loop) circuit.

[0059] The present disclosure encompasses various apparatuses and methods that can be understood as the block diagrams or circuit diagrams of FIG. 1, or derived from the above descriptions, and is not limited to a specific configuration. Hereinafter, more specific configuration examples and embodiments will be described not to narrow the scope of the present disclosure, but to assist in understanding the essence and operation of the present disclosure and the present invention, and to clarify them.

[0060] FIG. 4 is a circuit diagram showing a configuration example of the on-time generation circuit 220. The second timer circuit 222 includes a second capacitor C11, a second current source CS11, a second comparator COMP11, a second switch SW11, and a threshold voltage generation circuit 224.

[0061] One end of the second capacitor C11 is grounded. The second current source CS11 supplies a current Ia = β·V proportional to the input voltage V to the second capacitor C11, where β is a proportionality constant. IN proportional to the input voltage V to the second capacitor C11. IN to the second capacitor C11.

[0062] The threshold voltage generation circuit 224 generates a first threshold voltage V proportional to the output voltage V. When the proportionality constant is g, V = g·V. The threshold voltage generation circuit 224 may input the feedback signal V as a signal indicating the output voltage V. Alternatively, the switching voltage V of the switching pin SW may be input to the threshold voltage generation circuit 224. The threshold voltage generation circuit 224 may include a low-pass filter that smoothes the switching voltage V. OUT proportional to the output voltage V. TH1 to generate a first threshold voltage V. TH1 = g·V. OUT The threshold voltage generation circuit 224 may input the feedback signal V as a signal indicating the output voltage V. FB as a signal indicating the output voltage V. OUT Alternatively, the switching voltage V of the switching pin SW may be input to the threshold voltage generation circuit 224. SW to the threshold voltage generation circuit 224. SW The threshold voltage generation circuit 224 may include a low-pass filter that smoothes the switching voltage V.

[0063] The second comparator COMP11 compares the voltage V of the second capacitor C11 with the first threshold voltage V proportional to the output voltage V. The output of the second comparator COMP11 can be used as the on-time ONTIME. C1 of the second capacitor C11 with the first threshold voltage V OUT proportional to the output voltage V. TH1 The output of the second comparator COMP11 can be used as the on-time ONTIME.

[0064] The second switch SW11 is controlled by a turn-on signal TURN_ON or another signal. When the second switch SW11 is in the on state, the voltage V of the second capacitor C11 C11 is initialized to 0V.

[0065] When the turn-on signal TURN_ON is asserted, the second switch SW11 first turns on and then turns off. When the second switch SW11 turns off, the voltage V of the second capacitor C11 C11 increases from 0V at a constant slope proportional to the current Ia with the passage of time t at a constant slope of Ia / C11 = β·V IN / C11. V C11 = Ia / C11 × t = (β·V IN / C11) × t …(5)

[0066] And after a certain time (i.e., the on-time T ON ), when the voltage V C11 reaches the threshold voltage V TH , the on-time ONTIME is asserted. Therefore, Equation (6) holds. (β·V IN / C11) × T ON = g·V OUT …(6) Therefore, the on-time T ON measured by the second timer circuit 222 is represented by Equation (7). T ON = (g·C11 / β) × V OUT / V IN …(7) That is, α = (g·C11 / β).

[0067] Therefore, the second timer circuit 222 is configured such that at least one of g, C11, and β changes in response to the adjustment signal ADJ.

[0068] An adjustment signal ADJ may be input to the second current source CS11, and β may be changed according to the adjustment signal ADJ. Alternatively, the second capacitor C11 may be configured with a variable capacitance, and the capacitance value C11 may be controllable according to the adjustment signal ADJ. Alternatively, the gain g of the threshold voltage generation circuit 224 may be configured to be variable, and the gain g may be controllable according to the adjustment signal ADJ. Note that when controlling the capacitance of the second capacitor C11 or the gain g, it is necessary to control with the opposite polarity to β.

[0069] A configuration for controlling β of the second current source CS11 will be described.

[0070] FIG. 5 is a circuit diagram showing a configuration example of the second current source CS11. The second current source CS11 includes a voltage-current conversion circuit (V / I conversion circuit) 226 and a current amplification circuit 228. The V / I conversion circuit 226 includes a resistor R21 and generates a current Ib that is proportional to the input voltage V IN and inversely proportional to the resistor R21. Ib = V IN / R21 For example, the V / I conversion circuit 226 includes an operational amplifier OP21, a transistor M21, and a resistor R21.

[0071] The current amplification circuit 228 amplifies the current Ib with a gain γ and generates a current Ia. For example, the current amplification circuit 228 may be a current mirror circuit including transistors M22 and M23, and the size ratio of the transistors M22 and M23 is the current amplification factor γ.

[0072] In this second current source CS11, Equation (8) holds. Ia = Ib × γ = V IN / R21 × γ …(8) That is, β = γ / R21 Therefore, in order to control β, the resistance value of the resistor R21 may be made variable, or the size of the transistor M23 (or M22) may be configured to be variable.

[0073] Subsequently, the configuration of the on-time correction circuit 240 will be described.

[0074] FIG. 6 is a block diagram showing a configuration example of the on-time correction circuit 240. The on-time correction circuit 240 includes a first timer circuit 242 and an adjustment signal generation circuit 244.

[0075] The first timer circuit 242 receives a switching control signal SW_CTRL having a switching period T SW and starts measuring a reference period T using a specific edge (either a positive edge or a negative edge, hereinafter a positive edge) of the switching control signal SW_CTRL as a trigger. REF

[0076] Before the first timer circuit 242 completes the measurement of the reference period T, when the next specific edge (positive edge) of the switching control signal SW_CTRL occurs, the on-time correction circuit 240 generates a down signal DN. Also, when the measurement of the reference period T is completed before the next specific edge of the switching control signal SW_CTRL occurs, an up signal UP is generated. REF REF

[0077] The adjustment signal generation circuit 244 generates an adjustment signal ADJ that increases and decreases according to the up signal UP and the down signal DN.

[0078] When the adjustment signal ADJ is a digital signal, the adjustment signal generation circuit 244 can be constituted by an up-down counter. When the adjustment signal ADJ is an analog signal, the adjustment signal generation circuit 244 may be constituted by a charge pump.

[0079] FIG. 7 is a diagram for explaining the operation of the on-time correction circuit 240 of FIG. 6. The upper part shows the case where the switching frequency is high, and the lower part shows the case where the switching frequency is low. The first timer circuit 242 starts the timer using the positive edge E1 of the switching control signal SW_CTRL as a trigger. When the switching frequency is high as in the upper part, before the elapse of T REF the next edge E2 occurs, so a down signal DN is generated. ​​​

[0080] If the switching frequency is slow as described below, before the next edge E2 occurs, the measurement of T REF is completed (times out), and an up signal DN is generated.

[0081] FIG. 8 is a circuit diagram showing a configuration example of the first timer circuit 242.

[0082] The first timer circuit 242 includes a lamp signal generation circuit 250 and a comparison circuit 252.

[0083] The lamp signal generation circuit 250 generates a lamp signal V RAMP This lamp signal V RAMP has a constant slope and is reset in response to a specific edge (positive edge) of the switching control signal SW_CTRL.

[0084] The comparison circuit 252 generates a down signal DN when the lamp signal V RAMP is reset before reaching the reference value V corresponding to the reference period T REF and generates an up signal UP when the lamp signal V REF reaches the reference value V RAMP before reset. REF upon reaching the reference value V.

[0085] The lamp signal generation circuit 250 includes a first current source CS21, a first capacitor C21, and a first switch SW21.

[0086] The first current source CS21 generates a constant current Ic. The first switch SW21 is controlled in response to an edge detection signal EDGE which is a pulse based on a specific edge (positive edge) of the switching control signal SW_CTRL. The edge detection signal EDGE may be a turn-on signal TURN_ON. The voltage V of the capacitor C21 becomes the lamp signal V RAMP

[0087] ​The comparison circuit 252 may include a first comparator COMP21. The first comparator COMP21 compares the ramp signal V RAMP with a reference value V REF . If the output (comparison signal) COMPOUT of the first comparator COMP21 is low during one switching period, it represents a down signal DN, and if it transitions high during one switching period, it represents an up signal UP.

[0088] The subsequent adjustment signal generation circuit 244 includes an up-down counter 254. The up-down counter 254 counts up in a cycle where the comparison signal COMPOUT is high and counts down in a cycle where the comparison signal COMPOUT is low.

[0089] The first timer circuit 242 in FIG. 8 basically has the same configuration as the second timer circuit 222 of the on-time generation circuit 220. In this case, corresponding circuit elements (C11 and C21, SW11 and SW21, CS11 and CS12) may be arranged closely (paired) on a semiconductor chip so that the relative variation in circuit constants becomes small.

[0090] FIG. 9 is an operation waveform diagram of the first timer circuit 242 in FIG. 8. In the first cycle, since the switching period T SW1 is shorter than the reference period T REF , the ramp signal V RAMP does not reach the reference value V REF , the comparison signal COMPOUT is low, that is, a down signal DN is generated. As a result, the count value of the up-down counter 254 decreases.

[0091] When the count value of the up-down counter 254 represents the switching frequency, the above-mentioned coefficient α is controlled with a polarity opposite to that of the count value of the up-down counter 254. That is, when the count value of the up-down counter 254 decreases, the on-time T ON2 of the second cycle is longer than the on-time T ON1 of the first cycle, and as a result, the switching period T SW2 also becomes longer.

[0092] ON time T ON2 As a result of the increase in the ON time T, the switching period T SW2 becomes longer than the reference period T REF Let's assume that. In that case, the lamp signal V RAMP exceeds the reference value V REF and the comparison signal COMPOUT goes high, that is, the up signal UP is generated. As a result, the count value of the up-down counter 254 increases.

[0093] (Application) FIG. 10 is a diagram showing an example of an electronic device 700 including a step-down converter 100 according to an embodiment. The electronic device 700 is a battery-driven device such as, for example, a mobile phone terminal, a digital camera, a digital video camera, a tablet terminal, a portable audio player, or the like. The electronic device 700 includes a housing 702, a battery 704, a microprocessor 706, and a step-down converter 100. The step-down converter 100 receives the battery voltage V BAT (=V IN ) from the battery 704 at its input terminal and supplies the output voltage V OUT to the microprocessor 706 or other load connected to its output terminal.

[0094] The type of the electronic device 700 is not limited to battery-driven devices, and it may be an in-vehicle device, an OA device such as a facsimile machine, or an industrial device.

[0095] It is understood by those skilled in the art that the embodiments are illustrative, that there are various modifications to the combination of each of these components and each processing process, that such modifications are also included in the present disclosure, and that they can constitute the scope of the present invention.

Description of Reference Numerals

[0096] 100 Step-down converter 102 Input line 104 Output line 110 Main circuit M1 High-side Transistor M2 Low-side Transistor L1 Inductor C1 Output Capacitor 200 Control IC 202 Driver Circuit 210 Bottom Detection Circuit 220 On-time Generation Circuit 222 Second Timer Circuit 224 Threshold Voltage Generation Circuit C11 Second Capacitor CS11 Second Current Source COMP11 Second Comparator SW11 Second Switch 226 V / I Conversion Circuit 228 Current Amplification Circuit 230 Control Logic 240 On-time Correction Circuit 242 First Timer Circuit 244 Regulation Signal Generation Circuit 250 Lamp Signal Generation Circuit C21 First Capacitor CS21 First Current Source SW21 First Switch 252 Comparison Circuit COMP21 First Comparator 700 Electronic Device 702 Housing 704 Battery 706 Microprocessor

Claims

1. A control circuit for a buck converter, a bottom detection circuit that asserts a turn-on signal when the output voltage of the buck converter falls below a bottom level; A second timer circuit capable of measuring an on-time T triggered by an assertion of the turn-on signal, where an input voltage of the step-down converter is V ＯＮ and an output voltage is V ＩＮ When, assuming a controllable coefficient is α, T ＯＵＴ = α·V ＯＮ / V ＯＵＴ / V ＩＮ and an on-time generation circuit configured to satisfy the equation, From the assertion of the turn-on signal to the on-time T ＯＮ During this period, the high-side transistor is turned on, and subsequently, control logic that turns on the low-side transistor until the turn-on signal is asserted next; an on-time correction circuit that decreases the coefficient α when a switching period, which is the sum of the on-time of the high-side transistor and the off-time of the high-side transistor, is longer than a reference period, and increases the coefficient α when the switching period is shorter than the reference period; A control circuit comprising:

2. The on-time correction circuit includes a first timer circuit that receives a switching control signal having the switching period and starts measuring the reference period triggered by a specific edge of the switching control signal; the first timer circuit generates a down signal when the next specific edge of the switching control signal occurs before completing the measurement of the reference period, and generates an up signal when the measurement of the reference period is completed before the next specific edge of the switching control signal occurs; The control circuit according to claim 1, wherein the on-time correction circuit changes the coefficient α based on the up signal and the down signal.

3. The control circuit according to claim 2, wherein the specific edge is an edge corresponding to the turn-on of the high-side transistor.

4. The first timer circuit includes a ramp signal generation circuit that has a slope and generates a ramp signal that is reset in response to the specific edge of the switching control signal; a comparison circuit that generates the down signal when the ramp signal is reset before reaching a reference value corresponding to the reference period, and generates the up signal when the ramp signal reaches the reference value before reset; The control circuit according to claim 2 or 3, comprising:

5. The control circuit according to any one of claims 2 to 4, wherein the on-time correction circuit further includes an adjustment signal generation circuit that generates an adjustment signal that increases and decreases according to the up signal and the down signal, and controls the coefficient α according to the adjustment signal.

6. The control circuit according to claim 5, wherein the adjustment signal generation circuit is an up-down counter that counts up according to the up signal and counts down according to the down signal.

7. The second timer circuit includes a capacitor, With β as the proportionality constant, the input voltage V ＩＮ proportional current Ia = β·V ＩＮ a current source that supplies the capacitor with Compare the voltage of the capacitor with a threshold voltage proportional to the output voltage V ＯＵＴ and a comparator that compares them The control circuit according to any one of claims 1 to 6, including

8. The control circuit according to claim 7, wherein the on-time correction circuit changes the proportionality constant β.

9. The current source is including a resistor R, and the input voltage V ＩＮ is proportional to, and the current Ib = V ＩＮ / R that is inversely proportional to the resistor R to generate a voltage-current conversion circuit, a current amplification circuit that amplifies the current Ib by a gain γ to generate the current Ia, The control circuit according to claim 7 or 8, including

10. The control circuit according to claim 9, wherein the resistor R is a variable resistor, and the on-time correction circuit changes the resistance value of the resistor R.

11. The control circuit according to claim 9, wherein the gain γ of the current amplification circuit is variable, and the on-time correction circuit changes the gain γ.

12. The on-time generation circuit includes a threshold voltage generation circuit that generates the threshold voltage obtained by multiplying the output voltage V ＯＵＴ by a gain g. The control circuit according to claim 9, wherein the on-time correction circuit changes the gain g.

13. The control circuit according to claim 12, wherein the threshold voltage generation circuit includes a filter that smoothes the switching voltage generated at the connection node of the high-side transistor and the low-side transistor.

14. The control circuit according to any one of claims 1 to 13, which is integrally formed on a single semiconductor substrate.

15. A step-down converter including the control circuit according to any one of claims 1 to 14.

16. An electronic device including the control circuit according to any one of claims 1 to 14.

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