III-nitride-based high-frequency amplifier having a backside source terminal, a gate terminal, and / or a drain terminal

Abstract

An RF amplifier is provided that includes an interconnect structure 270 and a III-nitride-based RF amplifier die 210 mounted on the interconnect structure. The III-nitride-based RF amplifier die includes a semiconductor layer structure 230. A plurality of unit cell transistors are provided on an upper surface of the semiconductor layer structure, and a gate terminal 222, a drain terminal 224, and a source terminal 226 are provided on a lower surface of the semiconductor layer structure adjacent to the interconnect structure.

Description

Technical Field

[0001] This application claims priority under 35 U.S.C. § 119 to U.S. Provisional Patent Application No. 63 / 004,962, filed Apr. 3, 2020, the entire content of which is incorporated herein by reference.

[0002] The present invention relates to microelectronic devices, and more particularly, to group-III nitride-based radio frequency (RF) amplifiers.

Background Art

[0003] RF amplifiers are widely used in cellular communication systems and other applications. RF amplifiers are typically formed as semiconductor integrated circuit chips. Most RF amplifiers are implemented in silicon or using wide-bandgap semiconductor materials such as silicon carbide (SiC) and group-III nitride materials. As used herein, the term “group-III nitride” refers to semiconductor compounds formed between nitrogen and elements of group III of the periodic table, usually aluminum (Al), gallium (Ga), and / or indium (In). This term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds have an empirical formula in which 1 mole of nitrogen is combined with a total of 1 mole of group-III elements.

[0004] Silicon-based RF amplifiers are typically implemented using laterally diffused metal oxide semiconductor (LDMOS) transistors. Silicon LDMOS RF amplifiers can exhibit a high level of linearity and can be relatively inexpensive to manufacture. Group-III nitride-based RF amplifiers are typically implemented using high electron mobility transistors (HEMTs) and are used mainly in applications that require high output and / or high-frequency operation where LDMOS transistor amplifiers may have inherent performance limitations.

[0005] The RF amplifier can include one or more amplification stages, and each stage is typically implemented as a transistor amplifier. To improve the output power and current handling capacity, the RF amplifier is typically implemented in a "unit cell" configuration where a number of individual "unit cell" transistors are electrically arranged in parallel. The RF amplifier may be implemented as a single integrated circuit chip or "die", or may include multiple dies. When multiple RF amplifier dies are used, these dies may be connected in series and / or in parallel.

[0006] The RF amplifier often includes a matching circuit, such as an impedance matching circuit designed to improve the impedance match between the RF amplifier die and the transmission line connected thereto for an RF signal at the fundamental operating frequency, and a harmonic termination circuit designed to at least partially terminate harmonics, such as second and third order harmonics, that may be generated during device operation. The RF amplifier die, as well as the impedance matching and harmonic termination circuits, may be encapsulated within a package. Electrical leads may extend from the package for electrically connecting the RF amplifier to external circuit elements such as input and output RF transmission lines and a bias voltage source.

[0007] As described above, in many cases, group-III nitride-based RF amplifiers are used in high-power and / or high-frequency applications. Typically, a high level of heat is generated within a group-III nitride-based RF amplifier die during operation. If the RF die gets too hot, the performance of the RF amplifier (e.g., output power, efficiency, linearity, gain, etc.) may degrade and / or the RF amplifier die may be damaged. Thus, group-III nitride-based RF amplifiers are typically mounted within a package that can be optimized for heat removal. FIGS. 1A and 1B show a conventional packaged group-III nitride-based RF amplifier. In particular, FIG. 1A is a schematic side view of a conventional packaged group-III nitride-based RF amplifier 100, and FIG. 1B is a schematic cross-sectional view of an RF transistor amplifier die included in the packaged group-III nitride-based RF transistor amplifier 100, the cross-section being taken along line 1B-1B of FIG. 1A. FIGS. 1A-1B (and various other figures) are highly simplified figures, and it will be understood that an actual RF amplifier may include more unit cells as well as various circuits and elements not shown in the simplified figures herein.

[0008] As shown in FIG. 1A, a group-III nitride-based RF amplifier 100 includes an RF amplifier die 110 mounted within an open-cavity package 170. The package 170 includes a gate lead 172, a drain lead 174, a metal flange 176, and a ceramic sidewall and lid 178. The RF transistor amplifier die 110 is mounted on the upper surface of the metal flange 176 within a cavity formed by the metal flange 176 and the ceramic sidewall and lid 178. The RF amplifier die 110 has a top side 112 and a bottom side 114. The RF amplifier die 110 includes a bottom-side (also referred to as the "back" surface) metallization structure 120, a semiconductor layer structure 130, and a top-side metallization structure 140, which are sequentially stacked. The back-surface metallization structure 120 includes a metal source terminal 126. The RF amplifier 100 may be a HEMT-based RF amplifier, in which case the semiconductor layer structure 130 can include at least a channel layer and a barrier layer, which are typically formed on a semiconductor or insulating growth substrate (such as a SiC or sapphire substrate). The top-side metallization structure 140 includes, among other things, a gate terminal 142 and a drain terminal 144.

[0009] The input matching circuit 190 and / or the output matching circuit 192 may also be mounted within the housing 170. The matching circuits 190, 192 are impedance matching circuits that respectively match the impedance of the fundamental wave component of the RF signal input to or output from the RF transistor amplifier 100 to the input or output impedance of the RF transistor amplifier die 110, and / or harmonic termination circuits configured to short-circuit harmonics such as the second or third harmonic of the fundamental wave RF signal that may be present at the input or output of the RF transistor amplifier die 110 to ground. As schematically shown in FIG. 1A, the input matching circuit 190 and the output matching circuit 192 may be mounted on the metal flange 176. The gate lead 172 may be connected to the input matching circuit 190 by one or more first bond wires 182, and the input matching circuit 190 may be connected to the gate terminal 142 of the RF amplifier die 110 by one or more second bond wires 183. Similarly, the drain lead 174 may be connected to the output matching circuit 192 by one or more fourth bond wires 185, and the output matching circuit 192 may be connected to the drain terminal 144 of the RF amplifier die 110 by one or more third bond wires 184. The source terminal 126 of the RF transistor amplifier die 110 may be directly mounted on the metal flange 176. The metal flange 176 can provide an electrical connection to the source terminal 126 and can also function as a heat dissipation structure. The first to fourth bond wires 182 to 185 may form part of the input and / or output matching circuits. The gate lead 172 and the drain lead 174 can extend through the ceramic sidewall 178. The housing can include a plurality of components such as a lower portion of the sidewall that forms a frame supporting the gate and drain leads 172, 174, and a lid disposed on the frame. The interior of the device can include an air-filled cavity.

[0010] FIG. 1B is a schematic cross-sectional view of the RF amplifier die 110 taken through a portion of the top-side metallization structure 140. Dielectric layers that insulate the various conductive elements of the top-side metallization structure 140 from each other are not shown in FIG. 1B for simplicity of the drawing.

[0011] As shown in FIG. 1B, the RF amplifier die 110 comprises a group-III nitride-based HEMT RF amplifier having a plurality of unit cell transistors 116 each including a gate finger 152, a drain finger 154, and a source finger 156. The gate fingers 152 are electrically connected to a common gate bus 146, and the drain fingers 154 are electrically connected to a common drain bus 148. The gate bus 146 is electrically connected to a gate terminal 142 implemented as a gate bond pad (see FIG. 1A) (e.g., via a conductive via extending upward from the gate bus 146), and the drain bus 148 is electrically connected to a drain terminal 144 implemented as a drain bond pad (see FIG. 1A) (e.g., via a conductive via extending upward from the drain bus 148). The source fingers 156 are electrically connected to a source terminal 126 via a plurality of conductive source vias 166 extending through the semiconductor layer structure 130. The conductive source vias 166 can include metal-plated vias extending completely through the semiconductor layer structure 130.

[0012] Referring back to FIG. 1A, the metal flange 176 can function as a heat sink to dissipate heat generated in the RF amplifier die 110. The heat is mainly generated at the top of the RF amplifier die 110 where a relatively high current density is generated, for example, in the channel region of the unit cell transistors 116. This heat can be transferred to the metal flange 176 through both the source vias 166 and the semiconductor layer structure 130.

[0013] FIG. 1C is a schematic side view of a conventional packaged group III nitride-based RF transistor amplifier 100' similar to the RF transistor amplifier described above with reference to FIG. 1A. The RF transistor amplifier 100' differs from the RF transistor amplifier 100 in that it includes a different package 170'. The package 170' includes a metal submount 176 (which functions as a metal heat sink and can be implemented as a metal slug), as well as gate leads 172' and drain leads 174'. In some embodiments, a metal lead frame may be formed that is processed to provide the metal submount 176 and / or the gate leads 172' and drain leads 174'. The RF transistor amplifier 100' also includes a plastic overmold 178' that at least partially surrounds the RF transistor amplifier die 110, the leads 172', 174', and the metal submount 176. The plastic overmold 178' replaces the ceramic sidewalls and lid 178 included in the RF transistor amplifier 100.

[0014] Depending on the embodiment, the packaged transistor amplifier 100' can include, for example, a monolithic microwave integrated circuit (MMIC) as an RF transistor amplifier die 110. In this case, the RF transistor amplifier die 110 incorporates a plurality of discrete devices. Examples of such group III nitride-based high-frequency amplifiers are disclosed, for example, in U.S. Patent No. 9,947,616, the entire content of which is incorporated herein by reference. When the RF transistor amplifier die 110 is in an MMIC embodiment, the input matching circuit 190 and / or the output matching circuit 192 may be omitted (since they may instead be implemented within the RF transistor amplifier die 110), and the bond wires 182 and / or 185 can extend directly from the gate lead 172' and the drain lead 174' to the gate terminal 142 and the drain terminal 144. In some embodiments, the packaged RF transistor amplifier 100 can include a plurality of RF transistor amplifier dies connected in series to form a multi-stage RF transistor amplifier, and / or a plurality of transistor dies arranged in a plurality of paths (e.g., in parallel) to form an RF transistor amplifier having a plurality of RF transistor amplifier dies and a plurality of paths, such as a Doherty amplifier configuration.

Prior Art Documents

Patent Documents

[0015]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

[0016] According to an embodiment of the present invention, an RF amplifier is provided that includes an interconnect structure and a group-III nitride-based RF amplifier die mounted on the interconnect structure. The group-III nitride-based RF amplifier die includes a semiconductor layer structure, and a gate terminal, a source terminal, and a drain terminal on the semiconductor layer structure. A plurality of unit cell transistors are provided on top of the semiconductor layer structure, and at least two of the gate terminal, the drain terminal, and the source terminal are provided on the lower surface of the semiconductor layer structure adjacent to the interconnect structure.

[0017] In some embodiments, the drain terminal may be electrically connected to the unit cell transistor via one or more conductive drain vias, and / or the gate terminal may be electrically connected to the unit cell transistor via one or more conductive gate vias.

[0018] In some embodiments, the semiconductor layer structure may include at least a growth substrate, a channel layer, and a barrier layer, and the channel layer is between the growth substrate and the barrier layer. In some embodiments, the group-III nitride-based RF amplifier die further includes a metallization structure including a plurality of gate fingers, a plurality of drain fingers, and a plurality of source fingers on the barrier layer on the opposite side of the channel layer. In these embodiments, the gate fingers may be electrically connected to the gate terminal via one or more conductive gate vias, and the drain fingers may be electrically connected to the drain terminal via one or more conductive drain vias.

[0019] In some embodiments, one or more conductive gate vias and one or more conductive drain vias may be metal plated vias that extend through the semiconductor layer structure or at least through the growth substrate.

[0020] In some embodiments, the interconnect structure can include a gate pad electrically connected to the gate terminal, a drain pad electrically connected to the drain terminal, and a source pad electrically connected to the source terminal. In an exemplary embodiment, the gate pad, the drain pad, and the source pad may be electrically connected to the gate terminal, the drain terminal, and the source terminal, respectively, via contacts such as conductive epoxy patterns or solder bumps.

[0021] In some embodiments, the gate terminal may overlap the gate pad along a first axis perpendicular to the top surface of the interconnect structure, the drain terminal may overlap the drain pad along a second axis perpendicular to the top surface of the interconnect structure, and / or the source terminal may overlap the source pad along a third axis perpendicular to the top surface of the interconnect structure.

[0022] In some embodiments, all of the one or more conductive gate vias, the one or more conductive drain vias, and the one or more conductive source vias can have substantially the same shape and substantially the same cross-sectional area.

[0023] In some embodiments, the interconnect structure can include at least a first portion of the integrated circuit. In some embodiments, one or more conductive gate vias can constitute a second portion of the integrated circuit.

[0024] According to a further embodiment of the present invention, an RF amplifier is provided that includes an interconnect structure having a gate pad connected to an input matching circuit, a drain pad connected to an output matching circuit, and a source pad coupled to a heat dissipation structure. These RF amplifiers also include a Group-III nitride-based RF amplifier die mounted on the interconnect structure. The Group-III nitride-based RF amplifier die includes a semiconductor layer structure, a gate terminal on a first side of the semiconductor layer structure that overlaps the gate pad along a first axis perpendicular to the upper surface of the interconnect structure, a drain terminal on a first side of the semiconductor layer structure that overlaps the drain pad along a second axis perpendicular to the upper surface of the interconnect structure, a source terminal on a first side of the semiconductor layer structure that overlaps the source pad along a third axis perpendicular to the upper surface of the interconnect structure, a conductive gate via extending from a second side of the semiconductor layer structure to the first side of the semiconductor layer structure and electrically connected to the gate terminal, and a conductive drain via extending from a second side of the semiconductor layer structure to the first side of the semiconductor layer structure and electrically connected to the drain terminal.

[0025] In some embodiments, the Group-III nitride-based RF amplifier die may further include a plurality of gate fingers, drain fingers, and source fingers on a second side of the semiconductor layer structure, and at least a portion of the gate fingers may be electrically connected to the gate terminal via a conductive gate via, and at least a portion of the drain fingers may be electrically connected to the drain terminal via a conductive drain via.

[0026] The gate pad, drain pad, and source pad may be electrically connected to the gate terminal, drain terminal, and source terminal, respectively, via a conductive epoxy pattern.

[0027] In some embodiments, the RF amplifier die can further include a conductive source via extending from a second side of the semiconductor layer structure to the first side of the semiconductor layer structure and electrically connected to the source terminal.

[0028] In some embodiments, the conductive gate vias, the conductive drain vias, and the conductive source vias can all have substantially the same shape and substantially the same cross-sectional area.

[0029] According to a further embodiment of the present invention, an RF amplifier is provided that includes a Group-III nitride-based RF amplifier die. The Group-III nitride-based RF amplifier die includes a semiconductor layer structure including a channel layer and a barrier layer on the channel layer, a gate terminal, a drain terminal, a source terminal, a plurality of gate fingers electrically connected to the gate terminal via at least one conductive gate via, a plurality of drain fingers electrically connected to the drain terminal via at least one conductive drain via, and a plurality of source fingers electrically connected to the source terminal via at least one conductive source via. The gate fingers, the drain fingers, and the source fingers are all on a first side of the semiconductor layer structure. Further, the gate terminal, the drain terminal, and the source terminal are all on a second side opposite the first side of the semiconductor layer structure.

[0030] In some embodiments, the semiconductor layer structure may further include a growth substrate, and the channel layer may be between the growth substrate and the barrier layer.

[0031] In some embodiments, at least one conductive gate via and at least one conductive drain via may extend completely through the growth substrate.

[0032] In some embodiments, at least one conductive gate via and at least one conductive drain via may each include a metal-plated via that extends completely through the semiconductor layer structure.

[0033] In some embodiments, the RF amplifier may further include an interconnect structure including a gate pad electrically connected to the gate terminal, a drain pad electrically connected to the drain terminal, and a source pad electrically connected to the source terminal.

[0034] The gate pad, drain pad, and source pad may be electrically connected to the gate terminal, drain terminal, and source terminal, respectively, via a conductive epoxy pattern.

[0035] According to still other embodiments of the present invention, a group-III nitride-based RF amplifier die is provided that includes a semiconductor layer structure having a top side and a bottom side opposite the top side, a plurality of gate fingers on the top side of the semiconductor layer structure, and gate, drain, and source terminals on the bottom side of the semiconductor layer structure.

[0036] In some embodiments, the group-III nitride-based RF amplifier die may further include a plurality of drain fingers on the top side of the semiconductor layer structure, a plurality of source fingers on the top side of the semiconductor layer structure, one or more conductive gate vias, one or more conductive drain vias, and one or more conductive source vias. The gate terminal may be electrically connected to the plurality of gate fingers via one or more conductive gate vias, the drain terminal may be electrically connected to the plurality of drain fingers via one or more conductive drain vias, and the source terminal may be electrically connected to the plurality of source fingers via one or more conductive source vias.

[0037] In some embodiments, the semiconductor layer structure may include a growth substrate, a channel layer, and a barrier layer, where the channel layer is between the growth substrate and the barrier layer, and one or more conductive gate vias, one or more conductive drain vias, and one or more conductive source vias may extend completely through the growth substrate.

Brief Description of the Drawings

[0038]

Figure 1A

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DETAILED DESCRIPTION OF THE INVENTION

[0039] Conventional group-III nitride-based RF amplifiers such as the RF amplifier 100 of FIGS. 1A-1B can use bond wires to connect the RF amplifier die 110 to the gate lead 172 and the drain lead 174. These bond wires have an inherent inductance that may be used to implement part of the inductor in the impedance matching circuit and / or harmonic termination circuit of the RF amplifier. The amount of inductance provided can be changed by varying the length and / or cross-sectional area (e.g., diameter) of the bond wire so that the bond wire provides the desired amount of inductance. Unfortunately, as the application migrates to higher frequencies, the inductance of the bond wire may exceed the desired amount of inductance for the impedance matching circuit and / or harmonic termination circuit. When this occurs, bond wires having a very short and / or large cross-sectional area may be used in an attempt to reduce the inductance to an appropriate level. However, very short bond wires can be difficult to solder in place, which can increase manufacturing costs and / or lead to an increase in device failure rates. Bond wires having a large cross-sectional area may require larger gate bond pads and drain bond pads on the RF amplifier die, which requires an increase in the overall size of the RF amplifier die, which is also undesirable. Further, in some higher frequency applications, even very short bond wires with a large cross-sectional area may have too much inductance for the matching network to properly terminate, for example, second or third order harmonics. The RF amplifier may be implemented as an MMIC device to avoid the problem of the bond wire having too much inductance, but MMIC RF amplifiers are costly to manufacture, can only be used over a narrow frequency range, and have reduced flexibility.

[0040] According to an embodiment of the present invention, a group-III nitride-based RF amplifier is provided that includes an RF amplifier die having a gate terminal, a drain terminal, and a source terminal, all of which are located on the back surface of the RF amplifier die. The gate terminal, the drain terminal, and the source terminal may all be connected to corresponding gate pads, drain pads, and source pads on the interconnect structure using bump technologies such as solder bumps, conductive epoxy, or other low-inductance electrical connections, without the need for bond wires included in the conventional RF amplifiers of FIGS. 1A-1C. The RF amplifier die may include one or more gate vias and / or one or more drain vias used to connect a gate bus and / or a drain bus on the top side of the RF amplifier die to respective gate and drain terminals on the back surface of the RF amplifier die. The length of the conductive vias may be only a fraction (e.g., 10-30%) of the length of the conventional bond wires, and thus, the inductance of the connection between the gate and drain buses and the interconnect structure can be significantly reduced. As a result, without implementing the RF amplifier as a MMIC device, an impedance matching circuit and / or a harmonic termination circuit can be configured to have a desired amount of inductance. Accordingly, the size of the RF amplifier die can be reduced without degrading its performance, and since the frequency-specific portion of the device can be implemented as a separate chip or circuit, it can be used for applications in various different frequency bands.

[0041] Furthermore, wire bonding apparatuses typically used in mass production may have a tolerance of + / -0.0254 mm (1 mil), which means that the length of any particular wire bond can vary by about 0.1016 mm (4 mils). In high-frequency applications, the inductance variation associated with a 0.1016 mm (4 mil) wire bond can be quite large, so if the bond wire is 0.0254 to 0.0508 mm (1 to 2 mils) too short or too long from the desired nominal length, the performance of the matching circuit may degrade. By forming gate terminals and drain terminals on the back surface of the device and using bump technology to connect these terminals to corresponding pads on the interconnect structure, this process variation can be significantly eliminated, resulting in improved performance.

[0042] According to some embodiments of the present invention, an RF amplifier is provided that includes an interconnect structure and a group-III nitride-based RF amplifier die mounted on the interconnect structure. The group-III nitride-based RF amplifier die includes a semiconductor layer structure. A plurality of unit cell transistors are provided on top of the semiconductor layer structure, and gate terminals, drain terminals, and source terminals are provided on the bottom surface of the semiconductor layer structure adjacent to the interconnect structure. The gate terminals are electrically connected to the unit cell transistors via one or more conductive gate vias, the drain terminals are electrically connected to the unit cell transistors via one or more conductive drain vias, and the source terminals are electrically connected to the unit cell transistors via one or more conductive source vias. The gate vias, drain vias, and source vias can extend completely through the semiconductor layer structure.

[0043] The unit cell transistor may be a HEMT device, and each unit cell transistor may include a growth substrate, a channel layer, and a barrier layer. The channel layer is between the growth substrate and the barrier layer. The RF amplifier die may further include a top metallization structure having a plurality of gate fingers, a plurality of drain fingers, and a plurality of source fingers on the barrier layer on the opposite side of the channel layer. The gate fingers may be electrically connected to a gate terminal via one or more conductive gate vias, and the drain fingers may be electrically connected to a drain terminal via one or more conductive drain vias. The conductive gate vias and the conductive drain vias may be metal plated vias extending through the semiconductor layer structure or at least through the growth substrate.

[0044] The interconnect structure may include a gate pad electrically connected to the gate terminal, a drain pad electrically connected to the drain terminal, and a source pad electrically connected to the source terminal. In an exemplary embodiment, the gate pad, the drain pad, and the source pad may be electrically connected to the gate terminal, the drain terminal, and the source terminal respectively via a conductive epoxy pattern or a solder bump. In some embodiments, the interconnect structure may include at least a first portion of an integrated circuit. One or more conductive gate vias may constitute a second portion of the integrated circuit.

[0045] Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings.

[0046] Figures 2A to 2F show a group III nitride-based RF amplifier 200 according to a particular embodiment of the present invention. In particular, FIG. 2A is a schematic side view of the group III nitride-based RF amplifier 200. FIG. 2B is a schematic cross-sectional view of an RF amplifier die 210, which is part of the group III nitride-based RF amplifier 200 of FIG. 2A, taken along line 2B-2B of FIG. 2A. FIGS. 2C to 2F are schematic cross-sectional views of the RF amplifier die 210 taken along lines 2C-2C to 2F-2F of FIG. 2B, respectively. FIG. 2G is a schematic bottom view of the RF amplifier die 210. Finally, FIG. 2H is a circuit diagram of the group III nitride-based RF amplifier 200.

[0047] As shown in FIG. 2A, the group III nitride-based RF amplifier 200 includes an RF amplifier die 210 mounted on the upper surface of an interconnection structure 270. The RF amplifier die 210 has a top side 212 and a bottom side 214. The RF amplifier die 210 includes a bottom-side metallization structure 220, a semiconductor layer structure 230, and a top-side metallization structure 240, which are sequentially stacked. The bottom-side metallization structure 220 includes a gate terminal 222, a drain terminal 224, and a source terminal 226. The RF amplifier 200 may be a HEMT-based RF amplifier. In this case, as will be described in more detail with reference to FIGS. 2C and 2D, the semiconductor layer structure 230 may include at least a channel layer and a barrier layer. The top-side metallization structure 240 will be described in more detail with reference to FIG. 2B.

[0048] The interconnect structure 270 can include, for example, a printed circuit board (e.g., a multilayer printed circuit board) including conductive vias and / or pads, a metal-core printed circuit board, a redistribution layer (“RDL”) laminate substrate, an interposer, a metal flange, or a ceramic substrate. In other embodiments, the interconnect structure 270 can include a metal flange having an insulating pattern (e.g., a solder mask) on a top surface and conductive traces on an insulating layer providing electrical connections to, for example, the gate terminal 222 and the drain terminal 224. More generally, the interconnect structure 270 may comprise any suitable mounting surface for the RF amplifier die 210 that can make an electrical connection to the back surface 214 of the RF amplifier die 210. Two or more interconnect structures 270 may be provided in a stacked fashion. The RF transistor amplifier die 210 may be mounted on the interconnect structure 270 by a die manufacturer and may be packaged in any suitable package.

[0049] On the top surface of the interconnect structure 270, gate pads 272, drain pads 274, and source pads 276 are provided. In some embodiments, the interconnect structure 270 can include pads 272, 274, 276 that can form, for example, exposed copper pads on the top surface of the interconnect structure 270. The gate terminal 222 may overlap with the gate pad 272 along a first vertical axis extending perpendicular to the top surface of the semiconductor layer structure, the drain terminal 224 may overlap with the drain pad 274 along a second vertical axis extending perpendicular to the top surface of the semiconductor layer structure, and the source terminal 226 may overlap with the source pad 276 along a third vertical axis extending perpendicular to the top surface of the semiconductor layer structure. "Overlap" means that the axis extends through both the terminal and its corresponding pad, and "perpendicular" refers to a direction perpendicular to the main surface of the semiconductor layer structure 230. Each overlapping terminal and pad (e.g., the gate terminal 222 and the gate pad 272) may be physically and electrically connected to each other by any suitable means including, for example, conductive epoxy, solder joints, etc. It will be appreciated that any type of bump grid array technology can be used to connect the gate terminal 222, the drain terminal 224, and the source terminal 226 to their respective gate pads 272, drain pads 274, and source pads 276 while facilitating the dissipation of heat from the RF amplifier die 210. The interconnect structure 270 further includes a plurality of heat dissipation structures 290. In the illustrated embodiment, the heat dissipation structure 290 includes metal-filled vias extending through the interconnect structure 270. The heat generated in the RF amplifier die 210 can be dissipated through the metal-filled vias 290. The interconnect structure can also include a plurality of conductive traces (not shown) and / or conductive vias (not shown) that can function as RF signal transmission paths, as will be described in detail herein.

[0050] The RF amplifier die 210 comprises a group-III nitride-based HEMT RF amplifier including a plurality of unit cell transistors 216 electrically connected in parallel to each other. This can be best seen in FIG. 2B which schematically shows the top-side metallization structure 240 of the RF amplifier die 210. As shown in FIG. 2B, the top-side metallization structure 240 includes a gate bus 242 and a drain bus 244, a plurality of gate fingers 252, a plurality of drain fingers 254, and a plurality of source fingers 256, all of which may be formed on the upper surface of the semiconductor layer structure 230. The gate bus 242 and the gate fingers 252 may be implemented as a first monolithic metal pattern, and the drain bus 244 and the drain fingers 254 may be implemented as a second monolithic metal pattern. The gate fingers 252 may be formed of a material capable of making a Schottky contact to a group-III nitride-based semiconductor material such as Ni, Pt, Cu, Pd, Cr, W, and / or WSiN. The drain fingers 254 and the source fingers 256 may include a metal such as TiAlN capable of making an ohmic contact to a group-III nitride-based material. A dielectric layer (or a series of dielectric layers) useful for separating the gate metallizations 242, 252, the drain metallizations 244, 254, and the source metallizations 256 from each other is not shown in FIG. 2B for better illustration of the elements of the top-side metallization structure 240. Conductive gate bond pads 243 and / or conductive drain bond pads 253 may optionally be provided on the upper surface of the RF transistor amplifier die 210. The gate bond pad 243 may be electrically connected to the gate terminal 222, and the drain bond pad 253 may be electrically connected to the drain terminal 224.

[0051] One of the unit cell transistors 216 is also shown in FIG. 2B. As shown, the unit cell transistor 216 includes a gate finger 252, a drain finger 254, and a source finger 256, along with a portion underlying the semiconductor layer structure 230. Since all of the gate fingers 252 are electrically connected to a common gate bus 242, all of the drain fingers 254 are electrically connected to a common drain bus 244, and all of the source fingers 256 are electrically connected to each other via a source pad 226, it can be seen that the unit cell transistors 216 are all electrically connected in parallel with each other.

[0052] The unit cell transistor 216 may be a HEMT device. Suitable structures for III-nitride-based HEMT devices that can utilize embodiments of the present invention are described, for example, in U.S. Patent Application Publication No. 2002 / 0066908A1, entitled "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same," published on Jun. 6, 2002, assigned to the assignee of the present application; U.S. Patent Application Publication No. 2002 / 0167023A1, entitled "Group-III Nitride Based High Electron Mobility Transistor(HEMT) With Barrier / Spacer Layer," published on Nov. 14, 2002; U.S. Patent Application Publication No. 2004 / 0061129, entitled "Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact Recesses," published on Apr. 1, 2004; U.S. Patent No. 7,906,799, entitled "Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess," issued on Mar. 15, 2011; and U.S. Patent No. 6,316,793, entitled "Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates," issued on Nov. 13, 2001. The disclosures of these are hereby incorporated by reference in their entirety into this specification.

[0053] As further shown in FIG. 2B, a plurality of metal plating vias extending through the semiconductor layer structure 230 from the top metallization structure 240 are provided. The metal plating vias include a metal plating gate via 262, a metal plating drain via 264, and a metal plating source via 266. The metal plating gate via 262 physically and electrically connects the gate bus 242 to the gate terminal 222, the metal plating drain via 264 physically and electrically connects the drain bus 244 to the drain terminal 224, and the metal plating source via 262 physically and electrically connects the source fin 256 to the source terminal 226.

[0054] As further shown in FIG. 2B, the conductive gate via 262 and / or the conductive drain via 264 may be offset from the conductive source via 266 (in the Y direction of FIG. 2B). In particular, two or more conductive source vias 266 may be formed in each source finger 256, and the conductive source vias 266 formed in a particular source finger 256 may extend (at least generally) along a horizontal (X direction) axis. Thus, the conductive source vias 266 included in each source finger 256 can define respective horizontal axes in the figure of FIG. 2B, and line 2C-2C in FIG. 2B shows one such horizontal axis. As shown in FIG. 2B, the conductive gate via 262 and / or the conductive drain via 264 may be disposed between these horizontal axes (e.g., rather than being arranged in a row along these horizontal axes). In some cases, the conductive gate via 262 and / or the conductive drain via 264 may be disposed along the longitudinal axis defined by each drain finger 254. By offsetting the conductive gate via 262 and the conductive drain via 264 from the conductive source via 266, the distance between the conductive vias 262, 264, 266 can be increased, thereby reducing the likelihood that the wafer or die will crack due to mechanical vulnerability. This arrangement also reduces the parasitic gate-source and / or parasitic source-drain couplings that can occur between the various vias 262, 264, 266. Such parasitic couplings can lead to gain loss and / or instability.

[0055] Referring to FIGS. 2C and 2D, the semiconductor layer structure 230 includes a plurality of semiconductor layers. In the illustrated embodiment, a total of two semiconductor layers, namely, a channel layer 234 and a barrier layer 236 on the top side of the channel layer 234, are shown. The semiconductor layer structure 230 can include additional semiconductor layers and / or non-semiconductor layers. For example, the semiconductor layer structure 230 can include a growth substrate 232 on which other semiconductor layers are grown. The growth substrate 232 can include, for example, a 4H-SiC or 6H-SiC substrate. In other embodiments, the growth substrate can include different semiconductor materials (e.g., silicon or group III nitride-based materials, GaAs, ZnO, InP) or non-semiconductor materials (e.g., sapphire).

[0056] SiC has a much closer crystal lattice match to group III nitrides than sapphire (Al 2 O 3 ), which is a very common substrate material for group III nitride devices. The closer lattice match of SiC can result in higher quality group III nitride films than those generally available on sapphire. SiC also has a very high thermal conductivity, so the total output power of group III nitride devices on silicon carbide is typically not limited by heat dissipation from the substrate as much as in the case of the same devices formed on sapphire. Also, the availability of semi-insulating SiC substrates can result in device insulation and reduction of parasitic capacitance.

[0057] An optional buffer layer, nucleation layer, and / or transition layer (not shown) may be provided on the growth substrate 232 below the channel layer 234. For example, an AlN buffer layer may be included to provide an appropriate crystal structure transition between the SiC growth substrate 232 and the remainder of the semiconductor layer structure 230. Further, for example, a strain balanced transition layer may be provided as described in U.S. Patent Application Publication No. 2003 / 0102482A1, assigned to the assignee of the present application and published on Jun. 5, 2003, entitled "Strain Balanced Nitride Heterojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors", the disclosure of which is incorporated herein by reference as if fully set forth herein.

[0058] In some embodiments, the channel layer 234 is Al x Ga 1-x a group III nitride material such as N (0 ≦ x < 1). In a particular embodiment of the present invention, x = 0, which indicates that the channel layer 234 is gallium nitride ("GaN"). The channel layer 234 may be other group III nitrides such as InGaN, AlInGaN, etc. The channel layer 234 may be undoped or unintentionally doped and can be grown, for example, to a thickness greater than about 20 Å. The channel layer 234 may also be a multilayer structure such as a superlattice or combination of GaN, AlGaN, etc.

[0059] The channel layer 234 can have a bandgap smaller than at least a part of the bandgap of the barrier layer 236, and the channel layer 234 can also have an electron affinity greater than that of the barrier layer 236. In certain embodiments, the barrier layer 236 is AlN, AlInN, AlGaN, or AlInGaN having a thickness of about 0.1 nm to about 10 nm or more. In certain embodiments, the barrier layer 236 is thick enough to induce a significant carrier concentration at the interface between the channel layer 234 and the barrier layer 236 and has a sufficiently high Al composition and doping.

[0060] The barrier layer 236 may be a group III nitride, may have a larger bandgap than the channel layer 234, and may have a smaller electron affinity than the channel layer 234. In certain embodiments, the barrier layer 236 is undoped or doped with an n-type dopant at a concentration of less than about 10 19 cm -3 . In some embodiments of the present invention, the barrier layer 236 is Al x Ga 1-x N (0 < x < 1). In certain embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer 236 includes AlGaN having an aluminum concentration of about 5% to about 100%. In certain embodiments of the present invention, the aluminum concentration is greater than about 10%.

[0061] Due to the difference in bandgap between the barrier layer 236 and the channel layer 234 and the piezoelectric effect at the interface between the barrier layer 236 and the channel layer 234, a two-dimensional electron gas (2DEG) is induced in the channel layer 234 at the junction between the channel layer 234 and the barrier layer 236. The 2DEG functions as a highly conductive layer that enables conduction between the source region and its associated drain region of each unit cell transistor 216. The source region is a portion of the semiconductor layer structure 230 directly below the source finger 256, and the drain region is a portion of the semiconductor layer structure 230 directly below the corresponding drain finger 254.

[0062] An interlayer insulating layer 238 is formed over the gate fingers 252, drain fingers 254, and source fingers 256. The interlayer insulating layer 238 can include a dielectric material such as SiN, SiO 2 and the like.

[0063] Figures 2C to 2G show the metal-plated gate vias 262, metal-plated drain vias 264, and metal-plated source vias 266 in more detail. As shown in Figures 2C to 2F, the metal-plated gate vias 262, metal-plated drain vias 264, and metal-plated source vias 266 can extend completely through the semiconductor layer structure 230 to physically and electrically connect the gate bus 242 to the gate terminal 222, the drain bus 244 to the drain terminal 224, and the source fingers 256 to the source terminal 226.

[0064] In some embodiments, all of the metal-plated gate vias 262, metal-plated drain vias 264, and metal-plated source vias 266 may have the same shape and horizontal cross-section (i.e., the cross-section taken through the via in a plane parallel to the major surface of the semiconductor layer structure 230). For example, all of the vias 262, 264, 266 may be substantially cylindrical vias having the same diameter, or all may be frustum-shaped vias having the same diameter when measured at the same height above the bottom surface 214 of the RF amplifier die 210. Such a configuration may make it possible to easily form all of the vias 262, 264, 266 in a single manufacturing step. In other embodiments, the metal-plated gate vias 262 and / or the metal-plated drain vias 264 may have a larger cross-sectional area compared to the metal-plated source vias 266. This technique can be used to further reduce the self-inductance of the metal-plated gate vias 262 and / or the metal-plated drain vias 264 when required for a particular application.

[0065] The metal-plated gate via 262, the metal-plated drain via 264, and the metal-plated source via 266 may each be implemented by forming an opening through the semiconductor layer structure (e.g., by anisotropic etching) and then depositing metal plating that coats the sidewalls of the opening. Depending on the application, the metal may completely fill the opening such that the metal-plated via becomes a metal-filled via. However, in many applications, the RF amplifier die 210 may operate over a wide temperature range (due to outdoor applications and / or high levels of heat that may be generated within the RF amplifier die during device operation), which can lead to high stress levels within the device due to the significantly different coefficients of thermal expansion of the metal and the semiconductor material. In such cases, the central portions of the metal-plated vias 262, 264, 266 can be left open (i.e., filled with air) in order to reduce the amount of stress that occurs due to thermal cycling.

[0066] The cross-sectional areas of the vias 262, 264, 266 may be selected, for example, based on heat dissipation considerations and / or a desired amount of series inductance. Whether the metal-plated vias dissipate heat to the same extent as the semiconductor material through which the metal-plated vias pass depends on various considerations including the heat dissipation qualities of the semiconductor material and the metal used, the thickness of the metal plating, the cross-sectional area of the vias, and the like. Generally speaking, metals such as copper dissipate heat more efficiently than group III nitride-based semiconductor materials and silicon carbide semiconductor materials, but the air-filled openings in the center of the vias do not dissipate heat as efficiently as the semiconductor material.

[0067] As shown in FIG. 2G, the gate terminal 222, the drain terminal 224, and the source terminal 226 can each include a metallization pattern on the lower surface 232 of the semiconductor layer structure 230. A gap may be provided between the gate terminal 222 and the drain terminal 224 and between the drain terminal 224 and the source terminal 226 to electrically insulate the gate terminal 222, the drain terminal 224, and the source terminal 226 from each other. In some embodiments, an insulating pattern (not shown) may be deposited in the gap. As shown in FIG. 2G, the gate via 262, the drain via 264, and the source via 266 are physically and electrically connected to the gate terminal 222, the drain terminal 224, and the source terminal 226, respectively. The metal-plated gate via 262, the metal-plated drain via 264, and the metal-plated source via 266 are shown as having an elliptical horizontal cross-section in the embodiments of FIGS. 2A-2G, but it should also be noted that the metal-plated via having an elliptical horizontal cross-section is only an example. For example, it will be understood that a metal-plated via having any arbitrary horizontal cross-section including circular, square, rectangular, etc. may be used. It will also be understood that the shape and / or size of the horizontal cross-section of any particular metal-plated via need not be constant. For example, some or all of the metal-plated vias can be tapered vias having an area that varies as a function of depth. It will also be understood that the size and / or density of the metal-plated gate via 262, the metal-plated drain via 264, and the metal-plated source via 266 can be varied as well. For example, the size and / or density of the metal-plated drain via 264 may be selected based on the current handling ability of the device.

[0068] FIG. 2H is a circuit diagram of a group-III nitride-based RF amplifier 200. As shown in FIG. 2H, the group-III nitride-based RF amplifier 200 includes an RF input 201, an input impedance matching network 202, an input harmonic termination circuit 203, an RF amplifier 204, an output harmonic termination circuit 205, an output impedance matching network 206, and an RF output 207. The input impedance matching network 202 is coupled between the RF input 201 and the gate terminal of the RF amplifier 204. The input harmonic termination circuit 203 is coupled between the gate terminal of the RF amplifier 204 and ground and is implemented as a series L-C circuit. The output harmonic termination circuit 205 is coupled between the drain terminal of the RF amplifier 204 and ground and is also implemented as a series L-C circuit. In an exemplary embodiment, the harmonic termination circuits 203, 205 may both be configured to suppress second or third harmonics. The output impedance matching network 206 is coupled between the drain terminal of the RF amplifier 204 and the RF output 207. In the illustrated embodiment, the impedance matching networks 202, 206 both have a high-pass inductor-capacitor (``L-C'') configuration, but it will be understood that in other embodiments, one or both of the impedance matching networks 202, 206 can have other topologies (e.g., a low-pass L-C topology).

[0069] FIG. 2H shows one exemplary embodiment of a matching network, but it will be understood that many modifications can be made thereto. For example, in other embodiments, one or both of the impedance matching networks 202, 206 may be omitted, similar to one or both of the harmonic termination circuits 203, 205. Similarly, additional harmonic termination circuits may be provided (e.g., separate harmonic termination circuits at the input and / or output of the RF amplifier 204 for second and third harmonics). The various circuits may have configurations different from those shown. Further, the impedance matching circuit and the harmonic termination circuit at the input (or output) can be combined into a single multi-purpose circuit.

[0070] In a particular embodiment shown in FIG. 2H, the matching circuit includes a total of four inductances coupled to either the input (i.e., gate terminal) or the output (i.e., drain terminal) of the RF amplifier 204. The inherent inductance of the gate via 262 of the RF amplifier 200 can form part of the input-side inductance. The remainder of the input-side inductance can be implemented using discrete circuits or distributed inductances mounted on or within the interconnect structure 270. Similarly, the inherent inductance of the drain via 264 of the RF amplifier 200 can form part of the output-side inductance. The remainder of the output-side inductance can be implemented using discrete circuits or distributed inductances mounted on or within the interconnect structure 270.

[0071] As described above, group-III nitride-based RF amplifiers often include matching networks such as an input impedance matching circuit, an output impedance matching circuit, an input harmonic termination circuit, and an output harmonic termination circuit. In some cases, a group-III nitride-based RF amplifier may be implemented as a MMIC device where the matching circuit can be formed on the same die as the RF amplifier circuit. However, implementing a group-III nitride-based RF amplifier as a MMIC increases both the die size and the manufacturing cost, and also reduces flexibility because the matching circuit is typically precisely tuned to the planned operating frequency band of the MMIC, and thus separate MMIC devices have to be manufactured for each target operating frequency band and output power level. In other cases, the RF amplifier may be implemented on a separate die and the matching circuit may be implemented on one or more separate substrates. In one such example, the RF amplifier die is mounted on an interconnect structure and the matching network is implemented using additional dies (e.g., capacitor die, inductor die) mounted on and / or within the interconnect structure. The interconnect structure may be implemented, for example, as a printed circuit board, a metal core printed circuit board, an RDL stack, or a substrate having conductive vias and / or traces.

[0072] When mounting an RF amplifier die on an interconnection structure including a matching network, the conventional method is, as described above with reference to FIG. 1A, to mount the RF amplifier die on the top surface of the interconnection structure with the source terminal provided at the bottom of the RF amplifier die and the gate terminal and drain terminal formed at the top of the RF amplifier die. This configuration enables heat generated in the RF amplifier die during device operation to be removed from the device through the source vias of the RF amplifier die and through the heat dissipation structure of the interconnection structure such as conductive vias. The gate terminal and drain terminal on the top side of the RF amplifier die are electrically connected to the matching circuit on the interconnection structure via bond wires. These bond wires also provide part of the inductance of the matching network.

[0073] As the application migrates to higher frequencies, the amount of inductance required to properly perform impedance matching at the fundamental frequency and / or to terminate specific harmonics such as second and / or third harmonics typically decreases. In some applications, even when using very short and thick bond wires, the inductance of the bond wires may exceed the optimal amount of series inductance required by one or more of the matching circuits. If the inductance is greater than the optimal amount of series inductance for the impedance matching circuit, the reflection attenuation of the RF amplifier may increase and the operating bandwidth may decrease. If the inductance is greater than the optimal amount of series inductance for the harmonic termination circuit, the reduction of the problematic harmonic may not be achieved well, which may degrade the efficiency, power, and / or gain performance of the RF amplifier, and as a result, may increase the passive intermodulation distortion level, which may degrade other aspects of the communication system in which the RF amplifier is used. These problems can be avoided by switching to the MMIC implementation as described above, but the MMIC RF amplifier design has its own potential drawbacks.

[0074] The group-III nitride-based RF amplifier 200 according to an embodiment of the present invention replaces the gate bond wire and the drain bond wire existing in a conventional RF amplifier with a gate via and a drain via extending through the RF amplifier die 210, thereby avoiding the above-described problem that the series inductance is too large. Typically, the bond wire has a length of at least 0.508 mm (20 mils), and a bond wire length of 0.762 mm (30 mils) or more is common. In contrast, the gate via and the drain via may be much shorter, typically having a length of less than 0.2032 mm (8 mils), and in an exemplary embodiment, the length may be less than 0.127 mm (5 mils), less than 0.1016 mm (4 mils), or even less than 0.00762 mm (3 mils). Therefore, the series inductance introduced by the gate via and the drain via may be only a fraction (e.g., perhaps about 15 to 20% of the inductance introduced by conventional gate bond wires and drain bond wires) of the series inductance introduced by equivalent gate bond wires and drain bond wires, thereby ensuring that the series inductance is smaller than the optimal amount of series inductance required by various matching circuits of the group-III nitride-based RF amplifier. The additional series inductance required to obtain the optimal amount of series inductance for the matching network may be added using inductive chips and / or inductive traces (or other structures) attached to or implemented in the interconnect structure.

[0075] A ball bonder used to solder bond wires to gate and drain terminals on an RF amplifier die and to gate pads and drain pads on an interconnect structure typically has a tolerance of + / -0.0254 mm (1 mil) and potentially introduces a variation of up to 0.1016 mm (4 mils) in the length of each bond wire. By attaching the gate and drain terminals to the bottom side of the device, process variations during mass production can also be reduced. The amount of inductance associated with such variations in bond wire length can be quite large, especially at higher frequencies, and can degrade the performance of the impedance matching circuit and thus the performance of the RF amplifier. Further, by connecting the gate and drain terminals to corresponding gate pads and drain pads on the interconnect structure by a surface mount process using conductive epoxy or solder, it becomes possible to use smaller gate and drain terminals than might otherwise be required when bond wire connections are needed. Thus, an RF amplifier die according to an embodiment of the present invention may be smaller in applications where the gate terminal size and drain terminal size determine the size of the die. Further, by using ball bonding technology instead of wire bonding, the manufacturing cost can be reduced.

[0076] Accordingly, the RF amplifier according to an embodiment of the present invention can exhibit improvement in product assembly consistency, improvement in yield, improvement in product integration, cost reduction, and improvement in RF performance. For higher frequency applications, the inductance required by the matching circuit may be much lower in such applications, and thus, using conventional bond wires may introduce too much inductance, so the advantages may be greater. Further, the tolerance of the bond wire length may have a greater impact as the frequency is higher, and in high-frequency applications (especially in the case of low power), the size of the bond pad may affect the size of the die. In some embodiments, any of the RF amplifiers disclosed herein may be configured to operate at a frequency above 1 GHz. In other embodiments, these RF amplifiers may be configured to operate at a frequency above 2.5 GHz. In still other embodiments, these RF amplifiers may be configured to operate at a frequency above 3.1 GHz. In yet additional embodiments, these RF transistor amplifier dies may be configured to operate at a frequency above 5 GHz. In some embodiments, these RF amplifiers may be configured to operate in at least one of the frequency bands of 2.5 - 2.7 GHz, 3.4 - 4.2 GHz, or 5.1 - 5.8 GHz, or sub-portions thereof.

[0077] As will be described in more detail herein, the RF amplifier according to an embodiment of the present invention may be mounted in a package that protects the RF amplifier die and provides input leads and output leads for connecting the RF amplifier to external signals and power supplies. In an exemplary embodiment, the packaging may be a plastic overmold package that covers some but not all of the interconnect structure. In such an embodiment, the input leads and output leads may be implemented, for example, as conductive traces on the interconnect structure. However, it will be understood that any suitable packaging may be used, including ceramic packages, other plastic packages, and the like.

[0078] FIG. 3 is a schematic top view of an exemplary embodiment of the interconnection structure 270 included in the RF amplifier 200 of FIGS. 2A-2H. As shown in FIG. 3, the interconnection structure 270 can include a printed circuit board such as a multilayer printed circuit board or an RDL stack structure. The gate pad 272, the drain pad 274, and the source pad 276 are mounted on the top surface of the interconnection structure 270. Each of these pads can include a respective metal pattern (e.g., a copper pattern). The gate pad 272, the drain pad 274, and the source pad 276 may have the same or similar size and shape as the respective gate terminal 222, drain terminal 224, and source terminal 226 on the RF amplifier die 210. Under the source pad 276, a plurality of metal-filled vias 290 extending through the interconnection structure 270 may be provided. The metal-filled vias 290 can function as a heat sink that carries the heat generated in the RF amplifier die 210 and passed to the interconnection structure 270 through the semiconductor layer structure 230 and the source vias 260 to the bottom side of the interconnection structure 270, where the heat is dissipated to the surrounding environment. As also shown in FIG. 3, in some embodiments, additional metal-filled vias 290 may be provided under the gate pad 272 and / or under the source pad 276.

[0079] As further shown in FIG. 3, a plurality of additional integrated circuit chips 280 or other chips 282 may be mounted on the interconnection structure 270. These chips 280, 282 may include, for example, chips including capacitors and / or inductors that are part of an input and / or output matching circuit, chips including a bias circuit used to bias the RF amplifier die 210, other RF circuits such as transmit / receive switches, circulators, filters, etc. The interconnection structure 270 can also include a meandering or spiral trace pattern (not shown) that implements an inductor included in the input and / or output matching circuit. A number of other circuit elements may be mounted on the interconnection structure 270 or implemented within the interconnection structure 270.

[0080] Figures 4 and 5 are schematic diagrams showing the structures of the top metallizations of two RF amplifier dies according to further embodiments of the present invention.

[0081] As shown in FIG. 4, an RF amplifier die 310 according to an embodiment of the present invention is very similar to the RF amplifier die 210, except that the RF amplifier die 310 does not include a drain via 264, and the drain terminal of the RF amplifier die 310 is mounted on the top side of the semiconductor layer structure 230 in the manner described above with reference to the RF amplifier 100 of FIGS. 1A - 1B and may be connected to a drain pad on the interconnect structure via a bond wire. The RF amplifier die 310 can be used, for example, when the bond wire does not introduce too much inductance into any of the output matching networks. The remaining part of the RF amplifier die 310 may be the same as that of the RF amplifier 210, and thus, further description thereof is omitted.

[0082] As shown in FIG. 5, an RF amplifier die 410 according to an embodiment of the present invention is also very similar to the RF amplifier die 210, except that the RF amplifier die 410 does not include a gate via 262, and the gate terminal of the RF amplifier die 410 is mounted on the top side of the semiconductor layer structure 230 in the manner described above with reference to the RF amplifier 100 of FIGS. 1A - 1B and may be connected to a gate pad on the interconnect structure via a bond wire. The RF amplifier die 410 can be used, for example, when the bond wire does not introduce too much inductance into any of the input matching networks. The remaining part of the RF amplifier die 410 may be the same as that of the RF amplifier 210, and thus, further description thereof is omitted.

[0083] The RF amplifier according to an embodiment of the present invention can have any suitable design and can also include additional circuit elements. For example, the RF amplifier can include a fractional-mode resistor and / or a gate resistor as discussed, for example, in U.S. Patent No. 10,128,365, the entire content of which is incorporated herein by reference. FIGS. 6A and 6B are schematic top and bottom views of an RF amplifier die 510 according to a further embodiment of the present invention. The RF amplifier die 510 may be the same as the above-described RF amplifier die 210 except that the RF amplifier die 510 further includes a series gate resistor 246 and a fractional-mode resistor 248.

[0084] As shown in FIG. 6A, the series gate resistor 246 is included in the RF amplifier die 510. In the illustrated embodiment, the series gate resistor 246 is provided at the position where each gate finger 252 connects to the gate bus 242. As shown in FIGS. 6A and 6B, the gate bus 242 and / or the gate terminal 222 can also be segmented into a plurality of sections, and the fractional mode resistor 248 may be disposed between each section. In high-power devices, the gate may have a long gate width (i.e., further extend in the x direction) in order to increase the gate periphery of the device, and as a result, the feedback loop becomes long. Since these high-power devices may have a large mutual conductance value, the feedback loop may be prone to instability. For example, the feedback loop may generate unwanted signals that may be within or outside the operating frequency band of the device. The generation of such signals can be problematic and may render the device inoperable. The instability of the feedback loop tends to increase with the length of the feedback loop. The series gate resistor 246 and the fractional mode transistor 248 can stabilize these feedback loops within the device's gate fingers 252 and drain fingers 254. It will be understood that the series gate resistor 246 and / or the fractional mode transistor 248 may be included in any of the RF transistor amplifiers according to embodiments of the invention disclosed herein.

[0085] Figure 7A is a schematic cross-sectional view of a packaged RF transistor amplifier 600 including the RF transistor amplifier die 210 of FIG. 2B within an open-cavity package. As shown in FIG. 7A, the open-cavity package 610 includes a base 620, such as a metal flange, and an upper housing 630 that can include, for example, sidewalls and a lid such as a ceramic lid. The RF transistor amplifier die 210 may be mounted on the interconnect structure 270 using contacts such as, for example, solder pads, conductive adhesives, conductive bumps. The interconnect structure 270 may be mounted on the base 620 using, for example, a conductive die-attach material. The base 620 can include, for example, a metal base that can dissipate heat carried through the heat dissipation structure of the interconnect structure 270 to the outside of the ceramic package 610.

[0086] Additional components 650, 660 can be mounted on the interconnect structure 270. These additional components can include, for example, one or more input matching components 650 and / or one or more output matching components 660 that are used to perform impedance matching at the fundamental frequency and / or to terminate the intermodulation product to ground. These matching components 650, 660 can be passive RF components, for example, resistors, capacitors, and / or inductors (at least partially) implemented on an integrated passive device or a printed circuit board. The conductive leads 640 extend through the housing 610 to enable the RF transistor amplifier 600 to be connected to an external device / circuit / power supply. In the illustrated embodiment, wire bonds 670 are used to connect the conductive leads 640 to the passive RF components 650, 660 on the interconnect structure 270. The RF signal input to the RF transistor amplifier 600 on the first lead 640-1 is passed to the input matching circuit 650 via the wire bond 670-1, and from there it may be passed to the gate terminal 222 of the RF transistor amplifier die 210 via a first conductive trace or path (not shown) on / within the interconnect structure 270. The amplified output RF signal may be passed from the drain terminal 224 of the RF transistor amplifier die 210 to the output matching circuit 660 via a second conductive trace or path (not shown) on / within the interconnect structure 270, and from there to the bond wire 670-2, and the RF signal is output via the lead 640-2.

[0087] FIG. 7B is a schematic cross-sectional view of a packaged RF transistor amplifier 700 including the RF transistor amplifier die 210 of FIG. 2B within an overmolded plastic package. As shown in FIG. 7B, the packaged RF transistor amplifier 700 includes a base 720, such as a metal heat sink, which is part of a lead frame or metal slug and is at least partially surrounded by a plastic overmold 710. The RF transistor amplifier die 210 is mounted on an interconnect structure 270, which is mounted on the base 720. The base 720 can include, for example, a metal base that can dissipate heat carried through the heat dissipation structure of the interconnect structure 270. Additional components 750, 760 are mounted on the interconnect structure 270. These additional components can include, for example, an input matching component 750 and an output matching component 760 that are used to perform impedance matching at the fundamental frequency and / or to terminate the intermodulation product to ground. Conductive leads 740 extend through the plastic overmold 710 to enable connection of the RF transistor amplifier 700 to an external device / circuit / power supply. In the illustrated embodiment, wire bonds 770 are used to connect the conductive leads 740 to the passive RF components 750, 760 on the interconnect structure 270, but the wire bonds 770 may be omitted in other embodiments. Note that, herein, the term "overmolded" is used broadly to include, for example, a protective plastic coating deposited on a wafer before the wafer is diced into individual dies.

[0088] It will be appreciated that any of the RF transistor amplifiers according to embodiments of the invention discussed herein can be mounted in packages such as the open - cavity package and overmolded package shown in FIGS. 7A and 7B, respectively. Thus, the RF transistor die 210 and the interconnect structure 270 shown in FIGS. 7A - 7B can be replaced with an RF transistor die and an interconnect structure according to any of the embodiments of the invention discussed herein to provide many further embodiments of the packaged RF transistor amplifier. In some embodiments, the packaged RF transistor amplifier can include a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die, and the RF transistor amplifier die incorporates a plurality of discrete circuits in a single integrated die. Further and / or alternatively, the package can include a plurality of RF transistor amplifier dies connected in series to form a multi - stage RF transistor amplifier in a path, and / or a plurality of RF transistor amplifier dies arranged in a plurality of paths (e.g., in parallel) to form an RF transistor amplifier having a plurality of transistor amplifier dies and a plurality of paths such as a Doherty amplifier configuration. In some embodiments, the packaged RF transistor amplifier can include an RF transistor amplifier die according to an embodiment of the invention having conductive gate vias and / or conductive drain vias that provide electrical connection to a back - side interconnect structure, and a conventional RF transistor amplifier die such as the RF transistor die 110 of FIG. 1A having gate and drain terminals connected to other structures via wire bonds.

[0089] The number, spacing, density, and / or cross-sectional area of the conductive vias 262, 264, 266 may be appropriately changed. As described above, the size, shape, and / or number of the conductive vias may affect various performance parameters of the RF amplifier, such as heat dissipation performance and matching performance. Therefore, the shape, size, position, and / or density of different types of conductive vias may be selected to optimize various performance parameters. For example, FIG. 8A is a schematic cross-sectional view (taken along a line corresponding to line 2B-2B in FIG. 2A) of an RF amplifier die 800 that includes far more gate vias 262 than drain vias 264. Such a design can reduce the overall inductance by increasing the number of gate vias 262, and may be desirable when the input matching circuit requires a very low level of inductance. Similarly, FIG. 8B is a similar schematic cross-sectional view of an RF amplifier die 810, where the number of gate vias and drain vias is the same, but the size of the gate vias is increased to reduce the inductance. FIGS. 8C and 8D are schematic cross-sectional views of RF amplifier dies 820 and 830 in which the same change is made to the drain vias 264 instead of the gate vias 262. It will also be understood that the positions of the vias 262, 264 may be changed, as shown in FIG. 8E, which is a schematic cross-sectional view of yet another RF amplifier die 840.

[0090] The above-described exemplary embodiments include a single RF amplifier die having a single stage of amplifier, but it will be understood that the embodiments of the present invention are not limited thereto. In other embodiments, the amplifier may include multiple stages and may have a Doherty configuration or the like.

[0091] Embodiments of the concept of the present invention have been described above with reference to the accompanying drawings in which embodiments of the present invention are shown. However, the concept of the present invention may be embodied in many different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the concept of the present invention to those skilled in the art. Like numbers refer to like elements throughout.

[0092] Terms such as first, second, etc. may be used herein to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present invention, the first element can be called the second element, and similarly, the second element can be called the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0093] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the present invention. As used herein, the terms "comprises," "comprising," "includes," and / or "including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0094] When an element such as a layer, region, or substrate is referred to as extending "on" or "onto" another element, it should be understood that it can extend directly on or directly onto the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly on" or extending "directly onto" another element, no intervening elements are present. When an element is referred to as being "connected" or "coupled" to another element, it should also be understood that the element may be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, no intervening elements are present.

[0095] Relative terms such as "below", "above", "upper", "lower", "horizontal", "lateral", "vertical", etc. may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0096] In the drawings and the specification, typical embodiments of the present invention are disclosed and specific terms are used, but they are not for the purpose of limitation and are used only in a general and illustrative sense. The scope of the present invention is set forth in the following claims.

Claims

1. A group-III nitride-based RF amplifier die including a semiconductor layer structure, and a gate terminal, a source terminal, and a drain terminal on the semiconductor layer structure; An interconnection structure including a gate pad electrically connected to the gate terminal, a drain pad electrically connected to the drain terminal, and a source pad electrically connected to the source terminal; Comprising: A plurality of unit cell transistors are provided on the upper part of the semiconductor layer structure, and at least two of the gate terminal, the drain terminal, and the source terminal are provided on the lower surface of the semiconductor layer structure; The gate terminal is electrically connected to the unit cell transistor via one or more conductive gate vias extending through the semiconductor layer structure; The interconnection structure includes at least a first part of an integrated circuit; A high-frequency (“RF”) amplifier, wherein the one or more conductive gate vias constitute a second part of the integrated circuit.

2. The RF amplifier according to claim 1, wherein the drain terminal is electrically connected to the unit cell transistor via one or more conductive drain vias extending through the semiconductor layer structure.

3. The RF amplifier according to claim 2, wherein the semiconductor layer structure includes a growth substrate, a channel layer, and a barrier layer, and the channel layer is between the growth substrate and the barrier layer.

4. The group-III nitride-based RF amplifier die further includes a metallization structure including a plurality of gate fingers, a plurality of drain fingers, and a plurality of source fingers on the barrier layer on the opposite side of the channel layer; The RF amplifier according to claim 3, wherein the gate fingers are electrically connected to the gate terminal via the one or more conductive gate vias, and the drain fingers are electrically connected to the drain terminal via the one or more conductive drain vias.

5. The RF amplifier according to claim 1, wherein the gate pad, the drain pad, and the source pad are electrically connected to the gate terminal, the drain terminal, and the source terminal, respectively, via a conductive epoxy pattern.

6. The RF amplifier according to claim 5, wherein the gate terminal overlaps the gate pad along a first axis perpendicular to the upper surface of the interconnect structure, the drain terminal overlaps the drain pad along a second axis perpendicular to the upper surface of the interconnect structure, and the source terminal overlaps the source pad along a third axis perpendicular to the upper surface of the interconnect structure.

7. The RF amplifier according to claim 2, wherein the number of the conductive gate vias is different from the number of the conductive drain vias.

8. The RF amplifier according to claim 2, wherein the coupling inductance of the conductive gate vias is different from the coupling inductance of the conductive drain vias.

9. The RF amplifier according to claim 2, wherein at least one size of the conductive gate vias is different from at least one size of the conductive drain vias.

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