Method for manufacturing a display device

Abstract

To provide a method for manufacturing a display device, capable of successfully controlling the peeling of a lift-off layer that is used as a mask.SOLUTION: A method for manufacturing a display device includes the steps of: forming a lift-off layer on an array substrate having a display area where a plurality of pixel electrodes are arranged and a peripheral area surrounding the display area; forming, in the display area, a plurality of first openings at positions overlapping with the plurality of pixel electrodes of the lift-off layer, and forming, in the peripheral area, a plurality of second openings in the lift-off layer; forming an organic EL layer on the lift-off layer and on the pixel electrodes overlapping with the plurality of first openings; and peeling, from the array substrate, the lift-off layer and the organic EL layer on the lift-off layer. In the step of forming the plurality of first openings and the plurality of second openings, the lift-off layer is at least partially connected and continuously formed from an outer edge side of the array substrate to the display area.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a display device.

Background Art

[0002] Patent Documents 1 and 2 describe a method for manufacturing an OLED (Organic Light Emitting Diode) display device. The method for manufacturing the OLED display device of Patent Documents 1 and 2 describes a method for patterning an organic EL film by a so-called lift-off method. The lift-off layer formed as a polymer mask is peeled off from the array substrate after the formation of the organic EL film.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] When the lift-off layer is separately formed in the display area and the peripheral area, it is necessary to separately peel the lift-off layer in the display area and the peripheral area in the step of peeling the lift-off layer. For this reason, if peeling occurs in an unintended in-plane direction or an unintended in-plane area, generation of foreign matter and contact between the peeled lift-off layer and the array substrate may occur. As a result, the organic EL film and the pixel electrode formed on the array substrate may be damaged.

[0005] An object of the present invention is to provide a method for manufacturing a display device capable of favorably controlling the peeling of a lift-off layer used as a mask.

Means for Solving the Problems

[0006] A method for manufacturing a display device according to an aspect of the present invention includes a step of forming a lift-off layer on an array substrate having a display region in which a plurality of pixel electrodes are arranged and a peripheral region surrounding the display region, and in the display region, forming a plurality of first openings at positions overlapping the plurality of pixel electrodes of the lift-off layer, and in the peripheral region, forming a plurality of second openings in the lift-off layer, forming an organic EL layer on the lift-off layer and on the pixel electrodes overlapping the plurality of first openings, and peeling the lift-off layer and the organic EL layer on the lift-off layer from the array substrate. In the step of forming the plurality of first openings and the plurality of second openings, at least a part of the lift-off layer is continuously formed in a connected manner from the outer edge side of the array substrate to the display region.

Brief Description of the Drawings

[0007]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Embodiments for Carrying Out the Invention

[0008] Embodiments (modes) for carrying out the present invention will be described in detail with reference to the drawings. The present disclosure is not limited by the content described in the following embodiments. Further, the constituent elements described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the constituent elements described below can be combined as appropriate. Note that the disclosure is merely an example, and those that can be easily conceived by those skilled in the art with appropriate modifications while maintaining the gist of the present disclosure are naturally included in the scope of the present disclosure. In addition, for the purpose of making the description clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but this is merely an example and does not limit the interpretation of the present disclosure. Also, in the present disclosure and each figure, the same reference numerals may be given to the same elements as those described above with respect to the already shown figures, and detailed descriptions may be omitted as appropriate.

[0009] In this specification and the claims, when expressing the aspect of arranging another structure on a certain structure, when simply described as "on", unless otherwise specified, it includes both the case of arranging another structure directly on a certain structure in contact with it and the case of arranging another structure above a certain structure via yet another structure.

[0010] FIG. 1 is a plan view showing a display device according to the first embodiment. The display device 1 of this embodiment is an organic EL display device including an organic light emitting diode (OLED), which is a self-emitting element. The display device 1 includes an array substrate 2, pixels PX, a scanning line driving circuit 12, a signal line driving circuit 13, and a driving IC (Integrated Circuit) 210.

[0011] The array substrate 2 is a driving circuit substrate for driving each pixel PX, and is also called a backplane or an active matrix substrate. The array substrate 2 is formed with a substrate 21 as a base, and has a plurality of transistors, a plurality of capacitors, various wirings, etc. on the substrate 21. Although not particularly shown, a wiring substrate (for example, a flexible printed circuit (FPC)) for inputting various control signals and power from an external control substrate may be connected to the array substrate 2.

[0012] In the following description, the first direction Dx is a direction in a plane parallel to the substrate 21. The second direction Dy is a direction in a plane parallel to the substrate 21 and is a direction orthogonal to the first direction Dx. Note that the second direction Dy may intersect the first direction Dx without being orthogonal to it. The third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy, and is the normal direction of the substrate 21. Further, "plan view" refers to the positional relationship when viewed from the third direction Dz.

[0013] The scanning line driving circuit 12 is a driving circuit that supplies a signal to a scanning line (not shown) in the display area AA to drive a plurality of pixels PX. The signal line driving circuit 13 is a driving circuit that supplies a pixel signal to a signal line (not shown) in the display area AA to drive a plurality of pixels PX. The driving IC 210 is a circuit that supplies a control signal to the scanning line driving circuit 12 and the signal line driving circuit 13 to control the display of a plurality of pixels PX. Note that at least a part of the scanning line driving circuit 12 and the signal line driving circuit 13 may be integrally formed with the driving IC 210. Further, the driving IC 210 is provided on the array substrate 2. However, it is not limited thereto, and the driving IC 210 may be provided on a wiring substrate connected to the array substrate 2.

[0014] The array substrate 2 has a display area AA and a peripheral area GA. A plurality of pixels PX are provided in the display area AA. The plurality of pixels PX are arranged in a matrix in the display area AA. The peripheral area GA is an area outside the display area AA and is an area where no plurality of pixels PX are provided. A scanning line driving circuit 12, a signal line driving circuit 13, and a driving IC 210 are provided in the peripheral area GA. The scanning line driving circuit 12 is provided in an area extending along the second direction Dy in the peripheral area GA. The signal line driving circuit 13 and the driving IC 210 are provided in an area extending along the first direction Dx in the peripheral area GA.

[0015] The display area AA is a rectangular area having four sides AAs1, AAs2, AAs3, and AAs4. The side AAs1 extends in the first direction Dx. The side AAs2 extends in the first direction Dx and is adjacent to the side AAs1 in the second direction Dy. The sides AAs3 and AAs4 each extend in the second direction Dy and are disposed between the side AAs1 and the side AAs2.

[0016] The peripheral area GA is an area between the four sides AAs1, AAs2, AAs3, AAs4 and the end of the substrate 21. The peripheral area GA has a first partial area GAa, a second partial area GAb, a third partial area GAc, a fourth partial area GAd, and a fifth partial area GAe. The first partial area GAa is an area in the peripheral area GA that extends in the first direction Dx along the side AAs1 and is disposed between the side AAs1 and the end of the substrate 21 that extends in the first direction Dx. The second partial area GAb is an area in the peripheral area GA that extends in the first direction Dx along the side AAs2 and is located on the opposite side of the first partial area GAa across the display area AA in the second direction Dy.

[0017] The third partial region GAc is a region within the peripheral region GA that extends in the second direction Dy along the side AAs3 and is surrounded by the side AAs3, the end of the substrate 21 that extends in the second direction Dy, the extension line of the side AAs1, and the extension line of the side AAs2. The fourth partial region GAd is a region within the peripheral region GA that extends in the second direction Dy along the side AAs4 and is located on the opposite side of the third partial region GAc across the display region AA in the first direction Dx. The fifth partial region GAe is provided in a frame shape surrounding the display region AA and is a region between the display region AA and the regions from the first partial region GAa to the fourth partial region GAd. That is, the regions from the first partial region GAa to the fourth partial region GAd are outer edge regions arranged on the outer edge side of the array substrate 2, and the fifth partial region GAe is an intermediate region between the outer edge region and the display region AA.

[0018] In this embodiment, for ease of explanation, the display region AA is rectangular, and the peripheral region GA is in a rectangular frame shape surrounding the periphery of the display region AA. However, it is not limited thereto. The display region AA may be polygonal or may have an irregular shape with a notch or a curved portion in a part of its outer periphery. The peripheral region GA can also be made to have various shapes corresponding to the shape of the display region AA.

[0019] FIG. 2 is a plan view showing an example of a pixel of the display device according to the first embodiment. As shown in FIG. 2, the pixel PX has a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 each include an organic light-emitting diode as a light-emitting element 3 (see FIG. 3). In the following description, when there is no need to distinguish between the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, they are simply represented as the sub-pixel SPX.

[0020] The first sub-pixel SPX1 displays, for example, red (R). The second sub-pixel SPX2 displays, for example, green (G). The third sub-pixel SPX3 displays, for example, blue (B). The first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 are arranged side by side in the first direction Dx. However, it is not limited to this, and the pixel PX may have other arrangements. For example, the first sub-pixel SPX1 and the second sub-pixel SPX2 may be arranged adjacent to each other in the second direction Dy, and one third sub-pixel SPX3 may be arranged adjacent to the first sub-pixel SPX1 and the second sub-pixel SPX2 adjacent to each other in the second direction Dy and adjacent to the first direction Dx. Also, the pixel PX is not limited to three sub-pixels SPX, and may be composed of four or more sub-pixels SPX.

[0021] Figure 3 is a cross-sectional view taken along the line III-III' of Figure 2. As shown in Figure 3, the light-emitting element 3 is provided on the array substrate 2. The array substrate 2 has a substrate 21, a pixel electrode 23, a stacked electrode 25, a connection electrode 26, various transistors, various wirings, and various insulating films.

[0022] The substrate 21 is an insulating substrate, and for example, a glass substrate such as quartz or non-alkali glass, or a resin substrate such as polyimide is used. When a resin substrate having flexibility is used as the substrate 21, the display device 1 can be configured as a sheet display. Also, the substrate 21 is not limited to polyimide, and other resin materials may be used.

[0023] In this specification, in the direction perpendicular to the surface of the substrate 21, the direction from the substrate 21 toward the light-emitting element 3 is referred to as "upper side" or simply "up". Also, the direction from the light-emitting element 3 toward the substrate 21 is referred to as "lower side" or simply "down".

[0024] An undercoat film 91 is provided on a substrate 21. The undercoat film 91 has, for example, a three-layer laminated structure including insulating films 91a, 91b, and 91c. The insulating film 91a is a silicon oxide film, the insulating film 91b is a silicon nitride film, and the insulating film 91c is a silicon oxide film. The lower insulating film 91a is provided to improve the adhesion between the substrate 21 and the undercoat film 91. The middle insulating film 91b is provided as a film for blocking moisture and impurities from the outside. The upper insulating film 91c is provided as a blocking film to prevent hydrogen atoms contained in the silicon nitride film of the insulating film 91b from diffusing to the semiconductor layer 61 side.

[0025] The configuration of the undercoat film 91 is not limited to that shown in FIG. 3. For example, the undercoat film 91 may be a single-layer film or a two-layer laminated film, or may be laminated with four or more layers.

[0026] The light-shielding film 65 is provided on the insulating film 91a. The light-shielding film 65 is provided between the semiconductor layer 61 and the substrate 21. The light-shielding film 65 can suppress the intrusion of light from the substrate 21 side into the channel region 61a of the semiconductor layer 61.

[0027] The driving transistor DRT is provided on the undercoat film 91. In FIG. 3, one driving transistor DRT is shown corresponding to the light-emitting element 3, but a plurality of transistors constituting the pixel circuit may be provided corresponding to one light-emitting element 3.

[0028] The driving transistor DRT has a semiconductor layer 61, a source electrode 62, a drain electrode 63, and a gate electrode 64. The semiconductor layer 61 is provided on the undercoat film 91. For the semiconductor layer 61, polysilicon is used, for example. However, the semiconductor layer 61 is not limited thereto, and may be a microcrystalline oxide semiconductor, an amorphous oxide semiconductor, low-temperature polysilicon, or the like. Only an n-type TFT is shown as the driving transistor DRT, but a p-type TFT may be formed simultaneously. In the n-type TFT, the semiconductor layer 61 has a channel region 61a, a source region 61b, a drain region 61c, and a low-concentration impurity region 61d.

[0029] The gate insulating film 92 is provided on the undercoat film 91 covering the semiconductor layer 61. The gate insulating film 92 is, for example, a silicon oxide film. The gate electrode 64 is provided on the gate insulating film 92. Also, the first wiring 66 is provided in the same layer as the gate electrode 64. In the example shown in FIG. 3, the driving transistor DRT has a top gate structure. However, it is not limited thereto, and the driving transistor DRT may have a bottom gate structure or a dual gate structure in which gate electrodes 64 are provided on both the upper and lower sides of the semiconductor layer 61.

[0030] The interlayer insulating film 93 is provided on the gate insulating film 92 covering the gate electrode 64. The interlayer insulating film 93 has, for example, a laminated structure of a silicon nitride film and a silicon oxide film. The source electrode 62 and the drain electrode 63 are provided on the interlayer insulating film 93. The source electrode 62 is connected to the source region 61b through contact holes provided in the gate insulating film 92 and the interlayer insulating film 93. The drain electrode 63 is connected to the drain region 61c through contact holes provided in the gate insulating film 92 and the interlayer insulating film 93. A second wiring 67 serving as a routing wiring is connected to the source electrode 62.

[0031] A part of the second wiring 67 is formed in a region overlapping with the first wiring 66. A capacitance Cs1 is formed by the first wiring 66 and the second wiring 67 facing each other through the interlayer insulating film 93. Also, the capacitance Cs1 includes a capacitance formed by the semiconductor layer 61 and the first wiring 66 facing each other through the gate insulating film 92.

[0032] The first organic insulating film 94 is provided on the interlayer insulating film 93 covering the driving transistor DRT and the second wiring 67. As the first organic insulating film 94, an organic material such as photosensitive acrylic is used. The organic material such as photosensitive acrylic is superior in coverage of wiring steps and surface flatness compared to inorganic insulating materials formed by CVD or the like.

[0033] On the first organic insulating film 94, a stacked electrode 25, a capacitive insulating film 95, and a pixel electrode 23 are stacked in this order. The stacked electrode 25 is made of a conductive material having translucency, such as ITO (Indium Tin Oxide) for example. A connection electrode 26 is provided in the same layer as the stacked electrode 25. The connection electrode 26 is provided so as to cover the inside of a contact hole H1 provided in the first organic insulating film 94, and is connected to the second wiring 67 at the bottom of the contact hole H1.

[0034] The capacitive insulating film 95 is provided so as to cover the stacked electrode 25 and the connection electrode 26, and has an opening in a region overlapping the contact hole H1. The capacitive insulating film 95 is, for example, a silicon nitride film.

[0035] The light-emitting element 3 is provided on the capacitive insulating film 95. The light-emitting element 3 has a pixel electrode 23, an organic EL layer 31, and a counter electrode 24. Specifically, the pixel electrode 23 is provided on the capacitive insulating film 95. The pixel electrodes 23 are arranged separately for each sub-pixel SPX. A capacitance Cad is formed between the pixel electrode 23 and the stacked electrode 25 facing each other through the capacitive insulating film 95. The pixel electrode 23 is electrically connected to the connection electrode 26 and the second wiring 67 through the contact hole H1. Thereby, the pixel electrode 23 is electrically connected to the driving transistor DRT. The pixel electrode 23 is formed as a reflective electrode and has a stacked structure of IZO (Indium Zinc Oxide) / silver (Ag) / IZO. However, it is not limited thereto, and the pixel electrode 23 may be another metal material, an alloy, or a translucent conductive material.

[0036] A bank 96 (rib) is provided between adjacent pixel electrodes 23. The bank 96 is formed as an insulating layer serving as a partition wall between adjacent sub-pixels SPX. As the material of the bank 96, photosensitive acrylic or the like is used in the same manner as the first organic insulating film 94. The bank 96 is preferably opened so as to expose the surface of the pixel electrode 23 as a light-emitting region, and the opening end thereof has a gentle tapered shape.

[0037] An opening H2 is provided at a position overlapping with the bank 96 of the capacitive insulating film 95. The first organic insulating film 94 and the bank 96 are in contact through the opening H2. Thereby, moisture and outgassing that desorb from the first organic insulating film 94 during heat treatment or the like after the formation of the bank 96 can be drawn out to the outside through the bank 96.

[0038] The organic EL layer 31 is provided on the pixel electrode 23. In FIG. 3, the structure of the organic EL layer 31 is simplified and described as a single layer, but a hole transport layer, a light-emitting layer, and an electron transport layer are laminated in order from the pixel electrode 23 side. Each layer of the organic EL layer 31 may be formed by vapor deposition or may be formed by coating on solvent dispersion. Further, the organic EL layers 31R, 31G, and 31B are selectively formed for each sub-pixel SPX.

[0039] The counter electrode 24 is provided on the organic EL layer 31. The counter electrode 24 covers a plurality of organic EL layers 31 (sub-pixels SPX) and is provided from the display area AA to the peripheral area GA. In FIG. 3, since it is a top emission structure, the counter electrode 24 needs to have translucency. Here, the counter electrode 24 is formed of a metal material (for example, MgAg) as a thin film that allows the light emitted from the organic EL layer 31 to pass through. In the present embodiment, the pixel electrode 23 serves as an anode, and the counter electrode 24 serves as a cathode.

[0040] Sealing films 97, 98, and 99 are provided on the counter electrode 24. The sealing films 97, 98, and 99 have a laminated structure including a silicon nitride film, and have a laminated structure of a silicon nitride film, an organic resin, and a silicon nitride film. A silicon oxide film or an amorphous silicon layer may be provided between the silicon nitride film and the organic resin for the purpose of improving adhesion. Further, an overcoat film 80 is provided on the sealing film 99. The overcoat film 80 is formed of, for example, an organic resin.

[0041] FIG. 4 is a cross-sectional view taken along line IV-IV' of FIG. 1. As shown in FIG. 4, the counter electrode 24 is formed across the display region AA and the cathode contact portion (contact hole H3) provided in the vicinity of the display region AA, and is connected to the lower conductive layer 68 at the cathode contact portion (contact hole H3).

[0042] More specifically, the conductive layer 68 is provided on the interlayer insulating film 93. That is, the conductive layer 68 is provided in the same layer as the source electrode 62 and the drain electrode 63 and is formed of the same material. The counter electrode 24 is electrically connected to the conductive layer 68 via connection electrodes 23a and 26a provided inside the contact hole H3. The connection electrode 23a is provided in the same layer as the pixel electrode 23 and is formed of the same material as the pixel electrode 23. The connection electrode 26a is provided in the same layer as the overlapping electrode 25 and the connection electrode 26 and is formed of the same material as the overlapping electrode 25 and the connection electrode 26.

[0043] Also, as shown in FIG. 4, a dam structure 83 is provided in the peripheral region GA of the array substrate 2. The first convex portion 81 and the second convex portion 82 constituting the dam structure 83 are each formed in a convex cross-sectional shape. The first convex portion 81 and the second convex portion 82 are arranged adjacent to each other in this order from the display region AA toward the end side of the array substrate 2.

[0044] More specifically, the first organic insulating film 94 is removed inside (on the display region AA side) of the first convex portion 81 in the peripheral region GA, and the first convex portion 81 and the second convex portion 82 are provided on the interlayer insulating film 93 in the same layer as the first organic insulating film 94. The first convex portion 81 and the second convex portion 82 may be formed of the same material as the first organic insulating film 94 or may be formed of a material different from the first organic insulating film 94.

[0045] Note that the undercoat film 91, the gate insulating film 92, and the interlayer insulating film 93 are continuously formed from the display region AA to the outer periphery (the end of the array substrate 2) of the peripheral region GA. However, the present invention is not limited to this, and the undercoat film 91, the gate insulating film 92, and the interlayer insulating film 93 may be removed in a part of the peripheral region GA.

[0046] The sealing film 97 is provided across the display area AA to the peripheral area GA and covers the surfaces of the first convex portion 81 and the second convex portion 82. The sealing film 98 is provided on the sealing film 97 across the display area AA to the peripheral area GA. The sealing film 98 is provided inside (on the display area AA side) of the first convex portion 81 and is not provided on the top of the first convex portion 81. In other words, the first convex portion 81 can prevent the sealing film 98 formed of a material softer and more fluid than the sealing films 97 and 99 from flowing out to the outside from the end of the array substrate 2.

[0047] The sealing film 99 is provided across the display area AA to the peripheral area GA and covers the entire surface of the sealing film 98. The sealing film 99 is in contact with the sealing film 97 in an area outside the sealing film 98. More specifically, the sealing film 99 and the sealing film 97 are in contact with each other at the top of the first convex portion 81, the area between the first convex portion 81 and the second convex portion 82, and the top of the second convex portion 82. Thereby, the sealing films 97 and 99 can prevent moisture and the like from entering the inside of the sealing film 98.

[0048] The overcoat film 80 is provided across the display area AA to the peripheral area GA and covers the entire surface of the sealing film 99. The end of the overcoat film 80 overlaps the top of the second convex portion 82. In other words, the second convex portion 82 can prevent the overcoat film 80 formed of a material softer and more fluid than the sealing films 97 and 99 from flowing out to the outside from the end of the array substrate 2.

[0049] Note that the ends of the sealing films 97 and 99 coincide with the ends of the overcoat film 80 and are provided to overlap the top of the second convex portion 82. However, it is not limited to this, and the ends of the sealing films 97 and 99 may be at positions different from the ends of the overcoat film 80. Also, the end of the overcoat film 80 is not limited to being located at the top of the second convex portion 82 and may be disposed between the first convex portion 81 and the second convex portion 82.

[0050] As described above, since the dam structure 83 forms a double dam with the first convex portion 81 and the second convex portion 82, the sealing film 98 and the overcoat film 80 can be prevented from flowing out to the outside from the end portion of the array substrate 2. Note that the dam structure 83 is not limited to a structure having two convex portions (the first convex portion 81 and the second convex portion 82), and may be formed by one first convex portion 81 or may have three or more convex portions. Although not shown, the dam structure 83 is provided in a frame shape surrounding the periphery of the display region AA in plan view.

[0051] As described above, the display device 1 including the light-emitting element 3 is configured. Note that the display device 1 may be provided with a cover panel, a touch panel, or the like above the counter electrode 24 as necessary.

[0052] Next, a method for manufacturing the display device 1 will be described. FIG. 5 is an explanatory diagram for explaining a method for manufacturing a display device according to the first embodiment. Note that in each drawing of FIG. 5, the configuration of the array substrate 2 (from the substrate 21 to the capacitive insulating film 95) is shown in a simplified manner.

[0053] As shown in FIG. 5, the pixel electrode 23 and the bank 96 are formed on the array substrate 2 (step ST1). The pixel electrodes 23 are arranged separately for each sub-pixel SPX. The bank 96 is formed between adjacent pixel electrodes 23 and covers the end portions of the pixel electrodes 23. The pixel electrodes 23 are arranged in a matrix in the display region AA according to the arrangement of the pixels PX and the sub-pixels SPX (see FIGS. 1 and 2). In other words, the pixel electrodes 23 are arranged in the first direction Dx and the second direction Dy in the display region AA.

[0054] Next, a lift-off layer 52 is laminated to cover the plurality of pixel electrodes 23 and the plurality of banks 96 (step ST2). The lift-off layer 52 includes a sacrificial layer 50 and a resin layer 51. The sacrificial layer 50 and the resin layer 51 are laminated in this order on the plurality of pixel electrodes 23 and the plurality of banks 96. The lift-off layer 52 is formed of, for example, a resist resin. The sacrificial layer 50 is formed of a material that is more easily dissolved in a solvent used in a process of peeling off the lift-off layer 52 (steps ST5 and ST6 described later) than the resin layer 51.

[0055] The lift-off layer 52 is provided to cover a plurality of sub-pixels SPX in the display area AA. Although not shown in FIG. 5, the lift-off layer 52 is also continuously formed in the peripheral area GA (see FIG. 6).

[0056] Next, by photolithography and etching, a plurality of first openings OP1 are provided in the area overlapping with the first sub-pixel SPX1 of the lift-off layer 52 (step ST3). The plurality of first openings OP1 are provided in the area overlapping with the pixel electrode 23 of the first sub-pixel SPX1. The sacrificial layer 50 and the resin layer 51 are made of, for example, a negative resist resin material, and the exposed portions remain in the areas overlapping with the second sub-pixel SPX2 and the third sub-pixel SPX3. The inner wall of the first opening OP1 is formed in an inverted taper shape, and the lower end of the inner wall of the first opening OP1 overlaps with the bank 96 located at the end of the pixel electrode 23 of the first sub-pixel SPX1.

[0057] FIG. 6 is a plan view schematically showing the lift-off layer in the display area and the peripheral area provided on the array substrate. FIG. 6 schematically shows an enlargement of the four corners of the peripheral area GA and the display area AA.

[0058] As shown in FIG. 6, the lift-off layer 52 is continuously formed across the display area AA and the peripheral area GA. The lift-off layer 52 formed in the display area AA and the lift-off layer 52 formed in the peripheral area GA both have a structure in which the sacrificial layer 50 and the resin layer 51 are laminated.

[0059] More specifically, as shown in FIG. 6, in the step of step ST3, in the display area AA, a plurality of first openings OP1 are formed at positions overlapping a plurality of pixel electrodes 23 (see FIG. 5) of the lift-off layer 52, and in the peripheral area GA, a plurality of second openings OP2 are formed in the lift-off layer 52. The plurality of second openings OP2 are formed to appropriately control the peeling of the lift-off layer 52 in the peripheral area GA in the steps of peeling the lift-off layer 52 (steps ST5 and ST6 described later). Further, the plurality of second openings OP2 are provided at positions where at least a part thereof does not overlap with the contact hole H3 (see FIG. 7) which is the cathode contact portion.

[0060] The first opening OP1 is formed in a rectangular shape corresponding to the shape of the first sub-pixel SPX. The plurality of first openings OP1 are arranged in the first direction Dx and the second direction Dy corresponding to the arrangement of the plurality of first sub-pixels SPX. The opening width Lx1 of the first opening OP1 in the first direction Dx and the opening width Ly1 in the second direction Dy are respectively formed corresponding to the outer shape of the pixel electrode 23 exposed from the bank 96.

[0061] The first pattern width Wx1 is the length of the lift-off layer 52 in the first direction Dx between the plurality of first openings OP1 adjacent to each other in the first direction Dx in the display area AA. The first pattern width Wx1 corresponds to the width of the adjacent second sub-pixel SPX2 and third sub-pixel SPX3 in the first direction Dx. Further, the first pattern width Wy1 is the length of the lift-off layer 52 in the second direction Dy between the plurality of first openings OP1 adjacent to each other in the second direction Dy in the display area AA. The first pattern width Wy1 is formed to be smaller than the first pattern width Wx1.

[0062] In the peripheral region GA, the plurality of second openings OP2 are each formed in a rectangular shape and arranged in a matrix. The plurality of second openings OP2 are formed in a shape different from that of the plurality of first openings OP1. Also, the arrangement pitch of the plurality of second openings OP2 is different from the arrangement pitch of the plurality of first openings OP1. Specifically, the opening width Lx2 of the second opening OP2 in the first direction Dx is larger than the opening width Lx1 of the first opening OP1 in the first direction Dx. The opening width Ly2 of the second opening OP2 in the second direction Dy is smaller than the opening width Ly1 of the first opening OP1 in the second direction Dy. The second openings OP2 are formed in different directions from the first partial region GAa to the fourth partial region GAd, and the long sides of the second openings OP2 are arranged in a direction along the outer periphery of the array substrate 2. However, the present invention is not limited thereto, and the plurality of second openings OP2 may be formed in the same direction in the peripheral region GA.

[0063] The second pattern width Wx2 is the length of the lift-off layer 52 in the first direction Dx between the plurality of second openings OP2 adjacent to each other in the first direction Dx in the peripheral region GA. The first pattern width Wx1 of the lift-off layer 52 in the display region AA is larger than the second pattern width Wx2 of the lift-off layer 52 from the first partial region GAa to the fourth partial region GAd. Also, the second pattern width Wy2 is the length of the lift-off layer 52 in the second direction Dy between the plurality of second openings OP2 adjacent to each other in the second direction Dy in the peripheral region GA. The first pattern width Wy1 of the lift-off layer 52 in the display region AA is smaller than the second pattern width Wy2 of the lift-off layer 52 in the third partial region GAc and the fourth partial region GAd. The first pattern width Wy1 of the lift-off layer 52 in the display region AA is equal to or smaller than the second pattern width Wy2 of the lift-off layer 52 in the first partial region GAa and the second partial region GAb.

[0064] Note that the shapes and arrangement patterns of the first opening OP1 and the second opening OP2 shown in FIG. 6 are merely examples and can be changed as appropriate. Also, the first pattern widths Wx1, Wy1 and the second pattern widths Wx2, Wy2 of the lift-off layer 52 can also be changed as appropriate.

[0065] In the fifth partial area GAe, no opening is formed, and the lift-off layer 52 is formed in a frame shape surrounding the display area AA. As a result, in the step (step ST3) of forming the plurality of first openings OP1 and the plurality of second openings OP2, the lift-off layer 52 is formed continuously with at least a part thereof connected from the outer edge side of the array substrate 2 (from the first partial area GAa to the fourth partial area GAd) to the display area AA.

[0066] Next, referring back to FIG. 5, an organic EL layer 31(31R) is formed on the lift-off layer 52 and on the pixel electrode 23 that overlaps with the plurality of first openings OP1 (step ST4). That is, the organic EL layer 31(31R) is formed on the pixel electrode 23 of the first sub-pixel SPX1, and in the second sub-pixel SPX2 and the third sub-pixel SPX3, the lift-off layer 52 is provided on the pixel electrode 23, and the organic EL layer 31(31R) is formed on the lift-off layer 52.

[0067] Also, although not shown in FIG. 5, in the peripheral area GA as well, the organic EL layer 31 is formed on the lift-off layer 52 and on the array substrate 2 that overlaps with the plurality of second openings OP2 (see FIG. 7).

[0068] Next, the manufacturing apparatus dissolves the sacrificial layer 50 in the lift-off layer 52 (step ST5). As the processing liquid for the lift-off layer 52, one that dissolves the sacrificial layer 50 and does not dissolve the resin layer 51 and the organic EL layer 31 is selected. The dissolution of the sacrificial layer 50 proceeds from the inner wall of the first opening OP1 toward the inside of the lift-off layer 52.

[0069] Also, although not shown in FIG. 5, in the peripheral area GA as well, the dissolution of the sacrificial layer 50 in the lift-off layer 52 proceeds in the same step. That is, also in the peripheral area GA, the dissolution of the sacrificial layer 50 proceeds from the inner wall of the second opening OP2 toward the inside of the lift-off layer 52. Also, in the peripheral area GA, the dissolution of the sacrificial layer 50 also proceeds from the outer periphery of the lift-off layer 52.

[0070] Next, after the sacrificial layer 50 is dissolved, the lift-off layer 52 (resin layer 51) and the organic EL layer 31 on the lift-off layer 52 are peeled off from the array substrate 2 (step ST6). As a result, the organic EL layer 31 (31R) is formed on the pixel electrode 23 of the first sub-pixel SPX1, and the pixel electrodes 23 of the second sub-pixel SPX2 and the third sub-pixel SPX3 are exposed on the surface of the array substrate 2.

[0071] Here, as shown in FIG. 6, the lift-off layer 52 in the display area AA and the lift-off layer 52 in the peripheral area GA are continuously formed via the fifth partial area GAe. As a result, the lift-off layer 52 in the display area AA and the lift-off layer 52 in the peripheral area GA are peeled off integrally as a single lift-off layer 52 in the common peeling process shown in steps ST5 and ST6.

[0072] More specifically, in the example shown in FIG. 6, the dissolution of the sacrificial layer 50 progresses faster in the lift-off layer 52 in the display area AA where the first opening OP1 is formed and the lift-off layer 52 from the first partial area GAa to the fourth partial area GAd where the second opening OP2 is formed, compared to the lift-off layer 52 in the fifth partial area GAe where no opening is formed.

[0073] For example, in a state where the sacrificial layer 50 in the display area AA and the first partial area GAa to the fourth partial area GAd is dissolved and a part of the sacrificial layer 50 in the fifth partial area GAe remains, the peeled lift-off layer 52 is fixed to the array substrate 2 side in the fifth partial area GAe. Thereafter, when the sacrificial layer 50 in the fifth partial area GAe is dissolved, the lift-off layer 52 in the display area AA is peeled off from the array substrate 2 together with the lift-off layer 52 in the peripheral area GA.

[0074] FIG. 7 is a plan view schematically showing an organic EL layer formed on a display region and a peripheral region. As shown in FIG. 7, in the display region AA, the organic EL layers 31(31R) are arranged on the array substrate 2 corresponding to the first sub-pixels SPX1. Also, in the peripheral region GA, the organic EL layer 31 is formed on the array substrate 2 overlapping a plurality of second openings OP2 (see FIG. 6). The organic EL layer 31 in the peripheral region GA is provided at a position not overlapping with the pixel electrode 23 and does not function as a self-luminous element. That is, the organic EL layer 31 in the peripheral region GA is formed as a dummy organic EL layer 31d.

[0075] The position and shape of the first opening OP1 are set according to the position and shape of each sub-pixel SPX (pixel electrode 23). On the other hand, the second opening OP2 may be in any arrangement as long as the dummy organic EL layer 31d is provided at least partially non-overlapping with the contact hole H3. Also, in the third partial region GAc and the fourth partial region GAd, the arrangement pitch of the dummy organic EL layer 31d is formed in the same pattern as the arrangement pitch of the contact hole H3. However, it is not limited to this, and the arrangement pitch of the dummy organic EL layer 31d may be different from the arrangement pitch of the contact hole H3. Also, the second opening OP2 (dummy organic EL layer 31d) may be formed in a region where the contact hole H3 is not provided.

[0076] In the step of forming the organic EL layer 31 for each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, the positions of the first openings OP1 are formed at different positions corresponding to each sub-pixel SPX. On the other hand, the second opening OP2 may be repeatedly provided at the same position for each step of forming the organic EL layer 31 for each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, or may be at different positions.

[0077] The widths Lx3 and Ly3 of the organic EL layer 31 in the display area AA respectively correspond to the aperture widths Lx1 and Ly1 of the first opening OP1. The intervals Wx3 and Wy3 between adjacent organic EL layers 31 in the display area AA respectively correspond to the first pattern widths Wx1 and Wy1 of the lift-off layer 52. Also, the widths Lx4 and Ly4 of the organic EL layer 31 (dummy organic EL layer 31d) in the peripheral area GA respectively correspond to the aperture widths Lx2 and Ly2 of the second opening OP2. The intervals Wx4 and Wy4 between adjacent organic EL layers 31 (dummy organic EL layer 31d) in the peripheral area GA respectively correspond to the second pattern widths Wx2 and Wy2 of the lift-off layer 52. However, since the first opening OP1 and the second opening OP2 have a tapered shape, the shapes of the first opening OP1 and the second opening OP2 may not match the shape of the organic EL layer 31 on the array substrate 2.

[0078] Next, returning to FIG. 5, steps ST2 to ST6 are repeatedly executed for the second sub-pixel SPX2 and the third sub-pixel SPX3. That is, the lift-off layer 52 is laminated covering the plurality of pixel electrodes 23 and the plurality of banks 96, and a plurality of first openings OP1 are provided in the region overlapping with the second sub-pixel SPX2 of the lift-off layer 52 by photolithography and etching (step ST7).

[0079] An organic EL layer 31 (31G) is formed on the lift-off layer 52 and on the pixel electrodes 23 overlapping the plurality of first openings OP1 (step ST8). That is, the organic EL layer 31 (31G) is formed on the pixel electrode 23 of the second sub-pixel SPX2, and in the first sub-pixel SPX1 and the third sub-pixel SPX3, the lift-off layer 52 is formed on the pixel electrode 23, and the organic EL layer 31 (31G) is formed on the lift-off layer 52.

[0080] Although illustration is omitted hereinafter, in the same manner as steps ST5 and ST6, the lift-off layer 52 and the organic EL layer 31(31G) on the lift-off layer 52 are peeled off. Thereafter, the lift-off layer 52 is further laminated, and a plurality of first openings OP1 are provided in a region overlapping with the third sub-pixel SPX3 of the lift-off layer 52 by a photolithography method and etching. After the organic EL layer 31(31B) is formed on the pixel electrode 23 of the third sub-pixel SPX3, the lift-off layer 52 and the organic EL layer 31(31B) on the lift-off layer 52 are peeled off.

[0081] Note that the above-described manufacturing process is merely an example and can be changed as appropriate. For example, it is not limited to the process of forming the organic EL layer 31 in the order of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3, and any order may be used. Further, the second opening OP2 is not limited to a square shape, and may be other shapes such as a polygonal shape or a shape including a curved portion.

[0082] As described above, the manufacturing method of the display device 1 according to the present embodiment includes a step of forming a lift-off layer 52 (step ST2) on an array substrate 2 having a display area AA in which a plurality of pixel electrodes 23 are arranged and a peripheral area GA surrounding the display area AA; a step of forming a plurality of first openings OP1 at positions overlapping the plurality of pixel electrodes 23 of the lift-off layer 52 in the display area AA and forming a plurality of second openings OP2 in the lift-off layer 52 in the peripheral area GA (step ST3); a step of forming an organic EL layer 31 on the lift-off layer 52 and on the pixel electrodes 23 overlapping the plurality of first openings OP1 (step ST4); and a step of peeling off the lift-off layer 52 and the organic EL layer 31 on the lift-off layer 52 from the array substrate 2 (steps ST5 and ST6). In the step of forming the plurality of first openings OP1 and the second openings OP2 (step ST3), the lift-off layer 52 is formed continuously with at least a part thereof connected from the outer edge side of the array substrate 2 to the display area AA.

[0083] With such a configuration, in the manufacturing method of the display device 1, the lift-off layer 52 in the display area AA and the lift-off layer 52 in the peripheral area GA are peeled off integrally as a single lift-off layer 52 in the common peeling process shown in steps ST5 and ST6. That is, compared with the case where the lift-off layer 52 in the display area AA and the lift-off layer 52 in the peripheral area GA are formed separately, the peeling of the lift-off layer 52 can be easily controlled, and the remaining of foreign matters or the like on the array substrate 2 can be suppressed. Also, compared with the case where the lift-off layer 52 is formed separately, the movement of the peeled lift-off layer 52 to an unintended position can be suppressed, or the peeling of the lift-off layer 52 in an unintended area can be suppressed. Therefore, the manufacturing method of the display device 1 can favorably control the peeling of the lift-off layer 52 and suppress the damage to the organic EL layer 31 and the pixel electrode 23 of the array substrate 2.

[0084] (Second Embodiment) FIG. 8 is a plan view schematically showing the lift-off layer according to the second embodiment. In the following description, the same components as those described in the above-described embodiment are denoted by the same reference numerals, and redundant descriptions are omitted.

[0085] As shown in FIG. 8, in the array substrate 2A of the second embodiment, compared with the above-described first embodiment, in the fifth partial area GAe which is an intermediate area, a configuration in which a plurality of third openings OP3 are formed in the lift-off layer 52 is different. The plurality of third openings OP3 are arranged surrounding the display area AA.

[0086] Here, the fifth partial area GAe adjacent to the display area AA in the second direction Dy will be described. The opening width Lx5 in the first direction Dx of the third opening OP3 in the fifth partial area GAe adjacent to the display area AA in the second direction Dy is larger than the opening width Lx1 in the first direction Dx of the first opening OP1 in the display area AA. Also, the opening width Lx5 in the first direction Dx of the third opening OP3 in the fifth partial area GAe is equal to the opening width Lx2 in the first direction Dx of the second opening OP2 in the first partial area GAa and the second partial area GAb.

[0087] The opening width Ly5 of the third opening OP3 in the second direction Dy is larger than the opening width Ly1 of the first opening OP1 and the opening width Ly2 of the second opening OP2 in the second direction Dy in the display area AA.

[0088] The third pattern width Wx5 is the length of the lift-off layer 52 in the first direction Dx between a plurality of third openings OP3 adjacent to each other in the first direction Dx in the fifth partial region GAe. The third pattern width Wx5 is smaller than the first pattern width Wx1 in the display area AA and is equal to the second pattern width Wx2 in the first partial region GAa and the second partial region GAb.

[0089] The third pattern width Wy5 is the length of the lift-off layer 52 in the second direction Dy between the third opening OP3 and the second opening OP2 adjacent to each other in the second direction Dy. The third pattern width Wy5 is equal to the first pattern width Wy1 in the display area AA and is equal to the second pattern width Wy2 in the first partial region GAa and the second partial region GAb.

[0090] Next, the fifth partial region GAe adjacent to the display area AA in the first direction Dx will be described. The opening width Lx5 of the third opening OP3 in the first direction Dx in the fifth partial region GAe adjacent to the display area AA in the first direction Dx is larger than the opening width Lx1 of the first opening OP1 in the first direction Dx in the display area AA. Also, the opening width Lx5 of the third opening OP3 in the first direction Dx in the fifth partial region GAe is larger than the opening width Lx2 of the second opening OP2 in the first direction Dx in the third partial region GAc and the fourth partial region GAd.

[0091] The opening width Ly5 of the third opening OP3 in the second direction Dy is equal to the opening width Ly1 of the first opening OP1 in the second direction Dy in the display area AA. Also, the opening width Ly5 of the third opening OP3 in the second direction Dy is larger than the opening width Ly2 of the second opening OP2 in the second direction Dy in the third partial region GAc and the fourth partial region GAd.

[0092] The third pattern width Wx5 is the length in the first direction Dx of the lift-off layer 52 between the third opening OP3 and the second opening OP2 adjacent to each other in the fifth partial region GAe. The third pattern width Wx5 is smaller than the first pattern width Wx1 in the display region AA, and is equal to the second pattern width Wx2 in the third partial region GAc and the fourth partial region GAd. In other words, at least one of the first pattern width Wx1 and the second pattern width Wx2 is different from the third pattern width Wx5 in the first direction Dx of the lift-off layer 52 between the third openings OP3.

[0093] The third pattern width Wy5 is the length in the second direction Dy of the lift-off layer 52 between a plurality of third openings OP3 adjacent to each other in the second direction Dy. The third pattern width Wy5 is equal to the first pattern width Wy1 in the display region AA, and is smaller than the second pattern width Wy2 in the third partial region GAc and the fourth partial region GAd.

[0094] Thus, since a plurality of third openings OP3 are formed in the fifth partial region GAe, in the steps (steps ST5, ST6) of peeling the lift-off layer 52 from the array substrate 2, the time required for peeling the lift-off layer 52 in the peripheral region GA can be shortened. As a result, damage to the organic EL layer 31 and the pixel electrode 23 of the array substrate 2 can be suppressed in the peeling step.

[0095] Also, the first pattern width Wx1 is larger than the second pattern width Wx2, and the third pattern width Wx5 is formed to have a size equal to or larger than the second pattern width Wx2 and equal to or smaller than the first pattern width Wx1. That is, the third pattern widths Wx5 and Wy5 are formed so that abrupt changes do not occur with the first pattern widths Wx1 and Wxy and the second pattern widths Wx2 and Wy2 adjacent to each other in the first direction Dx and the second direction Dy. Thereby, it is possible to suppress the formation of a thin portion of the lift-off layer 52, or to suppress the concentration of stress during peeling. Therefore, in the steps (steps ST5, ST6) of peeling the lift-off layer 52 from the array substrate 2, it is possible to suppress a part of the region of the lift-off layer 52 from being separated from other regions and remaining on the array substrate 2.

[0096] (First Modified Example) FIG. 9 is a plan view schematically showing a lift-off layer according to a first modified example of the second embodiment. The opening widths Lx5 and Ly5 of the third opening OP3 and the third pattern widths Wx5 and Wy5 are not limited to the examples shown in FIG. 8 and can be changed as appropriate.

[0097] As shown in FIG. 9, in the array substrate 2B of the first modified example, the opening widths Lx5 and Ly5 of the third opening OP3 are different from the opening widths Lx1 and Ly1 of the first opening OP1 and are also different from the opening widths Lx2 and Ly2 of the second opening OP2.

[0098] Also, with respect to the fifth partial region GAe adjacent to the display region AA in the second direction Dy, the third pattern width Wx5 of the lift-off layer 52 between a plurality of third openings OP3 adjacent to each other in the first direction Dx is larger than the second pattern width Wx2 in the first partial region GAa and the second partial region GAb and smaller than the first pattern width Wx1 in the display region AA. Thus, the third pattern width Wx5 is formed to have a size between the first pattern width Wx1 and the second pattern width Wx2. Along the second direction Dy, the first pattern width Wx1, the third pattern width Wx5, and the second pattern width Wx2 decrease in this order.

[0099] Also, with respect to the fifth partial region GAe adjacent to the display region AA in the first direction Dx, the third pattern width Wy5 of the lift-off layer 52 between a plurality of third openings OP3 adjacent to each other in the second direction Dy is smaller than the second pattern width Wy2 in the third partial region GAc and the fourth partial region GAd and larger than the first pattern width Wy1 in the display region AA. Thus, the third pattern width Wy5 is formed to have a size between the first pattern width Wy1 and the second pattern width Wy2. Along the first direction Dx, the first pattern width Wy1, the third pattern width Wy5, and the second pattern width Wy2 increase in this order.

[0100] In the first modification example, the pattern width of the lift-off layer 52 in the display area AA and the peripheral area GA is gradually varied from the outer edge side of the peripheral area GA toward the display area AA. Thereby, in the process of peeling the lift-off layer 52 from the array substrate 2 (steps ST5 and ST6), the peeling speed of the lift-off layer 52, that is, the order of peeling from the display area AA, the fifth partial area GAe, and the first partial area GAa to the fourth partial area GAd can be well controlled.

[0101] (Third Embodiment) FIG. 10 is a plan view schematically showing a lift-off layer according to the third embodiment. As shown in FIG. 10, in the array substrate 2C of the third embodiment, the corner CN of the outer periphery of the lift-off layer 52 is formed in a zigzag shape. The corner CN of the outer periphery of the lift-off layer 52 is formed in a zigzag shape with a plurality of steps connected in a plan view. More specifically, the zigzag shape is formed by connecting a plurality of straight portions extending in the first direction Dx of the outer periphery of the lift-off layer 52 and straight portions extending in the second direction Dy alternately. The zigzag shape is not limited to the case where the straight portions are connected at right angles, and they may be connected at an angle other than a right angle, or each connection portion may be formed in a curved shape.

[0102] In the process of peeling the lift-off layer 52 from the array substrate 2 (steps ST5 and ST6), since the corner CN is formed in a zigzag shape, the contact area with the processing liquid becomes large, which becomes the starting point of the dissolution of the sacrificial layer 50. Thereby, in the third embodiment, the dissolution of the sacrificial layer 50 proceeds from the inner walls of the respective openings and also from the four corners CN. Thereby, in the third embodiment, the time required for peeling the lift-off layer 52 can be shortened.

[0103] (Second Modification Example) FIG. 11 is a plan view schematically showing a lift-off layer according to a second modification of the third embodiment. As shown in FIG. 11, in the array substrate 2D of the second modification, at least one side of the outer periphery of the lift-off layer 52 is formed with a notch NT recessed toward the display area AA side. In the example shown in FIG. 11, a plurality of notches NT are formed on each of the four sides from the first partial region GAa to the fourth partial region GAd.

[0104] In the steps (steps ST5 and ST6) of peeling the lift-off layer 52 from the array substrate 2, since the notch NT is formed on the outer periphery of the lift-off layer 52, the contact area with the processing liquid becomes large, which serves as a starting point for the dissolution of the sacrificial layer 50. Accordingly, in the third embodiment, as the dissolution of the sacrificial layer 50 proceeds from the inner walls of the respective openings, the dissolution of the sacrificial layer 50 also proceeds from the four corner portions CN and the four sides. Thereby, in the second modification, the time required for peeling the lift-off layer 52 can be shortened.

[0105] Note that in FIG. 11, the outer periphery of the lift-off layer 52 is formed with zigzag corner portions CN, but the present invention is not limited to this, and the corner portions CN may be formed in a curved shape, and a plurality of notches NT may be formed on each of the four sides. Further, the above-described embodiments and modifications can be combined. For example, in the fifth embodiment and the eleventh modification, the opening widths Lx1, Ly1 of the first opening OP1 and the opening widths Lx2, Ly2 of the second opening OP2 may be formed to gradually differ.

[0106] As described above, the preferred embodiments of the present invention have been described, but the present invention is not limited to such embodiments. The content disclosed in the embodiments is merely an example, and various changes can be made without departing from the spirit of the present invention. Appropriate changes made without departing from the spirit of the present invention naturally belong to the technical scope of the present invention. At least one of various omissions, substitutions, and changes of components can be made without departing from the gist of the above-described embodiments and modifications.

Description of Reference Numerals

[0107] 1 Display device 2, 2A, 2B, 2C, 2D Array Substrate 3 Light-Emitting Element 21 Substrate 23 Pixel Electrode 24 Counter Electrode 31, 31R, 31G, 31B Organic EL Layer 31d Dummy Organic EL Layer 50 Sacrificial Layer 51 Resin Layer 52 Lift-Off Layer 96 Bank AA Display Area GA Peripheral Area Lx1, Ly1, Lx2, Ly2, Lx5, Ly5 Aperture Width OP1 First Aperture OP2 Second Aperture OP3 Third Aperture PX Pixel SPX Sub-Pixel Wx1, Wy1 First Pattern Width Wx2, Wy2 Second Pattern Width Wx5, Wy5 Third Pattern Width

Claims

1. A step of forming a lift-off layer on an array substrate having a display area in which a plurality of pixel electrodes are arranged and a peripheral area surrounding the display area; A step of forming a plurality of first openings at positions overlapping the plurality of pixel electrodes of the lift-off layer in the display area, and forming a plurality of second openings in the lift-off layer in the peripheral area; A step of forming an organic EL layer on the lift-off layer and on the pixel electrodes overlapping the plurality of first openings; A step of peeling the lift-off layer and the organic EL layer on the lift-off layer from the array substrate, and In the step of forming the plurality of first openings and the plurality of second openings, the lift-off layer is formed continuously with at least a part thereof connected from the outer edge side of the array substrate to the display area; By the peeling step, In the display area, the organic EL layer is formed on the pixel electrodes for each of a plurality of sub-pixels; In the peripheral area, the organic EL layer formed in a region corresponding to the plurality of second openings is provided at a position not overlapping the pixel electrodes. A method of manufacturing a display device.

2. The peripheral area has an outer edge area in which the plurality of second openings are formed and which is disposed on the outer edge side of the array substrate, and an intermediate area between the outer edge area and the display area, and In the step of forming the plurality of first openings and the plurality of second openings, a plurality of third openings are formed in the lift-off layer in the intermediate area. The method of manufacturing a display device according to Claim 1.

3. The plurality of first openings, the plurality of second openings, and the plurality of third openings are each arranged in a first direction, and At least one of a first pattern width in the first direction of the lift-off layer between the plurality of first openings adjacent to each other in the first direction and a second pattern width in the first direction of the lift-off layer between the plurality of second openings adjacent to each other in the first direction is different from a third pattern width in the first direction of the lift-off layer between the plurality of third openings adjacent to each other in the first direction. The method of manufacturing a display device according to Claim 2.

4. The first pattern width is larger than the second pattern width, and The third pattern width is formed to have a size equal to or greater than the second pattern width and equal to or less than the first pattern width. The method of manufacturing a display device according to Claim 3.

5. The corners of the outer periphery of the lift-off layer are formed in a zigzag shape. A method for manufacturing a display device according to any one of claims 1 to 4.

6. At least one side of the outer periphery of the lift-off layer is formed with a notch recessed toward the display area side. A method for manufacturing a display device according to any one of claims 1 to 5.

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