Data processing system and data processing method

Abstract

To efficiently use resources in FPGA by eliminating auxiliary processing circuits that are provided in an FPGA circuit in preparation for software error and do not operate in normal processing.SOLUTION: A data processing system includes a computing unit comprising a programmable device, and an arithmetic processing unit connected to the computing unit. The computing unit includes: a plurality of processing circuits that executes, in parallel, data processing instructions provided from the arithmetic processing unit; an error detection unit which detects software error generated in a processing circuit executing a data processing instruction; and a processing circuit selection unit which selects a processing circuit to execute the data processing instruction from among the plurality of processing circuits. The processing circuit selection unit identifies a processing circuit in which the software error occurred, on the basis of the software error detected by the error detection unit, and selects a processing circuit to execute the data processing instruction, excluding the processing circuit in which the software error occurred, out of the plurality of processing circuits.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a data processing system and a data processing method.

Background Art

[0002] Regarding functional devices that perform required functions through programming, such as FPGA (Field-Programmable Gate Array), a functional device, a functional maintenance method, and a functional maintenance program that can continuously maintain the function have been provided. A plurality of functional units are provided, and the function is maintained by switching from a malfunctioning functional unit to a standby functional unit. A plurality of functional units, a failure detection unit, and a switching unit are provided to set an operating functional unit and a standby functional unit. That is, the malfunctioning functional unit is put on standby, and the functional unit that was on standby is operated. Therefore, an invention is disclosed that can maintain continuous functions without causing the system to stop operating due to a failure in the functional unit, and the reliability of the system is enhanced by maintaining the function.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] Due to its structure, soft errors may occur in an FPGA where the data written in the configuration memory (hereinafter referred to as CRAM) undergoes bit inversion due to radiation such as neutron rays or alpha rays. When a soft error occurs in the FPGA, the circuit configuration changes. Therefore, an FPGA in which a soft error has occurred may malfunction the device or output incorrect calculation results until the inverted bit is corrected. Since the output of the FPGA while a soft error is occurring lacks reliability, error correction and retry of commands before and after the occurrence of the error are necessary.

[0005] When integrating an FPGA into a mission-critical system, in addition to the normally operating processing circuit, a spare processing circuit (spare system) is prepared to make the system resistant to failures caused by soft errors. In this method, it is necessary to implement an inactive spare system, and there is a problem that circuit resources of the FPGA are consumed to implement a spare system that does not operate in normal processing.

Means for Solving the Problem

[0006] The problem of the present invention is a data processing system including an arithmetic unit composed of a programmable device and an arithmetic processing unit connected to the arithmetic unit. The arithmetic unit includes a plurality of processing circuits that each execute in parallel data processing instructions provided from the arithmetic processing unit, an error detection unit that detects a soft error occurring in a processing circuit during execution of a data processing instruction, and a processing circuit selection unit that selects a processing circuit to execute a data processing instruction from among the plurality of processing circuits. The processing circuit selection unit identifies a processing circuit in which a soft error has occurred based on the soft error detection result of the error detection unit, and selects a processing circuit to execute a data processing instruction excluding the processing circuit in which a soft error has occurred from among the plurality of processing circuits. This is achieved by a data processing system characterized by the above.

Effect of the Invention

[0007] According to the present invention, a redundant data processing system that effectively utilizes the capacity of a semiconductor can be realized.

[0008] Problems, configurations, and effects other than those described above will be clarified by the description of the following embodiments.

Brief Description of the Drawings

[0009]

Figure 1

Figure 2

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Figure 4

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Figure 10

Figure 11

Mode for Carrying Out the Invention

[0010] Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the drawings for explaining the embodiments, the same components are denoted by the same names and reference numerals, and the repeated description thereof will be omitted.

[0011] The present invention is not limited to the embodiments described below, and includes various modifications and equivalent configurations within the scope of the appended claims. For example, the above-described embodiments have been described in detail for easy understanding of the present invention, and the present invention is not necessarily limited to those having all the configurations described.

[0012] Further, the processing units described in the embodiments may be realized in hardware by designing some or all of them, for example, by using an integrated circuit, or may be realized in software by a processor interpreting and executing a program for realizing each function.

[0013] The tables, regions, etc. described in the embodiments may be a database (DB) or data stored in the main memory.

Embodiment

[0014] Figure 1 is an example of a system configuration diagram in an embodiment of the present invention. The data processing system 1 includes a CPU (Central Processing Unit) 2, a main memory 3, an arithmetic unit (FPGA (Field-Programmable Gate Array)) 4, and a host IF (Interface) 5. The CPU 2 and the arithmetic unit 4 share a data bus for the main memory 3 and perform data access to the main memory 3 through the data bus respectively.

[0015] The CPU 2 includes a host command processing unit 7 that receives a processing request from the host IF 5 and analyzes the command included in the request, an arithmetic unit processing unit 8 that performs communication processing of commands and their processing results with the arithmetic unit 4, and a control unit 9 that controls command processing in the system 1.

[0016] These control units and processing units may be stored in the main memory 3 and executed by the CPU 2, or may be realized by hardware.

[0017] The arithmetic unit 4 includes one or more DMACs (Direct Memory Access Controllers) 17, a DMAC selection unit 13 that selects a DMAC 17 to execute DMA command processing, a DMAC management table 14 that stores the status information of the DMAC, etc., and a command control unit 19 that transmits and receives DMA commands between the CPU 2 and the DMAC selection unit 13. Each DMAC 17 stores a plurality of processing circuits 18 that execute data processing based on DMA commands, and further includes an IP selection unit 15 that selects a processing circuit and an IP management table 16 that stores the status information of the processing circuit.

[0018] Also, the DMAC 17 selected by the DMAC selection unit 13 executes DMA with the main memory 3 during data processing based on the DMA command. That is, it directly reads commands and stores command execution results between the main memory 3 and the command execution result storage area 10, and stores command processing data read and processed data between the data storage area 11.

[0019] In the case where only one DMAC 17 is mounted on the arithmetic unit 4 in this embodiment, the DMAC selection unit 13 is not necessarily required.

[0020] The main memory 3 includes a command execution result storage area 10 for storing the details of the DMA command and its execution results, a data storage area 11 for storing data before and after the processing circuit processes the DMA command, and an IP error count management table 12 for managing the error count of the processing circuit.

[0021] The CPU 2 and the arithmetic unit 4 are connected by a PCIe (Peripheral Component Interconnect express) interface or the like. However, other communication protocols may be used for the connection.

[0022] FIG. 2 is an example of the hardware configuration of the arithmetic unit in the embodiment of the present invention.

[0023] The CPU 2 is connected to the arithmetic unit 4. In this example, PCIe 22 and an Internal Bus Switch 23 are mounted on the arithmetic unit and connected to the DMAC selection unit 13. The DMAC selection unit 13 is connected to a plurality of DMACs 17, and the DMAC 17 includes an IP group (processing circuit group) 26 on which a plurality of processing circuits 18 are mounted. As will be described later with reference to FIG. 4, each processing circuit 18 is provided in a corresponding IP control unit, but is shown in a simplified manner in FIGS. 1 to 3 for functional explanation.

[0024] The IP selection unit (arbiter) 15 selects the processing circuit 18 that executes the DMA command among these processing circuits.

[0025] The SEU (Single Event Upset) detection and correction mechanism 28 corrects errors in the processing circuit 18. Specifically, the SEU detection and correction mechanism 28 periodically performs a cyclic check on a CRAM (not shown) storing the circuit configuration of the FPGA included in the arithmetic unit 4, and corrects errors when detecting errors in the processing circuit 18.

[0026] FIG. 3 is an example of a DMAC in an embodiment of the present invention. Here, it is described that one DMAC 17 is selected by the DMAC selection unit 13 to execute a DMA command.

[0027] The DMAC 17 selected by the DMAC selection unit 13 acquires information regarding the DMA command from the command / execution result storage area 10 of the main memory 3 by DMA transfer based on the DMA command, and reads processing data from the data storage area 11 based on the acquired DMA command.

[0028] The IP selection unit 15 in the selected DMAC 17 receives the DMA command and the processing data, and sends them to the selected processing circuit 18 as data processing targets. In FIG. 3, IP0 in the processing circuit 18 is shown as being selected. The selected processing circuit IP0 executes the DMA command and outputs a command execution result and processed data. The selected DMAC 17 stores the command execution result and the processed data in the command / execution result storage area 10 and the data storage area 11 respectively by DMA. If an error occurs in the selected processing circuit IP0 during command processing, it is excluded from the selection targets, and another processing circuit as a selection target candidate is selected to continue the command processing.

[0029] FIG. 4 is an example of the detailed configuration of the arithmetic unit 4 in an embodiment of the invention. The DMAC 17 includes a receiving unit 42 that receives a DMA command from the DMAC selection unit 13, a transmitting unit 43 that transmits the processing result of the processing circuit 18 to the DMAC selection unit 13, and an IP selection unit 15 that selects and outputs the processing circuit 18 that executes the DMA command.

[0030] Each IP control unit 41 includes a processing circuit 18 and an error detection circuit 45 that detects a soft error generated by the processing circuit 18. The error detection circuit 45 detects the occurrence of a soft error by detecting a change in the circuit configuration of the processing circuit 18. Examples of the method for detecting a change in the circuit configuration include (1) adding an error correction code to a transmission path inside the processing circuit, (2) immediately decompressing compressed data and comparing the obtained result with the original data (when the processing circuit 18 supports data compression and decompression), and (3) verifying an error detection code given in advance during data decoding (when the processing circuit 18 supports data encryption and decryption). However, other methods may also be adopted.

[0031] Next, the tables used in this embodiment will be described with reference to FIGS. 9 - 11.

[0032] FIG. 9 shows an example of an IP error count management table 12 in an embodiment of the present invention. The IP error count management table 12 is stored in the main memory 3 and includes a #DMAC number 111 column for identifying each DMAC, a #IP number 112 column for identifying each processing circuit in each DMAC, an error occurrence count 113 column for the processing circuit corresponding to the #IP number, and an error count threshold 115 column for the processing circuit corresponding to the #IP number.

[0033] The IP error count management table 12 is referred to by the control unit 19 of the CPU 2, and the error occurrence count 113 is stored for each processing circuit 18 included in each DMAC. Then, when the error occurrence count 113 reaches a predetermined number, it is used to set the arbitration participation disabled column 134 of the IP management table 16, which will be described later, to 1 (ON) to make it non - selectable.

[0034] FIG. 10 shows an example of a DMAC management table 14 in an embodiment of the present invention. The DMAC management table 14 is stored in the arithmetic unit 4 and includes a #DMAC number 121 column, a Busy 122 column indicating whether all processing circuits belonging to the DMAC corresponding to the #DMAC number are in processing, and a command receivable column 123 indicating whether the DMAC corresponding to the #DMAC number can receive a command. When the system includes multiple DMACs, the DMAC selection unit 13 manages the use of DMACs using this table. When all the processing circuits 18 included in a DMAC are in processing, all the processing circuits 18 turn on the Busy column 122 (to 1) so that the DMAC is not selected. In this example, when all the processing circuits 18 are in processing, the command reception enabled column 123 is set to No so that the DMAC is not selected.

[0035] A column for registering the number of processing circuits 18 held by the DMAC and the number of processing circuits 18 in processing may be provided. When the DMAC selection unit makes a selection, the number of processing circuits 18 in processing is incremented by 1, and when the processing of the processing circuit 18 ends, the number of processing circuits 18 in processing is decremented by 1 to obtain the usage rate of the processing circuits 18 in the DMAC, and a DMAC with a low usage rate may be selected.

[0036] In addition to this, when the data processing amount for each process requested from the host varies greatly, instead of counting the number of processes, a column for counting the amount of data processed may be provided, and the DMAC to be used may be selected based on the data processing amount.

[0037] In addition to this, load information indicating that a large proportion of the processing circuits 18 held by the DMAC are in use, performance information indicating the processing speed of the DMAC, etc. may be provided so that it is possible to know which DMAC has a high usage priority and which has a low usage priority, and the system can be operated efficiently.

[0038] Furthermore, different types of processing circuits 18 may be installed for each DMAC, and the DMAC may be selected according to the process requested from the host.

[0039] FIG. 11 is an example of the IP management table 16 in an embodiment of the present invention. The IP management table 16 is provided for each DMAC, and includes a processing column 132 indicating whether the processing circuit 18 is in processing for each DMAC, a cycle correction waiting column 133 indicating whether waiting for cycle correction, an arbiter participation impossible column 134 indicating that processing cannot be performed, and a command reception possible column 135 indicating whether a command can be received.

[0040] If all columns of 132 - 134 are OFF(0), the command reception possible column is set to Yes, indicating that the processing circuit 18 is capable of processing. In addition, by storing information such as the type and version of the processing circuit 18, the available processing circuit 18 and the processing circuit 18 with a high usage priority can be represented.

[0041] Next, the command processing operation in the system of this embodiment will be described with reference to FIG. 5.

[0042] The host command processing unit 7 of the CPU 2 receives a processing request from the host, analyzes the host command included in the request, and passes the analysis result to the control unit 9. The host command is a read or write command for specified data with respect to a logical storage area that can be referenced by the host provided by the system 1, and the storage area is set in association with the main memory 3.

[0043] The control unit 9 identifies a DMA command (hereinafter, DMA command) involving data processing with the arithmetic unit 4 corresponding to the received host command, and data to be processed by the DMA command (hereinafter, data to be processed), and stores the DMA command in the command / execution result storage area 10 of the main memory 3 and the data to be processed in the data storage area 11, respectively.

[0044] Examples of instructions by the DMA command include, for example, "Read plaintext from address XX (in main memory 3), compress it, and write the compressed data to address XX", and "Read the compressed data from address XX (in main memory 3), decompress it, and write it to address XX". In this embodiment, the address of the data to be processed specified by the DMA command is directly used as the address of the data storage area 11. With such a configuration, by accessing the address of the command execution result storage area 10 where the DMA command is stored and referring to the DMA command, the address of the data storage area 11 where the data to be processed is stored can be specified.

[0045] Thereafter, the arithmetic unit processing unit 8 transmits a command reception notification including the address of the DMA command stored in the command execution result storage area 10 to the arithmetic unit 4 (S50). Note that the command reception notification may not include the address of the DMA command. In this case, the address of the command execution result storage area 10 where the DMA command is stored is determined in advance in the system 1, and the command control unit 19 that has received the command reception notification in the arithmetic unit 4 may access the address to read the DMA command.

[0046] In the arithmetic unit 4, the command reception notification is transmitted to the command control unit 19 via the PCIe 22 and the Internal Bus Switch 23. Based on the address of the command execution result storage area 10 included in the notification, the command control unit 19 reads the DMA command and the data to be processed based on the DMA command from the main memory 3, respectively, and transmits them to the DMAC selection unit 13. The DMAC selection unit 13 that has received the DMA command and the data to be processed refers to the command reception enabled column 123 of the DMAC management table 14 to determine whether there is a DMAC 17 that can receive the command (S51). Here, the fact that the DMAC can receive the command means that there is at least one data processing capable processing circuit 18 that is not blocked in the DMAC.

[0047] When there is a DMAC17 capable of receiving commands (Yes in S51), the DMAC selection unit 13 selects any one of the DMACs 17 capable of receiving commands, and transmits a DMA command and the data to be processed. As for the condition for selecting a DMAC, it is possible to select the first found DMAC capable of receiving commands. However, if the load status of the DMAC is examined and a DMAC with a low load is selected, the processing can be distributed, contributing to an improvement in processing efficiency.

[0048] When there is no DMAC17 capable of receiving commands (No in S51), for example, when the processing circuits 18 in all DMACs 17 are in the process of command processing, the DMAC selection unit 13 continues to monitor until a DMAC17 is found in which the processing is completed in any one of the processing circuits 18 and the Busy column 122 of the DMAC management table 14 becomes OFF (0).

[0049] In the selected DMAC17, the DMA command and the data to be processed are received by the receiving unit 42 and output to the IP selection unit 15. When the IP selection unit 15 receives the DMA command and the data to be processed, it refers to the command receivable column 135 of the IP management table 16 and determines whether there is a processing circuit 18 capable of receiving commands among the processing circuits 18 to be selected (S52). The fact that there is a processing circuit 18 capable of receiving commands means that there is a data - processable processing circuit 18 that is not in the process of processing, not waiting for cyclic correction, and not unavailable for arbiter participation.

[0050] When there is a processing circuit 18 capable of receiving commands (Yes in S52), the IP selection unit 15 selects any one of the processing circuits 18 capable of receiving commands and transmits a command reception notification. Regarding the selection of the processing circuit 18, if information such as the number of error occurrences is used to select a processing circuit with fewer error occurrences, it will lead to error reduction and enable more efficient processing.

[0051] When there is no processing circuit 18 capable of receiving commands (No in S52), the IP selection unit 15 continues to monitor until a processing circuit 18 in which the command receivable column 135 of the IP management table 16 becomes Yes is found.

[0052] When the IP selection unit 15 selects the processing circuit 18 capable of receiving commands, it passes the DMA command and the data to be processed to the corresponding IP control unit 41. When the IP control unit 41 transmits it to the selected processing circuit 18, the processing circuit 18 starts command processing (S53).

[0053] In performing command processing, the processing circuit 18 performs DMA for accessing the address of the data storage area 11 where the data to be processed is stored. Specifically, the receiving unit 42 receives the data read from the corresponding address, the processing circuit 18 processes the data, and notifies the completion of the processing to the transmitting unit 43. Upon receiving the completion notification from the processing circuit 18, the transmitting unit 43 transmits the processed data to the main memory 3 to execute DMA.

[0054] Returning to the description of FIG. 5, when the data to be processed read from the data storage area 11 is received by the receiving unit 42 and output to the processing circuit 18 selected via the IP selection unit 15, data processing based on the DMA command is executed. When the processing of the processing circuit 18 ends normally (No in S54), it transmits the DMA command including the processing result of the command to the command control unit 19 via the IP selection unit 15 and the DMAC selection unit 13, and transmits the processed data to the transmitting unit 43.

[0055] The transmitting unit 43 directly transmits and writes the processed data to the address of the data storage area 11 where the data to be processed is stored. Also, the command control unit 19 transmits the processing result and the address of the command execution result storage area 10 where the DMA command is stored to the CPU 2 (S57).

[0056] The processing result is received by the arithmetic processing unit 8 in the CPU 2, and the control unit 9 writes the response result to the address of the command execution result storage area 10 where the DMA command is stored. Further, the control unit 9 transmits the processing result to the host via the host IF 5.

[0057] If the processing circuit 18 generates an error (including an error caused by a soft error) during command processing (Yes in S54), the corresponding error detection circuit 45 detects the error and notifies the IP selection unit 15. The IP selection unit 15 that has received the error notification transmits an error DMA command including the number of the processing circuit in which the error has occurred to the command control unit 19. The command control unit 19 transmits the error DMA command to the arithmetic processing unit 8 of the CPU 2, and after receiving the DMA command, the control unit 9 of the CPU 2 executes error handling (S55). The details of the error handling will be described later with reference to FIG. 6.

[0058] The IP selection unit 15 sets the pending column 133 for cyclic correction corresponding to the processing circuit 18 in which the error has occurred in the IP management table 16 to ON (1) and the command receivable column 135 to No.

[0059] The SEU detection and correction mechanism 28 periodically performs a cyclic correction check of the CRAM and corrects the error of the processing circuit 18 in which the error has occurred with a cyclic correction period on the order of several hundred milliseconds (S56). When the error correction is completed, the IP selection unit 15 sets the pending column 133 for cyclic correction corresponding to the processing circuit 18 in which the error has occurred in the IP management table 16 to OFF (0), and if the corresponding in-processing column 132 and the arbiter participation disable column 134 are also OFF (0), the command receivable column 135 is set to Yes.

[0060] Also, the error detection circuit 45 may reset the arbiter participation disable column 134 in the IP management table 16 at a predetermined period, for example, the cyclic correction period, so that the corresponding processing circuit 18 can be selected. By such processing, it becomes possible to effectively use the available processing circuit 18.

[0061] FIG. 6 shows an example of the error handling process S55 of the CPU 2. When the control unit 9 receives an error DMA command from the IP selection unit 15 of the DMAC 17 where an error has occurred (S60), the control unit 9 increments by 1 the error occurrence count 113 of the corresponding processing circuit in the IP error count management table 12 (FIG. 9) (S61). It is determined whether the error occurrence count of the processing circuit is equal to or greater than the error count threshold in the IP error count management table 12 (S62). If it is equal to or greater than the error count threshold, access is made to the setting register 81 of the DMAC 17 to which the error command was transmitted, and the flag in the arbitration participation disabled 134 column corresponding to the processing circuit 18 that generated the error in the IP management table 16 (FIG. 11) is set to ON (S63). Thereafter, the processing circuit 18 is excluded from the selection targets by the IP selection unit 15 unless the arbitration participation disabled column 134 is reset to OFF (0). The assignment of processing to the processing circuit 18 is executed with reference to the DMAC management table 14 and the IP management table 16. The entities of the DMAC management table 14 and the IP management table 16 exist on the registers of the arithmetic unit 4.

[0062] The arithmetic unit processing unit 8 refers to the setting register 81 in the DMAC and issues a retry request for the DMA command (S65). That is, the arithmetic unit processing unit 8 resends to the arithmetic unit 4 a command reception notification including the address of the DMA command stored in the command execution result storage area 10, and thereafter the command processing operation is performed again according to the flow described in FIG. 5. Alternatively, after the command control unit 19 of the arithmetic unit 4 transmits the error DMA command to the CPU 2, it may access the address of the command execution result storage area 10 in which the DMA command is stored and execute the DMA command again.

[0063] If the error occurrence count is not equal to or greater than the error count threshold in S62, the control unit 9 retries the corresponding command.

[0064] FIG. 7 is an example of a sequence at the time of a soft error occurrence in an embodiment of the present invention. In FIG. 7, it is assumed that there is only one DMAC 17 in the arithmetic unit 4, or that the DMAC 17 that processes host commands has already been selected from a plurality of DMACs 17 for explanation.

[0065] When the command control unit 19 of the arithmetic unit 4 receives a command reception notification including the address of the DMA command stored in the command execution result storage area 10 from the arithmetic unit processing unit 8 of the CPU 2, based on the address, the command control unit 19 reads out the DMA command (hereinafter referred to as a command in FIGS. 7 and 8) and the data to be processed from the main memory 3 and transmits them to the DMAC selection unit 13 (S71).

[0066] When the IP selection unit 15 in the DMAC 17 receives the DMA command and the data to be processed, it refers to the IP management table 16 to select the processing circuit 18 that performs command processing and transfers it to the selected processing circuit 18 (S72). In this example, IP_0 of the DMAC 17 is selected. When a soft error occurs in IP_0 and the circuit configuration changes, a corresponding error detection circuit (not shown) detects the failure and notifies the error notification to the IP selection unit 15 (S73). The IP selection unit 15 returns an error DMA command (hereinafter referred to as an error command in FIGS. 7 and 8) including the number of the processing circuit in which the error has occurred to the command control unit 19 (S74).

[0067] When the command control unit 19 receives the error DMA command, it transmits it to the CPU 2 and requests a retry of the DMA command. When a command acceptance notification is transmitted again from the arithmetic unit processing unit 8 of the CPU 2 in response to the retry, the command control unit 19 transmits the DMA command and the data to be processed read from the main memory 3 to the DMAC 17 again, and the IP selection unit 15 receives this (S75).

[0068] The IP selection unit 15 selects a processing circuit IP_x that has not generated an error and transfers the command (S76). When IP_x correctly processes the command and the data processing of the requested content is completed, the data processing result is written to the data storage area 11 by DMA, and a DMA command including the processing result as a normal response is returned to the IP selection unit 15 (S77). The IP selection unit 15 returns the DMA command to the command control unit 19 (S78). During this period, in IP_0 where an error has occurred, the SEU detection and correction mechanism 28 corrects the correctable error in the cyclic correction period (S79) (S80). The IP selection unit 15 does not select IP_0 as a selection target for a certain period longer than the cyclic correction period, and adds it to the selection target after a certain period has elapsed.

[0069] FIG. 8 is an example of a processing sequence when an uncorrectable error occurs in an embodiment of the present invention. This example shows the sequence in the case of a system including a plurality of DMACs, but the DMAC is also applicable to a system with one DMAC.

[0070] When the command control unit 19 of the arithmetic unit 4 receives a command reception notification including the address of the DMA command stored in the command execution result storage area 10 from the arithmetic processing unit 8 of the CPU 2 (S82), based on the address, the command control unit 19 reads the DMA command and the data to be processed from the main memory 3 and transmits them to the DMAC selection unit 13 (S83). The DMAC selection unit 13 refers to the DMAC management table 14 and selects DMAC_0 as the DMAC 17 for performing command processing, and transmits the DMA command and the data to be processed (S84).

[0071] A series of operations ((S85)-(S88)) in which the IP selection unit 15 that has received the DMA command and the data to be processed in DMAC_0 selects the processing circuit IP_0 and executes command processing, and receives a notification of failure detection based on a soft error and transmits an error command are the same as those in FIG. 7, so detailed description is omitted. However, the error DMA command transmitted by the IP selection unit 15 includes not only the number of the processing circuit IP_0 where the error has occurred but also the number of the selected DMAC_0.

[0072] When the command control unit 19 receives a command acceptance notification again from the arithmetic processing unit 8 of the CPU 2 based on a command retry request (S92), it reads out the DMA command and the data to be processed from the main memory 3 and transmits them again to the DMAC selection unit 13 of the arithmetic unit 4 (S93). When the DMAC selection unit 13 selects DMAC_0 again, the DMA command and the data to be processed are transmitted to the IP selection unit 15 (S94). Since the processing circuit IP_0 is recognized as a selection target if error correction is being performed, when the IP selection unit 15 selects the processing circuit IP_0 again, the command processing is executed (S95).

[0073] If the error correction of the processing circuit IP_0 fails, that is, if it is an uncorrectable error, the error DMA command is returned again via the IP selection unit 15 and the DMAC selection unit 13 ((S96)-(S98)).

[0074] When receiving the error DMA command, the control unit 9 of the CPU 2 increments the occurrence count value of the processing circuit IP_0 in the 113 column of the error occurrence count corresponding to DMAC_0 and the processing circuit IP_0 in the IP error count management table 12, and compares the occurrence count with the corresponding error count threshold 115. If the occurrence count is equal to or greater than the threshold, the arbitration participation impossible column 134 of the processing circuit IP_0 in the IP management table 16 stored in the DMAC internal setting register 81 of DMAC_0 is set to 1 (ON), and the command receivable column 135 is set to No (S101). Thereafter, the IP selection unit 15 recognizes the processing circuit IP_0 as not receivable of commands and does not select it as a selection target.

[0075] According to the sequence example described above, in the correction process, when an uncorrectable soft error occurs in the processing circuit IP_0 and an error command occurs a specified number of times, it is permanently excluded from the selection targets. Therefore, the command processing is continued by other command-receivable processing circuits, and an infinite loop of command retry due to the selection of the processing circuit IP_0 can be prevented.

[0076] By controlling the arbiter participation of the processing circuit 18 using the DMAC internal setting register 81, it becomes easier to determine the arbiter participation conditions using the information registered in the IP error count management table 12 under conditions that match the needs of a system that performs soft error processing.

[0077] It is not necessarily required to block on a single error correction failure, but it can be blocked when the number of error correction failures reaches a predetermined number. Furthermore, since the processing circuit 18 that has been blocked once can be operated again, it can be reused within a predetermined period. The conditions for blocking the processing circuit 18 and the conditions for reuse can be appropriately adjusted according to the system to which they are applied.

[0078] According to the above-described embodiment, one or more DMACs 17 are included in the arithmetic unit 4 of the FPGA. Each DMAC 17 includes a plurality of processing circuits 18 that process commands from the host 150, and an IP selection unit 15 that selects a processing circuit 18 capable of executing a command when the command is received. When a soft error occurs in the processing circuit 18 during command execution and the circuit configuration is changed, the error of the processing circuit 18 is notified to the IP selection unit 15. The IP selection unit 15 excludes the processing circuit 18 from the selection target in response to the notification and can select another executable processing circuit 18. Therefore, even if a soft error occurs in the processing circuit during command execution, command execution can be continued in another executable processing circuit, and the influence of malfunction of the FPGA due to the occurrence of a soft error can be reduced.

[0079] Since each processing circuit 18 can execute commands in parallel as a processing system that operates normally, the usage efficiency of the circuit resources of the FPGA is increased compared to the case of having an inactive standby circuit. Also, when N processing circuits are mounted on the DMAC 17, system down can be avoided until errors occur in N - 1 processing circuits.

[0080] In addition, for the processing circuit 18 in which an error has occurred, the SEU detection and correction mechanism 28 performs error correction processing in the cycle correction period and implements repair of the circuit configuration. By being set to be selectable again from the IP selection unit 15 after the passage of a cycle, the redundancy of the processing circuit 18 is quickly recovered, and the influence of malfunction of the FPGA due to the occurrence of a soft error can be further reduced.

[0081] In addition, the control unit 19 of the CPU 2 receives an error command from the processing circuit 18 in which an error has occurred, counts and monitors the number of error occurrences in each processing circuit 18, and blocks the processing circuit in which an error occurrence exceeding a specified number has been detected so that it is not selected from the IP selection unit 15 in the same DMAC 17. For this reason, it is possible to avoid an infinite loop of command retry caused by the processing circuit in which an uncorrectable error that cannot be repaired by error correction being set to be selectable after the error correction is performed, and the availability at the time of occurrence of an uncorrectable error can be improved.

Explanation of Signs

[0082] 1 Data processing system, 2 CPU, 3 Main memory, 4 Arithmetic unit (FPGA), 5 Host IF, 7 Host command processing unit, 8 Arithmetic unit processing unit, 9 Processing request reception unit, 10 Command / execution result storage area, 11 Data storage area, 12 IP error count management table, 13 DMAC selection unit, 14 DMAC management table, 15 IP selection unit, 16 IP management table, 17 DMAC, 18 Processing circuit, 19 Command control unit

Claims

1. A data processing system including an arithmetic unit composed of a programmable device and an arithmetic processing unit connected to the arithmetic unit, The arithmetic unit includes, A plurality of processing circuits that each execute in parallel the data processing instructions provided from the arithmetic processing unit, An error detection unit that detects a soft error occurring in a processing circuit during execution of a data processing instruction, A processing circuit selection unit that selects a processing circuit for executing a data processing instruction from among the plurality of processing circuits, An error detection and correction circuit that detects soft errors for the plurality of processing circuits at a specific period and corrects the detected soft errors, The processing circuit selection unit identifies a processing circuit in which a soft error has occurred based on the soft error detection result of the error detection unit, and selects a processing circuit for executing a data processing instruction excluding the processing circuit in which a soft error has occurred among the plurality of processing circuits, After the elapse of the period from the identification of the processing circuit in which a soft error has occurred, the data processing system is characterized in that the processing circuit is selected as a target for selection as a processing circuit for executing a data processing instruction.

2. A data processing system including an arithmetic unit composed of a programmable device and an arithmetic processing unit connected to the arithmetic unit, The arithmetic unit includes, A plurality of processing circuits classified into a plurality of processing circuit groups that each execute in parallel the data processing instructions provided from the arithmetic processing unit, An error detection unit that detects a soft error occurring in a processing circuit during execution of a data processing instruction, And a processing circuit selection unit provided corresponding to each processing circuit group that selects a processing circuit for executing a data processing instruction from among the plurality of processing circuits, The processing circuit selection unit identifies a processing circuit in which a soft error has occurred based on the soft error detection result of the error detection unit, and selects a processing circuit that executes a data processing instruction excluding the processing circuit in which the soft error has occurred from among the plurality of processing circuits. A data processing system characterized by that.

3. The data processing system according to claim 1 or claim 2, wherein the processing circuit selection unit does not select the processing circuit as a processing circuit that executes a data processing instruction when a soft error occurs a specified number of times or more in a specific processing circuit.

4. In the arithmetic unit, the plurality of processing circuits are classified into a plurality of processing circuit groups, The data processing system according to claim 3, characterized in that a processing circuit selection unit is provided corresponding to each processing circuit group.

5. The arithmetic unit has a processing circuit group selection unit that selects a processing circuit group that executes a data processing instruction from among the plurality of processing circuit groups, The data processing system according to claim 4, wherein the processing circuit group selection unit selects a processing circuit group that executes a data processing instruction based on the execution status of the data processing instructions of the processing circuits belonging to each processing circuit group.

6. A data processing method in a data processing system including an arithmetic unit composed of a programmable device and an arithmetic processing unit connected to the arithmetic unit, The arithmetic unit is A plurality of processing circuits that execute in parallel the data processing instructions provided from the arithmetic processing unit, An error detection unit that detects a soft error occurring in a processing circuit during execution of a data processing instruction, And a processing circuit selection unit that selects a processing circuit that executes a data processing instruction from among the plurality of processing circuits, The error detection unit detects the occurrence of a soft error in a processing circuit during execution of a data processing instruction, An error detection and correction circuit detects soft errors in the plurality of processing circuits at a specific period and corrects the detected soft errors. The processing circuit selection unit identifies a processing circuit in which a soft error has occurred based on the soft error detection result of the error detection unit, and selects a processing circuit that executes the data processing instruction excluding the processing circuit in which the soft error has occurred among the plurality of processing circuits. A data processing method characterized in that, after the elapse of the period from the identification of the processing circuit in which the soft error has occurred, the processing circuit is selected as a processing circuit to execute a data processing instruction.

7. A data processing method in a data processing system including an arithmetic unit configured by a programmable device and an arithmetic processing unit connected to the arithmetic unit, The arithmetic unit includes a plurality of processing circuits classified into a plurality of processing circuit groups that each execute in parallel data processing instructions provided from the arithmetic processing unit, an error detection unit that detects a soft error occurring in a processing circuit during execution of a data processing instruction, and a processing circuit selection unit provided corresponding to each processing circuit group that selects a processing circuit to execute a data processing instruction from among the plurality of processing circuits. The data processing method is characterized in that the processing circuit selection unit identifies a processing circuit in which a soft error has occurred based on the soft error detection result of the error detection unit, and selects a processing circuit that executes a data processing instruction excluding the processing circuit in which the soft error has occurred among the plurality of processing circuits.

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