Memory system

Abstract

To reduce segmentation of data of a memory system with a semiconductor memory device and improve reliability of the data.SOLUTION: A memory system comprises a nonvolatile memory including blocks, a memory controller capable of controlling the nonvolatile memory. The memory controller holds a first tag information management table for managing tag information allocated to a logical address in the nonvolatile memory based on the number of erasures, and performs garbage collection of the nonvolatile memory based on the tag information.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] This embodiment relates to a memory system.

Background Art

[0002] In recent years, memory systems equipped with non-volatile memories such as NAND type flash memories have become widely popular.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In one embodiment of the present invention, fragmentation of data in a memory system equipped with a semiconductor memory device is suppressed and reliability is improved.

Means for Solving the Problems

[0005] The memory system of this embodiment includes a non-volatile memory having blocks and a memory controller capable of controlling the non-volatile memory. The memory controller holds a first tag information management table that manages tag information assigned to the logical addresses of the non-volatile memory based on the number of erase times It does. The tag information is assigned values arranged in order based on the information regarding the number of erasures. The memory controller is for data corresponding to a logical address to which tag information having a value equal to or less than that of the first tag information included in the tag information, excluding the tag information of invalid data, is assigned Performs garbage collection.

Brief Description of the Drawings

[0006]

Figure 1

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Mode for Carrying Out the Invention

[0007] Hereinafter, embodiments for carrying out the invention will be described. For substantially the same components, the same reference numerals will be given and the description thereof will be omitted.

[0008] (First Embodiment)

[0009] The memory system according to the first embodiment will be described with reference to FIGS. 1 to 7.

[0010] (Configuration)

[0011] The configuration of the memory system according to the first embodiment will be described with reference to FIGS. 1 to 4.

[0012] FIG. 1 is a block diagram showing an example of the configuration of the memory system according to the first embodiment. The memory system 1 includes a non-volatile memory and a memory controller 20, and is controlled by a host 2. In the memory system according to the present embodiment, as the non-volatile memory, for example, a NAND type flash memory (hereinafter simply referred to as a flash memory) 10 is provided. The host 2 is an information processing device that accesses the memory system 1. The host 2 may be a server that stores a large amount of diverse data in the memory system 1, or may be a personal computer.

[0013] The memory system 1 can be used as the main storage of the host 2. The memory system 1 may be built in the host 2, or may be connected to the host 2 via a cable or a network. The memory system 1 is, for example, an SSD (Solid State Drive), an SD TM card, an eMMC (embeded Multi Media Card), a UFS (Universal Flash Storage), or the like.

[0014] The flash memory 10 is controlled by a memory controller 20. In the present embodiment, the non-volatile memory is assumed to be the flash memory 10, but it is not limited thereto. The non-volatile memory may be, for example, any one of a NAND type flash memory, a NOR type flash memory, an MRAM (Magneto-resistive Random Access Memory), a PRAM (Phase change Random Access Memory), a ReRAM (Resistive Random Access Memory), and a FeRAM (Ferroelectric Random Access Memory).

[0015] The flash memory 10 includes a memory cell array including a plurality of memory cells arranged in a matrix. The memory cell array includes a plurality of blocks. A block functions as a minimum unit of a data erasure operation. Each block includes a plurality of pages. Each of the plurality of pages includes a plurality of memory cells connected to the same word line. A page is a unit of a data write operation and a data read operation. Instead of a page, a plurality of memory cells commonly connected to one word line may be used as a unit of a data write operation or a data read operation. The flash memory 10 may have a two-dimensional structure or a three-dimensional structure.

[0016] Also, the flash memory 10 can store, for example, firmware, a tag ID assignment table, and a tag ID management table T1a.

[0017] The memory controller 20 can receive instructions from the host 2 and control the flash memory 10 based on the received instructions. The memory controller 20 can be realized by a circuit such as an SoC (System on a Chip), for example. The memory controller 20 includes a control unit, a RAM (Random Access Memory) 22, a host interface circuit (hereinafter simply referred to as host I / F) 23, a memory interface circuit (hereinafter simply referred to as memory I / F) 24, and a data buffer 25.

[0018] The control unit is, for example, a CPU (Central Processing Unit) 21. The CPU 21 can control the overall operation of the memory controller 20. The CPU 21 controls the operation of the memory controller 20, for example, by executing firmware loaded on the RAM 22.

[0019] The RAM 22 is an example of a volatile memory. The RAM 22 can hold, for example, firmware loaded from the flash memory 10, a tag ID assignment table, a tag ID management table T1b, etc., and is used as a working area for the CPU 21. The RAM 22 may be provided outside the memory controller 20 or inside the memory controller 20. Note that, for example, DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory) is used as the RAM 22.

[0020] The host I / F 23 is connected to the host 2 via a host bus and controls the communication between the memory system 1 and the host 2. The host bus is, for example, a bus compliant with the SD standard. The host I / F 23 controls the transfer of data, commands, and addresses between the memory system 1 and the host 2.

[0021] Memory I / F 24 is connected to the flash memory 10 via the NAND bus and controls communication between the memory controller 20 and the flash memory 10. The NAND bus is, for example, a bus that transmits and receives signals conforming to the NAND interface.

[0022] The data buffer 25 temporarily holds data received from the host 2 and data read from the flash memory 10. The data buffer 25 is a volatile memory. The RAM 22 may have the function of the data buffer 25.

[0023] FIG. 2 is a diagram showing an example of the configuration of a tag information assignment table used in the memory system according to the first embodiment. In the description of this embodiment, the tag ID is the tag information. As shown in FIG. 2, the tag ID assignment table shows the correspondence between the average erase count of the flash memory 10 and the tag ID. The average erase count represents the average number of erase counts per block obtained by (the total number of erase counts of all blocks in the flash memory 10) / (the total number of all blocks in the flash memory 10). However, in this embodiment, as shown below, the average number of write commands per block issued by the host 2 to the memory system 1 is regarded as the average erase count.

[0024] For the data writing operation to a non-volatile memory such as the flash memory 10, there are writing of new data and data update. As writing operations when updating data, for example, there are an overwrite method and a logical overwrite method.

[0025] The overwrite method is a method that makes the flash memory 10 that cannot be overwritten appear to be overwritable. In this overwrite method, when data at an arbitrary position in an arbitrary block is updated, all data in the block is temporarily saved. Then, after performing an erase operation on the block, the saved data including the updated data is written back to the block in block units.

[0026] On the one hand, the logical writing method performs data writing in page units. In this method, when data is updated, the page in which the data exists is invalidated, and the updated data is arranged in another block or another page of the same block. That is, the logical address remains unchanged, while the physical address corresponding to the logical address is changed.

[0027] From the above, when updating data in the flash memory 10, it may involve data invalidation or erasure operations. That is, the average number of write commands issued to the memory system 1 per block is related to the average erasure count of the flash memory 10. Therefore, in the description of this embodiment, the average number of write commands issued to the memory system 1 per block will be represented as the average erasure count of the flash memory 10.

[0028] Also, the average number of write commands issued to the memory system 1 per block increases as time passes. Therefore, the average erasure count of the flash memory 10 also increases as time passes. Note that the average number of write commands issued to the memory system 1 per block is managed by, for example, the memory controller 20.

[0029] Note that, in the present embodiment, the average number of erasures and the average number of write commands issued by host 2 to memory system 1 per block are examples of parameters. Further, any information related to the number of erasures, such as the number of write commands issued by host 2 to memory system 1, the number of erase commands, the actual number of erasures, and combinations thereof, may be used as parameters. For example, in the description of the present embodiment, the average number of write commands issued by host 2 to memory system 1 per block is regarded as the average number of erasures, but the actual average number of erasures may also be used as a parameter. Also, not limited to the number of write commands issued by host 2 to memory system 1, the average number of commands issued by host 2 to memory system 1 per block, including other commands such as erase commands, may be regarded as the average number of erasures.

[0030] In this embodiment, the tag ID is an identifier assigned for each logical address of an arbitrary unit based on the average number of erasures. In this embodiment, the tag ID is assigned for each logical address in units of 4 KB. Also, in this embodiment, the tag ID is 4 bits and there are 16 of them from tag ID = 0 to tag ID = 15. And tag ID = 0 represents the case where the written data is invalid data. The 15 IDs from tag ID = 1 to tag ID = 15 represent the case where the written data is valid data, and they are assigned based on the average number of erasures such that the tag ID increases by 1 every time the average number of erasures increases by 5 times. As shown in FIG. 2, for example, in the case of data written when the average number of erasures is 5 times, tag ID = 1 is assigned to an arbitrary unit of logical address. Note that the tag ID may be any amount of information instead of 4 bits. The average number of erasures for each increase of the tag ID is not limited to 5 times, and any number of times may be assigned. Also, as shown in FIG. 2, the tag ID may be circulated and used in response to an increase in the average number of erasures. When using the tag ID for the nth round, the average number of erasures is obtained as being from ((n - 1) * (the number of tag IDs assigned based on the average number of erasures) + (tag ID - 1)) * (the average number of erasures for each increase of the tag ID) + 1 to ((n - 1) * (the number of tag IDs assigned based on the average number of erasures) + tag ID) * (the average number of erasures for each increase of the tag ID). In this embodiment, since the number of tag IDs assigned based on the average number of erasures is 15 and the average number of erasures for each increase of the tag ID is 5 times, for example, in the case of tag ID = 5 in the third round, the average number of erasures of the flash memory 10 when the data was written is obtained as being from 171 to 175 times.

[0031] FIG. 3(a) is a diagram schematically showing a block of a nonvolatile memory included in the memory system according to the first embodiment. FIG. 3(b) is a diagram showing an example of the configuration of a first tag information management table used in the memory system according to the first embodiment.

[0032] The first tag information management table is a table that manages tag information assigned for each logical address in an arbitrary unit. In the present embodiment, the first tag information management table is the tag ID management table T1 (T1a, T1b).

[0033] Specifically, for example, as shown in FIG. 3(a), the physical address of each block is segmented every 4 KB. Then, as shown in FIG. 3(b), the tag ID management table T1 records the tag IDs assigned for each 4 KB logical address based on the tag ID assignment table so as to correspond to the physical address of each 4 KB block shown in FIG. 3(a).

[0034] (Operation)

[0035] The operation of the memory system according to the first embodiment will be described with reference to FIGS. 4 to 7.

[0036] (Write operation and tag ID write operation)

[0037] FIG. 4 is a sequence diagram showing a write operation and a tag information write process in the memory system according to the first embodiment.

[0038] After the power-on of the memory system 1, the memory controller 20 loads the tag ID management table T1a from the flash memory 10 to the tag ID management table T1b on the RAM 22 (S110). In the description of the present embodiment, the tag ID management table T1a is loaded onto the RAM 22 after the power-on of the memory system 1, but the timing for loading the tag ID management table T1a onto the RAM 22 is not limited to this.

[0039] The host 2 issues a write command to the memory controller 20 and transmits data to the memory controller 20 (S120).

[0040] The memory controller 20 receives a write command and data from the host 2. Then, in response to receiving the write command and data, it writes the data to the flash memory 10 (S130). Also, the memory controller 20 manages the number of write commands received from the host 2. Note that the timing at which the memory controller 20 manages the number of write commands received from the host 2 may be any timing. However, the timing is preferably before recording the tag ID in the tag ID management table T1b.

[0041] The memory controller 20 assigns a tag ID based on the tag ID assignment table to the logical address where the data is written, and records the tag ID in the tag ID management table T1b loaded on the RAM 22 (S140).

[0042] When the writing of the tag ID to the tag ID management table T1b is completed, the memory controller 20 notifies the host 2 that the data writing is completed, and the writing and the tag ID writing process are completed (S150).

[0043] In the present embodiment, the memory controller 20 notifies the host 2 that the data writing is completed after the writing of the tag ID to the tag ID management table T1b (S140) is completed. However, after the data is written to the flash memory 10 (S130), the memory controller 20 may notify the host 2 that the data writing is completed. In that case, after notifying the host 2 that the data writing is completed, the memory controller 20 writes the tag ID to the tag ID management table T1b.

[0044] As described above, the tag ID is assigned at the timing when data is written to the flash memory 10. Also, the tag ID management table T1b loaded on the RAM 12 is updated at the timing when data is written to the flash memory 10. Then, for example, before turning off the power of the memory system 1, the updated tag ID management table T1b may be written to the tag ID management table T1a stored in the flash memory 10 to update the tag ID management table T1a stored in the flash memory 10. The timing for updating the tag ID management table T1a stored in the flash memory 10 is not limited to this. For example, the tag ID management table T1a stored in the flash memory 10 may be updated when no writing has been performed for a certain period, and is updated at an arbitrary timing.

[0045] FIG. 5 is a flowchart showing a write operation and a tag information writing process in the memory controller included in the memory system according to the first embodiment. Using FIG. 5, a more detailed tag ID writing process in step S140 in the memory controller 20 will be described.

[0046] When writing data to the flash memory 10 (S130), the memory controller 20 first determines whether the write operation is an update of data (S141).

[0047] If the write operation is not an update of data (S141; NO), that is, if it is a write of new data, the process proceeds to step S144. On the other hand, if the write operation is an update of data (S141; YES), the memory controller 20 determines whether it is a logical overwrite method (S142).

[0048] If it is not the logical overwrite method (S142; NO), that is, if it is the overwrite method, the process proceeds to step S144. On the other hand, if it is the logical overwrite method (S142; YES), the physical address where the data before the update was stored is invalidated. Therefore, the tag ID described in the tag ID management table T1b corresponding to the physical address where the data before the update was stored is set to tag ID = 0 (S143).

[0049] Subsequently, the memory controller 20 assigns a tag ID based on the tag ID assignment table to the logical address for storing the new data or the updated data (S144).

[0050] The memory controller 20 writes the tag ID assigned in step S144 to the tag ID management table corresponding to the logical address for storing the new data or the updated data (S145).

[0051] When the writing of the tag ID to the tag ID management table is completed, the memory controller 20 proceeds to step S150 shown in FIG. 4, and the writing operation and the tag ID writing process in the memory system 1 are completed.

[0052] (Erase operation and tag ID write operation)

[0053] FIG. 6 is a sequence diagram showing the erase operation and the tag information writing process in the memory system according to the first embodiment.

[0054] After the power of the memory system 1 is turned on, the memory controller 20 loads the tag ID management table T1a from the flash memory 10 to the tag ID management table T1b on the RAM 22 (S110). In the description of this embodiment, the tag ID management table T1a is loaded onto the RAM 22 after the power of the memory system 1 is turned on. However, the timing for loading the tag ID management table T1a onto the RAM 22 is not limited to this. If the tag ID management table T1a has already been loaded onto the RAM, step S110 may be skipped.

[0055] Host 2 issues an erase command to the memory controller 20 (S160).

[0056] The memory controller 20 receives the erase command from Host 2. Then, in response to receiving the erase command, the memory controller 20 erases the data (S170).

[0057] The memory controller 20 assigns a tag ID based on the tag ID assignment table and records the tag ID in the tag ID management table T1b loaded on the RAM 22. In the erase operation, since the data is erased, write tag ID = 0 to the tag ID management table T1b of the block where the erase operation was performed (S180).

[0058] When the writing of the tag ID by the memory controller 20 is completed, the memory controller 20 notifies Host 2 that the data erasure is completed, and the erase operation and the writing process of the tag ID are completed (S190).

[0059] In the present embodiment, the memory controller 20 notifies Host 2 that the data erasure is completed after the writing of the tag ID to the tag ID management table T1b (S180) is completed. However, after the data erasure (S170) of the flash memory 10 is performed, the memory controller 20 may notify Host 2 that the data erasure is completed. In that case, after notifying Host 2 that the data erasure is completed, the memory controller 20 writes the tag ID to the tag ID management table T1b.

[0060] (Garbage Collection)

[0061] The garbage collection operation in the memory controller 20 will be described with reference to FIG. 7.

[0062] In the present embodiment, garbage collection is a transfer process performed to aggregate valid data written at approximately the same time. The time when the valid data is written is managed by tag information.

[0063] FIG. 7 is a flowchart showing the garbage collection of a memory controller included in the memory system according to the first embodiment. In the description of this embodiment, for example, it is assumed that garbage collection is performed based on data written when the average number of erasures of the flash memory 10 is 1 to 5 times when the average number of erasures is 16 - 20 times. That is, when the current tag ID = 4, the data at the physical address corresponding to the logical address to which the tag ID = 1 is assigned serves as the basis for garbage collection. The tag ID serving as the basis for garbage collection is the first tag information. That is, in the description of this embodiment, the first tag information is tag ID = 1.

[0064] The memory controller 20 selects an arbitrary block to be garbage-collected included in the flash memory 10 (S210).

[0065] The memory controller 20 selects an arbitrary physical address of the selected block. The memory controller 20 reads the tag ID corresponding to the selected physical address from the tag ID management table T1b (S220).

[0066] The memory controller 20 checks whether the read tag ID is the first tag information (S230). In this embodiment, the data at the physical address corresponding to the logical address to which the same tag ID as the first tag information is assigned is the target of garbage collection. In the description of this embodiment, since the first tag information is tag ID = 1, it is checked whether the read tag ID is tag ID = 1.

[0067] If the read tag ID is not the first tag information (S230; NO), since it is not the target of garbage collection, the process proceeds to step S250. On the other hand, if the read tag ID is the first tag information (S230; YES), since it is the target of garbage collection, the number of tag IDs is counted (S240).

[0068] Subsequently, the memory controller 20 checks whether the confirmation as to whether all tag IDs assigned to the logical address corresponding to the physical address of the selected block is the first tag information has been performed (S250). If the confirmation as to whether all tag IDs assigned to the logical address corresponding to the physical address of the selected block is the first tag information has not been performed (S250; NO), the process returns to step S220.

[0069] If the confirmation as to whether all tag IDs assigned to the logical address corresponding to the physical address of the selected block is the first tag information has been performed (S250; YES), the memory controller 20 determines whether the number of tag IDs of the counted first tag information is less than the first threshold (S260). Here, the first threshold is, for example, half of the total number of tag IDs included in one block. In the present embodiment, the first threshold is assumed to be half of the total number of tag IDs included in one block, but it is not limited thereto and may be any value.

[0070] If the number of tag IDs of the counted first tag information is less than the first threshold (S260; YES), garbage collection is performed on the data written to the physical address corresponding to the logical address to which the first tag information included in the selected block is assigned (S270). On the other hand, if the number of tag IDs of the counted first tag information is greater than or equal to the first threshold (S260; NO), the process proceeds to step S280 without performing garbage collection. When the number of tag IDs of the counted first tag information is greater than or equal to the first threshold, it is considered that data with the same tag ID has already been aggregated in one block. Therefore, garbage collection is not performed.

[0071] The memory controller 20 checks whether the operations of steps S220 to S270 have been performed for all blocks to be subjected to garbage collection (S280).

[0072] If the operations from step S220 to step S270 have not been performed for all the blocks to be garbage-collected (S280; NO), the process returns to step S210. On the other hand, if the operations from step S220 to step S270 have been performed for all the blocks to be garbage-collected (S280; YES), the garbage collection is completed.

[0073] In the description of this embodiment, when the current tag ID = 4, the data of the physical address corresponding to the logical address assigned the tag ID = 1 was used as the first tag information that is the standard for garbage collection. However, the tag ID that is the standard for garbage collection is not limited to this. For example, when the current tag ID = 6, the data of the physical address corresponding to the logical address assigned the tag ID = 1 may be used as the standard for garbage collection, and the interval between the current tag ID and the tag ID that is the standard for garbage collection may be determined arbitrarily.

[0074] Also, for example, when the average number of erasures is 131 - 135 times, that is, when the assignment of the current tag ID is the second round of tag ID = 12, the tag ID = 9 is set as the tag ID that is the standard for garbage collection. At this time, the data assigned the tag ID = 9 corresponds to the data written when the average number of erasures was 41 - 45 times and the data written when the average number of erasures was 116 - 120 times. However, since both are tag ID = 9 and have the same tag ID, the same processing is performed.

[0075] (Effect)

[0076] As described above, by performing garbage collection based on data with the same tag ID, it becomes possible to aggregate data written at approximately the same time into one block. That is, after performing garbage collection, it is possible to suppress fragmentation of the data within the same block. Furthermore, when the number of tag IDs serving as the basis for garbage collection is less than the first threshold, by performing garbage collection, there is no need to perform garbage collection on blocks in which data already written at approximately the same time is aggregated. Therefore, unnecessary garbage collection can be suppressed, and it becomes possible to improve rewrite (write / erase) performance and extend the life of the block.

[0077] Also, in the present embodiment, although the first threshold is set to be half of the total number of tag IDs included in one block, when the first threshold is smaller, it is possible to suppress the frequency of garbage collection processing, and it becomes possible to extend the life of the block. Also, when the first threshold is larger, the frequency of garbage collection processing increases, but it becomes possible to aggregate data written at approximately the same time into more one block.

[0078] (Second Embodiment)

[0079] The memory system according to the second embodiment will be described with reference to FIGS. 8 to 14. The difference between the second embodiment and the first embodiment is that, in addition to the tag ID management table, it has a block unit tag ID management table. Except for having a block unit tag ID management table in addition to the tag ID management table, it is the same as the first embodiment, so the same reference numerals are used and detailed description is omitted.

[0080] (Structure)

[0081] The configuration of the information processing system including the memory system according to the second embodiment will be described with reference to FIGS. 8 and 10.

[0082] FIG. 8 is a block diagram showing an example of the configuration of a memory system according to the second embodiment.

[0083] As shown in FIG. 8, in addition to the tag ID management table T1a, the flash memory 10 can store a block unit tag ID management table T2a. Further, the RAM 22 can hold, for example, the data of the block unit tag ID management table T2a loaded from the flash memory 10 in the block unit tag ID management table T2b.

[0084] FIG. 9 is a diagram showing an example of the configuration of a tag information allocation table used in the memory system according to the second embodiment. In this embodiment, for example, the rewrite count life of the flash memory 10 is set to 3000 times. In this embodiment, the tag ID is 8 bits and is allocated based on the average erase count such that the tag ID increases by 1 every time the average erase count increases by 15 times so as to correspond to the rewrite count life of this flash memory 10. Also, among the tag IDs from tag ID = 0 to tag ID = 256, the tag IDs from tag ID = 0 to tag ID = 200 are used. Tag ID = 0 represents invalid data as in the first embodiment. In this embodiment, the tag ID does not circulate. In this embodiment, the rewrite count life is set to 3000 times, but it is not limited to this. The amount of information of the tag ID may be changed according to the rewrite count life, or the average number of erases for the tag ID to increase by 1 may be set to an arbitrary number.

[0085] FIG. 10(a) is a diagram schematically showing a non-volatile memory included in the memory system according to the second embodiment. FIG. 10(b) is a diagram showing an example of the configuration of a second tag information management table used in the memory system according to the second embodiment.

[0086] The second tag information management table is a table that manages the representative tag information of any unit of the first tag information management table. In this embodiment, the second tag information management table manages the representative tag information of the block unit of the first tag information management table, and is the block unit tag ID management table T2 (T2a, T2b).

[0087] Specifically, as shown in FIG. 10(a), the flash memory 10 is partitioned into blocks. As shown in FIG. 10(b), the block unit tag ID management table T2 manages the representative tag ID of each of the plurality of blocks of the flash memory 10 in the tag ID management table T1. In the present embodiment, the representative tag ID is the smallest tag ID. For example, if the smallest of the tag IDs assigned to the logical addresses corresponding to the physical addresses in 4KB units included in the block BLK1 is tag ID = 2, the tag ID = 2 is recorded in the block unit tag ID management table T2 corresponding to the block BLK1.

[0088] (Operation)

[0089] The operation of the memory system according to the second embodiment will be described with reference to FIGS. 11 to 14.

[0090] (Write operation and tag ID write operation)

[0091] FIG. 11 is a flowchart showing the tag information writing process during the write operation in the memory controller included in the memory system according to the second embodiment. Using FIG. 11, a more detailed tag ID write management sequence of step S140 shown in FIG. 4 in the memory controller will be described. Since the parts other than step 140 are the same as those in the first embodiment, detailed description thereof will be omitted.

[0092] Steps S141 to S145 are the same as those in FIG. 5.

[0093] The memory controller 20 checks the smallest tag ID described in the tag ID management table T1b in the block including the physical address for storing new data or updated data (S146). Note that the tag ID = 0 which is invalid data is excluded.

[0094] Subsequently, the memory controller 20 writes the confirmed minimum tag ID to the block unit tag ID management table T2b corresponding to the block including the physical address for storing new data or updated data (S147).

[0095] When the writing of the tag ID to the tag ID management table T1b and the writing of the minimum tag ID to the block unit tag ID management table T2b are completed, the process proceeds to step S150 shown in FIG. 4. Thus, the writing operation and the tag ID writing operation are completed.

[0096] (Garbage collection)

[0097] FIG. 12 is a flowchart showing the garbage collection process in the memory controller included in the memory system according to the second embodiment. The garbage collection operation in the memory controller will be described with reference to FIG. 12. Note that detailed descriptions of the same steps as those in FIG. 7 are omitted, and differences from FIG. 7 will be described.

[0098] The memory controller 20 selects a block using the block unit tag ID management table T2b (S310). The method of selecting a block will be described later.

[0099] The memory controller 20 selects an arbitrary physical address of the selected block in the same manner as in the first embodiment. The memory controller 20 reads the tag ID assigned to the logical address corresponding to the selected physical address from the tag ID management table T1b (S220).

[0100] The memory controller 20 checks whether the tag ID read from the tag ID management table T1b is greater than tag ID = 0 and less than or equal to the first tag information (S330). That is, it checks whether the tag information is less than or equal to the first tag information excluding the tag ID = 0 which is the tag information of invalid data. If the read tag ID is greater than tag ID = 0 and less than or equal to the tag ID targeted for garbage collection (S330; YES), it counts the number of tag IDs greater than tag ID = 0 and less than or equal to the first tag information (S340). If the read tag ID is greater than the first tag information (S330; NO), since it is not targeted for garbage collection, it proceeds to step S250.

[0101] Subsequently, the memory controller 20 checks whether the check has been performed on whether the tag ID assigned to the logical address corresponding to all physical addresses included in the selected block is greater than tag ID = 0 and less than or equal to the first tag information (S250). If the check on whether the tag ID assigned to the logical address corresponding to all physical addresses included in the selected block is greater than tag ID = 0 and less than or equal to the first tag information has not been performed (S250; NO), it returns to step S220.

[0102] If the check on whether the tag ID assigned to the logical address corresponding to all physical addresses included in the selected block is greater than tag ID = 0 and less than or equal to the first tag information has been performed (S250; YES), the memory controller 20 determines whether the counted number of tag IDs greater than tag ID = 0 and less than or equal to the first tag information is less than the first threshold (S360).

[0103] If the number of tag IDs greater than tag ID = 0 and less than or equal to the first tag information counted is less than the first threshold (S360; YES), garbage collection is performed on the data written to the physical address corresponding to the logical address with a tag ID greater than tag ID = 0 and less than or equal to the first tag information included in the selected block (S270). On the other hand, if the number of tag IDs greater than tag ID = 0 and less than or equal to the first tag information counted is greater than or equal to the first threshold (S260; NO), garbage collection is not performed and the process proceeds to step S280.

[0104] In the description of this embodiment, for example, when the average number of erasures of the flash memory 10 is 21 - 25 times, that is, when the tag ID = 5, the tag ID serving as the reference for garbage collection, which is the first tag information, is set to tag ID = 2. At this time, the data at the physical addresses where tag ID = 1 and tag ID = 2 are written in the tag ID management table T1b becomes the target of garbage collection.

[0105] FIG. 13 is a flowchart showing a part of the garbage collection process in the memory controller included in the memory system according to the second embodiment. A more detailed description of step S310 shown in FIG. 12 will be given with reference to FIG. 13.

[0106] The memory controller 20 reads the block unit management table T2a from the flash memory 10 into the block unit management table T2b on the RAM 22 (S311). If the block unit management table T2a has already been read from the flash memory 10 into the block unit management table T2b on the RAM 22, it is not necessary to read it again. The timing at which the memory controller 20 reads the block unit management table T2a from the flash memory 10 into the block unit management table T2b on the RAM 22 is not limited to this.

[0107] Subsequently, the memory controller 20 searches for and selects the block in which the smallest tag ID is recorded in the block unit tag ID management table T2b (S312). Then, the process proceeds to step S220 in FIG. 12.

[0108] (Read disturb inspection sequence)

[0109] In the flash memory 10, the data read operation is performed on the selected memory cell. However, not only the selected memory cell but also a voltage exceeding the threshold is applied to the non-selected memory cells around the selected memory cell. Therefore, the non-selected memory cells around the selected memory cell also enter a weak write state, and a read disturb occurs in which the threshold voltage changes to be higher. Due to the read disturb, the bit error rate of the flash memory 10 increases, and thus the reliability of the memory system 1 decreases. Therefore, for example, a read disturb inspection described later is performed, and the data written in the block with a large amount of corrected data is rewritten to a new block to maintain the reliability. Hereinafter, the processing operation of the read disturb inspection in the present embodiment will be described with reference to FIG. 14.

[0110] FIG. 14 is a flowchart showing the processing operation of the read disturb inspection in the memory controller included in the memory system according to the second embodiment.

[0111] As shown in FIG. 14, when the memory system 1 is powered on, the memory controller 20 reads the block unit management table T2a from the flash memory 10 to the block unit management table T2b on the RAM 22 (S410). In the present embodiment, the block unit management table T2a is read when the memory system 1 is powered on, but the timing for reading the block unit management table T2a is not limited to this.

[0112] The memory controller 20 checks whether the read disturb test has been completed (S420). The read disturb test is, for example, to shift and apply a read voltage to the block to be tested, pass the read data through an ECC (Error Correcting Code) correction circuit, and check the amount of corrected data. Here, by rewriting the data written in the block with a large amount of corrected data to a new block, it is made resistant to read disturb.

[0113] If the read disturb test has already been completed (S420; YES), the processing operation of the read disturb test is completed. On the other hand, if the read disturb test has not been completed (S420; NO), an arbitrary block is selected from the block unit tag ID management table T2b on the RAM. The memory controller 20 reads the minimum tag ID of the block unit described in the block unit management table T2b of the selected block (S430).

[0114] The memory controller 20 determines whether the minimum tag ID of the read block unit is greater than tag ID = 0 and less than the tag ID serving as the reference for the read disturb test (S440). In the present embodiment, the tag ID serving as the reference for the read disturb test is the second tag information. In the description of the present embodiment, the second tag information is set to tag ID = 4.

[0115] If the minimum tag ID of the read block unit is greater than or equal to the second tag information (S440; NO), the process proceeds to step S460. On the other hand, if the minimum tag ID of the read block unit is greater than tag ID = 0 and less than the second tag information (S440; YES), a read disturb test is performed on the block with a tag ID greater than tag ID = 0 and less than the second tag information serving as the reference for the read disturb test (S450). In the present embodiment, since the second tag information is tag ID = 4, if the minimum tag ID of the read block unit is any of tag ID = 1, 2, or 3, a read disturb test is performed on the selected block.

[0116] Subsequently, the memory controller 20 checks whether, for all the minimum tag IDs in block units of the block unit tag ID management table T2b, the tag ID is greater than 0 and less than the second tag information (S460).

[0117] If the check as to whether the tag ID is greater than 0 and less than the second tag information has not been completed for all the tag IDs in the block unit tag ID management table (S460; NO), the process returns to step S430.

[0118] If the check as to whether the tag ID is greater than 0 and less than the second tag information has been completed for all the minimum tag IDs in block units of the block unit tag ID management table (S460; YES), the processing operation of the read disturb check is completed. After the check, an operation of rewriting the data written in the block with more corrected data in the read disturb check to a new block may be performed.

[0119] In this embodiment, it is checked whether the read disturb check has ended, but the present invention is not limited thereto. For example, it may be checked whether a read operation has been performed a certain number of times or more since the previous read disturb check. In that case, if the read operation has not been performed a certain number of times or more since the previous read disturb check, the read disturb check sequence ends. On the other hand, if the read operation has been performed a certain number of times or more since the previous read disturb check, the process proceeds to step S430.

[0120] (Effect)

[0121] As described above, also in the second embodiment, the same effects as those in the first embodiment can be obtained. Also, in this embodiment, the tag IDs do not cycle. Therefore, when the tag IDs to be garbage-collected are set to be greater than tag ID = 0 and less than or equal to the first tag information, data that is always at the same level as or less frequently updated than the first tag information will always be targeted. Therefore, it is possible to aggregate data with a lower update frequency more efficiently than in the first embodiment. Furthermore, by providing the block unit tag ID management table T2, it becomes possible to perform a read disturb inspection focusing on the blocks in which data with a low update frequency has been aggregated. That is, it is possible to efficiently and early detect read disturb, and improve reliability. Also, when performing garbage collection, by using the block unit tag ID management table, it is possible to preferentially select the blocks in which data with a low update frequency exists and perform garbage collection, making it possible to more efficiently perform garbage collection.

Explanation of Signs

[0122] 1... Memory system, 2... Host, 10... Flash memory, 20... Memory controller, 21... CPU, 22... RAM, 23... Host I / F, 24... Memory I / F, 25... Data buffer.

Claims

1. A non-volatile memory having blocks, A memory controller capable of controlling the non-volatile memory, comprising, The memory controller holds a first tag information management table that manages tag information assigned to the logical addresses of the non-volatile memory based on information regarding the number of erase times, The tag information is assigned values arranged in order based on the information regarding the number of erase times, The memory controller performs garbage collection on data corresponding to logical addresses assigned tag information that is less than or equal to the value of the first tag information included in the tag information, excluding the tag information of invalid data. A memory system.

2. The memory system according to claim 1, wherein the information regarding the number of erase times is based on the number of write commands issued by a host.

3. The memory system according to claim 1, wherein the tag information is assigned when data is written to the non-volatile memory.

4. The memory system according to claim 1, wherein the tag information is assigned for each logical address in an arbitrary unit.

5. The memory system according to claim 1, wherein the memory controller performs the garbage collection when the number of logical addresses assigned tag information that is less than or equal to the value of the first tag information, excluding the tag information of invalid data within the block, is less than a first threshold.

6. The memory system according to claim 5, wherein the memory controller does not perform the garbage collection when the number of logical addresses assigned tag information that is less than or equal to the value of the first tag information, excluding the tag information of invalid data within the block, is greater than or equal to a first threshold.

7. The memory controller further holds a second tag information management table that manages one representative tag information among the tag information of the block in the first tag information management table, and performs a read disturb check based on the second tag information management table. The memory system according to claim 1.

8. The memory system according to claim 7, wherein the representative tag information is the smallest tag information of the block in the first tag information management table.

9. The memory system according to claim 7, wherein the memory controller performs the read disturb check on a block having tag information smaller than the second tag information included in the representative tag information in the second tag information management table.

10. A non-volatile memory having blocks, A memory controller capable of controlling the non-volatile memory, Comprising, The memory controller holds a first tag information management table that manages tag information assigned to the logical address of the non-volatile memory based on the number of write commands issued by the host, The memory controller performs garbage collection on data corresponding to the logical address to which the first tag information included in the tag information is assigned when the number of logical addresses to which the first tag information in the block is assigned is less than a first threshold. Memory system.

11. The memory system according to claim 10, wherein the tag information is assigned when data is written to the non-volatile memory.

12. The memory system according to claim 10, wherein the memory controller does not perform the garbage collection when the number of logical addresses to which the first tag information in the block is assigned is greater than or equal to a first threshold.

13. The memory controller further holds a second tag information management table that manages one representative tag information among the tag information of the blocks in the first tag information management table, and performs a read disturb check based on the second tag information management table. The memory system according to claim 10.

14. The memory controller performs the read disturb check on a block having tag information smaller than the second tag information included in the representative tag information in the second tag information management table. The memory system according to claim 13.

15. A non-volatile memory having blocks, and a memory controller capable of controlling the non-volatile memory, wherein the memory controller holds a first tag information management table that manages tag information assigned to the logical address of the non-volatile memory based on a parameter, and a second tag information management table that manages one representative tag information among the tag information of the blocks in the first tag information management table, performs garbage collection on the non-volatile memory based on the first tag information management table, and performs a read disturb check based on the second tag information management table. A memory system.

16. The parameter is information regarding the number of erasures. The memory system according to claim 15.

17. The parameter is the number of write commands issued by the host. The memory system according to claim 15.

18. The memory controller performs the garbage collection on the data corresponding to the logical address to which the first tag information included in the tag information is assigned in the first tag information management table, and performs the read disturb check on a block having tag information smaller than the second tag information included in the representative tag information in the second tag information management table. The memory system according to claim 15.

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