Semiconductor device

Abstract

The present invention realizes a high-performance semiconductor device.　A semiconductor device (1A) comprises: a group of semiconductor elements (30A) having collector electrodes (31) and emitter electrodes (32); a conductive plate (22) electrically connected to the collector electrodes (31); and a case (10) for containing these members. The semiconductor device (1A) further comprises an OUT terminal (40) that is disposed inside and outside the case (10) and that is provided with an extension part (42) having: a stem part (42a) that extends inward from one edge (11a) side of the case (10); and a pair of branch parts (42b, 42c) that branch from the stem part (42a) in a plan view and are electrically connected to the emitter electrodes (32). The semiconductor device (1A) still further comprises a P terminal (50) that is disposed inside and outside the case (10), that includes an extension part (52) sandwiched between the pair of branch parts (42b, 42c), and that is electrically connected to the conductive plate (22). In the semiconductor device (1A), it is possible to realize inductance reduction, overheat suppression during operation, and the like.

Description

Technical Field

[0001] The present invention relates to a semiconductor device.

Background Art

[0002] Regarding a semiconductor device including a circuit board on which semiconductor elements are mounted, and an output (OUT) terminal, a positive electrode (P) terminal, and a negative electrode (N) terminal connected to the circuit board, from the viewpoint of surge voltage suppression, a technique for reducing the inductance between the P and N is known.

[0003] For example, in a power module in which current flows from a V+ terminal through a part of a power board across a power device, through the power device to the other part of the power board, and then to a V− terminal, a technique is known in which the V− terminal is positioned higher than the V+ terminal to form a current loop and reduce the inductance by magnetic flux cancellation (Patent Document 1).

[0004] Also known is a power module including a circuit board including a conductive layer where a group of semiconductor elements on the upper arm side of an inverter circuit is arranged and a positive electrode terminal is connected, a conductive layer where a group of semiconductor elements on the lower arm side is arranged and an output terminal is connected, and a conductive layer where a negative electrode terminal is connected. Regarding such a power module, a technique is known in which the main current flowing from the positive electrode terminal is divided into two and flows through the conductive layer where the group of semiconductor elements on the upper arm side is arranged, flows through the group of semiconductor elements on the upper arm side to the conductive layer where the group of semiconductor elements on the lower arm side is arranged, and flows through the group of semiconductor elements on the lower arm side to the conductive layer where the negative electrode terminal is connected. At this time, a technique is known in which the inductance between the P and N is reduced by making the circuit board layout such that the current paths of the upper and lower arms are parallel and adjacent and the main current flows in opposite directions (Patent Documents 2-4).

[0005] In addition, there is known a semiconductor module in which semiconductor switching elements on the upper and lower arm sides are respectively disposed on a collector pattern disposed on an insulating plate, the collector is disposed on the collector pattern, and the emitter is connected by an emitter wire to an emitter pattern disposed on an insulating substrate. Regarding such a semiconductor module, there is known a technique in which a positive electrode is connected to the collector pattern on the upper arm side, a negative electrode is connected to the emitter pattern on the lower arm side, and portions of the positive electrode and the negative electrode parallel to the insulating plate are arranged so as to overlap when viewed from the vertical direction (Patent Document 5).

[0006] Also, there is known a power semiconductor module using two circuit boards, provided with an external lead terminal connected to a high-potential metal pattern of one circuit board, an external lead terminal connected to a low-potential metal pattern of the other circuit board, and an external lead terminal connected to the low-potential metal pattern of one circuit board and the high-potential metal pattern of the other circuit board. Regarding such a power semiconductor module, there is known a technique in which positions for connecting the external lead terminals for high potential and low potential respectively are arranged in the vicinity within a range where there are no problems in mounting technology and insulation design, the loop area of the path through which current flows from the high-potential metal pattern to the low-potential metal pattern is reduced, and the inductance generated in the current path is suppressed (Patent Document 6).

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Summary of the Invention

Problems to be Solved by the Invention

[0008] In a semiconductor device including an OUT terminal, a P terminal, and an N terminal as main current wirings, reducing the inductance between the P and N is effective from the viewpoint of surge voltage suppression. However, depending on the layout of the main current wirings such as the OUT terminal, the P terminal, and the N terminal, and the layout of the conductive plate to which the main current wiring is connected together with the semiconductor elements constituting the semiconductor device, it may not be possible to sufficiently reduce the inductance between the P and N, or it may not be possible to sufficiently exhibit the performance of the semiconductor elements. With the conventional technologies, there have been cases where it is not possible to realize a high-performance semiconductor device in which the inductance between the P and N is sufficiently reduced and the performance of the semiconductor elements is sufficiently exhibited.

[0009] In one aspect, the present invention aims to realize a high-performance semiconductor device.

Means for Solving the Problems

[0010] In one embodiment, a plurality of semiconductor elements having a first electrode on a first main surface and a second electrode on a second main surface opposite to the first main surface, a conductive plate electrically connected to the first electrode of the plurality of semiconductor elements, a case having one side and a side opposite to the one side, and enclosing the plurality of semiconductor elements and the conductive plate, a trunk portion disposed inside and outside the case and extending from one side of the case to the inside of the case, and a first extension portion having a first branch portion and a second branch portion branched from the trunk portion in a plan view and electrically connected to the second electrode of the plurality of semiconductor elements, the first main current wiring including the first extension portion, and a second main current wiring disposed inside and outside the case, having a second extension portion sandwiched between the first branch portion and the second branch portion inside the case, and electrically connected to the conductive plate. A semiconductor device is provided.

[0011] Also, in one aspect, a substrate, a case on which the substrate is disposed, a plurality of first semiconductor elements disposed inside the case, a plurality of second semiconductor elements disposed inside the case, a first conductive plate disposed on the substrate and electrically connected to the plurality of first semiconductor elements, a second conductive plate disposed on the substrate and electrically connected to the plurality of second semiconductor elements, a first external terminal portion disposed outside the case, and a first extension portion, a first connection portion, and a second connection portion disposed inside the case. The first extension portion connects the first external terminal portion to the first connection portion and the second connection portion to each other. The first connection portion and the second connection portion are electrically connected to the first conductive plate, a second external terminal portion disposed outside the case, and a second extension portion and a third connection portion disposed inside the case. The second extension portion connects the second external terminal portion to the third connection portion. The third connection portion is electrically connected to the second conductive plate, a second main current wiring. The first connection portion and the second connection portion are disposed so as to sandwich the second extension portion. A semiconductor device is provided in which an output current flows through the other when a power supply voltage is applied to one of the first main current wiring and the second main current wiring.

Effects of the Invention

[0012] In one aspect, it becomes possible to realize a high-performance semiconductor device.

[0013] The above and other objects, features, and advantages of the present invention will become apparent from the following description in connection with the accompanying drawings that represent preferred embodiments of the present invention as examples.

Brief Description of the Drawings

[0014]

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DETAILED DESCRIPTION OF THE INVENTION

[0015] [First Embodiment] FIG. 1 is a first example of a circuit diagram of a semiconductor device. FIG. 1 shows a circuit diagram of a semiconductor device 1a that constitutes an inverter circuit. The semiconductor device 1a includes semiconductor elements 2 and 3 connected in series. Here, switch elements such as IGBT (Insulated Gate Bipolar Transistor) and MOSFET (Metal Oxide Semiconductor Field Effect Transistor) are used for the semiconductor elements 2 and 3, respectively. Diode elements such as FWD (Free Wheeling Diode) and SBD (Schottky Barrier Diode) may be connected to the switch elements used for the semiconductor elements 2 and 3, respectively. In the example of FIG. 1, an RC (Reverse Conducting)-IGBT in which an IGBT2a and an FWD2b are connected is used as the semiconductor element 2, and an RC-IGBT in which an IGBT3a and an FWD3b are connected is used as the semiconductor element 3.

[0016] In the semiconductor element 2, the collector C of the IGBT2a is connected to the cathode K of the FWD2b, and the emitter E of the IGBT2a is connected to the anode A of the FWD2b. In the semiconductor element 3, the collector C of the IGBT3a is connected to the cathode K of the FWD3b, and the emitter E of the IGBT3a is connected to the anode A of the FWD3b. The emitter E of the IGBT2a of the semiconductor element 2 is connected to the collector C of the IGBT3a of the semiconductor element 3. The gates G of the IGBT2a and the IGBT3a are connected to a gate terminal G1 and a gate terminal G2, respectively. The emitters E of the IGBT2a and the IGBT3a are connected to a sense emitter terminal E1 and a sense emitter terminal E2, respectively.

[0017] The semiconductor element 2 constitutes the upper arm of the semiconductor device 1a that forms an inverter circuit. The semiconductor element 3 constitutes the lower arm of the semiconductor device 1a that forms an inverter circuit. The collector C of the semiconductor element 2 is connected to the positive (P) terminal to which the high-potential side power supply voltage is input. The emitter E of the semiconductor element 3 is connected to the negative (N) terminal to which the low-potential side power supply voltage is input. The connection node between the semiconductor element 2 and the semiconductor element 3 connected in series is connected to the output (OUT) terminal from which the output current is output. The P terminal, the N terminal, and the OUT terminal are also each referred to as the main current wiring. The collector C of the semiconductor element 2 is further connected to an SP (Surge Protection) terminal for sensing the voltage Vce (or the voltage Vds between the drain and the source) between the collector C and the emitter E of the semiconductor element 2 in parallel with the sense emitter terminal E1. The SP terminal is a terminal for determining that an overcurrent due to a saturation state is flowing through the semiconductor element 2 when it is equal to or higher than a predetermined value when the semiconductor element 2 is on.

[0018] Note that the semiconductor element 2 that constitutes the upper arm is not limited to one including a set of IGBT2a and FWD2b, and a plurality of sets each including a set of IGBT2a and FWD2b may be connected in parallel. The semiconductor element 3 that constitutes the lower arm is not limited to one including a set of IGBT3a and FWD3b, and a plurality of sets each including a set of IGBT3a and FWD3b may be connected in parallel.

[0019] Figure 2 is a second example of the circuit diagram of the semiconductor device. Figure 2 shows the circuit diagram of the semiconductor device 1b that forms a three-phase voltage type inverter circuit of the U-phase, V-phase, and W-phase. Three semiconductor devices 1a as shown in FIG. 1 are connected in parallel to each other between the P and N terminals, and the semiconductor device 1b as shown in FIG. 2 is realized. The OUT terminals (FIG. 1) of the three semiconductor devices 1a respectively correspond to the output nodes of the U-phase, V-phase, and W-phase in the semiconductor device 1b that forms a three-phase voltage type inverter circuit, and are connected to a load 4 such as a motor.

[0020] Here, an RC-IGBT is exemplified as the semiconductor element 2 and the semiconductor element 3. In addition, an RB (Reverse Blocking)-IGBT may be used as the semiconductor element 2 and the semiconductor element 3. Here, the semiconductor element 2 including the IGBT2a and the FWD2b, and the semiconductor element 3 including the IGBT3a and the FWD3b are exemplified. In addition, instead of the IGBT2a and the IGBT3a, other switching elements such as a MOSFET may be used, and instead of the FWD2b and the FWD3b, other diode elements such as an SBD may be used.

[0021] Subsequently, a configuration example of the semiconductor device will be described. FIGS. 3 to 5 are diagrams for explaining an example of a semiconductor device according to the first embodiment. FIG. 3(A) schematically shows a main part plan view of an example of the semiconductor device. FIG. 3(B) schematically shows a cross-sectional view taken along line III-III of FIG. 3(A). FIG. 4 schematically shows a main part plan view of an example of a case and an insulating circuit board of the semiconductor device. FIG. 5(A) schematically shows a main part plan view of an example of an OUT terminal of the semiconductor device. FIG. 5(B) schematically shows a main part plan view of an example of a P terminal of the semiconductor device. FIG. 5(C) schematically shows a main part plan view of an example of an N terminal of the semiconductor device.

[0022] The semiconductor device 1A shown in FIGS. 3(A) and 3(B) is an example of a so-called 2in1 type semiconductor device having the circuit configuration as shown in FIG. 1 above. The semiconductor device 1A includes a case 10, an insulating circuit board 20A, a plurality of semiconductor elements 30A, and a plurality of semiconductor elements 30B as shown in FIGS. 3(A) and 3(B) and FIG. 4. The semiconductor device 1A further includes an OUT terminal 40, a P terminal 50, and an N terminal 60 as shown in FIGS. 3(A) and 3(B) and FIGS. 5(A) to 5(C). The OUT terminal 40, the P terminal 50, and the N terminal 60 are also referred to as main current wirings, respectively.

[0023] For the case 10, for example, a resin case formed using a resin material such as PPS (Poly-Phenylene-Sulfide) resin is used. The case 10 has a side wall portion 12 that surrounds the inside. The case 10 may have a lid portion that covers the inside surrounded by the side wall portion 12. The case 10 is disposed, for example, on a support 100 such as a heat sink or a cooler.

[0024] An insulated circuit board 20A is disposed inside the case 10. A plurality of semiconductor elements 30A and a plurality of semiconductor elements 30B are mounted on the insulated circuit board 20A. The insulated circuit board 20A has an insulating substrate 21 (substrate), a conductive plate 22, a conductive plate 23, and a conductive plate 24 provided on one surface (main surface) of the insulating substrate 21, and a conductive plate 25 provided on the other surface (main surface) opposite to the one surface of the insulating substrate 21. As the insulating substrate 21, substrates such as alumina, composite ceramics mainly composed of alumina, aluminum nitride, and silicon nitride are used. As the conductive plates 22, 23, 24, and 25, conductive materials such as copper are used. For the insulated circuit board 20A, for example, a DCB (Direct Copper Bonding) substrate is used. Other substrates such as an AMB (Active Metal Brazed) substrate may be used for the insulated circuit board 20A. A group of semiconductor elements 30A and a group of semiconductor elements 30B are mounted on one surface side of the insulating substrate 21. Switch elements such as IGBTs and MOSFETs are used for the group of semiconductor elements 30A and the group of semiconductor elements 30B, respectively. Diode elements such as FWDs and SBDs are integrated into the group of semiconductor elements 30A and the group of semiconductor elements 30B, respectively.

[0025] The insulating substrate 21 of the insulated circuit board 20A has four sides 21a (first side), 21b (second side), 21c (third side), and 21d (fourth side) in a plan view. The side 21a and the side 21c are opposed to each other, and the side 21b and the side 21d are opposed to each other. The case 10 has sides 11a (fifth side) and 11c (sixth side) that sandwich the sides 21a and 21c of the insulating substrate 21 and are parallel to the sides 21a and 21c in a plan view. The side 11a of the case 10 is on the side of the side 21a of the insulating substrate 21, and the side 11c of the case 10 is on the side of the side 21c of the insulating substrate 21.

[0026] When the direction parallel to the side 21a of the insulating substrate 21 is defined as the X direction (first direction) and the direction perpendicular to the X direction is defined as the Y direction (second direction), the conductive plates 22, 23, and 24 provided on one surface of the insulating substrate 21 are arranged side by side in the Y direction in plan view. For example, in the semiconductor device 1A, they are arranged side by side in the order of the conductive plate 24, the conductive plate 23, and the conductive plate 22 in the Y direction. The conductive plates 22, 23, and 24 are arranged such that, for example, the area of the conductive plate 23 is larger than the area of the conductive plate 22, and the area of the conductive plate 22 is larger than the area of the conductive plate 24. A plurality (here, four as an example) of semiconductor elements 30A constituting the upper arm of the semiconductor device 1A are arranged on the conductive plate 22. The group of semiconductor elements 30A of the upper arm on the conductive plate 22 are arranged side by side in the X direction in plan view. A plurality (here, four as an example) of semiconductor elements 30B constituting the lower arm of the semiconductor device 1A are arranged on the conductive plate 23. The group of semiconductor elements 30B of the lower arm on the conductive plate 23 are arranged side by side in the X direction in plan view.

[0027] Each of the group of semiconductor elements 30A and the group of semiconductor elements 30B has a collector electrode 31 provided on one surface (main surface) and an emitter electrode 32 provided on the other surface (main surface) opposite to the one surface. Further, a gate electrode and a sense emitter electrode are provided on the surface side where the emitter electrode 32 is provided.

[0028] Each of the semiconductor elements 30A in the upper arm has its collector electrode 31 connected to the conductive plate 22 using a bonding material such as solder or sintered material, and its emitter electrode 32 connected to the conductive plate 23 using a wire 33. Each semiconductor element 30A in the upper arm has its collector electrode 31 electrically connected to the conductive plate 22 and its emitter electrode 32 electrically connected to the conductive plate 23. The gate electrode of each semiconductor element 30A in the upper arm is connected to an external gate terminal 14 provided on the side wall portion 12 on the side of the side 11a of the case 10 using a gate wire 34. The sense emitter electrode of each semiconductor element 30A in the upper arm is connected to an external sense emitter terminal 15 provided on the side wall portion 12 on the side of the side 11a of the case 10 using a sense emitter wire 35. Also, the conductive plate 22 to which the collector electrode 31 of each semiconductor element 30A in the upper arm is connected is connected to an external SP terminal 19 provided on the side wall portion 12 on the side of the side 11a of the case 10 using an SP wire 39. Hereinafter, these external SP terminals 19 and SP wires 39 are also referred to as the SP section 90.

[0029] Each of the semiconductor elements 30B in the lower arm has its collector electrode 31 connected to the conductive plate 23 using a bonding material such as solder or sintered material, and its emitter electrode 32 connected to the conductive plate 24 using a wire 36. Each semiconductor element 30B in the lower arm has its collector electrode 31 electrically connected to the conductive plate 23 and its emitter electrode 32 electrically connected to the conductive plate 24. The gate electrode of each semiconductor element 30B in the lower arm is connected to an external gate terminal 17 provided on the side wall portion 12 on the side of the side 11c of the case 10 using a gate wire 37. The sense emitter electrode of each semiconductor element 30B in the lower arm is connected to an external sense emitter terminal 18 provided on the side wall portion 12 on the side of the side 11c of the case 10 using a sense emitter wire 38.

[0030] On the conductive plate 22 to which the collector electrodes 31 of the semiconductor element group 30A of the upper arm are connected, a conductive block 22a (lead-out portion) to which the P terminal 50 (main current wiring) is connected is arranged. A conductive material such as copper is used for the conductive block 22a. The conductive block 22a is arranged at an intermediate position of the semiconductor element group 30A of the upper arm, that is, at a position sandwiched between the second and third of the four semiconductor elements 30A arranged in the X direction. The P terminal 50 is connected to the conductive block 22a and is electrically connected to the conductive plate 22 through the conductive block 22a.

[0031] On the conductive plate 23 to which the emitter electrodes 32 of the semiconductor element group 30A of the upper arm and the collector electrodes 31 of the semiconductor element group 30B of the lower arm are connected, two conductive blocks 23a (lead-out portions) to which the OUT terminal 40 (main current wiring) is connected are arranged. A conductive material such as copper is used for the conductive blocks 23a. The two conductive blocks 23a are arranged at the joint group of the wire 33 extending from the emitter electrode 32 of the semiconductor element group 30A of the upper arm and at an outer position of the semiconductor element group 30B of the lower arm, that is, at a position sandwiching the four semiconductor element groups 30B arranged in the X direction. The OUT terminal 40 is connected to the conductive block 23a and is electrically connected to the conductive plate 23 through the conductive block 23a.

[0032] On the conductive plate 24 to which the emitter electrodes 32 of the semiconductor element group 30B of the lower arm are connected, a conductive block 24a (lead-out portion) to which the N terminal 60 (main current wiring) is connected is arranged. A conductive material such as copper is used for the conductive block 24a. The conductive block 24a is arranged at an intermediate position of the joint group of the wire 36 extending from the emitter electrode 32 of the semiconductor element group 30B of the lower arm, that is, at a position sandwiched between the second and third of the joint groups arranged in the X direction. The N terminal 60 is connected to the conductive block 24a and is electrically connected to the conductive plate 24 through the conductive block 24a.

[0033] The conductive block 22a sandwiched between the semiconductor element groups 30A of the upper arm and the two conductive blocks 23a sandwiching the semiconductor element group 30B of the lower arm are shaped such that the length in the Y direction is longer than the length in the X direction in a plan view. The conductive block 24a sandwiched between the junction groups of the wires 36 extending from the semiconductor element group 30B of the lower arm is set such that the length in the X direction is longer than the length in the Y direction in a plan view. Thereby, the enlargement in the X direction and the Y direction of the semiconductor device 1A (its insulating circuit board 20A and the case 10) due to the arrangement of the conductive block 22a and the conductive block 23a is suppressed.

[0034] The two conductive blocks 23a to which the OUT terminal 40 is connected are shaped such that the sum of their planar sizes (areas) is larger than the planar size (area) of the conductive block 22a to which the P terminal 50 is connected, for example, √2 times or more. The two conductive blocks 23a to which the OUT terminal 40 is connected are shaped such that the sum of their planar sizes (areas) is larger than the planar size (area) of the conductive block 24a to which the N terminal 60 is connected, for example, √2 times or more. This is because the main current flowing through the OUT terminal 40 is theoretically √2 times larger than the main currents flowing through the P terminal 50 and the N terminal 60. When the sum of the planar sizes of the two conductive blocks 23a to which the OUT terminal 40 is connected is the same as or smaller than the respective planar sizes of the conductive block 22a to which the P terminal 50 is connected and the conductive block 24a to which the N terminal 60 is connected, the current density becomes high, and there is a concern about heat generation and migration at the junction between the OUT terminal 40 and the conductive block 23a.

[0035] An insulating circuit board 20A including conductive plates 22, 23, and 24 on which the semiconductor element group 30A of the upper arm and the semiconductor element group 30B of the lower arm are mounted and connected as described above is enclosed in a case 10. The OUT terminal 40, the P terminal 50, and the N terminal 60 are connected to the insulating circuit board 20A enclosed in the case 10.

[0036] As shown in FIGS. 3(A) and 5(A), the OUT terminal 40 has an external terminal portion 41 disposed outside the case 10 and an extension portion 42 disposed inside the case 10. The external terminal portion 41 is provided on one side 11a of the case 10. The extension portion 42 is continuous with the external terminal portion 41 and extends from one side 11a of the case 10 to the inside of the case 10. The OUT terminal 40 is disposed so as to penetrate an opening 12a provided in the side wall portion 12 on one side 11a of the case 10. The extension portion 42 has a trunk portion 42a extending from one side 11a of the case 10 to the inside of the case 10, and a branch portion 42b and a branch portion 42c branched from the trunk portion 42a in a plan view. The branch portion 42b and the branch portion 42c are connected to two conductive blocks 23a disposed on a conductive plate 23 to which the collector electrodes 31 of the semiconductor element 30B group of the lower arm are connected, by connection portions 42ba and 42ca, respectively. The extension portion 42 connects the external terminal portion 41 to the connection portions 42ba and 42ca of the two conductive blocks 23a of the branch portion 42b and the branch portion 42c to each other. The OUT terminal 40 is electrically connected to the conductive plate 23 via the connection portions 42ba and 42ca and the two conductive blocks 23a.

[0037] As shown in FIGS. 3(A) and 5(B), the P terminal 50 has an external terminal portion 51 disposed outside the case 10 and an extension portion 52 disposed inside the case 10. The external terminal portion 51 is provided on the other side 11c of the case 10. The extension portion 52 is continuous with the external terminal portion 51 and extends from the other side 11c of the case 10 to the inside of the case 10. The P terminal 50 is disposed so as to penetrate an opening 12c provided in the side wall portion 12 on the other side 11c of the case 10. The extension portion 52 is connected to a conductive block 22a disposed on a conductive plate 22 to which the collector electrodes 31 of the semiconductor element 30A group of the upper arm are connected, by a connection portion 52a. The extension portion 52 connects the external terminal portion 51 to the connection portion 52a of the conductive block 22a to each other. The P terminal 50 is electrically connected to the conductive plate 22 via the connection portion 52a and the conductive block 22a.

[0038] As shown in FIGS. 3(A) and 5(C), the N terminal 60 has an external terminal portion 61 disposed outside the case 10 and an extension portion 62 disposed inside the case 10. The external terminal portion 61 is provided on the other side 11c side of the case 10. The extension portion 62 is continuous with the external terminal portion 61 and extends from the other side 11c side of the case 10 to the inside of the case 10. The N terminal 60 and the P terminal 50 are arranged so as to penetrate through an opening 12c provided in the side wall portion 12 on the other side 11c side of the case 10. The extension portion 62 is connected to a conductive block 24a disposed on a conductive plate 24 to which the emitter electrodes 32 of the lower arm semiconductor element group 30B are connected, by a connection portion 62a. The extension portion 62 connects the external terminal portion 61 and the connection portion 62a with the conductive block 24a to each other. The N terminal 60 is electrically connected to the conductive plate 24 via the connection portion 62a and the conductive block 24a.

[0039] The P terminal 50 and the N terminal 60 are laminated via an insulating member 70 at least inside the case 10. As the insulating member 70, an insulating sheet, insulating paper, etc. are used. As the insulating member 70, resin materials such as an aramid resin, a polyamide resin, a fluororesin, and a polyimide resin are used, for example. In the semiconductor device 1A, they are arranged in the order of the N terminal 60, the insulating member 70, and the P terminal 50 in a direction away from the insulating circuit board 20A. That is, among the P terminal 50 and the N terminal 60, the N terminal 60 is arranged closer to the insulating circuit board 20A side. The P terminal 50 and the N terminal 60 are shaped such that they partially overlap in plan view. The N terminal 60 is not provided under the connection portion 52a of the P terminal 50. The P terminal 50 and the insulating member 70 are each provided with an opening 50a and an opening 70a, respectively. The connection portion 62a of the N terminal 60 is exposed from the opening 50a of the P terminal 50 and the opening 70a of the insulating member 70. The connection portion 62a of the N terminal 60 is joined to the conductive block 24a by laser welding or the like through the opening 50a of the P terminal 50 and the opening 70a of the insulating member 70.

[0040] As shown in FIG. 3(A), in a plan view, the extension portion 52 of the P terminal 50 and the extension portion 62 of the N terminal 60 extend from the side 11c of the case 10 to between the branch portion 42b and the branch portion 42c provided on the extension portion 42 of the OUT terminal 40. In a plan view, the connection portions 42ba and 42ca of the branch portion 42b and the branch portion 42c of the OUT terminal 40, which are connected to the two conductive blocks 23a, are arranged so as to sandwich the extension portion 52 of the P terminal 50 and the extension portion 62 of the N terminal 60. In a plan view, a group of semiconductor elements 30B of the lower arm is arranged between the branch portion 42b and the branch portion 42c of the OUT terminal 40.

[0041] In the semiconductor device 1A, in the Y direction, these elements are arranged in the order of the external terminal portion 61 of the N terminal 60, the conductive plate 24 to which the N terminal 60 is connected, the conductive plate 23 to which the OUT terminal 40 is connected, and the external terminal portion 41 of the OUT terminal 40.

[0042] Inside the case 10, as shown in FIG. 3(B), a sealing resin 110 for sealing the insulating circuit board 20A and the groups of semiconductor elements 30A and 30B mounted thereon may be provided. In FIG. 3(A), for the sake of convenience, the illustration of the sealing resin 110 is omitted. As the sealing resin 110, for example, resin materials such as epoxy resin and phenolic resin, and gel materials such as silicone are used. The sealing resin 110 may contain an insulating filler such as silica. A plurality of types of materials may be used for the sealing resin 110. For example, a laminated structure may be adopted in which a gel material such as silicone is provided as a buffer coat material in the lower layer and a resin material such as epoxy resin is provided in the upper layer thereof.

[0043] Subsequently, the operation of the semiconductor device 1A having the above-described configuration will be described. FIG. 6 and FIG. 7 are diagrams for explaining the flow of the main current during the operation of the semiconductor device according to the first embodiment. FIG. 6 schematically shows a plan view of a main part of an example of the semiconductor device. FIG. 7(A) schematically shows a plan view of a main part of an example of the semiconductor device. FIG. 7(B) schematically shows a cross-sectional view taken along line VII-VII of FIG. 7(A). In FIG. 6, FIG. 7(A), and FIG. 7(B), the flow of the main current during the operation is schematically shown by thick arrows.

[0044] During the operation of the semiconductor device 1A, a high-potential-side power supply voltage is input to the P terminal 50, and a low-potential-side power supply voltage is input to the N terminal 60. The main current entering from the P terminal 50 flows to the OUT terminal 40 through the route as shown in FIG. 6. That is, the main current entering from the external terminal portion 51 of the P terminal 50 flows through the extension portion 52, flows from its connection portion 52a through the conductive block 22a to the conductive plate 22 of the insulating circuit board 20A, and is supplied to the collector electrode 31 of the upper-arm semiconductor element 30A group. The main current supplied to the collector electrode 31 passes through the upper-arm semiconductor element 30A group controlled through the gate wire 34, flows through the emitter electrode 32 and the wire 33 connected thereto to the conductive plate 23 of the insulating circuit board 20A. Then, the main current flowing to the conductive plate 23 flows from the two conductive blocks 23a through the connection portions 42ba and 42ca of the OUT terminal 40 to the branch portions 42b and 42c and the trunk portion 42a of the extension portion 42, and flows to the external terminal portion 41 (output current).

[0045] Also, the main current entering from the OUT terminal 40 flows to the N terminal 60 through the route as shown in FIG. 6. That is, the main current entering from the external terminal portion 41 of the OUT terminal 40 flows through the trunk portion 42a of the extending portion 42, as well as the branching portions 42b and 42c, and flows from the connecting portions 42ba and 42ca through the two conductive blocks 23a to the conductive plate 23 of the insulating circuit board 20A, and is supplied to the collector electrodes 31 of the semiconductor element group 30B of the lower arm. The main current supplied to the collector electrodes 31 passes through the semiconductor element group 30B of the lower arm controlled through the gate wire 37, and flows through the emitter electrodes 32 and the wire 36 connected thereto to the conductive plate 24 of the insulating circuit board 20A. Then, the main current flowing through the conductive plate 24 flows from the conductive block 24a through the connecting portion 62a of the N terminal 60 to the extending portion 62 and flows to the external terminal portion 61.

[0046] In the semiconductor device 1A, outside the semiconductor element group 30B of the lower arm on the conductive plate 23, that is, so as to sandwich them, two conductive blocks 23a to which the connecting portions 42ba and 42ca of the OUT terminal 40 are respectively connected are arranged. In the semiconductor device 1A, it is suppressed that the main current flowing from the P terminal 50 to the OUT terminal 40 via the semiconductor element group 30A of the upper arm flows under the semiconductor element group 30B of the lower arm.

[0047] In the arrangement of the conventional OUT terminal, P terminal, and N terminal, for example, in the arrangement as in the above Patent Documents 1-5, both the main current flowing from the P terminal to the OUT terminal via the semiconductor element group of the upper arm and the main current flowing from the OUT terminal to the N terminal via the semiconductor element group of the lower arm can have a structure that both flow under the semiconductor element group of the lower arm.

[0048] In contrast, in the semiconductor device 1A, both the main current flowing from the P terminal 50 through the semiconductor element group 30A of the upper arm to the OUT terminal 40 and the main current flowing from the OUT terminal 40 through the semiconductor element group 30B of the lower arm to the N terminal 60 are suppressed from flowing both under the semiconductor element group 30B of the lower arm. Thereby, the temperature rise of the semiconductor element group 30B of the lower arm, that is, the temperature rise of the semiconductor element group 30B of the lower arm due to the superposition of the heat generation associated with the operation and the heat generation of the conductive plate 23 due to the main current is suppressed. Therefore, the performance degradation due to overheating of the semiconductor element group 30B of the lower arm and the performance degradation of the semiconductor device 1A including them are suppressed.

[0049] Also, in the semiconductor device 1A, two conductive blocks 23a to which the OUT terminal 40 is connected are arranged on the conductive plate 23, and a structure is adopted such that the total planar size of these two conductive blocks 23a is larger than the planar size of the conductive block 22a to which the P terminal 50 is connected and the planar size of the conductive block 24a to which the N terminal 60 is connected. Thereby, even when the output current increases, heat generation and migration at the joint between the two conductive blocks 23a and the connection portions 42ba and 42ca are suppressed.

[0050] In the semiconductor device 1A, the P terminal 50 (its extension 52) and the N terminal 60 (its extension 62) are laminated via an insulating member 70 so as to partially overlap in a plan view. In the semiconductor device 1A, as shown in FIGS. 7(A) and 7(B), the path of the main current flowing between the P terminal 50 and the N terminal 60 is closed in a relatively short distance, and the inductance is reduced by the magnetic flux cancellation between the opposing P terminal 50 and N terminal 60 via the insulating member 70. Thereby, the voltage jump accompanying the switching of the semiconductor element 30A group and the semiconductor element 30B group is suppressed, and the performance degradation of the semiconductor device 1A is suppressed. In the semiconductor device 1A, in order to close the loop of the main current path between the P terminal 50 and the N terminal 60, it is not necessary to separately arrange a pattern (conductive plate) on the insulating circuit board 20A. Therefore, a high mounting density of the insulating circuit board 20A and the semiconductor element 30A group and the semiconductor element 30B group mounted thereon is realized, and the increase in the size of the semiconductor device 1A due to the increase in the size of the insulating circuit board 20A is suppressed. In the semiconductor device 1A, since the loop of the main current path between the P terminal 50 and the N terminal 60 is realized in a relatively short distance, the inductance reduction effect is further enhanced.

[0051] Also, in the semiconductor device 1A, among the P terminal 50 and the N terminal 60 laminated via the insulating member 70, the N terminal 60 is arranged on the insulating circuit board 20A side (FIGS. 3(A) and 3(B)). The N terminal 60 (its extension 62) is arranged so as to face the gate wire 37 and the sense emitter wire 38 connected to the semiconductor element 30B group of the lower arm on the insulating circuit board 20A. That is, in the semiconductor device 1A, the N terminal 60 connected to the low potential side of the semiconductor element 30B group of the lower arm faces the gate wire 37 of the semiconductor element 30B group of the lower arm and the sense emitter wire 38 connected to the low potential side of the semiconductor element 30B group of the lower arm. In this case, the potential difference between the N terminal 60, the gate wire 37, and the sense emitter wire 38 becomes relatively small. Therefore, it becomes possible to arrange the N terminal 60 closer to the gate wire 37 and the sense emitter wire 38 compared to the case where the P terminal 50 faces the gate wire 37 and the sense emitter wire 38.

[0052] Furthermore, in the semiconductor device 1A, the OUT terminal 40 (its extension 42) is arranged to face the gate wire 34 and the sense emitter wire 35 connected to the group of semiconductor elements 30A of the upper arm on the insulating circuit board 20A (FIGS. 3(A) and 3(B)). That is, in the semiconductor device 1A, the OUT terminal 40 connected to the low potential side of the group of semiconductor elements 30A of the upper arm faces the gate wire 34 of the group of semiconductor elements 30A of the upper arm and the sense emitter wire 35 connected to the low potential side of the group of semiconductor elements 30A of the upper arm. In this case, the potential difference between the OUT terminal 40, the gate wire 34, and the sense emitter wire 35 becomes relatively small. Therefore, it becomes possible to arrange the OUT terminal 40 close to the gate wire 34 and the sense emitter wire 35.

[0053] Thus, in the semiconductor device 1A, it becomes possible to arrange the N terminal 60 close to the gate wire 37 and the sense emitter wire 38, and arrange the OUT terminal 40 close to the gate wire 34 and the sense emitter wire 35. Therefore, it becomes possible to realize a low profile of the semiconductor device 1A. Further, when the SP portion 90 electrically connected to the conductive plate 22 is arranged as in the semiconductor device 1A, between the external SP terminal 19 and the SP wire 39 of the SP portion 90 and the portion of the OUT terminal 40 facing the SP portion 90, for example, between the SP portion 90 and the OUT terminal 40 in the region Q shown in FIGS. 3(A) and 4, an insulating member such as an insulating sheet may be arranged. Alternatively, a portion of the OUT terminal 40 facing the external SP terminal 19 and the SP wire 39 of the SP portion 90, for example, the portion of the OUT terminal 40 in the region Q shown in FIGS. 3(A) and 4, may be partially removed. Thereby, the influence of the potential of the OUT terminal 40 arranged close to the gate wire 34 and the sense emitter wire 35 on the potential of the external SP terminal 19 and the SP wire 39 of the SP portion 90 can be suppressed, the generation of overcurrent can be accurately detected, and the destruction of the semiconductor device 1A can be effectively suppressed.

[0054] Incidentally, the relationship between the semiconductor device 1A and the elements described in claim 1 of the claims is as follows. The OUT terminal 40 corresponds to the "first main current wiring", the trunk portion 42a corresponds to the "trunk portion", the branch portions 42b and 42c correspond to the "first branch portion and the second branch portion", and the extension portion 42 corresponds to the "first extension portion", respectively. The P terminal 50 or the N terminal 60 corresponds to the "second main current wiring".

[0055] Here, when the P terminal 50 is the "second main current wiring", the extension portion 52 corresponds to the "second extension portion", the conductive plate 22 to which it is electrically connected corresponds to the "conductive plate", the group of semiconductor elements 30A on the upper arm corresponds to the "plurality of semiconductor elements", the collector electrode 31 of the group of semiconductor elements 30A on the upper arm electrically connected to the conductive plate 22 corresponds to the "first electrode", and the emitter electrode 32 of the group of semiconductor elements 30A on the upper arm corresponds to the "second electrode". Thus, when the P terminal 50 is the "second main current wiring", the N terminal 60 becomes the "third main current wiring" (claims 4 and 6), the insulating member 70 becomes the "insulating member" (claim 4), and the opening 50a becomes the "first opening" (claim 5).

[0056] Also, when the N terminal 60 is the "second main current wiring", the extension portion 62 corresponds to the "second extension portion", the conductive plate 24 to which it is electrically connected corresponds to the "conductive plate", the group of semiconductor elements 30B on the lower arm corresponds to the "plurality of semiconductor elements", the emitter electrode 32 of the group of semiconductor elements 30B on the lower arm electrically connected to the conductive plate 24 corresponds to the "first electrode", and the collector electrode 31 of the group of semiconductor elements 30B on the lower arm corresponds to the "second electrode". Thus, when the N terminal 60 is the "second main current wiring", the P terminal 50 becomes the "third main current wiring" (claim 4).

[0057] Also, the relationship between the semiconductor device 1A and the element described in claim 10 of the claims is as follows. The OUT terminal 40 corresponds to the "first main current wiring", the external terminal portion 41 corresponds to the "first external terminal portion", the extension portion 42 corresponds to the "first extension portion", and the connection portions 42ba and 42ca correspond to the "first connection portion and the second connection portion", respectively. The P terminal 50 or the N terminal 60 corresponds to the "second main current wiring".

[0058] Here, when the P terminal 50 is the "second main current wiring", the external terminal portion 51 corresponds to the "second external terminal portion", the extension portion 52 corresponds to the "second extension portion", the connection portion 52a corresponds to the "third connection portion", the conductive plate 23 corresponds to the "first conductive plate", the conductive plate 22 corresponds to the "second conductive plate", the group of semiconductor elements 30B in the lower arm corresponds to the "plurality of first semiconductor elements", and the group of semiconductor elements 30A in the upper arm corresponds to the "plurality of second semiconductor elements".

[0059] Thus, when the P terminal 50 is the "second main current wiring", the N terminal 60 becomes the "third main current wiring" (Claim 18), the external terminal portion 61 becomes the "third external terminal portion", the extension portion 62 becomes the "third extension portion", the connection portion 62a becomes the "fourth connection portion", the conductive plate 24 becomes the "third conductive plate", the wire 36 becomes the "first wire", the wire 33 becomes the "second wire", the opening 12a becomes the "first opening", and the opening 12c becomes the "second opening" (Claim 18). The insulating member 70 becomes the "insulating member" (Claim 19), the openings 50a and 70a become the "third opening" and the "fourth opening" respectively, and the conductive block 24a becomes the "conductive block" (Claim 20). The gate wire 37 becomes the "first gate wire", the sense emitter wire 38 becomes the "first sense emitter wire", the gate wire 34 becomes the "second gate wire", the sense emitter wire 35 becomes the "second sense emitter wire", the external gate terminal 17 becomes the "first external gate terminal", the external sense emitter terminal 18 becomes the "first external sense emitter terminal", the external gate terminal 14 becomes the "second external gate terminal", and the external sense emitter terminal 15 becomes the "second external sense emitter terminal" (Claim 21).

[0060] Also, when the N terminal 60 is the "second main current wiring", the external terminal portion 61 corresponds to the "second external terminal portion", the extension portion 62 corresponds to the "second extension portion", the connection portion 62a corresponds to the "third connection portion", the conductive plate 23 corresponds to the "first conductive plate", the conductive plate 24 corresponds to the "second conductive plate", the group of semiconductor elements 30A in the upper arm corresponds to the "plurality of first semiconductor elements", and the group of semiconductor elements 30B in the lower arm corresponds to the "plurality of second semiconductor elements".

[0061] Furthermore, in the semiconductor device 1A described in this first embodiment, the external terminal portions 51 of the P terminals 50 and the external terminal portions 61 of the N terminals 60 disposed outside the case 10 may be arranged to overlap with each other via an insulating member in a plan view. In the semiconductor device 1A, the P terminals 50 and the N terminals 60 can also be changed to a shape such that the external terminal portions 51 and the external terminal portions 61 overlap with each other via an insulating member in a plan view.

[0062] Also, three semiconductor devices 1A as described in this first embodiment can be used to form a three-phase voltage source inverter circuit (Fig. 2) for U-phase, V-phase, and W-phase. Here, an example of a 2-in-1 package for the semiconductor device 1A is shown. However, when forming a three-phase voltage source inverter circuit, the functional parts of each phase of U-phase, V-phase, and W-phase can be housed in one case to form a 6-in-1 package.

[0063] [Second Embodiment] Figs. 8 to 10 are diagrams for explaining an example of a semiconductor device according to the second embodiment. Fig. 8 schematically shows a plan view of a main part of an example of the semiconductor device. Fig. 9 schematically shows a plan view of a main part of an example of the case and the insulating circuit board, etc. of the semiconductor device. Fig. 10(A) schematically shows a plan view of a main part of an example of the OUT terminal of the semiconductor device. Fig. 10(B) schematically shows a plan view of a main part of an example of the P terminal of the semiconductor device. Fig. 10(C) schematically shows a plan view of a main part of an example of the N terminal of the semiconductor device.

[0064] The semiconductor device 1B shown in Fig. 8 is an example of a so-called 2-in-1 type semiconductor device having the circuit configuration as shown in Fig. 1 above. The semiconductor device 1B includes a case 10, an insulating circuit board 20B, a plurality of semiconductor elements 30A, and a plurality of semiconductor elements 30B as shown in Figs. 8 and 9. The semiconductor device 1B further includes an OUT terminal 40, a P terminal 50, and an N terminal 60 as shown in Figs. 8 and 10(A) to 10(C). The OUT terminal 40, the P terminal 50, and the N terminal 60 are also referred to as main current wirings, respectively.

[0065] Inside the case 10, an insulating circuit board 20B on which a group of semiconductor elements 30A of the upper arm and a group of semiconductor elements 30B of the lower arm are mounted is arranged. As shown in FIGS. 8 and 9, the insulating circuit board 20B has, on an insulating substrate 21 (substrate), for example, two conductive plates 23A and 23B on which two groups of semiconductor elements 30B of the lower arm are arranged, two by two. On each of the conductive plates 23A and 23B, conductive blocks 23a to which the branch portions 42b and 42c of the OUT terminal 40 are joined are arranged respectively. In the region between the conductive plate 23A and the conductive plate 23B, a part of the conductive plate 22 on which the group of semiconductor elements 30A of the upper arm is arranged and a part of the conductive plate 24 to which the group of semiconductor elements 30B of the lower arm are wire-connected extend. On a part of the conductive plate 22 and a part of the conductive plate 24 that extend in the region between the conductive plate 23A and the conductive plate 23B, a conductive block 22a and a conductive block 24a are arranged respectively. The conductive plate 22, the conductive plates 23A and 23B, and the conductive plate 24 are arranged such that, for example, the total area of the conductive plates 23A and 23B is larger than the area of the conductive plate 22, and the area of the conductive plate 22 is larger than the area of the conductive plate 24.

[0066] In order to suppress heat generation and the like at the joint between the OUT terminal 40, which has a relatively high current density, and the two conductive blocks 23a, the total planar size of the two conductive blocks 23a on the conductive plate 23A and the conductive plate 23B is set to be larger than the planar size of the conductive block 22a on the conductive plate 22 and also larger than the planar size of the conductive block 24a on the conductive plate 24. Also, in order to suppress the increase in size of the semiconductor device 1B (its insulating circuit board 20B and case 10), each of the two conductive blocks 23a is provided in a position sandwiched between the semiconductor element 30B of the lower arm and the semiconductor element 30A of the upper arm in the Y direction, and has a shape in which the length in the X direction (first direction) is longer than the length in the Y direction (second direction) in plan view. Further, the conductive block 22a and the conductive block 24a are provided in a shape in which the length in the Y direction is longer than the length in the X direction in plan view. The insulating circuit board 20B of the semiconductor device 1B is different from the insulating circuit board 20A of the semiconductor device 1A described in the first embodiment in that it has such a configuration.

[0067] The group of semiconductor elements 30A of the upper arm is arranged on the conductive plate 22, the collector electrode 31 is connected to the conductive plate 22, and the emitter electrode 32 is connected to the conductive plates 23A and 23B by the wire 33. To the group of semiconductor elements 30A of the upper arm, a gate wire 34 and a sense emitter wire 35 are connected, and they are respectively connected to the external gate terminal 14 and the external sense emitter terminal 15. Also, the group of semiconductor elements 30B of the lower arm is arranged, for example, two by two on the conductive plate 23A and on the conductive plate 23B, the collector electrode 31 is connected to the conductive plates 23A and 23B, and the emitter electrode 32 is connected to the conductive plate 24 by the wire 36. To the group of semiconductor elements 30B of the lower arm, a gate wire 37 and a sense emitter wire 38 are connected, and they are respectively connected to the external gate terminal 17 and the external sense emitter terminal 18. Also, to the conductive plate 22 to which the collector electrode 31 of the group of semiconductor elements 30A of the upper arm is connected, an SP portion 90 (the external SP terminal 19 and the SP wire 39 described in the first embodiment) is connected.

[0068] As shown in FIGS. 8 and 10(A), the OUT terminal 40 has an external terminal portion 41 arranged outside the case 10 and an extension portion 42 arranged inside the case 10, and is arranged so as to penetrate an opening 12a provided in the side wall portion 12 on the side of one side 11a of the case 10. The branched portions 42b and 42c branched from the trunk portion 42a of the extension portion 42 of the OUT terminal 40 are respectively connected to the two conductive blocks 23a at the respective connection portions 42ba and 42ca. The OUT terminal 40 is electrically connected to the conductive plates 23A and 23B via the connection portions 42ba and 42ca and the two conductive blocks 23a.

[0069] As shown in FIGS. 8 and 10(B), the P terminal 50 has an external terminal portion 51 disposed outside the case 10 and an extending portion 52 disposed inside the case 10, and is disposed so as to penetrate an opening 12c provided in the side wall portion 12 on the other side 11c side of the case 10. The extending portion 52 is connected to the conductive block 22a on the conductive plate 22 at the connecting portion 52a. The P terminal 50 is electrically connected to the conductive plate 22 via the connecting portion 52a and the conductive block 22a.

[0070] As shown in FIGS. 8 and 10(C), the N terminal 60 has an external terminal portion 61 disposed outside the case 10 and an extending portion 62 disposed inside the case 10, and is disposed so as to penetrate the opening 12c provided in the side wall portion 12 on the other side 11c side of the case 10 together with the P terminal 50. The extending portion 62 is connected to the conductive block 24a on the conductive plate 24 at the connecting portion 62a. The N terminal 60 is electrically connected to the conductive plate 24 via the connecting portion 62a and the conductive block 24a.

[0071] The P terminal 50 and the N terminal 60 are laminated via an insulating member 70 such as an insulating sheet at least inside the case 10. In the semiconductor device 1B, they are arranged in the order of the N terminal 60, the insulating member 70, and the P terminal 50 in a direction away from the insulating circuit board 20B. The P terminal 50 and the N terminal 60 are shaped such that they partially overlap in plan view. The N terminal 60 is not provided under the connecting portion 52a of the P terminal 50. The connecting portion 62a of the N terminal 60 is exposed from the opening 50a of the P terminal 50 and the opening 70a of the insulating member 70. The connecting portion 62a of the N terminal 60 is joined to the conductive block 24a by laser welding or the like through the opening 50a of the P terminal 50 and the opening 70a of the insulating member 70. As shown in FIG. 8, in plan view, the extending portion 52 of the P terminal 50 and the extending portion 62 of the N terminal 60 extend from the side 11c side of the case 10 to between the branch portion 42b and the branch portion 42c of the OUT terminal 40. In plan view, the connecting portions 42ba and 42ca of the branch portion 42b and the branch portion 42c of the OUT terminal 40, which are connected to the two conductive blocks 23a, are arranged so as to sandwich the extending portion 52 of the P terminal 50 and the extending portion 62 of the N terminal 60.

[0072] In the semiconductor device 1B, in the Y direction, the external terminal portion 61 of the N terminal 60, the conductive plate 24 to which the N terminal 60 is connected, the conductive plates 23A and 23B to which the OUT terminal 40 is connected, and the external terminal portion 41 of the OUT terminal 40 are arranged in this order.

[0073] Inside the case 10, according to the example of FIG. 3(B) above, a sealing resin for sealing the insulating circuit board 20B and the groups of semiconductor elements 30A and 30B mounted thereon may be provided. In FIG. 8, for the sake of convenience, the illustration of the sealing resin is omitted.

[0074] During the operation of the semiconductor device 1B having the above configuration, a high-potential-side power supply voltage is input to the P terminal 50, and a low-potential-side power supply voltage is input to the N terminal 60. The main current entering from the external terminal portion 51 of the P terminal 50 flows through the extension portion 52, flows from its connection portion 52a through the conductive block 22a to the conductive plate 22 of the insulating circuit board 20B, and is supplied to the collector electrodes 31 of the group of semiconductor elements 30A in the upper arm. The main current supplied to the collector electrodes 31 passes through the group of semiconductor elements 30A in the upper arm controlled through the gate wire 34, and flows through the emitter electrodes 32 and the wire 33 connected thereto to the conductive plates 23A and 23B of the insulating circuit board 20B. Then, the main current flowing through the conductive plates 23A and 23B flows from the two conductive blocks 23a through the connection portions 42ba and 42ca of the OUT terminal 40 to the branch portions 42b and 42c and the trunk portion 42a of the extension portion 42, and flows to the external terminal portion 41.

[0075] Also, the main current entering from the external terminal portion 41 of the OUT terminal 40 flows through the trunk portion 42a of the extension portion 42, as well as the branch portions 42b and 42c, and flows from the connection portions 42ba and 42ca through two conductive blocks 23a to the conductive plates 23A and 23B of the insulating circuit board 20B, and is supplied to the collector electrodes 31 of the semiconductor element group 30B of the lower arm. The main current supplied to the collector electrodes 31 passes through the semiconductor element group 30B of the lower arm controlled through the gate wire 37, and flows through the emitter electrodes 32 and the wire 36 connected thereto to the conductive plate 24 of the insulating circuit board 20B. Then, the main current flowing through the conductive plate 24 flows from the conductive block 24a through the connection portion 62a of the N terminal 60 to the extension portion 62 and flows to the external terminal portion 61.

[0076] In the semiconductor device 1B, two conductive blocks 23a to which the OUT terminal 40 is connected are arranged in the region between the connection portions of the wire 33 extending from the semiconductor element group 30A of the upper arm and the semiconductor element group 30B of the lower arm on the conductive plates 23A and 23B. In the semiconductor device 1B, the main current flowing from the P terminal 50 through the semiconductor element group 30A of the upper arm to the OUT terminal 40 is suppressed from flowing under the semiconductor element group 30B of the lower arm. Therefore, in the semiconductor device 1B, both the main current flowing from the P terminal 50 through the semiconductor element group 30A of the upper arm to the OUT terminal 40 and the main current flowing from the OUT terminal 40 through the semiconductor element group 30B of the lower arm to the N terminal 60 are suppressed from both flowing under the semiconductor element group 30B of the lower arm. Thereby, the performance degradation due to overheating of the semiconductor element group 30B of the lower arm and the performance degradation of the semiconductor device 1B including them are suppressed.

[0077] Also, in the semiconductor device 1B, the P terminal 50 (its extension 52) and the N terminal 60 (its extension 62) are laminated via the insulating member 70 so as to partially overlap in a plan view. In the semiconductor device 1B, the path of the main current flowing between the P terminal 50 and the N terminal 60 is closed in a relatively short distance, and the inductance is reduced by the magnetic flux cancellation between the opposing P terminal 50 and N terminal 60 via the insulating member 70. As a result, the voltage overshoot accompanying the switching of the semiconductor element 30A group and the semiconductor element 30B group is suppressed, and the performance degradation of the semiconductor device 1B is suppressed. In the semiconductor device 1B, in order to close the loop of the main current path between the P terminal 50 and the N terminal 60, it is not necessary to separately arrange a pattern (conductive plate) on the insulating circuit board 20B, so high mounting density is achieved and the enlargement of the semiconductor device 1B is suppressed.

[0078] Also, in the semiconductor device 1B, an N terminal 60 connected to the low-potential side of the semiconductor element group 30B of the lower arm faces the gate wire 37 of the semiconductor element group 30B of the lower arm and the sense emitter wire 38 connected to the low-potential side of the semiconductor element group 30B of the lower arm. Therefore, it becomes possible to arrange the N terminal 60 relatively close to the gate wire 37 and the sense emitter wire 38. Further, in the semiconductor device 1B, an OUT terminal 40 connected to the low-potential side of the semiconductor element group 30A of the upper arm faces the gate wire 34 of the semiconductor element group 30A of the upper arm and the sense emitter wire 35 connected to the low-potential side of the semiconductor element group 30A of the upper arm. Therefore, it becomes possible to arrange the OUT terminal 40 relatively close to the gate wire 34 and the sense emitter wire 35. By arranging the N terminal 60 close to the gate wire 37 and the sense emitter wire 38 and arranging the OUT terminal 40 close to the gate wire 34 and the sense emitter wire 35, the low-profile of the semiconductor device 1B is realized. Also, when an SP portion 90 electrically connected to the conductive plate 22 is arranged as in the semiconductor device 1B, an insulating member such as an insulating sheet may be arranged between the SP portion 90 and the OUT terminal 40, for example, between the SP portion 90 and the OUT terminal 40 in the region Q shown in FIG. 8. Alternatively, a portion of the OUT terminal 40 that faces the SP portion 90, for example, the portion of the OUT terminal 40 in the region Q shown in FIG. 8, may be partially removed. Thereby, it is possible to suppress the influence of the potential of the OUT terminal 40 arranged close to the gate wire 34 and the sense emitter wire 35 on the potential of the SP portion 90 and suppress the destruction of the semiconductor device 1B due to overcurrent.

[0079] Note that the relationship between the semiconductor device 1B and the elements described in claims 1 and 10 of the claims is the same as that described in the first embodiment for the semiconductor device 1A, except that the conductive plate 23 of the semiconductor device 1A described in the first embodiment becomes the conductive plates 23A and 23B in the semiconductor device 1B. The conductive plates 23A and 23B of the semiconductor device 1B become the "first output conductive pattern" and the "second output conductive pattern" (claim 22).

[0080] Furthermore, in the semiconductor device 1B described in this second embodiment, the external terminal portions 51 of the P terminals 50 and the external terminal portions 61 of the N terminals 60 disposed outside the case 10 may be arranged to overlap with each other via an insulating member in a plan view. In the semiconductor device 1B, the P terminals 50 and the N terminals 60 can also be changed to a shape such that the external terminal portions 51 and the external terminal portions 61 overlap with each other via an insulating member in a plan view.

[0081] Also, three semiconductor devices 1B as described in this second embodiment can be used to form a three-phase voltage source inverter circuit (Fig. 2) for U-phase, V-phase, and W-phase. Here, an example of a 2-in-1 package for the semiconductor device 1B is shown. However, when forming a three-phase voltage source inverter circuit, the functional parts of each phase of U-phase, V-phase, and W-phase can be housed in one case to form a 6-in-1 package.

[0082] [Third Embodiment] Figs. 11 to 13 are diagrams for explaining an example of a semiconductor device according to the third embodiment. Fig. 11 schematically shows a plan view of a main part of an example of the semiconductor device. Fig. 12 schematically shows a plan view of a main part of an example of the case and the insulating circuit board, etc. of the semiconductor device. Fig. 13(A) schematically shows a plan view of a main part of an example of the OUT terminal of the semiconductor device. Fig. 13(B) schematically shows a plan view of a main part of an example of the P terminal of the semiconductor device. Fig. 13(C) schematically shows a plan view of a main part of an example of the N terminal of the semiconductor device.

[0083] The semiconductor device 1C shown in Fig. 11 is an example of a so-called 2-in-1 type semiconductor device having the circuit configuration as shown in Fig. 1 above. The semiconductor device 1C includes a case 10, an insulating circuit board 20C, a plurality of semiconductor elements 30A, and a plurality of semiconductor elements 30B as shown in Figs. 11 and 12. The semiconductor device 1C further includes an OUT terminal 40, a P terminal 50, and an N terminal 60 as shown in Figs. 11 and 13(A) to 13(C). The OUT terminal 40, the P terminal 50, and the N terminal 60 are also referred to as main current wirings, respectively.

[0084] Inside the case 10, an insulating circuit board 20C on which a group of semiconductor elements 30A for the upper arm and a group of semiconductor elements 30B for the lower arm are mounted is arranged. As shown in FIGS. 11 and 12, the insulating circuit board 20C has a conductive plate 22, a conductive plate 23, and a conductive plate 24 arranged on an insulating substrate 21 (substrate). In the semiconductor device 1C, in the Y direction from the conductive plate 24, the conductive plate 24, the conductive plate 23, and the conductive plate 22 are arranged in this order. The conductive plate 22, the conductive plate 23, and the conductive plate 24 are arranged such that, for example, the area of the conductive plate 23 is larger than the area of the conductive plate 22, and the area of the conductive plate 22 is larger than the area of the conductive plate 24. A group of semiconductor elements 30A for the upper arm is arranged on the conductive plate 22, and a group of semiconductor elements 30B for the lower arm is arranged on the conductive plate 23. In the group of semiconductor elements 30A for the upper arm, the collector electrode 31 is connected to the conductive plate 22, and the emitter electrode 32 is connected to the conductive plate 23 by a wire 33. A gate wire 34 and a sense emitter wire 35 are connected to the group of semiconductor elements 30A for the upper arm, and they are respectively connected to an external gate terminal 14 and an external sense emitter terminal 15. Also, in the group of semiconductor elements 30B for the lower arm, the collector electrode 31 is connected to the conductive plate 23, and the emitter electrode 32 is connected to the conductive plate 24 by a wire 36. A gate wire 37 and a sense emitter wire 38 are connected to the group of semiconductor elements 30B for the lower arm, and they are respectively connected to an external gate terminal 17 and an external sense emitter terminal 18. Also, an SP section 90 (the external SP terminal 19 and the SP wire 39 described in the first embodiment) is connected to the conductive plate 22 to which the collector electrode 31 of the group of semiconductor elements 30A for the upper arm is connected.

[0085] On the conductive plate 22 to which the collector electrode 31 of the group of semiconductor elements 30A for the upper arm is connected, two conductive blocks 22a to which a P terminal 50 is connected are arranged. The two conductive blocks 22a are arranged at positions outside the group of semiconductor elements 30A for the upper arm, that is, at positions sandwiching four groups of semiconductor elements 30A arranged in the X direction.

[0086] On the conductive plate 23 to which the emitter electrodes 32 of the semiconductor element group 30A in the upper arm and the collector electrodes 31 of the semiconductor element group 30B in the lower arm are connected, a conductive block 23a to which the OUT terminal 40 is connected is arranged. The conductive block 23a is arranged at the position of the joint group of the wires 33 extending from the emitter electrodes 32 of the semiconductor element group 30A in the upper arm and at the intermediate position of the semiconductor element group 30B in the lower arm, that is, at the position sandwiched between the second and the third of the four semiconductor elements 30B arranged in the X direction.

[0087] On the conductive plate 24 to which the emitter electrodes 32 of the semiconductor element group 30B in the lower arm are connected, two conductive blocks 24a to which the N terminal 60 is connected are arranged. The two conductive blocks 24a are arranged at the outer position of the joint group of the wires 36 extending from the emitter electrodes 32 of the semiconductor element group 30B in the lower arm, that is, at the position sandwiching the joint group arranged in the X direction.

[0088] The two conductive blocks 22a sandwiching the semiconductor element group 30A in the upper arm, the conductive block 23a sandwiched by the semiconductor element group 30B in the lower arm, and the two conductive blocks 24a sandwiching the joint group of the wires 36 extending from the semiconductor element group 30B in the lower arm are set to a predetermined shape in order to suppress the increase in size of the semiconductor device 1C (its insulating circuit board 20C and case 10). That is, the two conductive blocks 22a on the conductive plate 22 and the conductive block 23a on the conductive plate 23 are set such that the length in the Y direction is longer than the length in the X direction in plan view. The two conductive blocks 24a on the conductive plate 24 are set such that the length in the X direction is longer than the length in the Y direction in plan view. Further, in order to suppress heat generation and the like at the joint between the OUT terminal 40 and the conductive block 23a where a relatively high current density is generated, the planar size of the conductive block 23a on the conductive plate 23 is larger than the sum of the planar sizes of the two conductive blocks 22a on the conductive plate 22 and is also set to be larger than the sum of the planar sizes of the two conductive blocks 24a on the conductive plate 24.

[0089] As shown in FIGS. 11 and 13(A), the OUT terminal 40 has an external terminal portion 41 disposed outside the case 10 and an extension portion 42 disposed inside the case 10. The external terminal portion 41 is provided on one side 11a side of the case 10. The extension portion 42 is continuous with the external terminal portion 41 and extends from one side 11a side of the case 10 to the inside of the case 10. The OUT terminal 40 is disposed so as to penetrate an opening 12a provided in the side wall portion 12 on one side 11a side of the case 10. The extension portion 42 is connected to a conductive block 23a disposed on a conductive plate 23 to which the collector electrodes 31 of the lower arm semiconductor element group 30B are connected, by a connection portion 42d. The extension portion 42 connects the external terminal portion 41 and the connection portion 42d to each other. The OUT terminal 40 is electrically connected to the conductive plate 23 via the connection portion 42d and the conductive block 23a.

[0090] As shown in FIGS. 11 and 13(B), the P terminal 50 has an external terminal portion 51 disposed outside the case 10 and an extension portion 52 disposed inside the case 10. The external terminal portion 51 is provided on the other side 11c side of the case 10. The extension portion 52 is continuous with the external terminal portion 51 and extends from the other side 11c side of the case 10 to the inside of the case 10. The P terminal 50 is disposed so as to penetrate an opening 12c provided in the side wall portion 12 on the other side 11c side of the case 10. The extension portion 52 has a trunk portion 52b extending from the other side 11c side of the case 10 to the inside of the case 10, and a branch portion 52c and a branch portion 52d branched from the trunk portion 52b in a plan view. The branch portion 52c and the branch portion 52d are connected to two conductive blocks 22a disposed on a conductive plate 22 to which the collector electrodes 31 of the upper arm semiconductor element group 30A are connected, by a connection portion 52ca and a connection portion 52da, respectively. The extension portion 52 connects the external terminal portion 51 and the connection portions 52ca and 52da of the two conductive blocks 22a of the branch portion 52c and the branch portion 52d to each other. The P terminal 50 is electrically connected to the conductive plate 22 via the connection portion 52ca and the connection portion 52da and the two conductive blocks 22a.

[0091] As shown in FIGS. 11 and 13(C), the N terminal 60 has an external terminal portion 61 disposed outside the case 10 and an extension portion 62 disposed inside the case 10. The external terminal portion 61 is provided on the other side 11c side of the case 10. The extension portion 62 is continuous with the external terminal portion 61 and extends from the other side 11c side of the case 10 to the inside of the case 10. The N terminal 60 is arranged to penetrate an opening 12c provided in the side wall portion 12 on the other side 11c side of the case 10 together with the P terminal 50. The extension portion 62 has a trunk portion 62b extending from the other side 11c side of the case 10 to the inside of the case 10, and a branch portion 62c and a branch portion 62d branched from the trunk portion 62b in a plan view. The branch portion 62c and the branch portion 62d are connected to two conductive blocks 24a disposed on a conductive plate 24 to which the emitter electrodes 32 of the lower arm semiconductor element group 30B are connected, by connection portions 62ca and 62da, respectively. The extension portion 62 connects the external terminal portion 61 to the connection portions 62ca and 62da of the two conductive blocks 24a of the branch portion 62c and the branch portion 62d to each other. The N terminal 60 is electrically connected to the conductive plate 24 via the connection portions 62ca and 62da and the two conductive blocks 24a.

[0092] The P terminal 50 and the N terminal 60 are laminated via an insulating member 70 such as an insulating sheet at least inside the case 10. In the semiconductor device 1C, they are arranged in the order of the N terminal 60, the insulating member 70, and the P terminal 50 in a direction away from the insulating circuit board 20C. The P terminal 50 and the N terminal 60 are shaped so as to partially overlap in plan view. The N terminal 60 is not provided under the connection portions 52ca and 52da of the P terminal 50. The P terminal 50 and the insulating member 70 are respectively provided with an opening 50a and an opening 70a (notch). The connection portions 62ca and 62da of the N terminal 60 are exposed from the opening 50a of the P terminal 50 and the opening 70a of the insulating member 70. The connection portions 62ca and 62da of the N terminal 60 are provided under the opening 50a of the P terminal 50 and the opening 70a of the insulating member 70. The connection portions 62ca and 62da of the N terminal 60 are joined to the two conductive blocks 24a by laser welding or the like through the opening 50a of the P terminal 50 and the opening 70a of the insulating member 70.

[0093] As shown in FIG. 11, in plan view, the extending portion 42 of the OUT terminal 40 extends between the branch portion 52c and the branch portion 52d provided on the extending portion 52 of the P terminal 50, and between the branch portion 62c and the branch portion 62d provided on the extending portion 62 of the N terminal 60. In plan view, the connection portions 52ca and 52da of the branch portion 52c and the branch portion 52d of the P terminal 50, which are connected to the two conductive blocks 22a, are arranged so as to sandwich the extending portion 42 of the OUT terminal 40. In plan view, the connection portions 62ca and 62da of the branch portion 62c and the branch portion 62d of the N terminal 60, which are connected to the two conductive blocks 24a, are arranged so as to sandwich the extending portion 42 of the OUT terminal 40. In plan view, the group of semiconductor elements 30A of the upper arm is arranged between the branch portion 52c and the branch portion 52d of the P terminal 50.

[0094] In the semiconductor device 1C, in the Y direction, these elements are arranged in the order of the external terminal portion 61 of the N terminal 60, the conductive plate 24 to which the N terminal 60 is connected, the conductive plate 22 to which the P terminal 50 is connected, and the external terminal portion 41 of the OUT terminal 40.

[0095] Inside the case 10, a sealing resin for sealing the insulating circuit board 20C and the groups of semiconductor elements 30A and 30B mounted thereon may be provided according to the example of FIG. 3(B) above. Incidentally, in FIG. 11, for the sake of convenience, the illustration of the sealing resin is omitted.

[0096] During the operation of the semiconductor device 1C having the above configuration, a high-potential side power supply voltage is input to the P terminal 50, and a low-potential side power supply voltage is input to the N terminal 60. The main current entering from the external terminal portion 51 of the P terminal 50 flows through the trunk portion 52b, the branch portions 52c and 52d of the extension portion 52, and flows from the connection portions 52ca and 52da through the two conductive blocks 22a to the conductive plate 22 of the insulating circuit board 20C, and is supplied to the collector electrodes 31 of the group of semiconductor elements 30A in the upper arm. The main current supplied to the collector electrodes 31 passes through the group of semiconductor elements 30A in the upper arm controlled through the gate wire 34, and flows through the emitter electrodes 32 and the wire 33 connected thereto to the conductive plate 23 of the insulating circuit board 20C. Then, the main current flowing through the conductive plate 23 flows from the conductive block 23a through the connection portion 42d of the OUT terminal 40 to the extension portion 42 and flows to the external terminal portion 41.

[0097] Also, the main current entering from the external terminal portion 41 of the OUT terminal 40 flows through the extension portion 42, and from its connection portion 42d through the conductive block 23a to the conductive plate 23 of the insulating circuit board 20C, and is supplied to the collector electrodes 31 of the group of semiconductor elements 30B in the lower arm. The main current supplied to the collector electrodes 31 passes through the group of semiconductor elements 30B in the lower arm controlled through the gate wire 37, and flows through the emitter electrodes 32 and the wire 36 connected thereto to the conductive plate 24 of the insulating circuit board 20C. Then, the main current flowing through the conductive plate 24 flows from the two conductive blocks 24a through the connection portions 62ca and 62da of the N terminal 60 to the branch portions 62c and 62d and the trunk portion 62b of the extension portion 62, and flows to the external terminal portion 61.

[0098] In the semiconductor device 1C, the main current flowing from the P terminal 50 through the semiconductor element group 30A of the upper arm to the OUT terminal 40 is suppressed from flowing under the semiconductor element group 30B of the lower arm. Therefore, in the semiconductor device 1C, both the main current flowing from the P terminal 50 through the semiconductor element group 30A of the upper arm to the OUT terminal 40 and the main current flowing from the OUT terminal 40 through the semiconductor element group 30B of the lower arm to the N terminal 60 are suppressed from flowing under the semiconductor element group 30B of the lower arm. As a result, the performance degradation due to overheating of the semiconductor element group 30B of the lower arm and the performance degradation of the semiconductor device 1C including them are suppressed.

[0099] Also, in the semiconductor device 1C, the P terminal 50 (its extension 52) and the N terminal 60 (its extension 62) are laminated via the insulating member 70 so as to partially overlap in a plan view. In the semiconductor device 1C, the path of the main current flowing between the P terminal 50 and the N terminal 60 is closed in a relatively short distance, and the inductance is reduced by the magnetic flux cancellation between the opposing P terminal 50 and N terminal 60 via the insulating member 70. As a result, the voltage rise accompanying the switching of the semiconductor element group 30A and the semiconductor element group 30B is suppressed, and the performance degradation of the semiconductor device 1C is suppressed. In the semiconductor device 1C, since it is not necessary to separately arrange a pattern (conductive plate) on the insulating circuit board 20C for closing the loop of the main current path between the P terminal 50 and the N terminal 60, high mounting density is achieved and the increase in size of the semiconductor device 1C is suppressed.

[0100] Also, in the semiconductor device 1C, an N terminal 60 connected to the low potential side of the semiconductor element 30B group of the lower arm faces the gate wire 37 of the semiconductor element 30B group of the lower arm and the sense emitter wire 38 connected to the low potential side of the semiconductor element 30B group of the lower arm. Further, in the semiconductor device 1C, an OUT terminal 40 connected to the low potential side of the semiconductor element 30A group of the upper arm faces the gate wire 34 of the semiconductor element 30A group of the upper arm and the sense emitter wire 35 connected to the low potential side of the semiconductor element 30A group of the upper arm. The N terminal 60 can be arranged relatively close to the gate wire 37 and the sense emitter wire 38, and the OUT terminal 40 can be arranged relatively close to the gate wire 34 and the sense emitter wire 35, enabling the semiconductor device 1C to be made low-profile. Also, when an SP portion 90 electrically connected to the conductive plate 22 is arranged as in the semiconductor device 1C, an insulating member such as an insulating sheet may be arranged between the SP portion 90 and the OUT terminal 40, for example, between the SP portion 90 and the OUT terminal 40 in the region Q shown in FIG. 11. Alternatively, a portion of the OUT terminal 40 that faces the SP portion 90, for example, the portion of the OUT terminal 40 in the region Q shown in FIG. 11, may be partially removed. Thereby, it is possible to suppress the influence of the potential of the OUT terminal 40 arranged close to the gate wire 34 and the sense emitter wire 35 on the potential of the SP portion 90 and suppress the destruction of the semiconductor device 1C caused by overcurrent.

[0101] Note that the relationship between the semiconductor device 1C and the elements described in claim 1 of the claims is as follows. The OUT terminal 40 corresponds to the "second main current wiring", the extension portion 42 corresponds to the "second extension portion", and the conductive plate 23 corresponds to the "conductive plate". The P terminal 50 or the N terminal 60 corresponds to the "first main current wiring".

[0102] Here, when the P terminal 50 is the "first main current wiring", the trunk portion 52b corresponds to the "trunk portion", the branch portions 52c and 52d correspond to the "first branch portion and the second branch portion", the extension portion 52 corresponds to the "first extension portion", the group of semiconductor elements 30A in the upper arm corresponds to the "plurality of semiconductor elements", the emitter electrodes 32 of the group of semiconductor elements 30A in the upper arm correspond to the "first electrode", and the collector electrodes 31 of the group of semiconductor elements 30A in the upper arm correspond to the "second electrode". Thus, when the P terminal 50 is the "first main current wiring", the N terminal 60 becomes the "third main current wiring" (Claims 7 and 9), the insulating member 70 becomes the "insulating member" (Claim 7), and the opening 50a becomes the "second opening" (Claim 8).

[0103] Also, when the N terminal 60 is the "first main current wiring", the trunk portion 62b corresponds to the "trunk portion", the branch portions 62c and 62d correspond to the "first branch portion and the second branch portion", the extension portion 62 corresponds to the "first extension portion", the group of semiconductor elements 30B in the lower arm corresponds to the "plurality of semiconductor elements", the collector electrodes 31 of the group of semiconductor elements 30B in the lower arm correspond to the "first electrode", and the emitter electrodes 32 of the group of semiconductor elements 30B in the lower arm correspond to the "second electrode". Thus, when the N terminal 60 is the "first main current wiring", the P terminal 50 becomes the "third main current wiring" (Claim 7).

[0104] Also, the relationship between the semiconductor device 1C and the element described in Claim 10 of the claims is as follows. The OUT terminal 40 corresponds to the "second main current wiring", the external terminal portion 41 corresponds to the "second external terminal portion", the extension portion 42 corresponds to the "second extension portion", and the connection portion 42d corresponds to the "third connection portion". The P terminal 50 or the N terminal 60 corresponds to the "first main current wiring".

[0105] Here, when the P terminal 50 is the "first main current wiring", the external terminal portion 51 corresponds to the "first external terminal portion", the extension portion 52 corresponds to the "first extension portion", the connection portions 52ca and 52da correspond to the "first connection portion and the second connection portion", the conductive plate 22 corresponds to the "first conductive plate", the conductive plate 23 corresponds to the "second conductive plate", the group of semiconductor elements 30A in the upper arm corresponds to the "plurality of first semiconductor elements", and the group of semiconductor elements 30B in the lower arm corresponds to the "plurality of second semiconductor elements".

[0106] Thus, when the P terminal 50 is the "first main current wiring", the N terminal 60 becomes the "third main current wiring" (Claim 13), the external terminal portion 61 becomes the "third external terminal portion", the extension portion 62 becomes the "third extension portion", the connection portions 62ca and 62da become the "fourth connection portion and the fifth connection portion", the conductive plate 24 becomes the "third conductive plate", the wire 33 becomes the "first wire", the wire 36 becomes the "second wire", the opening 12c becomes the "first opening", and the opening 12a becomes the "second opening" (Claim 13). The insulating member 70 becomes the "insulating member" (Claim 14), the opening 50a becomes the "third opening and the fourth opening", the opening 70a becomes the "fifth opening and the sixth opening", and the conductive block 24a becomes the "conductive block" (Claim 15). The gate wire 34 becomes the "first gate wire", the sense emitter wire 35 becomes the "first sense emitter wire", the gate wire 37 becomes the "second gate wire", the sense emitter wire 38 becomes the "second sense emitter wire", the external gate terminal 14 becomes the "first external gate terminal", the external sense emitter terminal 15 becomes the "first external sense emitter terminal", the external gate terminal 17 becomes the "second external gate terminal", and the external sense emitter terminal 18 becomes the "second external sense emitter terminal" (Claim 16).

[0107] Also, when the N terminal 60 is the "first main current wiring", the external terminal portion 61 corresponds to the "first external terminal portion", the extension portion 62 corresponds to the "first extension portion", the connection portions 62ca and 62da correspond to the "first connection portion and the second connection portion", the conductive plate 24 corresponds to the "first conductive plate", the conductive plate 23 corresponds to the "second conductive plate", the group of semiconductor elements 30B in the lower arm corresponds to the "plurality of first semiconductor elements", and the group of semiconductor elements 30A in the upper arm corresponds to the "plurality of second semiconductor elements".

[0108] Still, in the semiconductor device 1C described in the third embodiment, the external terminal portions 51 of the P terminal 50 and the external terminal portions 61 of the N terminal 60 disposed outside the case 10 may be arranged to overlap with each other via an insulating member in a plan view. In the semiconductor device 1C, the P terminal 50 and the N terminal 60 can also be changed to a shape such that the external terminal portions 51 and the external terminal portions 61 overlap with each other via an insulating member in a plan view.

[0109] Also, three semiconductor devices 1C as described in the third embodiment can be used to configure a three-phase voltage source inverter circuit (FIG. 2) for U-phase, V-phase, and W-phase. Here, an example in which the semiconductor device 1C is a 2-in-1 package is shown. However, when configuring a three-phase voltage source inverter circuit, the functional parts of each phase of U-phase, V-phase, and W-phase can be housed in one case to form a 6-in-1 package.

[0110] [Fourth Embodiment] FIG. 14 is a diagram for explaining an example of a semiconductor device according to the fourth embodiment. FIG. 14 schematically shows a plan view of a main part of an example of the semiconductor device. The semiconductor device 1D shown in FIG. 14 is an example of a so-called 6-in-1 type semiconductor device having the circuit configuration as shown in FIG. 2 above. For example, the semiconductor device 1D has a configuration in which three insulating circuit boards 20C (FIG. 12) on which a group of semiconductor elements 30A and a group of semiconductor elements 30B as described in the third embodiment are mounted are arranged side by side in the X direction inside the case 10.

[0111] In the semiconductor device 1D, an OUT terminal 40 is connected to a conductive block 23a disposed on a conductive plate 23 of each insulating circuit board 20C. The OUT terminal 40 penetrates an opening 12a on the side of the side 11a of the case 10, and an extension 42 extending from an external terminal portion 41 outside the case 10 into the case 10 is connected to the conductive block 23a at a connection portion 42d. The OUT terminal 40 is electrically connected to the conductive plate 23 via the connection portion 42d and the conductive block 23a. The OUT terminals 40 connected to the respective insulating circuit boards 20C correspond to the output nodes of the U phase, V phase, and W phase, respectively.

[0112] In the semiconductor device 1D, a P terminal 50 is connected to two conductive blocks 22a disposed on a conductive plate 22 of each insulating circuit board 20C. The P terminal 50 penetrates an opening 12c on the side of the side 11c of the case 10, and a branch portion 52c and a branch portion 52d of an extension 52 extending from an external terminal portion 51 outside the case 10 into the case 10 are connected to the two conductive blocks 22a at connection portions 52ca and 52da, respectively. The P terminal 50 is electrically connected to the conductive plate 22 via the connection portions 52ca and 52da and the two conductive blocks 22a. The P terminal 50 has a shape such that a branch portion 52d connected to one conductive block 22a of one of the adjacent insulating circuit boards 20C and a branch portion 52c connected to one conductive block 22a of the other insulating circuit board 20C facing the one conductive block 22a in the X direction are continuous. That is, it can be said that the P terminal 50 of the semiconductor device 1D has a shape in which three P terminals 50 are continuous or three are integrated as described in the third embodiment.

[0113] In the semiconductor device 1D, an N terminal 60 is connected to two conductive blocks 24a disposed on a conductive plate 24 of each insulating circuit board 20C. The N terminal 60 passes through an opening 12c on the side of the side 11c of the case 10, and a branch portion 62c and a branch portion 62d of an extension portion 62 extending from an external terminal portion 61 outside the case 10 into the case 10 are connected to the two conductive blocks 24a by a connection portion 62ca and a connection portion 62da, respectively. The N terminal 60 is electrically connected to the conductive plate 24 via the connection portion 62ca, the connection portion 62da, and the two conductive blocks 24a. The N terminal 60 has a shape such that a branch portion 62d connected to one conductive block 24a of one of the adjacent insulating circuit boards 20C and a branch portion 62c connected to one conductive block 24a of the other insulating circuit board 20C facing the one conductive block 24a in the X direction are continuous. That is, it can be said that the N terminal 60 of the semiconductor device 1D has a shape in which three N terminals 60 are continuous or three are integrated as described in the third embodiment.

[0114] As shown in FIG. 14, it is possible to realize a semiconductor device 1D having functions of three of the above-described semiconductor devices 1C responsible for three-phase outputs of U-phase, V-phase, and W-phase, that is, functional units of each phase of U-phase, V-phase, and W-phase. In the semiconductor device 1D, it is possible to provide P terminals 50 and N terminals 60 having the above-described continuous shape between functional units of different phases.

[0115] Note that a semiconductor device capable of three-phase outputs of U-phase, V-phase, and W-phase can also be realized by providing three independent P terminals 50 and three independent N terminals 60 without adopting the above-described continuous shape.

[0116] Here, an example in which conductive plates 22-24 of each phase of U-phase, V-phase, and W-phase are provided on three insulating substrates 21 is shown, but it is also possible to provide all of the conductive plates 22-24 of each phase of U-phase, V-phase, and W-phase on one insulating substrate.

[0117] FIG. 15 is a diagram for explaining another example of the semiconductor device according to the fourth embodiment. FIG. 15 schematically shows a plan view of a main part of an example of the semiconductor device. In the semiconductor device 1Da shown in FIG. 15, an external terminal portion 51 of a P terminal 50 having a continuous shape and an external terminal portion 61 of an N terminal 60 having a continuous shape are drawn out from an opening 12b and an opening 12d provided in side wall portions 12 on the side of a side 11b and a side 11d perpendicular to a side 11c of a case 10. The semiconductor device 1Da is different from the semiconductor device 1D (FIG. 14) in that it has such a configuration.

[0118] As described above, the positions where the P terminal 50 and the N terminal 60 are drawn out from the case 10 can be appropriately changed based on the use of the semiconductor device 1Da (such as the installation location in the equipment and the arrangement relationship with other components such as capacitors).

[0119] Note that the relationship between the functional parts of each phase of the U phase, V phase, and W phase of the semiconductor device 1D or the semiconductor device 1Da and the elements described in claims 1 and 10 of the claims is the same as the relationship described for the semiconductor device 1C.

[0120] Also, it can be said that the relationship between the functional parts of different phases is as follows. The OUT terminal 40 of one functional unit (Claim 13) corresponds to the "second main current wiring", the external terminal portion 41 corresponds to the "second external terminal portion", the extension portion 42 corresponds to the "second extension portion", and the connection portion 42d corresponds to the "third connection portion". For example, the P terminal 50 corresponds to the "first main current wiring", the external terminal portion 51 corresponds to the "first external terminal portion", the extension portion 52 corresponds to the "first extension portion", the connection portions 52ca and 52da correspond to the "first connection portion and the second connection portion", the conductive plate 22 corresponds to the "first conductive plate", the conductive plate 23 corresponds to the "second conductive plate", the group of semiconductor elements 30A in the upper arm corresponds to the "plurality of first semiconductor elements", and the group of semiconductor elements 30B in the lower arm corresponds to the "plurality of second semiconductor elements". When the P terminal 50 is the "first main current wiring", the N terminal 60 becomes the "third main current wiring", the external terminal portion 61 becomes the "third external terminal portion", the extension portion 62 becomes the "third extension portion", the connection portions 62ca and 62da become the "fourth connection portion and the fifth connection portion", and the conductive plate 24 becomes the "third conductive plate".

[0121] Also, the OUT terminal 40 of the other functional unit (Claim 17) corresponds to the "fifth main current wiring", the external terminal portion 41 corresponds to the "fifth external terminal portion", the extension portion 42 corresponds to the "fifth extension portion", and the connection portion 42d corresponds to the "eighth connection portion". For example, the P terminal 50 corresponds to the "fourth main current wiring", the external terminal portion 51 corresponds to the "fourth external terminal portion", the extension portion 52 corresponds to the "fourth extension portion", the connection portions 52ca and 52da correspond to the "sixth connection portion and the seventh connection portion", the conductive plate 22 corresponds to the "fourth conductive plate", the conductive plate 23 corresponds to the "fifth conductive plate", the group of semiconductor elements 30A in the upper arm corresponds to the "plurality of third semiconductor elements", and the group of semiconductor elements 30B in the lower arm corresponds to the "plurality of fourth semiconductor elements". When the P terminal 50 is the "fourth main current wiring", the N terminal 60 becomes the "sixth main current wiring", the external terminal portion 61 becomes the "sixth external terminal portion", the extension portion 62 becomes the "sixth extension portion", the connection portions 62ca and 62da become the "ninth connection portion and the tenth connection portion", and the conductive plate 24 becomes the "sixth conductive plate". The wire 33 is the "third wire", the wire 36 is the "fourth wire", the opening 12c, or the openings 12b and 12d are the "seventh opening", and the opening 12a is the "eighth opening".

[0122] Still, in the semiconductor device 1D or the semiconductor device 1Da described in the fourth embodiment, the external terminal portions 51 of the P terminal 50 and the external terminal portions 61 of the N terminal 60 disposed outside the case 10 may be arranged to overlap with each other via an insulating member in a plan view. In the semiconductor device 1D or the semiconductor device 1Da, the P terminal 50 and the N terminal 60 can also be changed to a shape such that the external terminal portions 51 and the external terminal portions 61 thereof overlap with each other via an insulating member in a plan view.

[0123] [Fifth Embodiment] FIGS. 16 to 18 are diagrams for explaining an example of a semiconductor device according to the fifth embodiment. FIG. 16 schematically shows a plan view of a main part of an example of the semiconductor device. FIG. 17 schematically shows a plan view of a main part of an example of a case and an insulating circuit board of the semiconductor device. FIG. 18(A) schematically shows a plan view of a main part of an example of an OUT terminal of the semiconductor device. FIG. 18(B) schematically shows a plan view of a main part of an example of a P terminal of the semiconductor device. FIG. 18(C) schematically shows a plan view of a main part of an example of an N terminal of the semiconductor device.

[0124] The semiconductor device 1E shown in FIG. 16 is an example of a so-called 2-in-1 type semiconductor device having a circuit configuration as shown in FIG. 1 above. The semiconductor device 1E is a form of a modified example of the semiconductor device 1C (FIG. 11) described in the third embodiment above.

[0125] As shown in FIGS. 16 and 17, the insulating circuit board 20E of the semiconductor device 1E includes a conductive plate 22 on which a group of semiconductor elements 30A of the upper arm are arranged, a conductive plate 23 to which wires 33 extending from the group of semiconductor elements 30A of the upper arm are joined and on which a group of semiconductor elements 30B of the lower arm are arranged, and a conductive plate 24 to which wires 36 extending from the group of semiconductor elements 30B of the lower arm are joined. In the semiconductor device 1E, in the Y direction from the conductive plate 24, the conductive plates 24, 23, and 22 are arranged in this order. The conductive plates 22, 23, and 24 are arranged such that, for example, the area of the conductive plate 23 is larger than the area of the conductive plate 22, and the area of the conductive plate 22 is larger than the area of the conductive plate 24. As shown in FIGS. 16 and 17, the insulating circuit board 20E has a configuration in which the conductive block 23a of the conductive plate 23 is arranged between the joint group of the wires 33 extending from the group of semiconductor elements 30A of the upper arm and the group of semiconductor elements 30B of the lower arm. The conductive block 23a is shaped such that the length in the X direction is longer than the length in the Y direction, and its planar size is larger than the sum of the planar sizes of the two conductive blocks 22a and larger than the sum of the planar sizes of the two conductive blocks 24a.

[0126] As shown in FIG. 16, in a plan view, the extending portion 42 of the OUT terminal 40 extends between a branch portion 52c and a branch portion 52d provided on the extending portion 52 of the P terminal 50. In a plan view, the connection portions 52ca and 52da of the branch portions 52c and 52d of the P terminal 50, which are connected to the two conductive blocks 22a, are arranged so as to sandwich the extending portion 42 of the OUT terminal 40.

[0127] As shown in FIGS. 16 and 18(A), the OUT terminal 40 of the semiconductor device 1E is shaped such that the width of the extension portion 42 in the X direction is relatively wider than that of the semiconductor device 1C. As shown in FIGS. 16, 18(B), and 18(C), the P terminal 50 and the N terminal 60 of the semiconductor device 1E are shaped such that the extension portions 52 and 62 avoid the extension portion 42 of the OUT terminal 40 in accordance with the shape of the extension portion 42 of the OUT terminal 40. As shown in FIGS. 16 and 18(C), a notch portion (FIG. 13(C)) along the extension portion 42 of the OUT terminal 40 may not be provided at the opposing portion of the extension portion 62 of the N terminal 60.

[0128] Inside the case 10, in accordance with the example of FIG. 3(B), a sealing resin for sealing the insulating circuit board 20E and the groups of semiconductor elements 30A and 30B mounted thereon may be provided. Incidentally, in FIG. 16, the illustration of the sealing resin is omitted for the sake of convenience.

[0129] Other configurations of the semiconductor device 1E can be the same as those of the semiconductor device 1C described in the third embodiment. With such a configuration of the semiconductor device 1E, the same effects as those described for the semiconductor device 1C can be obtained. Incidentally, the relationship between the semiconductor device 1E and the elements described in claims 1 and 10 of the claims is the same as the relationship described for the semiconductor device 1C.

[0130] Incidentally, in the semiconductor device 1E described in this fifth embodiment, the external terminal portions 51 of the P terminal 50 and the external terminal portions 61 of the N terminal 60 disposed outside the case 10 may be arranged to overlap via an insulating member in a plan view. In the semiconductor device 1E, the P terminal 50 and the N terminal 60 can also be changed to a shape such that the external terminal portions 51 and 61 thereof overlap via an insulating member in a plan view.

[0131] Also, three semiconductor devices 1E as described in this fifth embodiment can be used to form a three-phase voltage source inverter circuit (Fig. 2) for the U-phase, V-phase, and W-phase. Here, an example where the semiconductor device 1E is a 2-in-1 package is shown. However, when forming a three-phase voltage source inverter circuit, the functional parts of each phase of the U-phase, V-phase, and W-phase can be housed in one case to form a 6-in-1 package. When using a 6-in-1 package in this way, according to the example of the semiconductor device 1D (Fig. 14) described in the fourth embodiment above, the functions of three semiconductor devices 1E, that is, the P terminals 50 of the functional parts of each phase of the U-phase, V-phase, and W-phase can be made continuous, and the N terminals 60 of the functional parts of each phase of the U-phase, V-phase, and W-phase can be made continuous. The external terminal part 51 of the P terminal 50 having a continuous shape and the external terminal part 61 of the N terminal 60 having a continuous shape can be drawn out from the side 11c of the case 10. In addition, according to the example of the semiconductor device 1Da (Fig. 15) described in the fourth embodiment above, they can also be drawn out from the sides 11b and 11d perpendicular to the side 11c.

[0132] [Sixth Embodiment] Figs. 19 to 22 are diagrams for explaining an example of a semiconductor device according to the sixth embodiment. Fig. 19 schematically shows a plan view of a main part of an example of the semiconductor device. Fig. 20 schematically shows a plan view of a main part of an example of the case and the insulating circuit board, etc. of the semiconductor device. Fig. 21(A) schematically shows a plan view of a main part of an example of the OUT terminal of the semiconductor device. Fig. 21(B) schematically shows a plan view of a main part of an example of the P terminal of the semiconductor device. Fig. 21(C) schematically shows a plan view of a main part of an example of the N terminal of the semiconductor device. Fig. 22 schematically shows a plan view of a main part of an example of the insulating member arrangement.

[0133] The semiconductor device 1F shown in Fig. 19 is an example of a so-called 2-in-1 type semiconductor device having the circuit configuration as shown in Fig. 1 above. In the semiconductor device 1F, a P terminal 50 and an N terminal 60 that are partially overlapped and stacked via an insulating member 70 are arranged in the order of the P terminal 50, the insulating member 70, and the N terminal 60 in a direction away from the insulating circuit board 20F. That is, in the semiconductor device 1F, among the P terminal 50 and the N terminal 60, the P terminal 50 is arranged closer to the insulating circuit board 20F side.

[0134] As shown in Figs. 19 and 20, the insulating circuit board 20F of the semiconductor device 1F includes a conductive plate 22 on which a group of upper arm semiconductor elements 30A are arranged, a conductive plate 23 to which wires 33 extending from the group of upper arm semiconductor elements 30A are joined and on which a group of lower arm semiconductor elements 30B are arranged, and a conductive plate 24 to which wires 36 extending from the group of lower arm semiconductor elements 30B are joined. In the semiconductor device 1F, in the Y direction from the conductive plate 22, the conductive plates 22, 23, and 24 are arranged in this order. The conductive plate 22, the conductive plate 23, and the conductive plate 24 are arranged such that, for example, the area of the conductive plate 23 is larger than the area of the conductive plate 22, and the area of the conductive plate 22 is larger than the area of the conductive plate 24. As shown in Figs. 19 and 20, the insulating circuit board 20F has a configuration in which a conductive block 23a of the conductive plate 23 is arranged between a group of joints of wires 33 extending from the group of upper arm semiconductor elements 30A and the group of lower arm semiconductor elements 30B. The conductive block 23a has a shape such that the length in the X direction is longer than the length in the Y direction, and its planar size is larger than the sum of the planar sizes of the two conductive blocks 22a and also larger than the sum of the planar sizes of the two conductive blocks 24a.

[0135] As shown in Figs. 19 and 21(A), the OUT terminal 40 of the semiconductor device 1F has a shape such that the width in the X direction of the extending portion 42 is relatively wide. As shown in Figs. 19, 21(B), and 21(C), the P terminal 50 and the N terminal 60 of the semiconductor device 1F have shapes such that the extending portions 52 and 62 are shaped to avoid the extending portion 42 of the OUT terminal 40.

[0136] The OUT terminal 40 penetrates through the opening 12a on the side 11a of the case 10, and an external terminal portion 41 and an extension portion 42 are provided outside and inside the case 10 respectively. The extension portion 42 is connected to the conductive block 23a at the connection portion 42d. The OUT terminal 40 is electrically connected to the conductive plate 23 via the connection portion 42d and the conductive block 23a. The P terminal 50 penetrates through the opening 12c on the side 11c of the case 10, and an external terminal portion 51 and an extension portion 52 are provided outside and inside the case 10 respectively. A branch portion 52c and a branch portion 52d branched from the trunk portion 52b of the extension portion 52 are connected to two conductive blocks 22a at the connection portions 52ca and 52da respectively. The P terminal 50 is electrically connected to the conductive plate 22 via the connection portions 52ca and 52da and the two conductive blocks 22a. The N terminal 60 penetrates through the opening 12c on the side 11c of the case 10, and an external terminal portion 61 and an extension portion 62 are provided outside and inside the case 10 respectively. A branch portion 62c and a branch portion 62d branched from the trunk portion 62b of the extension portion 62 are connected to two conductive blocks 24a at the connection portions 62ca and 62da respectively. The N terminal 60 is electrically connected to the conductive plate 24 via the connection portions 62ca and 62da and the two conductive blocks 24a.

[0137] The P terminal 50 and the N terminal 60 are stacked via an insulating member 70 such as an insulating sheet at least inside the case 10. In the semiconductor device 1F, they are arranged in the order of the P terminal 50, the insulating member 70, and the N terminal 60 in a direction away from the insulating circuit board 20F. The P terminal 50 and the N terminal 60 are shaped such that they partially overlap in a plan view. Below the connection portions 62ca and 62da of the N terminal 60, the P terminal 50 is not provided. Openings 60a and 70a (notches) are provided in the N terminal 60 and the insulating member 70, respectively. The connection portions 52ca and 52da of the P terminal 50 are exposed from the opening 60a of the N terminal 60 and the opening 70a of the insulating member 70. Below the opening 60a of the N terminal 60 and the opening 70a of the insulating member 70, the connection portions 52ca and 52da of the P terminal 50 are provided. The connection portions 52ca and 52da of the P terminal 50 are joined to the two conductive blocks 22a by laser welding or the like through the opening 60a of the N terminal 60 and the opening 70a of the insulating member 70.

[0138] As shown in FIG. 19, in a plan view, the extension portion 42 of the OUT terminal 40 extends between the branch portions 52c and 52d provided in the extension portion 52 of the P terminal 50 and between the branch portions 62c and 62d provided in the extension portion 62 of the N terminal 60. In a plan view, the connection portions 52ca and 52da of the branch portions 52c and 52d of the P terminal 50, which are connected to the two conductive blocks 22a, are arranged so as to sandwich the extension portion 42 of the OUT terminal 40. In a plan view, the connection portions 62ca and 62da of the branch portions 62c and 62d of the N terminal 60, which are connected to the two conductive blocks 24a, are arranged so as to sandwich the extension portion 42 of the OUT terminal 40. In a plan view, the group of semiconductor elements 30A of the upper arm is arranged between the branch portions 52c and 52d of the P terminal 50. In a plan view, the group of semiconductor elements 30B of the lower arm is arranged between the branch portions 62c and 62d of the N terminal 60.

[0139] In the semiconductor device 1F, in the Y direction, these elements are arranged in the order of the external terminal portion 51 of the P terminal 50, the conductive plate 22 to which the P terminal 50 is connected, the conductive plate 24 to which the N terminal 60 is connected, and the external terminal portion 41 of the OUT terminal 40.

[0140] Inside the case 10, in accordance with the example of FIG. 3(B) above, a sealing resin for sealing the insulating circuit board 20F and the groups of semiconductor elements 30A and 30B mounted thereon may be provided. In FIG. 19, for the sake of convenience, the illustration of the sealing resin is omitted.

[0141] In the semiconductor device 1F, among the P terminal 50 and the N terminal 60 laminated via the insulating member 70, the P terminal 50 is arranged closer to the insulating circuit board 20F. The P terminal 50 and the N terminal 60 can be arranged in the vertical direction (the direction perpendicular to the X direction and the Y direction) of the insulating circuit board 20F in the reverse manner to that of the semiconductor device 1C (FIG. 11) and the semiconductor device 1E (FIG. 16) etc., like this semiconductor device 1F.

[0142] However, in the semiconductor device 1F, the relatively high-potential P terminal 50 located closer to the insulating circuit board 20F faces the gate wire 34 connected to the group of semiconductor elements 30A in the upper arm and the relatively low-potential sense emitter wire 35. Further, the relatively high-potential P terminal 50 faces the SP portion 90 (the external SP terminal 19 and the SP wire 39 described in the first embodiment above) connected to the conductive plate 22. Also, in the semiconductor device 1F, the relatively high-potential OUT terminal 40 faces the gate wire 37 connected to the group of semiconductor elements 30B in the lower arm and the relatively low-potential sense emitter wire 38.

[0143] Therefore, as shown in FIG. 22, an insulating member 71 is disposed in a region overlapping the gate wire 34, the sense emitter wire 35, and the SP section 90 in a plan view. For example, the insulating member 71 is disposed on a surface of the P terminal 50 facing the gate wire 34, the sense emitter wire 35, and the SP section 90. By disposing such an insulating member 71, the influence of the potential of the P terminal 50 on the potentials of the gate wire 34 and the sense emitter wire 35 can be suppressed. Also, as shown in FIG. 22, an insulating member 72 is disposed in a region overlapping the gate wire 37 and the sense emitter wire 38 in a plan view. For example, the insulating member 72 is disposed on a surface of the OUT terminal 40 facing the gate wire 37 and the sense emitter wire 38. By disposing such an insulating member 72, the influence of the potential of the OUT terminal 40 on the potentials of the gate wire 37 and the sense emitter wire 38 can be suppressed.

[0144] Incidentally, for example, in the semiconductor device 1C (FIG. 11) and the semiconductor device 1E (FIG. 16), it is also possible to dispose the P terminal 50 closer to the insulating circuit board 20C or the insulating circuit board 20E among the P terminal 50 and the N terminal 60. Also in this case, in order to suppress the influence of the potential of the P terminal 50, it is desirable to dispose an insulating member between the P terminal 50 and the insulating circuit board 20C or the insulating circuit board 20E according to the example of the semiconductor device 1F. However, when the P terminal 50 is disposed closer to the insulating circuit board 20C or the insulating circuit board 20E in this way, the P terminal 50 faces the gate wire 37 and the sense emitter wire 38 connected to the lower arm semiconductor element 30B group, and the potential difference from the P terminal 50 increases. Therefore, from the viewpoint of suppressing the potential difference from the P terminal 50, it is desirable to adopt a layout such as that of the semiconductor device 1F, that is, a layout in which the P terminal 50 faces the gate wire 34, the sense emitter wire 35, and the SP section 90 connected to the upper arm semiconductor element 30A group.

[0145] Incidentally, the relationship between the semiconductor device 1F and the element described in claim 1 of the claims is as follows. The OUT terminal 40 corresponds to the "second main current wiring", the extension part 42 corresponds to the "second extension part", and the conductive plate 23 corresponds to the "conductive plate". The P terminal 50 or the N terminal 60 corresponds to the "first main current wiring".

[0146] Here, when the P terminal 50 is the "first main current wiring", the trunk part 52b corresponds to the "trunk part", the branch parts 52c and 52d correspond to the "first branch part and the second branch part", the extension part 52 corresponds to the "first extension part", the group of semiconductor elements 30A in the upper arm corresponds to the "plurality of semiconductor elements", the emitter electrode 32 of the group of semiconductor elements 30A in the upper arm corresponds to the "first electrode", and the collector electrode 31 of the group of semiconductor elements 30A in the upper arm corresponds to the "second electrode".

[0147] Also, when the N terminal 60 is the "first main current wiring", the trunk part 62b corresponds to the "trunk part", the branch parts 62c and 62d correspond to the "first branch part and the second branch part", the extension part 62 corresponds to the "first extension part", the group of semiconductor elements 30B in the lower arm corresponds to the "plurality of semiconductor elements", the collector electrode 31 of the group of semiconductor elements 30B in the lower arm corresponds to the "first electrode", and the emitter electrode 32 of the group of semiconductor elements 30B in the lower arm corresponds to the "second electrode". Thus, when the N terminal 60 is the "first main current wiring", the P terminal 50 becomes the "third main current wiring" (Claim 7), the insulating member 70 becomes the "insulating member" (Claim 7), and the opening 60a becomes the "second opening" (Claim 8).

[0148] Also, the relationship between the semiconductor device 1F and the element described in Claim 10 of the claims is as follows. The OUT terminal 40 corresponds to the "second main current wiring", the external terminal part 41 corresponds to the "second external terminal part", the extension part 42 corresponds to the "second extension part", and the connection part 42d corresponds to the "third connection part". The P terminal 50 or the N terminal 60 corresponds to the "first main current wiring".

[0149] Here, when the P terminal 50 is the "first main current wiring", the external terminal portion 51 corresponds to the "first external terminal portion", the extension portion 52 corresponds to the "first extension portion", the connection portions 52ca and 52da correspond to the "first connection portion and the second connection portion", the conductive plate 22 corresponds to the "first conductive plate", the conductive plate 23 corresponds to the "second conductive plate", the group of semiconductor elements 30A in the upper arm corresponds to the "plurality of first semiconductor elements", and the group of semiconductor elements 30B in the lower arm corresponds to the "plurality of second semiconductor elements".

[0150] Also, when the N terminal 60 is the "first main current wiring", the external terminal portion 61 corresponds to the "first external terminal portion", the extension portion 62 corresponds to the "first extension portion", the connection portions 62ca and 62da correspond to the "first connection portion and the second connection portion", the conductive plate 24 corresponds to the "first conductive plate", the conductive plate 23 corresponds to the "second conductive plate", the group of semiconductor elements 30B in the lower arm corresponds to the "plurality of first semiconductor elements", and the group of semiconductor elements 30A in the upper arm corresponds to the "plurality of second semiconductor elements".

[0151] When the N terminal 60 is the "first main current wiring" in this way, the P terminal 50 becomes the "third main current wiring" (Claim 23), the external terminal portion 51 becomes the "third external terminal portion", the extension portion 52 becomes the "third extension portion", the connection portion 52ca and / or the connection portion 52da becomes the "fourth connection portion", the conductive plate 22 becomes the "third conductive plate", the wire 36 becomes the "first wire", the wire 33 becomes the "second wire", the opening 12c becomes the "first opening", and the opening 12a becomes the "second opening" (Claim 23). The insulating member 70 becomes the "first insulating member", the insulating member 71 becomes the "second insulating member", and the insulating member 72 becomes the "third insulating member" (Claim 24), the opening 60a becomes the "third opening", the opening 70a becomes the "fourth opening", and the conductive block 22a becomes the "conductive block" (Claim 25). The gate wire 37 becomes the "first gate wire", the sense emitter wire 38 becomes the "first sense emitter wire", the gate wire 34 becomes the "second gate wire", the sense emitter wire 35 becomes the "second sense emitter wire", the external gate terminal 17 becomes the "first external gate terminal", the external sense emitter terminal 18 becomes the "first external sense emitter terminal", the external gate terminal 14 becomes the "second external gate terminal", and the external sense emitter terminal 15 becomes the "second external sense emitter terminal" (Claim 26).

[0152] In addition, in the semiconductor device 1F described in this sixth embodiment, the external terminal portions 51 of the P terminal 50 and the external terminal portions 61 of the N terminal 60 arranged outside the case 10 may be arranged so as to overlap with each other via an insulating member in a plan view. In the semiconductor device 1F, the P terminal 50 and the N terminal 60 can also be changed to a shape such that the external terminal portions 51 and the external terminal portions 61 thereof overlap with each other via an insulating member in a plan view.

[0153] Also, three semiconductor devices 1F as described in this sixth embodiment can be used to form a three-phase voltage type inverter circuit (Fig. 2) for the U-phase, V-phase, and W-phase. Here, an example where the semiconductor device 1F is a 2-in-1 package is shown. However, when forming a three-phase voltage type inverter circuit, the functional parts of each phase of the U-phase, V-phase, and W-phase can be housed in one case to form a 6-in-1 package. When using such a 6-in-1 package, according to the example of the semiconductor device 1D (Fig. 14) described in the fourth embodiment above, the functions of three semiconductor devices 1F, that is, the P terminals 50 of the functional parts of each phase of the U-phase, V-phase, and W-phase can be made into a continuous shape, and the N terminals 60 of the functional parts of each phase of the U-phase, V-phase, and W-phase can be made into a continuous shape. The external terminal part 51 of the P terminal 50 having a continuous shape and the external terminal part 61 of the N terminal 60 having a continuous shape can be drawn out from the side 11c of the case 10. In addition, according to the example of the semiconductor device 1Da (Fig. 15) described in the fourth embodiment above, they can also be drawn out from the sides 11b and 11d perpendicular to the side 11c.

[0154] [Seventh Embodiment] Figs. 23 to 26 are diagrams for explaining an example of a semiconductor device according to the seventh embodiment. Fig. 23 schematically shows a plan view of a main part of an example of the semiconductor device. Fig. 24 schematically shows a plan view of a main part of an example of the case and the insulating circuit board, etc. of the semiconductor device. Fig. 25(A) schematically shows a plan view of a main part of an example of the OUT terminal of the semiconductor device. Fig. 25(B) schematically shows a plan view of a main part of an example of the P terminal of the semiconductor device. Fig. 25(C) schematically shows a plan view of a main part of an example of the N terminal of the semiconductor device. Fig. 26 schematically shows a plan view of a main part of an example of the insulating member arrangement.

[0155] The semiconductor device 1G shown in FIG. 23 is an example of a so-called 2-in-1 type semiconductor device having the circuit configuration as shown in FIG. 1 above. The semiconductor device 1G is a form in which, with respect to the semiconductor device 1A (FIG. 3) described in the first embodiment above, the vertical arrangement of the P terminal 50 and the N terminal 60 (the arrangement in the direction away from the insulating circuit board 20G) is reversed, that is, when the P terminal 50 is arranged closer to the insulating circuit board 20G.

[0156] As shown in FIGS. 23 and 24, the insulating circuit board 20G of the semiconductor device 1G includes a conductive plate 22 on which the group of upper-arm semiconductor elements 30A is arranged, a conductive plate 23 to which the wires 33 extending from the group of upper-arm semiconductor elements 30A are joined and on which the group of lower-arm semiconductor elements 30B is arranged, and a conductive plate 24 to which the wires 36 extending from the group of lower-arm semiconductor elements 30B are joined. In the semiconductor device 1G, the conductive plates 22, 23, and 24 are arranged in this order in the Y direction from the conductive plate 22. The conductive plates 22, 23, and 24 are arranged such that, for example, the area of the conductive plate 23 is larger than the area of the conductive plate 22, and the area of the conductive plate 22 is larger than the area of the conductive plate 24. The two conductive blocks 23a of the conductive plate 23 are shaped such that the total of their planar sizes is larger than the planar size of the conductive block 22a of the conductive plate 22 and also larger than the planar size of the conductive block 24a of the conductive plate 24.

[0157] The OUT terminal 40 of the semiconductor device 1G has a shape as shown in FIGS. 23 and 25(A), penetrates through the opening 12a on the side of the side 11a of the case 10, and external terminal portions 41 and extension portions 42 are provided outside and inside the case 10, respectively. Branch portions 42b and 42c branched from the trunk portion 42a of the extension portion 42 are connected to two conductive blocks 23a by connection portions 42ba and 42ca, respectively. The OUT terminal 40 is electrically connected to the conductive plate 23 via the connection portions 42ba and 42ca and the two conductive blocks 23a. The P terminal 50 has a shape as shown in FIGS. 23 and 25(B), penetrates through the opening 12c on the side of the side 11c of the case 10, and external terminal portions 51 and extension portions 52 are provided outside and inside the case 10, respectively. The extension portion 52 is connected to the conductive block 22a by a connection portion 52a. The P terminal 50 is electrically connected to the conductive plate 22 via the connection portion 52a and the conductive block 22a. The N terminal 60 has a shape as shown in FIGS. 23 and 25(C), penetrates through the opening 12c on the side of the side 11c of the case 10, and external terminal portions 61 and extension portions 62 are provided outside and inside the case 10, respectively. The extension portion 62 is connected to the conductive block 24a by a connection portion 62a. The N terminal 60 is electrically connected to the conductive plate 24 via the connection portion 62a and the conductive block 24a.

[0158] The P terminal 50 and the N terminal 60 are laminated via an insulating member 70 such as an insulating sheet, at least inside the case 10. In the semiconductor device 1G, they are arranged in the order of the P terminal 50, the insulating member 70, and the N terminal 60 in a direction away from the insulating circuit board 20G. The P terminal 50 and the N terminal 60 are shaped such that they partially overlap in plan view. Under the connection portion 62a of the N terminal 60, the P terminal 50 is not provided. Openings 60a and 70a are provided in the N terminal 60 and the insulating member 70, respectively. The connection portion 52a of the P terminal 50 is exposed from the opening 60a of the N terminal 60 and the opening 70a of the insulating member 70. Under the opening 60a of the N terminal 60 and the opening 70a of the insulating member 70, the connection portion 52a of the P terminal 50 is provided. The connection portion 52a of the P terminal 50 is joined to the conductive block 22a by laser welding or the like through the opening 60a of the N terminal 60 and the opening 70a of the insulating member 70.

[0159] As shown in FIG. 23, in a plan view, the extension portion 52 of the P terminal 50 and the extension portion 62 of the N terminal 60 extend to between the branch portion 42b and the branch portion 42c provided on the extension portion 42 of the OUT terminal 40. In a plan view, the connection portions 42ba and 42ca of the branch portion 42b and the branch portion 42c of the OUT terminal 40, which are connected to the two conductive blocks 23a, are arranged so as to sandwich the extension portion 52 of the P terminal 50 and the extension portion 62 of the N terminal 60. In a plan view, a group of semiconductor elements 30B of the lower arm is arranged between the branch portion 42b and the branch portion 42c of the OUT terminal 40.

[0160] In the semiconductor device 1G, in the Y direction, these elements are arranged in the order of the external terminal portion 51 of the P terminal 50, the conductive plate 22 to which the P terminal 50 is connected, the conductive plate 24 to which the N terminal 60 is connected, and the external terminal portion 41 of the OUT terminal 40.

[0161] Inside the case 10, according to the example of FIG. 3(B) above, a sealing resin for sealing the insulating circuit board 20G and the groups of semiconductor elements 30A and 30B mounted thereon may be provided. Incidentally, in FIG. 23, the illustration of the sealing resin is omitted for the sake of convenience.

[0162] In the semiconductor device 1G, among the P terminal 50 and the N terminal 60 laminated via the insulating member 70, the P terminal 50 is arranged closer to the insulating circuit board 20G. The P terminal 50 and the N terminal 60 can be arranged in the vertical direction (a direction perpendicular to the X direction and the Y direction) of the insulating circuit board 20G in the reverse order to that of the semiconductor device 1A (FIG. 3) etc., like this semiconductor device 1G.

[0163] In the semiconductor device 1G, a relatively high-potential P terminal 50 located on the side closer to the insulating circuit board 20G faces a gate wire 34 connected to the semiconductor element 30A group of the upper arm and a relatively low-potential sense emitter wire 35. Further, in the semiconductor device 1G, the P terminal 50 faces an SP portion 90 (the external SP terminal 19 and the SP wire 39 described in the first embodiment) connected to the conductive plate 22. Also, in the semiconductor device 1G, a relatively high-potential OUT terminal 40 faces a gate wire 37 connected to the semiconductor element 30B group of the lower arm and a relatively low-potential sense emitter wire 38.

[0164] Therefore, as shown in FIG. 26, an insulating member 73 is disposed in a region overlapping the gate wire 34, the sense emitter wire 35, and the SP portion 90 in a plan view. For example, the insulating member 73 is disposed on the surface of the P terminal 50 on the side facing the gate wire 34, the sense emitter wire 35, and the SP portion 90. By disposing such an insulating member 73, the influence of the potential of the P terminal 50 on the potentials of the gate wire 34 and the sense emitter wire 35 can be suppressed. Also, as shown in FIG. 26, an insulating member 74 is disposed in a region overlapping the gate wire 37 and the sense emitter wire 38 in a plan view. For example, the insulating member 74 is disposed on the surface of the OUT terminal 40 on the side facing the gate wire 37 and the sense emitter wire 38. By disposing such an insulating member 74, the influence of the potential of the OUT terminal 40 on the potentials of the gate wire 37 and the sense emitter wire 38 can be suppressed.

[0165] FIG. 26 shows an example in which two insulating members 74 are provided, but if the shape does not overlap with the conductive block 24a or the like in a plan view, a shape in which the two insulating members 74 are connected, that is, one insulating member 74 can also be provided.

[0166] Incidentally, the relationship between the semiconductor device 1G and the element described in claim 1 of the claims is as follows. The OUT terminal 40 corresponds to the "first main current wiring", the trunk portion 42a corresponds to the "trunk portion", the branch portions 42b and 42c correspond to the "first branch portion and the second branch portion", and the extension portion 42 corresponds to the "first extension portion", respectively. The P terminal 50 or the N terminal 60 corresponds to the "second main current wiring".

[0167] Here, when the P terminal 50 is the "second main current wiring", the extension portion 52 corresponds to the "second extension portion", the conductive plate 22 corresponds to the "conductive plate", the group of semiconductor elements 30A on the upper arm corresponds to the "plurality of semiconductor elements", the collector electrode 31 of the group of semiconductor elements 30A on the upper arm electrically connected to the conductive plate 22 corresponds to the "first electrode", and the emitter electrode 32 of the group of semiconductor elements 30A on the upper arm corresponds to the "second electrode". Thus, when the P terminal 50 is the "second main current wiring", the N terminal 60 becomes the "third main current wiring" (Claim 4).

[0168] Also, when the N terminal 60 is the "second main current wiring", the extension portion 62 corresponds to the "second extension portion", the conductive plate 24 corresponds to the "conductive plate", the group of semiconductor elements 30B on the lower arm corresponds to the "plurality of semiconductor elements", the emitter electrode 32 of the group of semiconductor elements 30B on the lower arm electrically connected to the conductive plate 24 corresponds to the "first electrode", and the collector electrode 31 of the group of semiconductor elements 30B on the lower arm corresponds to the "second electrode". Thus, when the N terminal 60 is the "second main current wiring", the P terminal 50 becomes the "third main current wiring" (Claim 4), the insulating member 70 becomes the "insulating member" (Claim 4), and the opening 60a becomes the "first opening" (Claim 5).

[0169] Also, the above semiconductor device 1 G The relationship with the element described in Claim 10 of the claims is as follows. The OUT terminal 40 corresponds to the "first main current wiring", the external terminal portion 41 corresponds to the "first external terminal portion", the extension portion 42 corresponds to the "first extension portion", and the connection portions 42ba and 42ca correspond to the "first connection portion and the second connection portion", respectively. The P terminal 50 or the N terminal 60 corresponds to the "second main current wiring".

[0170] Here, when the P terminal 50 is the "second main current wiring", the external terminal portion 51 corresponds to the "second external terminal portion", the extending portion 52 corresponds to the "second extending portion", the connecting portion 52a corresponds to the "third connecting portion", the conductive plate 23 corresponds to the "first conductive plate", the conductive plate 22 corresponds to the "second conductive plate", the group of semiconductor elements 30B in the lower arm corresponds to the "plurality of first semiconductor elements", and the group of semiconductor elements 30A in the upper arm corresponds to the "plurality of second semiconductor elements".

[0171] Also, when the N terminal 60 is the "second main current wiring", the external terminal portion 61 corresponds to the "second external terminal portion", the extending portion 62 corresponds to the "second extending portion", the connecting portion 62a corresponds to the "third connecting portion", the conductive plate 23 corresponds to the "first conductive plate", the conductive plate 24 corresponds to the "second conductive plate", the group of semiconductor elements 30A in the upper arm corresponds to the "plurality of first semiconductor elements", and the group of semiconductor elements 30B in the lower arm corresponds to the "plurality of second semiconductor elements".

[0172] In addition, in the semiconductor device 1G described in this seventh embodiment, the external terminal portions 51 of the P terminal 50 and the external terminal portions 61 of the N terminal 60 disposed outside the case 10 may be arranged to overlap with each other via an insulating member in a plan view. In the semiconductor device 1G, the P terminal 50 and the N terminal 60 can also be changed to a shape such that their external terminal portions 51 and 61 overlap with each other via an insulating member in a plan view.

[0173] Moreover, three semiconductor devices 1G as described in this seventh embodiment can be used to form a three-phase voltage source inverter circuit (Figure 2) of U-phase, V-phase, and W-phase. Here, an example of making the semiconductor device 1G a 2in1 package is shown, but when forming a three-phase voltage source inverter circuit, the functional portions of each phase of U-phase, V-phase, and W-phase can be housed in one case to form a 6in1 package.

[0174] [Eighth Embodiment] FIG. 27 is a diagram for explaining an arrangement example of main current wirings of a semiconductor device according to an eighth embodiment. FIG. 27(A) schematically shows a first example of a main part cross-sectional view of a portion passing through P and N terminals of the semiconductor device, and FIG. 27(B) schematically shows a second example of a main part cross-sectional view of a portion passing through P and N terminals of the semiconductor device. FIG. 27(C) schematically shows a first example of a main part cross-sectional view of a portion passing through an OUT terminal of the semiconductor device, and FIG. 27(D) schematically shows a second example of a main part cross-sectional view of a portion passing through an OUT terminal of the semiconductor device.

[0175] The semiconductor device 1Ha shown in FIG. 27(A) has a configuration in which a P terminal 50 and an N terminal 60 are drawn out from an opening 13a provided in a lid portion 13 that covers the inside of a case 10 surrounded by a side wall portion 12. The P terminal 50 has an external terminal portion 51 disposed outside the case 10 and an extension portion 52 disposed inside the case 10, and is joined to a conductive block 22a on a conductive plate 22 provided on an insulating substrate 21 of an insulating circuit board 20H. The N terminal 60 has an external terminal portion 61 disposed outside the case 10 and an extension portion 62 disposed inside the case 10, and is joined to a conductive block 24a on a conductive plate 24 provided on the insulating substrate 21 of the insulating circuit board 20H. An insulating member 70 is disposed between the P terminal 50 and the N terminal 60. The P terminal 50 and the N terminal 60 are routed inside the case 10 in a state of facing each other with the insulating member 70 interposed therebetween, and reduction of inductance due to closing of the loop is achieved.

[0176] The semiconductor device 1Hb shown in Fig. 27(B) is obtained by reversing the positions of the P terminal 50 and the N terminal 60 with respect to the semiconductor device 1Ha shown in Fig. 27(A). The P terminal 50 and the N terminal 60 are drawn out from an opening 13a provided in a lid portion 13 that covers the inside of the case 10 surrounded by the side wall portion 12. The P terminal 50 has an external terminal portion 51 disposed outside the case 10 and an extension portion 52 disposed inside the case 10, and is joined to a conductive block 22a on a conductive plate 22 provided on an insulating substrate 21 of the insulating circuit board 20H. The N terminal 60 has an external terminal portion 61 disposed outside the case 10 and an extension portion 62 disposed inside the case 10, and is joined to a conductive block 24a on a conductive plate 24 provided on the insulating substrate 21 of the insulating circuit board 20H. An insulating member 70 is disposed between the P terminal 50 and the N terminal 60. The P terminal 50 and the N terminal 60 are routed in a state of facing each other via the insulating member 70 inside the case 10, and reduction of inductance due to closing the loop is achieved.

[0177] Like the semiconductor device 1Ha and the semiconductor device 1Hb, the P terminal 50 and the N terminal 60 may be configured to be drawn out not only from the side wall portion 12 of the case 10 but also from the lid portion 13 of the case 10. The positions where the P terminal 50 and the N terminal 60 are drawn out from the case 10 can be appropriately changed based on the uses of the semiconductor device 1Ha and the semiconductor device 1Hb (such as the installation location in the equipment and the arrangement relationship with other components such as capacitors).

[0178] In addition, the semiconductor device 1Hc shown in FIG. 27(C) has a configuration in which the OUT terminal 40 is drawn out from the opening 13b provided in the lid portion 13 of the case 10. The OUT terminal 40 has an external terminal portion 41 disposed outside the case 10 and an extension portion 42 disposed inside the case 10, and is joined to a conductive block 23a on a conductive plate 23 provided on the insulating substrate 21 of the insulating circuit board 20H. Similar to the P terminal 50 and the N terminal 60, the OUT terminal 40 may be configured to be drawn out not only from the side wall portion 12 of the case 10 but also from the lid portion 13 of the case 10. The OUT terminal 40 may be routed inside the case 10 based on the drawing position from the lid portion 13 as in the semiconductor device 1Hd shown in FIG. 27(D). The position where the OUT terminal 40 is drawn out from the case 10 can be appropriately changed based on the use of the semiconductor device 1Hc and the semiconductor device 1Hd (such as the installation location in the device and the arrangement relationship with other components such as capacitors).

[0179] Regarding the semiconductor devices 1A, 1B, 1C, 1D, 1Da, 1E, 1F, 1G described in the first to seventh embodiments, a configuration in which the P terminal 50 and the N terminal 60 are drawn out from the lid portion 13 of the case 10 can also be adopted according to the examples of FIGS. 27(A) and 27(B). Also, regarding the semiconductor devices 1A, 1B, 1C, 1D, 1Da, 1E, 1F, 1G described in the first to seventh embodiments, a configuration in which the OUT terminal 40 is drawn out from the lid portion 13 of the case 10 can also be adopted according to the examples of FIGS. 27(C) and 27(D).

[0180] FIG. 28 is a diagram for explaining a first example of a semiconductor device according to the eighth embodiment. FIG. 28 schematically shows a main part of an example of the semiconductor device Plane in the figure. The semiconductor device 1He shown in FIG. 28 is an example of a modification of the semiconductor device 1F (FIG. 19) described in the sixth embodiment, in which, according to the example of FIG. 27(B), the P terminal 50 and the N terminal 60 are routed inside the case 10, and the external terminal portions 51 and 61 are drawn out of the case 10 in a direction away from the insulating circuit board 20F (the direction toward the front of the paper). In FIG. 28, for the sake of convenience, the illustration of the lid portion 13 of the case 10 as shown in FIG. 27(B) is omitted. The P terminal 50 and the N terminal 60 can also be arranged as in this semiconductor device 1He.

[0181] FIG. 29 is a diagram for explaining a second example of a semiconductor device according to the eighth embodiment. FIG. 29(A) schematically shows a main part of an example of the semiconductor device. Plane FIG. 29(B) schematically shows a cross-sectional view taken along line XXIX-XXIX of FIG. 29(A). The semiconductor device 1Hf shown in FIGS. 29(A) and 29(B) is an example of a modification of the semiconductor device 1F (FIG. 19) described in the sixth embodiment, in which linear P terminals 50 and N terminals 60 are arranged on both sides of the OUT terminal 40 in a plan view. The P terminal 50 and the N terminal 60 of the semiconductor device 1Hf are routed inside the case 10 according to the example of FIG. 27(A), and the external terminal portions 51 and 61 are drawn out of the case 10 in a direction away from the insulating circuit board 20F (the direction toward the front of the paper). In FIG. 29(A), for the sake of convenience, the illustration of the lid portion 13 of the case 10 as shown in FIG. 27(A) is omitted. As shown in FIG. 29(A), the linear P terminals 50 and N terminals 60 arranged on both sides of the OUT terminal 40 are shaped such that the extending portions 52 and 62 straddle the OUT terminal 40, as shown in FIG. 29(B), and the external terminal portions 51 and 61 are drawn out from the opening 13a of the lid portion 13 of the case 10. The P terminal 50 and the N terminal 60 can also be arranged as in this semiconductor device 1Hf.

[0182] Also, when linear P terminals 50 and N terminals 60 are arranged on both sides sandwiching the OUT terminal 40 and their extraction positions are appropriately set, it becomes possible to reduce the size of the P terminals 50 and N terminals 60, omit the insulator by avoiding facing the gate wire 34 and the sense emitter wire 35, and the like.

[0183] FIG. 30 is a diagram for explaining a third example of a semiconductor device according to the eighth embodiment. FIG. 30 schematically shows a main part of an example of the semiconductor device. Plane The figure is schematically shown. The semiconductor device 1Hg shown in FIG. 30 is different from the semiconductor device 1Hf (FIG. 29) in that the P terminals 50 and N terminals 60 are arranged so as not to overlap each other in a plan view. By arranging the P terminals 50 and N terminals 60 in such a manner, it becomes possible to avoid routing and reduce the size of the P terminals 50 and N terminals 60 inside the case 10, and avoid facing the gate wire 34 and the sense emitter wire 35. The P terminals 50 and N terminals 60 are shaped to straddle the OUT terminal 40 according to the example of FIG. 29(B) and are drawn out from the opening 13a of the lid portion 13 of the case 10. The P terminals 50 and N terminals 60 can also be arranged like this semiconductor device 1Hg.

[0184] From FIGS. 28 to 30, the configuration in which the P terminals 50 and N terminals 60 are drawn out from the lid portion 13 of the case 10 is shown. Similarly for the OUT terminal 40, it is possible to adopt a configuration in which it is drawn out from the lid portion 13 of the case 10 according to the examples of FIGS. 27(C) and 27(D). When the extension portion 42 of the OUT terminal 40 has the branch portions 42b and 42c and the extension portion 52 of the P terminal 50 and the extension portion 62 of the N terminal 60 are sandwiched therebetween, depending on the position where the external terminal portion 41 is drawn out from the lid portion 13 of the case 10, the OUT terminal 40 can be shaped to straddle the P terminals 50 and N terminals 60 according to the example of FIG. 29(B) and be drawn out from the lid portion 13 of the case 10.

[0185] Also, it is possible to configure a three-phase voltage type inverter circuit (Fig. 2) of U-phase, V-phase, and W-phase by using three semiconductor devices 1He, 1Hf, or 1Hg as described in the eighth embodiment. Here, an example in which the semiconductor devices 1He, 1Hf, or 1Hg are 2-in-1 packages is shown. However, when configuring a three-phase voltage type inverter circuit, the functional parts of each phase of U-phase, V-phase, and W-phase can be housed in one case to form a 6-in-1 package.

[0186] Regarding the semiconductor devices 1A, 1B, 1C, 1D, 1Da, 1E, 1F, 1G described in the first to seventh embodiments above, a configuration can be adopted in which the P terminal 50 and the N terminal 60 are drawn out from the lid portion 13 of the case 10, and also a configuration can be adopted in which the OUT terminal 40 is drawn out from the lid portion 13 of the case 10.

[0187] The above is merely illustrative of the principles of the present invention. Further, numerous modifications and changes are possible for those skilled in the art, and the present invention is not limited to the exact configurations and application examples shown and described above. All corresponding modifications and equivalents are considered to be within the scope of the present invention by the appended claims and their equivalents.

Explanation of Reference Numerals

[0188] 1a, 1b, 1A, 1B, 1C, 1D, 1Da, 1E, 1F, 1G, 1Ha, 1Hb, 1Hc, 1Hd, 1He, 1Hf, 1Hg Semiconductor device 2, 3, 30A, 30B Semiconductor element 2a, 3a IGBT 2b, 3b FWD 4 Load 10 Case 11a, 11b, 11c, 11d, 21a, 21b, 21c, 21d Side 12 Side wall portion 12a, 12b, 12c, 12d, 13a, 13b, 50a, 60a, 70a Opening 13 Lid portion 14, 17 External gate terminal 15, 18 External sense emitter terminal 19 External SP terminal Insulated circuit boards 20A, 20B, 20C, 20E, 20F, 20G, 20H Insulated substrate 21 Conductive plates 22, 23, 23A, 23B, 24, 25 Conductive blocks 22a, 23a, 24a Collector electrode 31 Emitter electrode 32 Wires 33, 36 Gate wires 34, 37 Sense emitter wires 35, 38 SP wire 39 OUT terminal 40 External terminal parts 41, 51, 61 Extensions 42, 52, 62 Trunks 42a, 52b, 62b Branching parts 42b, 42c, 52c, 52d, 62c, 62d Connection parts 42ba, 42ca, 52a, 52ca, 52da, 62a, 62ca, 62da Connection part 42d P terminal 50 N terminal 60 Insulating members 70, 71, 72, 73, 74 SP part 90 Support 100 Sealing resin 110 Anode A Cathode K Collector C Emitter E Gate G Sense emitter terminals E1, E2 Gate terminals G1, G2 SP terminal SP Region Q X, Y directions

Claims

1. A plurality of semiconductor elements having a first electrode on a first main surface and a second electrode on a second main surface opposite to the first main surface; A conductive plate electrically connected to the first electrodes of the plurality of semiconductor elements; A case having one side and a side opposite to the one side, and enclosing the plurality of semiconductor elements and the conductive plate; A first main current wiring disposed inside and outside the case, including a trunk portion extending from one side of the case to the inside of the case, and a first extension portion having a first branch portion and a second branch portion branched from the trunk portion in a plan view and electrically connected to the second electrodes of the plurality of semiconductor elements; A second main current wiring disposed inside and outside the case, having a second extension portion sandwiched between the first branch portion and the second branch portion inside the case, and electrically connected to the conductive plate; A semiconductor device comprising:

2. The second extension portion extends from a side opposite to one side of the case to between the first branch portion and the second branch portion inside the case, The semiconductor device according to claim 1, wherein the plurality of semiconductor elements are disposed between the first branch portion and the second branch portion in a plan view.

3. The semiconductor device according to claim 2, wherein at least one of the plurality of semiconductor elements is disposed between the first branch portion and the second main current wiring and between the second branch portion and the second main current wiring in a plan view.

4. The semiconductor device according to claim 2 or 3, further comprising a third main current wiring disposed opposite to a main surface of the second main current wiring via an insulating member and extending from the outside of the case to the inside of the case.

5. The semiconductor device according to claim 4, wherein the second main current wiring has a first opening, and the third main current wiring is exposed from the first opening.

6. The semiconductor device according to claim 5, wherein the third main current wiring has a lower potential than the second main current wiring.

7. The semiconductor device according to claim 2 or 3, further comprising a third main current wiring that is disposed to face the main surface of the first main current wiring via an insulating member and extends from the outside of the case to the inside of the case.

8. The semiconductor device according to claim 7, wherein the first main current wiring has a second opening, and the third main current wiring is exposed from the second opening.

9. The semiconductor device according to claim 8, wherein the third main current wiring has a lower potential than the first main current wiring.

10. A substrate, A case in which the substrate is disposed, A plurality of first semiconductor elements disposed inside the case, A plurality of second semiconductor elements disposed inside the case, A first conductive plate disposed on the substrate and electrically connected to the plurality of first semiconductor elements, A second conductive plate disposed on the substrate and electrically connected to the plurality of second semiconductor elements, A first external terminal portion disposed outside the case, and a first extension portion, a first connection portion, and a second connection portion disposed inside the case. The first extension portion connects the first external terminal portion to the first connection portion and the second connection portion to each other. The first connection portion and the second connection portion are electrically connected to the first conductive plate, a first main current wiring, A second external terminal portion disposed outside the case, and a second extension portion and a third connection portion disposed inside the case. The second extension portion connects the second external terminal portion to the third connection portion to each other. The third connection portion is electrically connected to the second conductive plate, a second main current wiring, comprising The first connection portion and the second connection portion are disposed so as to sandwich the second extension portion. A semiconductor device in which a power supply voltage is applied to one of the first main current wiring and the second main current wiring, causing an output current to flow through the other.

11. The substrate has a first side, a second side, a third side, and a fourth side in a plan view, the first side and the third side are opposed to each other, and the second side and the fourth side are opposed to each other. The case sandwiches the first side and the third side in a plan view and has a fifth side and a sixth side parallel to the first side and the third side, the fifth side is on the side of the first side, and the sixth side is on the side of the third side. In a first direction parallel to the first side, the first connection portion and the second connection portion are arranged so as to sandwich the second extension portion. The semiconductor device according to claim 10, wherein the second conductive plate and the first conductive plate are arranged side by side in a second direction parallel to the second side and perpendicular to the first direction.

12. In the first direction, the first connection portion and the second connection portion are arranged so as to sandwich the plurality of first semiconductor elements. The semiconductor device according to claim 11.

13. A third conductive plate disposed on the substrate; A third external terminal portion disposed outside the case, and a third extension portion, a fourth connection portion, and a fifth connection portion disposed inside the case. The third extension portion connects the third external terminal portion to the fourth connection portion and the fifth connection portion to each other, and the fourth connection portion and the fifth connection portion are electrically connected to the third conductive plate. A third main current wiring; Comprising The plurality of first semiconductor elements are disposed on the first conductive plate. The plurality of second semiconductor elements are disposed on the second conductive plate. A first wire electrically connecting the plurality of first semiconductor elements and the second conductive plate; A second wire electrically connecting the plurality of second semiconductor elements and the third conductive plate; Further comprising The case includes a first opening where the first external terminal portion is disposed, and a second opening where the second external terminal portion is disposed. The third external terminal portion is disposed in the first opening. In the second direction, they are arranged in the order of the third external terminal portion, the third conductive plate, the first conductive plate, and the second external terminal portion. The high-potential side power supply voltage is input from the first external terminal portion. The low-potential side power supply voltage is input from the third external terminal portion. The semiconductor device according to claim 11, wherein an output current is output from the second external terminal portion.

14. The first main current wiring is disposed on the third main current wiring. The semiconductor device according to claim 13, wherein an insulating member is disposed between the first main current wiring and the third main current wiring.

15. The first main current wiring has a third opening and a fourth opening. The insulating member has a fifth opening and a sixth opening in the third opening and the fourth opening, respectively. The fourth connection portion and the fifth connection portion are exposed from the fifth opening and the sixth opening, respectively. The fourth connection portion and the fifth connection portion are each welded to a conductive block disposed on the third conductive plate, and are electrically connected to the third conductive plate through the conductive block. The semiconductor device according to claim 14.

16. A plurality of first sense emitter wires electrically connected to the emitters of the plurality of first semiconductor elements, A plurality of second sense emitter wires electrically connected to the emitters of the plurality of second semiconductor elements, A plurality of first gate wires electrically connected to the gates of the plurality of first semiconductor elements, A plurality of second gate wires electrically connected to the gates of the plurality of second semiconductor elements, A first external sense emitter terminal electrically connected to each of the plurality of first sense emitter wires, A second external sense emitter terminal electrically connected to each of the plurality of second sense emitter wires; A first external gate terminal electrically connected to each of the plurality of first gate wires; A second external gate terminal electrically connected to each of the plurality of second gate wires; Comprising: The plurality of second sense emitter wires and the plurality of second gate wires are disposed directly below the third extension portion; The semiconductor device according to claim 14, wherein the plurality of first sense emitter wires and the plurality of first gate wires are disposed directly below the second extension portion.

17. A plurality of third semiconductor elements disposed inside the case; A plurality of fourth semiconductor elements disposed inside the case; A fourth conductive plate disposed on the substrate and electrically connected to the plurality of third semiconductor elements; A fifth conductive plate disposed on the substrate and electrically connected to the plurality of fourth semiconductor elements; A sixth conductive plate disposed on the substrate; A fourth external terminal portion disposed outside the case, and a fourth extension portion, a sixth connection portion, and a seventh connection portion disposed inside the case, wherein the fourth extension portion connects the fourth external terminal portion to the sixth connection portion and the seventh connection portion to each other, and the sixth connection portion and the seventh connection portion are electrically connected to the fourth conductive plate, a fourth main current wiring; A fifth external terminal portion disposed outside the case, and a fifth extension portion and an eighth connection portion disposed inside the case, wherein the fifth extension portion connects the fifth external terminal portion to the eighth connection portion to each other, and the eighth connection portion is electrically connected to the fifth conductive plate, a fifth main current wiring; A sixth external terminal portion disposed outside the case, a sixth extension portion, a ninth connection portion, and a tenth connection portion disposed inside the case, wherein the sixth extension portion connects the sixth external terminal portion to the ninth connection portion and the tenth connection portion to each other, and the ninth connection portion and the tenth connection portion are electrically connected to the sixth conductive plate, a sixth main current wiring, comprising, The sixth connection portion and the seventh connection portion are arranged so as to sandwich the fifth extension portion, The plurality of third semiconductor elements are arranged on the fourth conductive plate, The plurality of fourth semiconductor elements are arranged on the fifth conductive plate, A third wire electrically connecting the plurality of third semiconductor elements and the fifth conductive plate, A fourth wire electrically connecting the plurality of fourth semiconductor elements and the sixth conductive plate, further comprising, The case includes a seventh opening where the fourth external terminal portion is disposed, and an eighth opening where the fifth external terminal portion is disposed, and the sixth external terminal portion is disposed in the seventh opening, In the second direction, the sixth external terminal portion, the sixth conductive plate, the fourth conductive plate, and the fifth external terminal portion are arranged in this order, A high-potential side power supply voltage is input from the fourth external terminal portion, A low-potential side power supply voltage is input from the sixth external terminal portion, An output current is output from the fifth external terminal portion, The first extension portion and the fourth extension portion are continuous, The semiconductor device according to claim 13, wherein the third extension portion and the sixth extension portion are continuous.

18. A third conductive plate disposed on the substrate, A third external terminal portion disposed outside the case, a third extension portion and a fourth connection portion disposed inside the case, wherein the third extension portion connects the third external terminal portion to the fourth connection portion to each other, and the fourth connection portion is electrically connected to the third conductive plate, a third main current wiring, comprising, The plurality of first semiconductor elements are arranged on the first conductive plate, The plurality of second semiconductor elements are arranged on the second conductive plate, A first wire for electrically connecting the plurality of first semiconductor elements and the third conductive plate, A second wire for electrically connecting the plurality of second semiconductor elements and the first conductive plate, and further includes The case includes a first opening where the first external terminal portion is arranged and a second opening where the second external terminal portion is arranged, and the third external terminal portion is arranged in the second opening, In the second direction, the third external terminal portion, the third conductive plate, the first conductive plate, and the first external terminal portion are arranged in this order, A high-potential side power supply voltage is input from the second external terminal portion, A low-potential side power supply voltage is input from the third external terminal portion, The output current is output from the first external terminal portion. The semiconductor device according to claim 11.

19. The second main current wiring is arranged on the third main current wiring, An insulating member is arranged between the second main current wiring and the third main current wiring. The semiconductor device according to claim 18.

20. The second main current wiring has a third opening, The insulating member has a fourth opening in the third opening, and the fourth connection portion is exposed from the fourth opening, The fourth connection portion is welded to a conductive block arranged on the third conductive plate and is electrically connected to the third conductive plate through the conductive block. The semiconductor device according to claim 19.

21. A plurality of first sense emitter wires electrically connected to the emitters of each of the plurality of first semiconductor elements, A plurality of second sense emitter wires electrically connected to the emitters of each of the plurality of second semiconductor elements, A plurality of first gate wires electrically connected to the gates of each of the plurality of first semiconductor elements; A plurality of second gate wires electrically connected to the gates of each of the plurality of second semiconductor elements; A first external sense emitter terminal electrically connected to each of the plurality of first sense emitter wires; A second external sense emitter terminal electrically connected to each of the plurality of second sense emitter wires; A first external gate terminal electrically connected to each of the plurality of first gate wires; A second external gate terminal electrically connected to each of the plurality of second gate wires; Comprising; The plurality of first sense emitter wires and the plurality of first gate wires are arranged directly below the third extension portion; The semiconductor device according to claim 19, wherein the plurality of second sense emitter wires and the plurality of second gate wires are arranged directly below the first extension portion.

22. The first conductive plate has a first output conductive pattern in which a part of the plurality of first semiconductor elements are arranged on the upper part and a second output conductive pattern in which the rest of the plurality of first semiconductor elements are arranged on the upper part, which are separated from each other; The first connection portion is electrically connected to the first output conductive pattern; The second connection portion is electrically connected to the second output conductive pattern; The semiconductor device according to claim 19, wherein a part of the second conductive plate, a part of the third conductive plate, the second extension portion, the third extension portion, the third connection portion, and the fourth connection portion are arranged between the first output conductive pattern and the second output conductive pattern.

23. A third conductive plate arranged on the substrate; A third external terminal portion disposed outside the case, and a third extension portion and a fourth connection portion disposed inside the case, wherein the third extension portion connects the third external terminal portion and the fourth connection portion to each other, and the fourth connection portion is electrically connected to the third conductive plate, a third main current wiring, comprising the plurality of first semiconductor elements are disposed on the second conductive plate, the plurality of second semiconductor elements are disposed on the third conductive plate, a first wire electrically connecting the plurality of first semiconductor elements and the first conductive plate, a second wire electrically connecting the plurality of second semiconductor elements and the second conductive plate, further comprising the case includes a first opening where the first external terminal portion is disposed and a second opening where the second external terminal portion is disposed, and the third external terminal portion is disposed in the first opening, in the second direction, the third external terminal portion, the third conductive plate, the first conductive plate, and the second external terminal portion are arranged in this order, a high-potential side power supply voltage is input from the third external terminal portion, a low-potential side power supply voltage is input from the first external terminal portion, an output current is output from the second external terminal portion, the semiconductor device according to claim 11.

24. the first main current wiring is disposed on the third main current wiring, a first insulating member is disposed between the first main current wiring and the third main current wiring, a second insulating member is disposed between the third main current wiring and the plurality of second semiconductor elements, a third insulating member is disposed between the second main current wiring and the plurality of first semiconductor elements, the semiconductor device according to claim 23.

25. the first main current wiring has a third opening, the first insulating member has a fourth opening in the third opening, and the fourth connection portion is exposed from the fourth opening, The semiconductor device according to claim 24, wherein the fourth connection portion is welded to a conductive block disposed on the third conductive plate and is electrically connected to the third conductive plate via the conductive block. **Claim 26** a plurality of first sense emitter wires electrically connected to the emitters of each of the plurality of first semiconductor elements; a plurality of second sense emitter wires electrically connected to the emitters of each of the plurality of second semiconductor elements; a plurality of first gate wires electrically connected to the gates of each of the plurality of first semiconductor elements; a plurality of second gate wires electrically connected to the gates of each of the plurality of second semiconductor elements; a first external sense emitter terminal electrically connected to each of the plurality of first sense emitter wires; a second external sense emitter terminal electrically connected to each of the plurality of second sense emitter wires; a first external gate terminal electrically connected to each of the plurality of first gate wires; a second external gate terminal electrically connected to each of the plurality of second gate wires; and the plurality of first sense emitter wires and the plurality of first gate wires are disposed directly below the third insulating member, the semiconductor device according to claim 24, wherein the plurality of second sense emitter wires and the plurality of second gate wires are disposed directly below the second insulating member.

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