Providing a track access reason for track access that results in the release of cached resources prefetched for the track

Abstract

A computer program product, system, and method are provided for providing a track access reason for a track access that results in the release of a prefetched cache resource for the track. A first request for a track is received from a process, for which a prefetched cache resource is being held for an expected second request for the track. A track access reason specifying a reason for the first request is provided for the first request. The prefetched cache resource is released before the second request for the track is received. An indication of the track in a list of unexpectedly released tracks and the track access reason for the first request is provided.

Description

Technical Field

[0001] The present invention relates to a computer program product, a system, and a method for providing a track access reason for track access that results in the release of cached resources prefetched for a track.

Background Art

[0002] In a storage environment, a host system can first communicate a read / write request through a high-speed channel to a storage system connected through a bus interface or a Peripheral Component Interconnect Express (PCIe)(R) interface. For read / write requests through a high-speed channel that are expected to complete within a threshold time, the host system holds the application thread for the read / write request in a spin loop and waits for the request to complete. This saves processor time associated with a context switch that deactivates the thread and reactivates the thread in response to an interrupt when a response to the read / write request is received. If the data for a read / write request transmitted over the high-speed channel is not in the cache, then the storage system may fail the read / write request, and the host system can communicate the same read / write request through a storage area network via a host adapter that is slower than processing I / O requests through a bus, e.g., a PCIe interface. Communicating a read / write request through a second channel requires the host system to perform a context switch from the task of handling the read / write request to another task while waiting for the read / write request to complete. Context switching is costly because the processor running the task has to clear all registers as well as the L1 and L2 caches for the new task and then, when the new task is completed, reactivate the context-switched task and return the state data to the registers as well as the L1 and L2 caches for the context-switched task while waiting for the read / write request to complete.

[0003] Certain read / write operations need to be completed within a threshold time; otherwise, they are failures. To process a read or write request, the storage system will have to allocate cache resources, including resources and segments within the cache storage, as well as access track metadata for processing that read or write request. The track metadata provides information regarding the format of the data within the track and the layout of the recording for performing reads and writes to the track. However, the allocation of cache resources includes a substantial portion of the delay in processing read / write requests, including accessing metadata from storage.

[0004] In the art, there is a need for an improved technique for managing host write requests to a cache over a high-speed channel to improve the likelihood that cache resources prefetched for a track will be available for a predicted write request received over the high-speed channel. SUMMARY OF THE INVENTION

[0005] A computer program product, system, and method are provided for providing a track access reason for a track access that results in the release of cache resources prefetched for the track. For that purpose, a first request for the track is received from a process, where the cache resources prefetched to the cache are being held for a second request for the predicted track. A track access reason specifying a reason for the first request is provided for the first request. The prefetched cache resources are released before a second request for the track is received. A display is made of the track in a list of unexpectedly released tracks and the track access reason for the first request. BRIEF DESCRIPTION OF THE DRAWINGS

[0006]

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DETAILED DESCRIPTION OF THE INVENTION

[0007] Access to a write set may be stalled if events occur that would prevent write access to a track for an extended period of time in order to allow other processes to access the tracks held for that write set, such as long, busy, or unsupported copy service states, or volume ineligibility due to other processes. Stalling access to tracks in a write set causes the release of cache resources prefetched for the tracks in the write set. Releasing prefetched cache resources will cause an obstacle to the first channel write requests to retry writing to the tracks in the stalled write set if there are no cache resources pre-allocated for these requests when the write requests are received.

[0008] Prefetching cache resources prior to an access request increases the likelihood that write requests sent by the host on the first high-speed channel will complete within the threshold time required to process access requests on the first channel that require high-speed processing. This keeps the time that the host thread spins on the write request task within an acceptable time threshold for write requests sent on the bus interface. However, considering that cache resources would have to be allocated if they were not already allocated prior to the request for the requested target track, the likelihood that the write request can complete within the threshold time is low. If the write request fails on the first channel, the host redrives the write request on the second channel. Processing the write request on the second channel allocates the cache resources required when processing the write request on the second channel.

[0009] The described embodiments provide an improvement in computer technology for handling failures of access requests to a track for which cached resources prefetched for the track are not available, by providing track access reasons for a process that requested access to the track, which resulted in the release of the cached resources prefetched for the track. Hosts and other processes can use the track access reasons to determine how to continue to process write requests regarding the track, or for other troubleshooting and debugging operations regarding why other processes are requesting access to a track for which the prefetched cached resources are held for fast first-channel writes.

[0010] FIG. 1 illustrates an embodiment of a storage environment in which a host 100 directs read and write requests to a storage system 102, also referred to as a storage controller, a control device, a server, to access tracks within a volume configured in a storage device 104 in a disk enclosure 106. The host 100 includes a processor complex 108 of one or more processor devices and a memory 110 including an operating system 111 executed by the processor complex 108. The host operating system 111 generates read and write requests to tracks configured in the storage device 104. The host 100 includes hardware for communicating read and write requests on two different channels. The "first channel" may comprise a bus interface such as Peripheral Component Interconnect Express (PCIe) including a bus 112, a bus switch 114 for connecting one or more devices including the processor complex 108 and the memory system 110 on the bus 112, and a bus host adapter 116 for extending the bus interface to the storage system 102 through an external bus interface cable 118. For example, additional bus interface technologies for extending the bus interface may be utilized, including a PCIe extender cable or component such as a distributed PCIe switch, to permit PCIe over Ethernet using, for example, ExpEther(R) technology.

[0011] A "second channel" for connecting the host 100 and the storage system 102 may use a network host adapter 120 connected to the bus 112, and the network host adapter 120 connects to another network 122 through which the host 100 and the storage system 102 additionally communicate. The first channel through the bus interface may comprise an access channel faster than the second channel using the network 122 interface via the network host adapter 120.

[0012] The storage system 102 includes a bus interface comprising bus 124a, 124b, a bus switch 126 for connecting to endpoint devices on bus 124a, 124b, and a bus host adapter 128 for connecting to an external bus interface cable 118 to permit communication to the host 100 through the bus interface through the first channel. The storage system 102 includes an input / output bay 130 having a bus host adapter 128, one or more device adapters 132 for connecting to the storage device 104, and one or more network host adapters 134 for connecting to the network 122 and the host system.

[0013] Storage system 102 includes a processor complex 136 of one or more processor devices and a memory 138 having a cache 140 for caching tracks accessed by a connected host 100. Memory 138 includes a write access manager 142 for managing write requests to cache 140, a storage manager 144 for managing access requests from host 100 regarding tracks in storage 104 and processes in storage system 102, and a cache manager 145 for managing requests to tracks in cache 140. Devices 136, 138, 128, 132, and 134 are connected through bus interfaces implemented in bus lanes 124a, 124b, and bus switch 126.

[0014] Write access cache manager 142 prefetches cache resources, including metadata and other releases, into cache 140 so that such write requests can be completed quickly and with low latency for a defined set of write requests expected on the first channel.

[0015] A track may comprise any data unit configured within storage 104, such as a track that is part of a larger grouping of multiple tracks, such as a volume, logical device, etc., a logical block address (LBA).

[0016] The write access manager 142 and / or the cache manager 145 maintain cache management information 146 in the memory 138 to manage the read (non-modified) and write (modified) tracks in the cache 140. The cache management information 146 may include a track index 148 that provides the index of a track in the cache 140 to a cache control block in the control block directory 150, and a least recently used (LRU) list 152 for the tracks in the cache 140. The control block directory 150 includes a plurality of cache control blocks, with one cache control block for each track in the cache 140, and provides metadata for the tracks in the cache 140. The track index 148 associates a track with a cache control block that provides information about the track in the cache 140. When it is determined that the cache LRU list 152 is full or has reached a threshold level, a track is demoted from the LRU list 152 to make room to stage additional tracks from the storage 104 into the cache 140.

[0017] The cache management information 146 may further include write set information 200 of a write set of tracks established by the host 100 for the tracks to be written on the first channel. The write access manager 140 may prefetch cache resources for the tracks in the write set prior to receiving a write transaction. The host 100 may anticipate multiple streams of sequential write transactions to different ranges of tracks and establish multiple write sets for multiple ranges of tracks for which track resources will be allocated.

[0018] Host operating system 111 may establish a write set 200 for a range of tracks 204 in order to cause write access manager 142 to pre-allocate cache resources for the write set in anticipation of sequential write transactions that are likely to be directed immediately to those tracks shown in the write set. These pre-allocated cache resources reduce the latency in processing them when the sequential write requests are ultimately received. Further, by allocating cache resources for a first subset of a limited (constant) number of tracks within the write set, the cache resources are retained only for those tracks that are most likely to be written as part of a sequential write stream. Further, the number of tracks for which cache resources are retained is limited to allow those cache resources to be available for access by other processes in host operating system 111 or other connected hosts 100.

[0019] The write access manager 142 maintains a list 500 of unexpectedly released tracks, and this list has information regarding the track access reason for access requests from an internal process 154 or an external process, which caused the release of cache resources prefetched for the tracks in the write set 200 held for write requests to tracks on the first channel, and which led to the release of cache resources prefetched for the tracks in that write set. The process 154 requesting access to a track may include copy services, such as copying a track's integrity group, a destage / stage operation, an operation to cause QUIESCE on a volume including the tracks in the write set, etc. The list 500 of unexpectedly released tracks should be large enough to avoid entries being overwritten in a short time, and should have a sufficient number of entries to provide sufficient detail regarding track access that causes the release of prefetched cache resources to allow thorough debugging regarding the cause of the unexpected release of prefetched cache resources.

[0020] The cache resources held and accessed for tracks within the track range 302 may comprise segments within the cache 140 for use with the tracks to be written, segments within non-volatile storage if the copy of the written track is to be stored in the same or a different cluster in non-volatile storage, track metadata for the tracks, and other types of cache resources necessary to process write transactions to the tracks.

[0021] In certain embodiments, there may be a plurality of hosts 100 connected to storage system 102 through first and second channels to access tracks in storage device 104. In such a case, storage system 102 will have at least one bus host adapter 128 for connecting to the bus interface 118 of each connected host 100, and one or more network host adapters 134 for connecting to the plurality of network host adapters 120 on the plurality of hosts 100.

[0022] In one embodiment, bus interfaces 112, 114, 116, 118, 124a, 124b, 126, and 128 may comprise Peripheral Component Interconnect Express (PCIe) bus interface technology. In alternative embodiments, bus interfaces 112, 114, 116, 118, 124a, 124b, 126, and 128 may utilize other suitable bus interface technology other than PCIe. Bus host adapters 116 and 128 may comprise PCIe host adapters that provide an interface for connecting to PCIe cable 118. Network 122 may comprise a Storage Area Network (SAN), Local Area Network (LAN), Wide Area Network (WAN), Fibre Connection (FICON(R)), Internet, Intranet, etc., and network host adapters 120, 134 provide a network 122 connection between host 100 and storage system 102. (FICON is a registered trademark of International Business Machines Corporation worldwide).

[0023] Storage system 102 may comprise a storage system, also known as a control device and a storage controller, such as an International Business Machines Corporation (IBM(R)) DS8000(R) and DS8880 storage system, or a storage controller and storage system from another vendor. (IBM and DS8000 are trademarks of International Business Machines Corporation throughout the world). Host operating system 111 may comprise an operating system such as a Z Systems operating system (Z / OS(R)) from International Business Machines Corporation ("IBM"), or other operating systems known in the art. (Z / OS is a registered trademark of IBM throughout the world).

[0024] The storage device 104 in the disk enclosure 106 may include storage devices of different types or classes, such as magnetic hard disk drives, solid-state storage devices (SSDs) composed of solid-state electronics, EEPROM (Electrically Erasable Programmable Read-Only Memory), flash memory, flash disks, random access memory (RAM) drives, storage-class memory (SCM), etc., such as phase change memory (PCM), resistive random access memory (RRAM), spin transfer torque memory (STT-RAM), conductive bridging RAM (CBRAM), magnetic hard disk drives, optical disks, tapes, etc. The volume in the storage space may be further composed of an array of devices, such as just a bunch of disks (JBOD), direct access storage devices (DASD), an array of redundant arrays of independent disks (RAID), virtualized devices, etc. Further, the storage device 104 in the disk enclosure 106 may include heterogeneous storage devices from different vendors and different types of storage devices, such as a first type of storage device having a lower data transfer rate than an SSD, such as a hard disk drive, and a second type of storage device, such as an SSD.

[0025] FIG. 2 illustrates an embodiment with an example of write set information 200 for a write set established to receive write requests on a first channel, and this information 200 i includes a write set identifier (ID) 202 that provides a unique identifier for the write set, a range 204 of tracks for which sequential write transactions on the first channel are expected and for which cache resources should be accessed prior to the sequential write transaction, a track access list 300 that indicates for each track within the range 204 of tracks whether the cache resources are held for the track and whether the track has been written after receiving the established write set 200 i and a prefetch cursor 206 that indicates tracks within a range 302 of tracks for which cache resources should be allocated for sequential write transactions in the write set 202. i In certain embodiments, the prefetch cursor 206 may be set during normal processing to point to the tracks that the write access manager 142 expects the host 100 to be writing (if actively writing) or about to write (if not actively writing). The prefetch cursor 206 points to where the write access manager 142 determines the host 100 is during those processes.

[0026] FIG. 3 illustrates an embodiment of a track access list entry 300 in the track access list 300 that includes a track identifier (ID) 302, a cache resource holding flag 304 that indicates whether cache resources are held for the track 302, and a track write flag 306 that indicates whether the track 302 has been written after the write set 202 was established.

[0027] i

[0028] ​​FIG. 4 illustrates an embodiment with a second channel write request 400 received from host 100 on a second channel, including a write operation code 402, an extent definition range 404 of a subset of tracks in a write set 408 to which one or more subsequent write transactions 406 will be directed, and a retry flag 410 on a first channel indicating whether the write transaction 406 in the second channel write request 400 will be retried later on the faster first channel.

[0029] FIG. 5 illustrates an embodiment with an entry 500 in a list 500 of unexpectedly released tracks, including a track 502 identifying an accessed track for which a prefetched cache resource has been released, a volume 504 including that track, a write set 506 in which that track was included for first channel writing, and a track access reason 508 indicating why process 154 or another process accessed that track. The track access reason may indicate, for example, volume QUIESCE, read or write to a track on a second channel, read to a track, etc. The track access reason can include any reason that may help a host 100, process, or user debug a failure of a write on a first channel, or that may allow a host 100 to adjust its operations to reduce the cause of a track access reason that results in an unexpected release of a prefetched cache resource. i

[0030] ​FIG. 6 illustrates an embodiment of operations performed by cache manager 145 to process a request to a track, such as a first request, from process 154 or another external process, with a track access reason code. The track access reason code may be maintained within a task control block (TCB) or other task management operations implementing process 154. When a track access request (first request) is received (at block 600), if there is no cached resource prefetched for the track to be accessed, for example, a write request on a first channel or held for a second request (at block 602), then the track access request within cache 140 is processed (at block 604). If there is a cached resource prefetched for the track (at block 602), then cache manager 145 sends (at block 606) a request to write access manager 142 to release the cached resource prefetched for the track, along with the track access reason provided by process 154 for the first request. When an acknowledgement is received from write access manager 142 that the prefetched cached resource has been released (at block 608), control proceeds to block 604 to allow the first request from process 154 to complete.

[0031] Figure 7 shows an embodiment in which write access manager 142 performs operations to process a request from cache manager 145 to release a prefetched cache resource with a track access reason for a request. When receiving a request to release a prefetched cache resource (at block 700), write access manager 142 releases the prefetched cache resource for the requested track (at block 702). To indicate that the cache resource is not being held 304, the track access list entry 300 for the requested track in track access list 300 i is updated (at block 704). An entry 500 is included to show the requested track 502, the volume of the track 504, the write set 506 that includes the track, and the track access reason code 508 that indicates the reason for the request regarding the track i so that the list 500 of unexpectedly released tracks is updated (at block 706).

[0032] According to the embodiments of FIGS. 6 and 7, write access manager 142 has the ability to track the reason for a subsequent write failure to a predicted track on a fast first channel such that another process 154 requests tracks in a write set in which a prefetched cache resource is held and those prefetched cache resources are released. The host 100 or user may use the track access reason 508 provided for the release of the prefetched cache resource that would have caused a first channel write request to fail to debug and troubleshoot the reason for the unexpected release of the prefetched cache resource before the predicted write is received on the first channel.

[0033] FIG. 8 illustrates an embodiment with operations performed by a write access manager 142 to write to a track in a write set received on a first channel and to process a second request in response to a first request from process 154. When a write request is received on the first channel (at block 800), the write access manager 142 determines (at block 802) whether a prefetched cache resource is available for the track to be written. If available, the write request on the first channel is processed (at block 804). If there is no prefetched cache resource available for writing (at block 802), then at that time the write access manager 142 searches (at block 806) a list 500 of unexpectedly released tracks for an entry 500 having the requested track 502 and the write set 504 that includes that track. If no entry 500 i is found in the list 500 (at block 808), then at that time the failure is returned to the host (at block 810) without a track access reason 508 so that the host or another process can handle the failure or assist in troubleshooting it. If an entry 500 i for the track and write set is in the list (at block 808), then at that time the write access manager 142 returns the failure (at block 812) with the track access reason 508 within the located entry 500 i . i

[0034] ​In one embodiment, the process that results in the release of prefetched cache resources may include a host 100 request on a second channel regarding the track. In such a case, the track access reason code may indicate a second channel track access. As an example, if there is an error on the first channel link that causes a host timeout, then the host may retry writing to the track through the second channel link. In such a case, the write access manager 142 may indicate the track access reason code as a second channel write. Analysis of the storage system 102 dump may reveal that the host retried the failed write on the second channel and that the first channel link may need to be diagnosed as a possible cause of this failure.

[0035] The track access reason code may also indicate that an unexpected release of prefetched cache resources was caused by the QUIESCE of a volume containing the track that forms the consistency group of the track including the requested track by a copy service. This information would allow the host or user to diagnose that the cause of subsequent failures of writes on the first channel was due to the result of the copy service.

[0036] In a certain process, reading data such as logged data may occur immediately after a write on the first channel. If the reading follows the write too closely, then a conflict for track access may cause the release of cache resources prefetched for the track that are being held for the expected first channel write. When the host 100 receives an obstruction to a first channel write request that includes a track access reason code indicating a read of the track, it may then throttle the read to avoid a conflict with the expected write to the track.

[0037] In one embodiment, when the second channel comprises a Fibre Connection (FICON(R)) link, which is a trademark of International Business Machines Corporation (IBM) for the ANSI FC-SB-3 single-byte command code set-3 mapping protocol for Fibre Channel (FC), the first channel comprises an IBM zHyperLink, and the host operating system 111 comprises Z / OS(R), the host 100 may retry failed zHyperLink (first channel) writes via the FICON interface (second channel).

[0038] The present invention may be implemented as a system, method, and / or computer program product. The computer program product may include a computer readable storage medium (s) having computer readable program instructions thereon for causing a processor to implement aspects of the present invention.

[0039] A computer-readable storage medium can be a tangible device that can hold and store instructions for use by an instruction-executing device. The computer-readable storage medium can be, for example, but not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. A non-exhaustive list of more specific examples of computer-readable storage media includes a portable computer diskette, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a flexible disk, a mechanically encoded device such as a punch card or raised structures in grooves having instructions recorded thereon, and any suitable combination of the foregoing. The computer-readable storage medium should not be construed herein as being a transient signal per se, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagating through a waveguide or other transmission medium (e.g., an optical pulse passing through an optical fiber cable), or an electrical signal transmitted through a wire.

[0040] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to respective computing / processing devices or to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network may comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers, and / or edge servers. A network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards them for storage on a computer-readable storage medium within respective computing / processing devices.

[0041] Computer-readable program instructions for carrying out the operation of the present invention may be source code or object code written in any combination of one or more programming languages, including assembler instructions, instruction-set-architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, firmware instructions, state-setting data, or object-oriented programming languages such as Java, Smalltalk, C++, or the like, as well as conventional procedural programming languages such as the "C" programming language or similar programming languages. The computer-readable program instructions may be executed entirely on the user's computer, partially on the user's computer, as a stand-alone software package, partially on the user's computer and partially on a remote computer, or entirely on the remote computer or server. In the latter scenario, the remote computer may be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., through the Internet using an Internet service provider). In some embodiments, for example, an electronic circuit including a programmable logic circuit, a field-programmable gate array (FPGA), or a programmable logic array (PLA) may execute the computer-readable program instructions by utilizing the state information of the computer-readable program instructions to personalize the electronic circuit for performing aspects of the present invention.

[0042] Aspects of the present invention are described herein with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer readable program instructions.

[0043] These computer readable program instructions may be provided to the processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in one or more blocks of the flowchart and / or block diagram. These computer readable program instructions may be stored in a computer readable storage medium, which may direct a computer, a programmable data processing apparatus, and / or other devices to function in a particular manner, such that the computer readable storage medium containing the instructions comprises a manufacture including instructions which implement the aspects of the function / act specified in one or more blocks of the flowchart and / or block diagram.

[0044] The computer readable program instructions may be loaded onto a computer, other programmable apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus, or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable apparatus, or other device implement the functions / acts specified in one or more blocks of the flowchart and / or block diagram.

[0045] The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram may represent a module, segment, or portion of code that comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the blocks may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and / or flowchart illustrations, and combinations of blocks in the block diagrams and / or flowchart illustrations, can be implemented by special purpose hardware-based systems that perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

[0046] The computing components of FIG. 1, including host 100 and storage system 102, may be implemented in one or more computer systems such as computer system 902 shown in FIG. 9. Computer system / server 902 may be described in the general context of computer system-executable instructions, such as program modules, being executed by a computer system. Generally, program modules may include routines, programs, objects, components, logic, data structures, etc. that perform particular tasks or implement particular abstract data types. Computer system / server 902 may be implemented in a distributed cloud computing environment where tasks are performed by remote processing devices linked through a communications network. In a distributed cloud computing environment, program modules may be located in both local and remote computer system storage media including memory storage devices.

[0047] As shown in FIG. 9, the computer system / server 902 is shown in the form of a general-purpose computing device. The components of the computer system / server 902 may include, but are not limited to, one or more processors or processing units 904, a system memory 906, and a bus 908 that couples various system components including the system memory 906 to the processor 904. The bus 908 may represent any one or more of several types of bus structures, including a memory bus or memory controller, a peripheral bus, an accelerated graphics port, and a processor or local bus using any of a variety of bus architectures. By way of example and not limitation, such architectures include Industry Standard Architecture (ISA) bus, Micro Channel Architecture (MCA) bus, Enhanced ISA (EISA) bus, Video Electronics Standards Association (VESA) local bus, and Peripheral Component Interconnect (PCI) bus.

[0048] The computer system / server 902 typically includes various computer system readable media. Such media may be any available media that is accessible by the computer system / server 902 and includes both volatile and nonvolatile media, removable and non-removable media.

[0049] System memory 906 can include a computer system readable medium in the form of volatile memory, such as random access memory (RAM) 910 and / or cache memory 912. Computer system / server 902 may further include other removable / non-removable, volatile / non-volatile computer system storage media. By way of example only, a storage system 913 can be provided for reading from and writing to a non-removable, non-volatile magnetic medium (not shown, typically called a “hard drive”). Although not shown, a magnetic disk drive for reading from and writing to a removable, non-volatile magnetic disk (e.g., a “floppy disk”), and an optical disk drive for reading from or writing to a removable, non-volatile optical disk such as a CD-ROM, DVD-ROM or other optical media can be provided. In such instances, each can be connected to bus 908 by one or more data medium interfaces. As further illustrated and described below, memory 906 may include at least one program product having a set of (e.g., at least one) program modules configured to execute the functions of embodiments of the present invention.

[0050] The program / utilities 914 having a set (at least one) of program modules 916 may be stored in the memory 906, such as, by way of example and not limitation, an operating system, one or more application programs, other program modules, and program data. Each of the operating system, one or more application programs, other program modules, and program data, or some combination thereof, may include an implementation of a networking environment. The components of the computer 902 may generally be implemented as program modules 916 that execute the functions and / or methodologies of the various embodiments of the invention as described herein. The system of FIG. 1 may be implemented as one or more computer systems 902, and if implemented in a plurality of computer systems 902, the computer systems may communicate through a network.

[0051] The computer system / server 902 may communicate with one or more external devices 918 such as a keyboard, a pointing device, a display 920, and one or more devices that enable a user to interact with the computer system / server 902, and / or any device that enables the computer system / server 902 to communicate with one or more other computing devices (e.g., a network card, a modem, etc.). Such communication may occur via an input / output (I / O) interface 922. Additionally, the computer system / server 902 may communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), and / or a public network (e.g., the Internet) via a network adapter 924. As shown, the network adapter 924 communicates with other components of the computer system / server 902 via a bus 908. It should be understood that other hardware and / or software components may be used in conjunction with the computer system / server 902, although not shown. Examples include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archive storage systems.

[0052] The terms "an embodiment", "embodiment", "embodiments", "the embodiment", "the embodiments", "one or more embodiments", "some embodiments", and "an embodiment" mean "one or more (but not all) embodiments of the present invention(s)" unless expressly specified otherwise.

[0053] The terms "including", "comprising", "having" and their variants mean "including but not limited to" unless expressly specified otherwise.

[0054] A list of listed items does not imply that any or all of those items are mutually exclusive unless explicitly specified otherwise.

[0055] The terms "a", "an", and "the" mean "one or more" unless explicitly specified otherwise.

[0056] Devices that are communicating with each other do not necessarily need to communicate with each other continuously unless explicitly instructed otherwise. In addition, devices that are communicating with each other may communicate directly or indirectly through one or more relay points.

[0057] The description of embodiments using several components that are communicating with each other does not imply that all such components are required. Conversely, various optional components are described to show possible embodiments over a wide range of the present invention.

[0058] When a single device or article is described herein, it will immediately become apparent that more than one device / article may be used instead (regardless of whether they cooperate). Similarly, when more than one device or article is described herein (regardless of whether they cooperate), it will immediately become apparent that a single device / article may be used instead of more than one device / article, or that a different number of devices / articles may be used instead of the number of devices or programs shown. The functionality and / or features of a device may be embodied by one or more other devices that are not explicitly described as having such functionality / features. Accordingly, other embodiments of the present invention need not include the device itself.

[0059] The foregoing description of various embodiments of the invention has been presented for purposes of illustration and description. This description is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. It is intended that the scope of the invention be defined not by this detailed description, but rather by the claims appended hereto. The above specification, examples and data provide a complete description of the manufacture and use of the compositions of the invention. Since many embodiments of the invention can be made without departing from the scope of the invention, the invention resides within the scope of the appended claims.

Claims

1. A computer program for processing an access request to a track in a storage cached in a cache, the computer program comprising: receiving, from a process, a first request for the track, wherein a cached resource prefetched into the cache is held for a second request for a predicted track, and a track access reason specifying a reason for the first request is provided for the first request; releasing the prefetched cached resource before the second request to the track is received, the releasing comprising setting the prefetched cached resource to a state not held in the cache; indicating the track and the track access reason for the first request in a list of unexpectedly released tracks; and causing an operation including the above to be executed.

2. The computer program according to claim 1, wherein the second request includes a write to the track in a write set of tracks to be written, and the write set includes the track indicated by the track in the list of unexpectedly released tracks.

3. The operation includes: receiving the second request to the track; determining that the prefetched cached resource is no longer available for the second request; in response to determining that the prefetched cached resource is no longer held, searching the list of unexpectedly released tracks for the track; and returning, with a failure related to the second request, the track access reason for the first request in the list of unexpectedly released tracks. The computer program according to claim 1, further comprising

4. The second request includes a first write request received on a first channel from a host, and the host, in response to receiving a failure for the first write request on the first channel, uses the track access reason to determine whether to retry the first write request as a second write request to the track on a second channel. The computer program according to claim 1.

5. The first request regarding the track to cause the prefetched cache resource to be released includes a write request to the track on the second channel, and the track access reason indicates a second channel write request as the reason for the failure returned to the host. The host uses the track access reason to determine a link failure on the first channel. The computer program according to claim 4.

6. The process of generating the first request regarding the track includes an internal process in a storage system having the cache, and the operation is receiving the first request from the internal process by a cache manager that manages access to the cache in the storage system; in response to determining that the prefetched cache resource is being held, sending, by the cache manager, a request to release the prefetched cache resource and the track access reason to a write access manager that is requested to release the prefetched cache resource for writing to the track as part of sequential writing to a write set of the track, and the write access manager indicates the track and the track access reason in a list of the unexpectedly released tracks. Sending The computer program according to claim 1, further comprising **Claim 7** The process for starting the first request includes a copy service that forms a consistency group including the track and causes QUIESCE in the volume including the track, and the track access reason indicates a write error due to QUIESCE of the volume. The computer program according to claim 1. **Claim 8** The process for starting the first request includes reading the track triggered by writing to the track preceding the track requested by the second request, the reading requests release of the prefetched cache resource, and the operation returns a failure for the second request, including the track access reason indicating that the prefetched cache resource has been released for reading to the track, and in response to receiving the track access reason indicating that the prefetched cache resource has been released for the reading to the track, throttles the read request to the track for which the cache resource was prefetched to avoid a conflict in the read content to the track to be written The computer program according to claim 1, further comprising **Claim 9** A system for processing access requests to tracks in storage, comprising a processor, a cache for caching tracks in the storage, and a computer-readable storage medium having computer-readable program code embodied therein that performs operations when executed by the processor and the operations are Receiving, from a process, a first request regarding the track, wherein a cached resource prefetched into the cache is held for a second request regarding a predicted track, and a track access reason specifying a reason for the first request is provided for the first request; Releasing the prefetched cached resource before the second request to the track is received, wherein releasing comprises putting the prefetched cached resource in a state not held in the cache; Indicating the track and the track access reason for the first request in a list of unexpectedly released tracks; Including; A system.

10. The system according to claim 9, wherein the second request includes a write to the track in a write set of tracks to be written, and the write set including the track is indicated by the track in the list of unexpectedly released tracks.

11. The operation further includes: Receiving the second request to the track; Determining that the prefetched cached resource is no longer available for the second request; Searching the list of unexpectedly released tracks for the track in response to determining that the prefetched cached resource is no longer held; Returning the track access reason for the first request in the list of unexpectedly released tracks, along with a failure regarding the second request. The system according to claim 9, further including.

12. The second request includes a first write request received from a host on a first channel, and in response to receiving a failure for the first write request on the first channel, the host uses the track access reason to determine whether to retry the first write request as a second write request to the track on a second channel. The system according to claim 9.

13. The first request regarding the track to cause the prefetched cache resource to be released includes a write request to the track on the second channel, the track access reason indicates a second channel write request as the reason for the failure returned to the host, and the host uses the track access reason to determine a link failure on the first channel. The system according to claim 12.

14. The process that generates the first request regarding the track includes an internal process in a storage system having the cache, and the operation receiving the first request from the internal process by a cache manager that manages access to the cache in the storage system, and in response to determining that the prefetch cache resource is being held, sending, by the cache manager, a request to release the prefetch cache resource and the track access reason to a write access manager that is requested to release the prefetch cache resource for writing to the track as part of sequential writes to a write set of the track, wherein the write access manager indicates the track and the track access reason in a list of tracks unexpectedly released, sending The system according to claim 9, further comprising.

15. A method for processing an access request to a track in storage cached in a cache, comprising: Receiving, from a process, a first request for the track, wherein a cached resource prefetched into the cache is held for a second request for a predicted track, and a track access reason specifying a reason for the first request is provided for the first request; Releasing the prefetched cached resource before the second request for the track is received, wherein releasing comprises putting the prefetched cached resource in a state not held in the cache; Indicating the track and the track access reason for the first request in a list of unexpectedly released tracks; and a method. **Claim 16** The method according to claim 15, wherein the second request comprises a write to the track in a write set of tracks to be written, and the write set including the track is indicated by the track in the list of unexpectedly released tracks. **Claim 17** Receiving the second request for the track; Determining that the prefetched cached resource is no longer available for the second request; In response to determining that the prefetched cached resource is no longer held, searching the list of unexpectedly released tracks for the track; Returning the track access reason for the first request in the list of unexpectedly released tracks, with a failure associated with the second request; and further comprising the method according to claim 15. **Claim 18** The second request includes a first write request received from a host on a first channel, and the host uses the track access reason to determine whether to retry the first write request as a second write request to the track on a second channel in response to receiving a failure for the first write request on the first channel. The method according to claim 15.

19. The first request regarding the track to cause the prefetched cache resource to be released includes a write request to the track on the second channel, the track access reason indicates a second channel write request as the reason for the failure returned to the host, and the host uses the track access reason to determine a link failure on the first channel. The method according to claim 18.

20. The process that generates the first request regarding the track includes an internal process in a storage system having the cache, receiving the first request from the internal process by a cache manager that manages access to the cache in the storage system, and in response to determining that the prefetched cache resource is being held, sending, by the cache manager, a request to release the prefetched cache resource and the track access reason to a write access manager that is requested to release the prefetched cache resource for writing to the track as part of a sequential write to a write set of the track, wherein the write access manager indicates the track and the track access reason in a list of the unexpectedly released tracks. Sending, The method according to claim 15, further comprising.

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