Memory Controller, Method for Controlling Memory Controller, and Program

Abstract

To provide a memory controller that prevents a reduction in the efficiency of utilization of a memory.SOLUTION: A memory controller issuing a command for accessing a plurality of memories sharing a data signal comprises: a holding circuit 101 that holds read and / or write access requests; and a control circuit 102 that selects an arbitrary access request from the access requests held in the holding circuit, and issues a read command and / or a write command. The control circuit performs control not to select, of the access requests held in the holding circuit, an access request to memories other than a memory to which the read command and / or write command has just been issued, for a predetermined period from the issuance of the read command and / or write command.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to a memory controller, a control method of the memory controller, and a program, and particularly relates to a technique of selecting an arbitrary memory access request from a plurality of memory access requests and issuing a command when connected to a DRAM.

Background Art

[0002] As a main memory device of a computer system, generally DRAM (Dynamic Random Access Memory) is used. With the high functionality and high performance of computer systems, the performance requirements for DRAMs have been increasing, and various techniques for memory controllers have been proposed to maximize their performance.

[0003] When the memory controller switches the memory to issue read / write commands to a plurality of memories that share data, the intervals between read / write commands to different memories need to satisfy timing constraints defined so that the shared signals do not collide. As a result, a gap occurs in the data bus, which becomes a factor in reducing the memory utilization efficiency.

[0004] Patent Document 1 discloses that a memory controller mediates a plurality of memory access requests so that the number of memory switches is reduced, thereby suppressing a decrease in memory utilization efficiency.

Prior Art Documents

Patent Documents

[0005]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0006] However, Patent Document 1 does not mention the behavior when there is no memory access request to the memory to which a read / write command was issued immediately before. When selecting a memory access request to a memory different from the immediately preceding one, it is necessary to wait for the issuance of the read / write command for the selected memory access request until a period elapses during which it becomes impossible to issue a read / write command to a different memory from the read / write command issued immediately before. During this time, even if the memory controller receives a memory access request to the memory to which a read / write command was issued immediately before, the memory is switched by the read / write command of the memory access request already selected, resulting in a decrease in memory utilization efficiency.

[0007] The present invention has been made in view of the above problems, and an object thereof is to provide a technique for suppressing a decrease in memory utilization efficiency.

Means for Solving the Problems

[0008] A memory controller according to an aspect of the present invention that achieves the above object is a memory controller that issues a command to access a plurality of memories that share a data signal, a holding circuit that holds read and / or write access requests, and a control circuit that selects an arbitrary access request from the access requests held in the holding circuit and issues a read command and / or a write command, and the control circuit is characterized in that it controls so as not to select an access request to a memory other than the memory to which a read command and / or a write command was issued immediately before from among the access requests held in the holding circuit for a predetermined period from the issuance of the immediately preceding read command and / or write command.

Effects of the Invention

[0009] According to the present invention, it becomes possible to suppress a decrease in memory utilization efficiency.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Mode for Carrying Out the Invention

[0011] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential to the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0012] FIG. 1 is a configuration diagram of a memory controller 100 in the present embodiment. The memory controller 100 is connected to a DRAM 110 composed of a plurality of banks and a bus master 120. The DRAM 110 is composed of two memory devices (memory 0 and memory 1), and memory 0 and memory 1 share a data signal. In the present embodiment, two DRAMs share a data signal, but the number of DRAMs sharing the data signal is not limited to two and may be three or more. The bus master 120 transmits a memory access request including address information and write data to the memory controller 100. The memory controller 100 generates a DRAM command based on the memory access request received from the bus master 120 and transmits it to one of the plurality of DRAMs 110. Further, the memory controller 100 performs data transfer with the DRAM 110 based on the transmitted DRAM command.

[0013] The memory controller 100 includes an access holding circuit 101, a read / write control circuit 102, a page control circuit 103, a bank state management circuit 104, and a command selector 105.

[0014] First, the access holding circuit 101 will be described. The access holding circuit 101 is a buffer that holds multiple memory access requests. The access holding circuit 101 is composed of m (m >= 2) entries. Here, m can be any number. Also, FIG. 2 is a configuration diagram of the access holding circuit entry 1011 in this embodiment. In this embodiment, there are m access holding circuit entries 1011 shown in FIG. 2 in the access holding circuit 101. As shown in FIG. 2, the access holding circuit entry 1011 has fields for access type, target memory, target bank, target page, target column, and remaining read / write command count. The access holding circuit 101 converts and holds the memory access request received from the bus master 120 so as to correspond to each field. The information stored in each field is as follows.

[0015] (a) Access type field Indicates the access type of the memory access request stored in the entry A WRITE memory access request is for writing data A READ memory access request is for reading data (b) Target memory field Indicates the memory that is the target of the memory access request stored in the entry (c) Target bank field The bank address that the memory access request stored in the entry accesses (d) Target page field The page address that the memory access request stored in the entry accesses (e) Target column field The leading column address accessed by the memory access request stored in the entry (f) Remaining read / write command count field The number of remaining DRAM read / write commands to be executed by the memory access request stored in the entry When storing a memory access request in the access holding circuit 101, it is stored in an entry following the last memory access request being stored. When reading a memory access request from the access holding circuit 101, it can be read from any entry.

[0016] Subsequently, the entry control signal input to the access holding circuit 101 will be described. The entry control signal includes an entry number field, a deletion field, and an update field. When 1 is set in the deletion field, the access holding circuit 101 deletes the entry indicated by the entry number field. When 1 is set in the update field, the access holding circuit 101 updates the column field of the entry indicated by the entry number field to the leading column address accessed by the next DRAM command. Also, the remaining read / write command count field is updated to a value subtracted by 1.

[0017] Next, the read / write control circuit 102 will be described. The read / write control circuit 102 can refer to all of the memory access requests stored in the access holding circuit 101. The read / write control circuit 102 selects an arbitrary memory access request from among the memory access requests stored in the access holding circuit 101, where the page to be accessed is open and no command issuance wait due to memory switching occurs. Whether the page to be accessed by the memory access request is open or not can be determined from the target memory field, target bank field, and target page field of the access holding circuit entry 1011 and the bank state generated by the bank state management circuit 104. Then, the read / write control circuit 102 generates a read command or a write command from the selected memory access request and outputs it to the command selector 105. The read / write control circuit 102 of the present embodiment has a function of selecting a memory access request so as to issue a read command and a write command continuously in order to suppress the read / write switching penalty.

[0018] Subsequently, the procedure for the read / write control circuit 102 to generate an entry control signal will be described. When the last read command or write command executed by the memory access request is issued, the processing of the corresponding memory access request is completed. Therefore, the read / write control circuit 102 generates an entry control signal to delete the corresponding entry from the access holding circuit 101. On the other hand, when a read command or write command that is not the last one is issued, the read / write control circuit 102 generates an entry control signal to update the corresponding entry in the access holding circuit 101. However, when the last read command or write command is issued, there is no need to update the corresponding entry. Whether the issued read command or write command is the last one can be determined by whether the remaining read / write command count field of the access holding circuit entry 1011 is 1.

[0019] Next, the page control circuit 103 will be described. The page control circuit 103 can refer to all of the memory access requests stored in the access holding circuit 101. The inputs to the page control circuit 103 are the memory access requests stored in the access holding circuit 101 and the bank states output from the bank state management circuit 104. Based on the memory access requests stored in the access holding circuit 101 and the bank states output from the bank state management circuit 104, the page control circuit 103 generates page control commands such as active commands or precharge commands. Then, the generated page control commands are output to the command selector 105.

[0020] Next, the bank state management circuit 104 will be described. The bank state management circuit 104 updates the bank state based on the command issuance state input from the command selector 105. The command issuance state includes the type of command issued to the DRAM 110 and information on the memory, bank, and page to which the command was issued. The bank state includes whether a page is open for each bank constituting the DRAM 110 and the open page address.

[0021] Finally, the command selector 105 will be described. The command selector 105 selects one from the read / write control command input from the read / write control circuit 102 and the page control command input from the page control circuit 103 and issues it to the DRAM 110. Although not described in this embodiment, a refresh command or the like may also be selected and issued. Further, the command selector 105 outputs the command issuance state composed of the type of command issued to the DRAM 110 and the memory, bank, and page to which the command was issued to the read / write control circuit 102 and the bank state management circuit 104.

[0022] Figure 3 is a configuration diagram of the read / write control circuit 102 in the present embodiment. The read / write control circuit 102 includes a page open determination circuit 1051, a priority access type determination circuit 1052, a memory switching determination circuit 1053, a memory access request selection circuit 1054, a timer 1055, and a timer 1056. The timer 1055 is a timer corresponding to memory 0 of a plurality of DRAMs 110, and the timer 1056 is a timer corresponding to memory 1.

[0023] The page open determination circuit 1051 determines, based on the bank state, for each of the memory access requests stored in the access holding circuit 101, whether the target bank of the target memory has opened the target page. The page open determination circuit 1051 outputs only the memory access requests for which the target page is open among the memory access requests stored in the access holding circuit 101 to the priority access type determination circuit 1052, and masks the other memory access requests.

[0024] The priority access type determination circuit 1052 determines, for each of the memory access requests output by the page open determination circuit 1051, whether the access type corresponds to the priority access type. The priority access type is generated by the priority access type determination circuit 1052 based on the memory access requests stored in the access holding circuit 101 and the bank state, and indicates the period during which either the read command or the write command is preferentially issued. The priority access type determination circuit 1052 outputs only the memory access requests corresponding to the priority access type among the memory access requests output by the page open determination circuit 1051 to the memory switching determination circuit 1053, and masks the other memory access requests.

[0025] When the command issuance state output from the command selector 105 indicates the issuance of a read command to a memory other than memory 0, the timer 1055 sets the period during which a read command cannot be issued to a different memory after the issuance of a read command to a certain memory. Also, when the command issuance state output from the command selector 105 indicates the issuance of a write command to a memory other than memory 0, the timer 1055 sets the period during which a write command cannot be issued to a different memory after the issuance of a write command to a certain memory. Except during the setting, the value of the timer 1055 is decremented with the passage of time and stops at 0. In this embodiment, the period during which a read command or a write command cannot be issued to a different memory after the issuance of a read command or a write command to a certain memory is set in the timer, but it is not limited to this. The period during which a read / write command cannot be issued to a different memory after the issuance of a read / write command to a certain memory may be increased or decreased, and thereby, the relationship between the occurrence frequency of memory switching and the waiting time of memory access requests can be adjusted.

[0026] The timer 1056 sets the timer when the command issuance state output from the command selector 105 is a read command and a write command to a memory other than memory 1, and decrements it with the passage of time otherwise. Other behaviors of this are the same as those of the timer 1055.

[0027] The memory switching determination circuit 1053 determines, for each of the memory access requests output by the priority access type determination circuit 1052, whether waiting for a timing constraint for memory switching is necessary. Whether waiting for a timing constraint for memory switching is necessary for a memory access request can be determined by whether the value of the timer corresponding to the target memory of the memory access request is non-zero. When the target memory of the memory access request is Memory 0, the timer 1055 for Memory 0 is referred to. Also, when the target memory of the memory access request is Memory 1, the value of the timer 1056 for Memory 1 is referred to. The memory switching determination circuit 1053 outputs only the memory access requests for which no command issuance wait due to memory switching occurs among the memory access requests output by the priority access type determination circuit 1052 to the memory access request selection circuit 1054. And the memory access requests for which a command issuance wait occurs are masked.

[0028] The memory access request selection circuit 1054 selects an arbitrary memory access request from the memory access requests output by the memory switching determination circuit 1053. Then, the memory access request selection circuit 1054 generates a read command or a write command for the selected memory access request and outputs it to the command selector 105.

[0029] <Operation> Figures 4 and 5 are diagrams showing operation examples of memory access request selection in the present embodiment. The premise of these operation examples is that the priority access type is read, and it is assumed that for the memory access requests held in the access holding circuit 101, the target bank of the target memory has the target page open. The timing constraints and the states of the memory access requests held in the access holding circuit 101 are shown in the figures. For example, regarding the timing constraints, tCCD = 2 cycles, and the period during which a read command cannot be issued to different memories = 6 cycles. Also, for each of the memory access requests held in the access holding circuit 101, identifiers such as memory access requests 0 to 2 are given for explanation.

[0030] FIG. 4 is a diagram showing an operation example 1 of memory access request selection in the present embodiment. The access holding circuit 101 at time T1 holds a memory access request 0 (access type: READ, target memory: 0, remaining read / write command count: 2) and a memory access request 1 (access type: READ, target memory: 1, remaining read / write command count: 1). At T1, the read / write control circuit 102 can select either the memory access request 0 or the memory access request 1. However, in this operation example, it is assumed that a read command for the previously received memory access request 0 is issued. As a result, the timer 1056 for memory 1 sets a period during which a read command cannot be issued to a different memory after issuing a read command to a certain memory, and starts decrementing.

[0031] The access holding circuit 101 at time T3 holds a memory access request 0 (access type: READ, target memory: 0, remaining read / write command count: 1) and a memory access request 1 (access type: READ, target memory: 1, remaining read / write command count: 1). At T3, the value of the timer 1056 for memory 1 is 5. Since the value is not 0, the memory access request 1 is masked, and the read / write control circuit 102 selects the memory access request 0.

[0032] At times T4 and T5, the access holding circuit 101 holds only a memory access request 1 (access type: READ, target memory: 1, remaining read / write command count: 1). However, the values of the timer 1056 are 6 (at T4) and 5 (at T5). Since the values are not 0, the memory access request 1 is masked. Therefore, the read / write control circuit 102 does not select a memory access request.

[0033] At time T6, the access holding circuit 101 holds the memory access request 1 (access type: READ, target memory: 1, remaining read / write command count: 1) and the memory access request 21 (access type: READ, target memory: 0, remaining read / write command count: 2). That is, at T6, it is assumed that the memory access request 2 to memory 0 is stored in the access holding circuit 101. The value of the timer 1056 is 4 (T6). Since the value is not 0, the memory access request 1 is masked, and the read / write control circuit 102 selects the memory access request 2. Then, at T15 after a predetermined period (6 cycles) during which a read command cannot be issued to different memories, the value of the timer 1056 becomes 0, the mask of the memory access request 1 is released, and the read / write control circuit 102 selects the memory access request 1.

[0034] Subsequently, FIG. 5 is a diagram showing an operation example 2 of memory access request selection in the present embodiment. The difference from the operation example 1 is that the memory access request 2 to memory 0 is not stored in the access holding circuit 101 at T6.

[0035] At T1, the read / write control circuit 102 can select either the memory access request 0 or the memory access request 1. In this operation example, it is assumed that a read command for the previously received memory access request 0 is issued. As a result, the timer 1056 for memory 1 sets the period during which a read command cannot be issued to a different memory after issuing a read command to a certain memory, and starts decrementing.

[0036] In T3, the value of timer 1056 is 5. Since the value is not 0, memory access request 1 is masked, and the read / write control circuit 102 selects memory access request 0. From T4 to T9, only memory access request 1 is held in the access holding circuit 101. However, since timer 1056 is not 0, memory access request 1 is masked, and the read / write control circuit 102 does not select any memory access requests. Then, at T10 after a predetermined period (6 cycles) during which read commands cannot be issued to different memories from T4 to T9, the value of timer 1056 becomes 0, the mask of memory access request 1 is released, and the read / write control circuit 102 selects memory access request 1.

[0037] Note that in FIGS. 4 and 5, the embodiments have been described by taking the read command as an example, but the same applies to the write command. For example, in the above, an example has been described in which the timer sets a period during which a read command cannot be issued to a different memory after the read command is issued and starts decrementing. Similarly, a period during which a write command cannot be issued to a different memory after the write command is issued may be set and decrementing may be started.

[0038] As described above, even when there is no memory access request to the memory to which the read / write command was last issued, it is configured not to select a memory access request that requires waiting for command issuance due to memory switching. Thereby, it becomes possible to suppress a decrease in memory utilization efficiency.

[0039] The disclosure of this specification includes the following memory controller, memory controller control method, and program.

[0040] (Item 1) A memory controller that issues commands for accessing a plurality of memories that share data signals, a holding circuit that holds read and / or write access requests, A control circuit that selects an arbitrary access request from the access requests held in the holding circuit and issues a read command and / or a write command. The control circuit controls so as not to select, within a predetermined period from the issuance of the immediately preceding read command and / or write command, an access request to a memory other than the memory to which the immediately preceding read command and / or write command was issued, among the access requests held in the holding circuit. A memory controller characterized by this.

[0041] (Item 2) The predetermined period is, when a read command was issued immediately before, a predetermined period during which a read command cannot be issued to a memory different from the memory to which the immediately preceding read command was issued. The memory controller according to item 1, characterized by this.

[0042] (Item 3) The predetermined period is, when a write command was issued immediately before, a predetermined period during which a write command cannot be issued to a memory different from the memory to which the immediately preceding write command was issued. The memory controller according to item 1 or 2, characterized by this.

[0043] (Item 4) The control circuit selects an access request based on a priority access type indicating which of a read command and a write command is to be issued with priority. The memory controller according to any one of items 1 to 3, characterized by this.

[0044] (Item 5) For each of the memory access requests stored in the holding circuit, a first determination circuit that determines whether or not the target bank of the target memory has the target page open, and outputs a memory access request for which the target page is open. The memory controller according to any one of items 1 to 4, further comprising this.

[0045] (Item 6) A memory controller according to item 5, further comprising a second determination circuit that outputs a memory access request corresponding to a priority access type indicating which of a read command and a write command is to be preferentially issued among the memory access requests output by the first determination circuit.

[0046] (Item 7) A memory controller according to item 6, further comprising a third determination circuit that outputs a memory access request in which no command issuance wait due to memory switching occurs among the memory access requests output by the second determination circuit.

[0047] (Item 8) A memory controller according to item 7, further comprising a request selection circuit that selects an arbitrary memory access request from the memory access requests output by the third determination circuit and generates and outputs a read command or a write command of the selected memory access request.

[0048] (Item 9) The memory controller according to any one of items 1 to 8, wherein the control circuit can select an access request to a memory other than the memory to which a read command and / or a write command was immediately issued after the elapse of the predetermined period.

[0049] (Item 10) A memory controller according to any one of items 1 to 9, further comprising a timer that sets a period during which a read command cannot be issued to a different memory after the issuance of a read command and starts decrementing.

[0050] (Item 11) A memory controller according to any one of items 1 to 10, further comprising a timer that sets a period during which a write command cannot be issued to a different memory after the issuance of a write command and starts decrementing.

[0051] (Item 12) A control method for a memory controller that issues commands to access a plurality of memories that share data signals, wherein the memory controller includes a holding circuit that holds read and / or write access requests, and a control circuit that selects an arbitrary access request from the access requests held in the holding circuit and issues a read command and / or a write command, and the control method includes: a step of controlling so as not to select, within a predetermined period from the issuance of the immediately preceding read command and / or write command, access requests to memories other than the memory to which the immediately preceding read command and / or write command was issued, among the access requests held in the holding circuit. A control method for a memory controller, characterized by having this.

[0052] (Item 13) A program for causing a computer to function as the memory controller according to any one of Items 1 to 11.

[0053] (Other Embodiments) The present invention can also be realized by supplying a program that realizes one or more functions of the above-described embodiments to a system or device via a network or a storage medium, and having one or more processors in the computer of the system or device read and execute the program. It can also be realized by a circuit (for example, an ASIC) that realizes one or more functions.

[0054] The invention is not limited to the above-described embodiments, and various changes and modifications are possible without departing from the spirit and scope of the invention. Therefore, claims are attached to disclose the scope of the invention.

Explanation of Signs

[0055] 100: Memory controller, 101: Access hold circuit, 102: Read / write control circuit, 103: Page control circuit, 104: Bank state management circuit, 105: Command selector, 110: DRAM, 120: Bus master, 1011: Access hold circuit entry, 1051: Page open determination circuit, 1052: Priority access type determination circuit, 1053: Memory switching determination circuit, 1054: Memory access request selection circuit, 1055: Timer (for memory 0), 1056: Timer (for memory 1)

Claims

1. A memory controller that issues commands to access a plurality of memories that share data signals, a holding circuit that holds read and / or write access requests, and a control circuit that selects an arbitrary access request from the access requests held in the holding circuit and issues a read command and / or a write command. The control circuit controls so as not to select an access request to a memory other than the memory to which a read command and / or a write command was issued immediately before, from among the access requests held in the holding circuit, for a predetermined period from the issuance of the immediately preceding read command and / or write command. A memory controller characterized by that.

2. The memory controller according to claim 1, wherein the predetermined period is a predetermined period during which a read command cannot be issued to a memory different from the memory to which the immediately preceding read command was issued, when the immediately preceding read command was issued.

3. The memory controller according to claim 1, wherein the predetermined period is a predetermined period during which a write command cannot be issued to a memory different from the memory to which the immediately preceding write command was issued, when the immediately preceding write command was issued.

4. The memory controller according to claim 1, wherein the control circuit selects an access request based on a priority access type indicating which of a read command and a write command is to be issued with priority.

5. The memory controller according to claim 1, further comprising a first determination circuit that determines, for each memory access request stored in the holding circuit, whether or not a target bank of a target memory has opened a target page, and outputs a memory access request for which the target page is opened.

6. The memory controller according to claim 5, further comprising a second determination circuit that outputs a memory access request corresponding to a priority access type indicating which of a read command and a write command is to be preferentially issued during a period in which the memory access requests output by the first determination circuit are issued.

7. The memory controller according to claim 6, further comprising a third determination circuit that outputs a memory access request in which a command issuance wait due to memory switching does not occur among the memory access requests output by the second determination circuit.

8. The memory controller according to claim 7, further comprising a request selection circuit that selects an arbitrary memory access request from the memory access requests output by the third determination circuit and generates and outputs a read command or a write command of the selected memory access request.

9. The memory controller according to claim 1, wherein after the elapse of the predetermined period, the control circuit can select an access request to a memory other than the memory to which a read command and / or a write command was immediately previously issued.

10. The memory controller according to claim 1, further comprising a timer that sets a period during which a read command cannot be issued to a different memory after the read command is issued and starts decrementing.

11. The memory controller according to claim 1, further comprising a timer that sets a period during which a write command cannot be issued to a different memory after the write command is issued and starts decrementing.

12. A control method for a memory controller that issues commands to access a plurality of memories that share data signals, the memory controller comprising: a holding circuit that holds read and / or write access requests; and a control circuit that selects an arbitrary access request from the access requests held in the holding circuit and issues a read command and / or a write command, the control method comprising: a step of controlling so as not to select, for a predetermined period from the issuance of the immediately preceding read command and / or write command, an access request to a memory other than the memory to which the immediately preceding read command and / or write command was issued, among the access requests held in the holding circuit. A control method for a memory controller, characterized by having this.

13. A program for causing a computer to function as the memory controller according to any one of Claims 1 to 11.

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