Hybrid library latch array

Abstract

A static random access memory (SRAM) includes fast SRAM bit cells and fast multiplexer circuits formed in a first row of fast cells in a hybrid standard cell architecture. Slower SRAM bit cells and slower multiplexer circuits are formed in a second row of slower cells. The slower multiplexer circuits provide column outputs to the faster SRAM bit cells and the faster multiplexer circuits provide column outputs to the slower SRAM bit cells. Thus, one SRAM column has fast bit cells and a slower multiplexer stage while an adjacent SRAM column has slower bit cells and a faster multiplexer stage, thereby providing an improved performance balance when reading the SRAM.

Description

Technical Field

[0001] This application relates to SRAM and SRAM bit cells. Conventionally, SRAM uses 6T or 8T bit cells. Since SRAM typically includes a large number of bit cells, ensuring the efficiency of SRAM bit cell area utilization is important for reducing the cost of SRAM in terms of the silicon area used.

Summary of the Invention

Means for Solving the Problems

[0002] (Disclosure of Embodiments of the Invention) Thus, in one embodiment, a static random access memory (SRAM) includes a first plurality of bit cells and a first plurality of multiplexer circuits. The SRAM further includes a second plurality of bit cells and a second plurality of multiplexer circuits. The first plurality of bit cells are coupled to a first multiplexer circuit of the second plurality of multiplexer circuits, and the second plurality of bit cells are coupled to a second multiplexer circuit of the first plurality of multiplexer circuits. The first plurality of bit cells and the first plurality of multiplexer circuits have a first performance level, and the second plurality of bit cells and the second plurality of multiplexer circuits have a second performance level lower than the first performance level.

[0003] In another embodiment, a method for operating a static random access memory (SRAM) includes supplying a first bit cell output from a first plurality of bit cells to a first multiplexer, the first plurality of bit cells having a first performance level and the first multiplexer having a second performance level lower than the first performance level. The first multiplexer supplies any one of the first bit cell outputs as a first multiplexer output signal from the first multiplexer. The method further includes supplying a second bit cell output from a second plurality of bit cells having the second performance level to a second multiplexer having the first performance level. The second multiplexer supplies any one of the second bit cell outputs as a second multiplexer output signal.

[0004] A static random access memory (SRAM) includes a first plurality of SRAM bit cells and a first multiplexer circuit formed from standard cells within a first row of cells having a first performance level. A second plurality of SRAM bit cells and a second multiplexer circuit are formed within a second row of cells having a second performance level lower than the first performance level. The second multiplexer circuit receives each first output of the first plurality of bit cells and selects any one of the respective first outputs as a second multiplexer output signal. The first multiplexer circuit receives each second output of the second plurality of SRAM bit cells and selects any one of the respective second outputs as a first multiplexer output signal.

[0005] The present invention will be better understood by reference to the accompanying drawings, and its numerous objects, features, and advantages will become apparent to those skilled in the art.

Brief Description of the Drawings

[0006]

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[0007] The use of the same reference numerals in different drawings indicates similar or identical items.

[0008] Eight-transistor (8T) static random access memory (SRAM) arrays do not scale well with respect to area at more advanced technology nodes. However, circuits built with standard cell design rules continue to scale relatively well at more advanced technology nodes. By building an SRAM array with standard cell design rules, it is possible to use a smaller area even when there are more transistors. FIG. 1 shows an SRAM bit cell implemented as a latch bit cell 100 having an individual read port and a write port. The latch bit cell 100 uses 12 transistors per bit as compared to the eight transistors of an 8T SRAM bit cell, but note that it still uses less area in certain manufacturing technologies due to the use of standard cell design rules. A significant difference between the latch type bit cell and the classical 6T / 8T SRAM bit cell is that the latch bit cell invalidates feedback during writing. In contrast, in a 6T / 8T bit cell, a pass gate needs to resist pull-up to perform a write. The latch bit cell does not have such a conflict during writing.

[0009] The approach of FIG. 1 implemented using standard cell design rules means that there is no overhead required for the use of custom SRAM macros, thereby reducing the area. For example, the use of standard cell layout rules enables the adjacency of 0-connected poly pitch (CPP) (the horizontal distance between transistors) to standard cell logic. More conventional approaches to SRAM have boundary cells and edge cells required for lithography purposes. Since the standard cell design rules scale well, implementing SRAM cells based on the latch bit cell 100 and the standard cell design rules enables the SRAM design to scale in area similar to future standard architectures.

[0010] The latch bit cell shown in FIG. 1 amortizes the local inverter that is normally present in the latch over more cells. The latch bit cell shown in FIG. 1 removes the local inverter that would have been conventionally used for the input to the latch, including the write bit line (WBL), the write word line (WWL), the active low write word line (WWLX), the read word line (RWL), and the active low read word line (RWLX). In more conventional latch arrays, CMOS combinational stages are used between the latches. The latch bit cell 100 uses a tri-state output for RBL101. The use of the tri-state driver by the latch bit cell enables the outputs (read bit lines) of several cells, for example, 16 cells, to be combined together using a tri-state output driver to avoid any additional combinational stages (NOR / NANDing, etc.) of the output data.

[0011] Figure 2 shows the stick layout of the latch bit cell 100, showing seven transistors in the horizontal direction. The boxes indicate the source / drain connections of the transistors. The gate regions of the transistors are shown as vertical lines with the same labels as the transistors in Figure 1. The long vertical line 201 indicates a shared gate connection, for example, by transistors PFBO and NFBO and transistors PINV and NINV. If there is a blank in the box, there are nodes that are not named in Figure 1, but the unlabeled source / drain connections and gate connections can be easily seen in Figure 1. The layout includes dummy cell (DUM) transistors. A dummy is a transistor that is formed but not connected. The use of dummy transistors provides an efficient way to provide separation between other transistors. Also, the use of dummy transistors provides an advantage in the ability to change the type of transistor used with respect to the threshold voltage (Vt). In an embodiment, the write part of the latch (transistors PPG, NPG, PINV, NINV, NFB1, NFB0, PFB0, PFB1) does not require high performance, while the read part of the latch (transistors PRP1, PRP0, NRP0, NRP1) requires high performance. Note that the first letter of the transistor name indicates the type of transistor (N or P), and the remaining letters indicate its function (PG is pass gate, INV is inverter, FB is feedback, RP is read port).

[0012] Referring to FIG. 3, the read portion 301 of the latch bit cell 100 including transistors PRP0, PRP1, NRP0, and NRP1 enables implementation using lower Vt transistors (such as ultra-low Vt (ulvt)), thereby providing the required high performance. On the other hand, the write portion 303 of the latch bit cell 100 on the left side of the dummy transistor in FIG. 3 is implemented with higher threshold voltage transistors (such as low Vt (lvt) transistors). Transistors with higher Vt provide lower performance but also less leakage, and transistors with lower Vt are utilized only when required for performance. Thus, this layout option enables different threshold voltages to be utilized for the read and write ports with different performance requirements, thereby reducing leakage current compared to having to use lower Vt devices for all devices to meet the performance requirements for only a portion of the bit cell. The transistors in the read and write ports share diffusion between adjacent cells and, if possible, reduce the xtor (transistor) load by half for a non-optimized design.

[0013] Referring again to FIG. 1, the operation of the latch bit cell 100 will be described. The data to be written into the cell on the write bit line WBL102 (also referred to herein as write data (WD)) is supplied to a pass gate 103 formed from transistors NPG and PPG. The gates or those transistors are coupled to a write word line (WWL) and a write word line X (WWLX), respectively, where "X" indicates that the signal is active low. When WWL and WWLX are asserted, the data on WBL is passed as data "D" to an inverter 104 formed by transistors PINV and NINV. Transistors NFB1 and PFB1 turn off when WWL and WWLX are asserted. The gates of NFB0 and PFB0 in the feedback portion of the bit latch cell 100 receive the output D_X (the inverted value of "D") from the inverter. Also, the gates of PRP1 and NRP1 in the read portion 106 of the latch receive D_X. When WWL and WWLX are de-asserted, the pass gate 103 is blocked and transistors NFB1 and PFB1 turn on, thereby enabling D_X to turn on either transistor NFB0 or PFB0 to supply "D" as a feedback signal. Transistors NFB1, NFB0, PFB0, PFB1 function as a keeper circuit 108 and, together with the inverter formed by transistors PINV and NINV, ensure that the data on node D is maintained when WWL and WWLX are de-asserted. In this way, the value of D is maintained in the write portion of the latch bit cell 100 and is available when the latch is read. In the latch bit cell 100, the PMOS transistors PINV, PFB1, PRP1 are coupled to the power supply voltage (VDD) at their sources. The NMOS transistors NINV, NFB1, NRP1 are coupled to a second power supply voltage (ground) at their sources.

[0014] To read a latch bit cell, the read word line (RWL) and RWLX are asserted, turning on NRP0 and PRP0 respectively. Note that "X" indicates an active low signal. Assertion of RWL and RWLX enables the value of D_X to determine the value of the output signal read bit line (RBL) 101, which is also referred to herein as read data (RD). When RWL and RWLX are de-asserted, the RBL is set to high impedance, allowing other SRAM cells to drive the RBL when selected to be read.

[0015] Figure 4 shows an embodiment in which a group of 32 latch bit cells is formed into two groups of latch bit cells (bits <31:16> and bits <15:0>). Each group of latch bit cells supplies bits to a multiplexer 401, which selects bits from either bits <31:16> or bits <15:0> and supplies the selected bits onto rdData403. In the embodiment of Figure 4, the 3-state driver on the read side of the latch bit cell enables driving the same RBL with 16 bits (only one active at a time). Thus, to ensure that multiple latch bit cells do not drive the RBL simultaneously, only one RWL / RWLX is turned on at a time in each group [31:16] and [15:0], which can cause a high current situation. It is also important to ensure that either one of the RWL / RWLX signals is active and that one of the bit cells drives a high or low logic level on the RBL. All de-asserted RWL / RWLX pairs result in a floating node on the RBL, which can cause high current draw in downstream CMOS gates receiving a signal intermediate between VDD and VSS.

[0016] FIG. 5 shows a block diagram of an embodiment having a 64-row and 2-column bit cell, and multiplexer 501 selects 1 bit from 64 rows and 2 columns. Although not shown in FIG. 5 for ease of explanation, the embodiment shown in FIG. 5 also requires a write column multiplexer function. One way to achieve this is to supply the WWL / WWLX pair to the even physical columns and another WWL / WWLX pair to the odd physical columns. In this way, every other cell can be written to. Another way to achieve the write multiplexer function is to use a write mask, as further described herein.

[0017] During a write operation, if a word line for a particular word line is asserted, all bits within the word line can change state. Instead of changing the state of all bits within the word line, it is advantageous to write only to the selected cells of the word line, which helps to make the write operation more efficient. Thus, in another embodiment shown in FIG. 6, the latch bit cell 600 includes a write mask. The write mask utilizes a write 1X (WRONEX) signal (where "X" indicates that the signal is active low) and a write 0 (WRZERO) signal. The write mask circuit is formed by transistors PWD601 and NWD603, where WD represents write data. When WRONEX is asserted (active low), the write data (WD) node is pulled high through transistor PWD, and when WRZERO is asserted, the WD node is pulled low through transistor NWD. The write mask allows the write word line for a row of cells to be asserted without changing the state of all cells. For example, by asserting the word line and using the write mask to ensure that only the target cells are written, only one byte or several bits on the word line can be changed. In addition to the transistors PWD and NWD used to determine the value of WD, the write-masked latch bit cell 600 includes transistors NFB2 and PFB2 used in the keeper circuit 605. These transistors are used to ensure that the feedback function of the keeper circuit continues to operate so that the latch bit cell maintains its state even when WWL and WWLX are asserted. When WWLX is asserted, NFB1 turns off, and when WWL is asserted, PFB1 turns off. Transistors NFB2 and PFB2 ensure that the keeper circuit continues to drive "D" with the correct value from the node between NFB0 and PFB0 when the bit has a write mask that effectively prevents writing to the latch bit cell when WWL and WWLX are asserted. Note that WD floats when WRONEX and WRZERO are de-asserted.By incorporating the PWD and NWD transistors into the bit cell itself, the capacitance on the intermediate node WD is kept low enough to avoid cell stability issues when WWL / WWLX is asserted. The keeper stack (KSTK) nodes PKSTK602 and NKSTK604 are labeled in FIG. 6.

[0018] FIG. 7 is a stick diagram of the layout of the write-masked latch bit cell 600 shown in FIG. 6. It should be noted that the solution in FIG. 6 increases the cell size by four transistors and includes extra dummy cells compared to the layout shown in FIG. 2. Thus, the write-masked latch bit cell 600 (FIG. 6) shows an increase from 3CPP to 10CPP compared to the layout of FIG. 2 (7CPP) for the latch bit cell 100 shown in FIG. 1.

[0019] FIG. 8 shows a more efficient embodiment of the write-masked latch bit cell 800 as compared to the write-masked latch bit cell 600 of FIG. 6. Note that the extra transistors NFB2 and PFB2 coupled to the keeper stack node in the write-masked latch bit cell 600 replace NFB1 and PFB1 in the write-masked latch bit cell 800. The write-masked latch bit cell 800 does not disable the keeper circuit 805 by turning off NFB1 and PFB1 when WWL and WWLX are asserted (see FIGS. 1 and 6). Instead, the write-masked latch bit cell 800 simply disables the keeper in response to WRONEX or WRZERO being asserted. This ensures that the latch bit cell 800 retains its state when the latch bit cell 800 is masked. Note that WWL and WWLX are coupled only to the passgate transistors PPG and NPG in the write-masked latch bit cell 800. When WRONEX is asserted (active low), transistor NFB2 turns off, and when WRZERO is asserted, transistor PFB2 turns off. Assuming WWLX and WWL are asserted, when WRONEX is asserted, node WD goes high, node D goes high, and when WRZERO is asserted (active low), node WD goes low, node D goes low. When each mask line (WRONEX and WRZERO) is de-asserted, both NFB2 and PFB2 turn on, and the keeper circuit maintains the value of node D according to the value of D_X provided by the inverter formed by transistors PINV and NINV. D_X turns on transistor NFB0 to maintain a low value for node D, or turns on PFB0 to maintain a high value for node D. The write mask circuit is formed by transistors PWD801 and NWD803, which is the same as the embodiment shown in FIG. 6.The read side of the written-mask latch bit cell 800 formed by transistors PRP1, PRP0, NRP0, and NRP1 is the same as the previous latch bit cell embodiments 100 and 600 shown in FIGS. 1 and 6, respectively.

[0020] Whenever either WRONEX or WRZERO is asserted, the keeper circuits of all bit cells in the column coupled to WRONEX and WRZERO are disabled. This is because by asserting WRONEX, NFB2 is turned off, preventing D_X from being pulled to VSS via NFB0 and NFB2, and by asserting WRZERO, PFB2 is turned off, preventing D_X from being pulled to BDD via PFB0 and PBF2. Thus, node D floats in response to the assertion of WRONEX or WRZERO. If the assertion of WRONEX or WRZERO is long enough, at least part of the keeper circuit is turned off due to NFB1 or PFB1 being disabled by the assertion of WRONEX or WRZERO, so the cells along the column can change state. Therefore, WRONEX and WRZERO should be asserted as pulse writes. Consequently, these signals should be asserted as self-timed pulses with a length of several inverter delays, for example 50 ps. The pulses can be generated using, for example, nine inverters. The number of inverters depends on the technology used. Figure 9 shows an embodiment of a pulse circuit 901 for WRZERO and a pulse circuit 903 for WRONEX. Note that an odd number of inverters is used in each of the pulse circuits shown in Figure 9. In Figure 9, the inputs (write 0 and write 1) to the logic gates are assumed to be active high. Many other pulse generator circuits that provide suitable pulse widths for WRONEX and WRZERO are known to those skilled in the art. The pulse should be long enough to write one cell, but short enough so that other cells along the column do not lose their state because node D floats during the pulse. Thus, compared to the write mask latched bit cell shown in Figure 6, the area penalty for additional write mask capabilities is relatively small.

[0021] Figure 10 shows an example of the layout of the circuit in FIG. 8. Note that only one dummy transistor is required for the latch bit cell 800. The layout of the latch bit cell 800 shown in FIG. 10 has only one extra CPP with respect to the baseline latch bit cell 100 shown in FIG. 2.

[0022] Figure 11 shows the latch array columns of the latch shown in FIG. 1, formed in a single standard cell row. Note that the term "single standard cell row" refers to the physical row of the integrated circuit and not the logical row of the SRAM. In a standard design using non-hybrid standard cell library rules, all devices typically have the same number of fins. In a conventional standard cell architecture, all rows of devices have the same height. In the world of finfets, this generally also means that the number of fins per finger is the same. FIG. 12A shows a conventional standard cell architecture of PFETs and NFETs having two fins per finger. Each standard cell is uniform in the row and has P and N transistors.

[0023] The hybrid standard cell architecture utilizes alternating rows of high-performance standard cells and high-density (but lower-performance) standard cells. For example, in one embodiment, this means that for high-performance cells there are two fins per transistor finger and for lower-performance cells there is one fin per transistor finger. As shown in FIG. 12B, it results in alternating rows of higher and lower cells and shorter rows. The advantage of the hybrid standard cell architecture is a smaller area and reduced power, but the shorter cell height results in a performance reduction compared to the larger two-fin cells. FIG. 12C shows an exemplary one fin per transistor finger device 1201 and two fins per transistor finger device 1203.

[0024] FIG. 13 shows that as a result of migrating from a conventional standard cell library to a hybrid standard cell library approach to construct a standard cell latch array, the performance between adjacent bits may become unbalanced. For example, the bit cells in column 1301 are formed from "fast" standard cells having, for example, two fins per finger. The logic SRAM column 1301 is within a physical fast row of the hybrid row architecture in the illustrated embodiment. The bit cells in column 1303 are "slow" cells having, for example, one fin per finger. Thus, reading Rddata[1] 1302 from any of the bit cells in column 1301 is done faster than reading Rddata[0] 1304 from column 1302. Thus, adjacent bits are read at different timings (one fast and the other slow), which is undesirable.

[0025] To provide more balanced performance between high-speed cells and low-speed cells, the embodiment shown in FIG. 14 uses a group of bit cells from one column, e.g., the bit cells within column 1401 (high-speed physical row) or 1403 (low-speed physical row), but uses a multiplexer circuit from other rows. For example, low-speed multiplexer 1407 selects one bit from 32 high-speed bit cells. The 32 high-speed bit cells are high-speed bit cell 1404 (only one of bits <15:0> is shown) and high-speed bit cell 1406 (only one of bits <31:16> is shown). High-speed multiplexer 1415 selects one bit from 32 low-speed bit cells. The 32 low-speed bit cells are low-speed bit cell 1409 (only one of bits <15:0> is shown) and low-speed bit cell 1411 (only one of bits <31:16> is shown). Similarly, high-speed bit cells 1421 and 1423 use low-speed multiplexer 1425, and low-speed bit cells 1427 and 1429 use high-speed multiplexer 1431. The read data (Rddata[1]) supplied by high-speed multiplexer 1435 has a high-speed multiplexer (2 fins), but has low-speed bit cells (1 fin), and the read data (Rddata[0]) has a low-speed multiplexer (1 fin), but has high-speed bit cells (2 fins). Thus, one logical SRAM column has high-speed bit cells and a low-speed multiplexer stage, while an adjacent SRAM logical column has low-speed bit cells and a high-speed multiplexer stage. This provides an improved performance balance compared to an array where every other bit has significantly different timings, i.e., high and low.

[0026] FIG. 15 shows a higher level block diagram of an array of bit cells. FIG. 14 shows the latch bit cell of FIG. 1 being utilized as the bit cells within columns 1401 and 1403, while in other embodiments, other bit cells can be used. FIG. 16 shows an embodiment in which the masked write latch bit cell 600 of FIG. 6 or the masked write latch bit cell 800 of FIG. 8 is utilized. FIG. 16 shows that the mask signals WRONEX and WRZERO signals are distributed to the bit cells.

[0027] As described above, a hybrid cell standard cell architecture having alternating rows of high performance standard cells and high density standard cells, in which the bit cells and multiplexing stages alternate to provide a more balanced read timing, has been described. The description of the invention set forth herein is illustrative and is not intended to limit the scope of the invention as set forth in the appended claims. Variations and modifications of the embodiments disclosed herein can be made based on the description set forth herein without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A static random access memory (SRAM), comprising: A first plurality of bit cells and a first plurality of multiplexer circuits; A second plurality of bit cells and a second plurality of multiplexer circuits; The first plurality of bit cells are coupled to a first multiplexer circuit among the second plurality of multiplexer circuits; The second plurality of bit cells are coupled to a second multiplexer circuit among the first plurality of multiplexer circuits; The first plurality of bit cells and the first plurality of multiplexer circuits have a first performance level, and the second plurality of bit cells and the second plurality of multiplexer circuits have a second performance level lower than the first performance level; A static random access memory (SRAM).

2. The SRAM includes rows in which a first cell having the first performance level and a second cell having the second performance level are alternately arranged. The SRAM according to Claim 1.

3. A third plurality of bit cells having the first performance level; A fourth plurality of bit cells having the second performance level; The third plurality of bit cells are coupled to a third multiplexer circuit among the second plurality of multiplexer circuits; The fourth plurality of bit cells are coupled to a fourth multiplexer circuit among the first plurality of multiplexer circuits. The SRAM according to Claim 1.

4. The first multiplexer circuit and the third multiplexer circuit are coupled to a fifth multiplexer circuit among the second plurality of multiplexer circuits; The second multiplexer circuit and the fourth multiplexer circuit are coupled to a sixth multiplexer circuit among the first plurality of multiplexer circuits. The SRAM of claim 3.

5. The first performance level is determined at least in part according to a first number of fins per transistor finger, the second performance level is determined at least in part according to a second number of fins per transistor finger, and the first number of fins is greater than the second number of fins. The SRAM of claim 1.

6. The first number of fins is 2 and the second number of fins is 1. The SRAM of claim 5.

7. The first plurality of bit cells form at least a part of a first column of the SRAM, and the second plurality of bit cells form at least a different part of a second column of the SRAM. The SRAM of claim 1.

8. The first column and the second column are adjacent within the SRAM. The SRAM of claim 7.

9. Each of the first plurality of bit cells and the second plurality of bit cells is a latch bit cell. The SRAM of claim 7.

10. Each of the first plurality of bit cells and the second plurality of bit cells is a write-masked bit cell. The SRAM of claim 7.

11. A method for operating a static random access memory (SRAM), comprising: Supplying a first bit cell output from a first plurality of bit cells having a first performance level to a first multiplexer having a second performance level, wherein the second performance level is lower than the first performance level, and Supplying any one of the first bit cell outputs as a first multiplexer output signal from the first multiplexer, and Supplying a second bit cell output from a second plurality of bit cells having the second performance level to a second multiplexer having the first performance level, and Supplying any one of the second bit cell outputs as a second multiplexer output signal, including Method.

12. Supplying a third bit cell output from a third plurality of bit cells having the first performance level to a third multiplexer having the second performance level and supplying a third multiplexer output signal, and Supplying a fourth bit cell output from a fourth plurality of bit cells having the second performance level to a fourth multiplexer having the first performance level and supplying a fourth multiplexer output signal, including The method of claim 11.

13. Supplying the first multiplexer output signal and the third multiplexer output signal to a fifth multiplexer circuit having the second performance level and supplying a fifth multiplexer output signal, and Supplying the second multiplexer output signal and the fourth multiplexer output signal to a sixth multiplexer circuit having the first performance level and supplying a sixth multiplexer output signal, including The method of claim 12.

14. Supplying the fifth multiplexer output signal as a read data bit from a first SRAM column (column), and supplying the sixth multiplexer output signal as another read data bit from a second SRAM column adjacent to the first SRAM column, The method of claim 13. **Claim 15** The first performance level is determined at least in part according to a first number of fins per transistor fin, the second performance level is determined at least in part according to a second number of fins per transistor fin, and the first number of fins is greater than the second number of fins. The method of claim 11. **Claim 16** The first number of fins is 2 and the second number of fins is 1. The method of claim 15. **Claim 17** supplying the first bit cell output from a first written masked bit cell and the second bit cell output from a second written masked bit cell The method of claim 11. **Claim 18** A static random access memory (SRAM) comprising: a first plurality of SRAM bit cells and a first multiplexer circuit formed within a first row of first cells having a first performance level; a second plurality of SRAM bit cells and a second multiplexer circuit formed within a second row of second cells having a second performance level lower than the first performance level; The second multiplexer circuit is coupled to receive a first output of each of the first plurality of SRAM bit cells and selects any one of the first outputs as a second multiplexer output signal; The first multiplexer circuit is coupled to receive a second output of each of the second plurality of SRAM bit cells and selects any one of the second outputs as a first multiplexer output signal. Static random access memory (SRAM).

19. The first plurality of SRAM bit cells and the second plurality of SRAM bit cells are in adjacent SRAM columns (columns). The SRAM of claim 18.

20. A third plurality of bit cells in the first row having the first performance level, A fourth plurality of bit cells in the second row having the second performance level, comprising: The third plurality of bit cells are coupled to a third multiplexer circuit in the second row, and the fourth plurality of bit cells are coupled to a fourth multiplexer circuit in the first row. The SRAM of claim 18.

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