Analog Circuit Design

Abstract

The primary design unit is configured to receive information representing technical requirements for the analog circuit, identify a plurality of circuit portions for forming the analog circuit based on the received information, determine, for each circuit portion of the plurality of circuit portions, respective technical criteria for the circuit portion, and generate a set of designs, including determining the respective technical criteria for each circuit portion and generating the set of designs with the respective designs for each circuit portion, obtaining, for at least one circuit portion, information related to parasitics that will occur in the analog circuit if the analog circuit includes the designed circuit portion, adapting the design of the at least one circuit portion based on the obtained information regarding the parasitics, and outputting a completed circuit design including the adapted at least one circuit portion based on the obtained information regarding the parasitics.

Description

Technical Field

[0001] The present disclosure relates to methods and systems for analog circuit design, and more particularly, to methods and systems for automating the design process of analog circuits.

Background Art

[0002] Analog components have the most manufacturing test defects in chips, accounting for 95% of the defects in the field. In recent years, although the circuit design of digital circuits has been automated to some extent, the automation of analog circuit design has been difficult so far due to problems such as parasitic effects. In conventional analog circuit design, designers often manually perform "best guess" estimates and specification guard banding based on past knowledge and experience. As a result, the circuit often becomes excessive, inefficient, and prone to failure. Therefore, in the design of analog circuits, it is desired to build a more efficient and reliable process.

Summary of the Invention

Means for Solving the Problems

[0003] Aspects of the present invention are as described in the independent claims, and any features are as described in the dependent claims. Aspects of the present invention may be provided in relation to each other, and features of one aspect may be applied to other aspects.

[0004] In a first aspect, an analog circuit design apparatus is provided. The analog circuit design apparatus receives information representing technical requirements of an analog circuit, identifies a plurality of circuit portions for forming the analog circuit based on the received information, determines respective technical criteria for each of the plurality of circuit portions with respect to each circuit portion, Generate a series of designs including respective designs for each of the circuit portions, For at least one circuit portion of the plurality of circuit portions, obtain information related to parasitic elements that occur in the analog circuit when the circuit portion in which the analog circuit is designed is provided, Based on the obtained information related to the parasitic elements, adapt the design of at least one circuit portion, Output a completed circuit design having at least one circuit portion adapted based on the obtained information related to the parasitic elements, Comprising at least one design unit configured as such.

[0005] It will be understood that obtaining information related to parasitic elements may include extracting information related to parasitic elements.

[0006] In such a design apparatus, it becomes possible to estimate and consider parasitic elements, which have been difficult in analog circuits until now, at the initial design stage. Furthermore, this analog circuit design apparatus can automatically design an analog circuit according to customer requirements by implementing machine learning. As a result, it is no longer necessary for a designer to manually redesign the analog circuit.

[0007] In some examples, information related to the context of a component or portion of a circuit may be obtained and used as part of the design process, that is, what occurs when that portion or component of the circuit is placed in situ in the completed circuit (in some examples the context may be provided as part of the technical criteria, but in other examples may be provided as something in addition to the technical criteria). The context may include parameters and variables that occur during use of the circuit portion or component. The context of any given circuit portion or component may be generated based on a simulation of the performance of the circuit portion(s) or component(s) that interact with that given circuit portion or component, or by simulation of the completed circuit comprising that given circuit portion or component. For example, at least one design unit may be configured to generate at least one respective design for a corresponding circuit portion based on the context of at least one other circuit portion.

[0008] It will be appreciated that the analog circuit design apparatus may comprise a primary design unit and a plurality of secondary design units. The primary design unit identifies a plurality of circuit portions for forming an analog circuit based on received information, determines respective technical criteria for each of the plurality of circuit portions for that circuit portion, and may be configured to provide the respective technical criteria for each circuit portion to at least one of the plurality of secondary design units.

[0009] Each of the plurality of secondary design units of the analog circuit design apparatus (a) designs each of the plurality of circuit portions based on the technical criteria provided by the primary design unit, (b) It may be configured to output a design that shows the results of each circuit part.

[0010] The primary design unit further (c) obtains a set of designs with each design for each circuit part from each of a plurality of secondary design units, (d) generates at least an initial design of the analog circuit based on the set of designs, (e) may be configured to obtain information related to parasitic elements that would occur in the analog circuit if the analog circuit includes that circuit portion.

[0011] At least one of the secondary design units may be configured to adapt the design of its respective circuit portion based on the information related to parasitic elements, The primary design unit may be configured to output a completed circuit design including the at least one adapted circuit portion.

[0012] In some examples, the analog circuit design unit is configured to input parasitic elements and circuit designs into a database by repeating steps (a) to (e) a plurality of times, and each time steps (a) to (e) are repeated, new technical criteria are provided by the primary design unit. The analog circuit design unit may be configured to repeat steps (a) to (e) for predefined circuit parts or elements that match a specific or selected circuit structure, and / or known or selected structures or functional blocks (such as DACs, level shifters, comparators, etc.). The predefined circuit portions may be susceptible to variations. For example, the bridge capacitors of a DAC depend on the parasitic elements of the input device and the total capacitance to the input stage of a comparator including any wiring.

[0013] The analog circuit design device may be configured to obtain information regarding parasitic elements that would occur in an analog circuit if the analog circuit had the circuit portion for which it was designed, by mathematically simulating the performance of at least one of (i) the design circuit portion and (ii) the completed analog circuit having the design circuit portion in a virtual test bench.

[0014] Additionally or alternatively, the design device may be configured to obtain information related to parasitic elements experienced in an analog circuit if the analog circuit had the circuit portion for which it was designed, by performing a lookup in a database of circuit designs and parasitic elements. The parasitic elements may be derived, for example, using various terms including, but not limited to, configuration, process, phase, and any other sizing factors, from a database lookup of individual circuit elements (portions of the circuit).

[0015] Additionally or alternatively, the analog circuit design device may be configured to obtain information regarding parasitic elements resulting from the generated design, by performing a lookup in the database of circuit designs and parasitic elements for similar generated designs. It will be understood that the similar generated designs may include designs having similarity, for example, greater than a selected threshold level of common features.

[0016] Additionally or alternatively, the design device is configured to perform a lookup in the database of circuit designs and parasitic elements for at least one of each of the similar circuit portions, and the design device is configured to obtain information related to parasitic elements experienced by the generated design based on the values of the parasitic elements obtained via the lookup for at least one of each of the circuit portions.

[0017] In some examples, the design device is configured to use a machine learning model to predict parasitic elements and obtain information related to the parasitic elements experienced by the generated design. Additionally or alternatively, the design device may be configured to use a machine learning model for predicting parasitic elements to obtain information related to the parasitic elements generated by each respective circuit portion. In some examples, the machine learning model may be trained using the design device.

[0018] It will be understood that the parasitic elements include at least one of parasitic capacitance, parasitic resistance, and parasitic inductance.

[0019] In some examples, the analog circuit design device is configured to adapt the design of each respective circuit portion when information about the parasitic elements generated by the generated design indicates that the parasitic elements are greater than a selected threshold level. In some examples, the technical criteria can specify an acceptable threshold level for the parasitic elements. In such examples, information about the parasitic elements generated by the generated design may indicate that the circuit (and / or portion of the circuit) no longer meets the technical criteria. In such examples, adapting the design of each portion based on the information related to the parasitic elements may include adapting the technical criteria, for example, adapting the technical criteria of at least one respective circuit portion.

[0020] In other aspects, a method for training a machine learning model for predicting parasitic elements in a designed analog circuit is provided. The method includes in each of a plurality of secondary design units of an analog circuit design device, (a) designing each respective circuit portion of the plurality of circuit portions based on technical criteria provided by a primary design unit, (b) outputting the design resulting from each respective circuit portion, in the primary design unit of the analog circuit design device, (c) Obtain a series of designs including the design of each circuit portion from at least one of the plurality of secondary design units, (d) Generate at least an initial design of the analog circuit based on the series of designs, (e) Obtain information related to at least one of the circuit portions and parasitic elements occurring in the generated design by mathematically simulating the performance of the design generated using a virtual test bench, Repeat steps (a) to (e) multiple times, and each time steps (a) to (e) are repeated, a new technical criterion is provided by the primary design unit.

[0021] In some examples, this method may further comprise step (f) of inputting into a database of parasitic elements and corresponding circuit designs. This step may be repeated when steps (a) to (e) are repeated. Next, the database may be used to train a machine learning model (such as a neural network, convolutional neural network, or deep learning module) to estimate, for example, the parasitic elements of circuit designs not included in the database. The neural network may comprise at least one of a deep residual network (ResNet), highway network, dense connection network (DenseNet), and capsule network.

[0022] In other aspects, a method for designing an analog circuit is provided. The method comprises Receiving information representing the technical requirements of the analog circuit, Identifying a plurality of circuit portions for forming the analog circuit based on the received information, Determining, for each circuit portion of the plurality of circuit portions, a respective technical criterion for the circuit portion, Generating a series of designs including the design for each circuit portion for each circuit portion, For at least one circuit portion among the plurality of circuit portions, when the analog circuit includes a circuit portion for which the analog circuit is designed, obtain information related to parasitic elements that occur in the analog circuit, Adapt the design of at least one circuit portion based on the obtained information related to the parasitic elements, Output a completed circuit design including at least one circuit portion adapted based on the obtained information related to the parasitic elements. It is provided with this.

[0023] The method further includes In the primary design device of the analog circuit design device, Based on the received information, identify a plurality of circuit portions for forming the analog circuit, For each circuit portion of the plurality of circuit portions, determine respective technical criteria for the circuit portion, It may be provided that the respective technical criteria for each circuit portion are provided to at least one of a plurality of secondary design units.

[0024] The method further includes In each of the plurality of secondary design units of the analog circuit design device, (a) Design each circuit portion of the plurality of circuit portions based on the technical criteria provided by the primary design unit, (b) Output the design resulting from each circuit portion, In the primary design unit, further (c) Obtain a series of designs including the respective designs of each circuit portion from each of the plurality of secondary design units, (d) Generate at least an initial design of the analog circuit based on the series of designs, (e) It may be provided to obtain information related to parasitic elements that would occur in the analog circuit when the analog circuit includes the circuit portion.

[0025] It will be understood that obtaining information related to parasitic elements may include extracting information related to parasitic elements.

[0026] The method further in at least one of the secondary design units, adapting the design of each circuit portion based on information related to parasitic elements, and in the primary design unit, outputting a completed circuit design including at least one adapted circuit portion may also be included.

[0027] The method comprises inputting parasitic elements and circuit designs into a database by repeating steps (a) to (e) a plurality of times, and each time steps (a) to (e) are repeated, new technical criteria may be provided by the primary design unit. The method may comprise repeating steps (a) to (e) for predefined circuit portions or elements that match a specified or selected circuit structure, and / or for known or selected structures or functional blocks (e.g., DAC, level shifter, comparator, etc.). The predefined circuit portions may be susceptible to variations. For example, the bridge capacitors of a DAC depend on the parasitic elements of the input device and the total capacitance to the input stage of a comparator including any wiring.

[0028] In some examples, the method includes obtaining information related to parasitic elements that would occur in an analog circuit if the analog circuit had its designed circuit portions by mathematically simulating the performance of the generated design in a virtual test bench.

[0029] Additionally or alternatively, the method may include obtaining information related to parasitic elements that would occur in an analog circuit if the analog circuit had its designed circuit portions by performing a lookup in a database of circuit designs and parasitic elements.

[0030] Additionally or alternatively, the method may include obtaining information regarding parasitic elements that would occur in an analog circuit if the analog circuit comprised the circuit portion for which it was designed, by performing a lookup in a database of circuit designs and parasitic elements for similar generated designs. It will be understood that the similar generated designs may comprise designs having a similarity greater than a selected threshold level of common features, for example.

[0031] Additionally or alternatively, the method may include, for each respective circuit portion that is similar, performing a lookup in a database of circuit designs and parasitic elements for at least one of the respective circuit portions, and obtaining information related to parasitic elements that would occur in an analog circuit if the analog circuit comprised the circuit portion for which it was designed, based on the values of the parasitic elements obtained via the lookup for at least one of the respective circuit portions.

[0032] Additionally or alternatively, the method may include obtaining information related to parasitic elements that would occur in an analog circuit if the analog circuit comprised the circuit portion for which it was designed, using a machine learning model to predict the parasitic elements. Additionally or alternatively, the method may include obtaining information related to parasitic elements caused by each respective circuit portion, using a machine learning model for predicting parasitic elements. In some examples, the machine learning model may be one learned using a design device.

[0033] It will be understood that the parasitic elements include at least one of parasitic capacitance, parasitic resistance, and parasitic inductance.

[0034] In some examples, adapting the design of each such circuit portion is performed when information related to parasitic elements indicates that the parasitic elements are greater than a selected parasitic threshold level. In some examples, the technical criteria can specify an acceptable threshold level for the parasitic elements. In such examples, information regarding parasitic elements resulting from the generated design may indicate that the circuit (and / or portion of the circuit) no longer meets the technical criteria. In such examples, adapting the design of each portion based on the information related to the parasitic elements may include adapting the technical criteria, for example, adapting the technical criteria of at least each circuit portion.

[0035] In some examples, adapting the design of each portion based on the information related to the parasitic elements includes adapting the corresponding technical criteria of each circuit portion.

[0036] It will be appreciated that the method may further include fabricating an analog circuit for the output design.

[0037] In other aspects, a computer-readable non-transitory storage medium is provided that includes a computer program configured to cause a processor to execute any of the methods described above.

Brief Description of the Drawings

[0038]

Figure 1A

Figure 1B

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6A

Figure 6B

Figure 7

[0039] Next, embodiments of the present disclosure will be described by way of example only with reference to the accompanying drawings.

[0040] FIG. 1A is a simplified functional schematic diagram of an exemplary analog electronic circuit, which in this example is an analog-to-digital converter (ADC) 1000. The analog circuit may include several portions or components such as a comparator 1001, a DAC 1002, a level shifter 1003, and an operational amplifier 1004. Initially, each portion or component may be considered separately, but when applied in situ to the entire circuit, the context or environment in which the portion or component operates may affect how the component / block operates and thus the parasitic elements that occur in the circuit portion or the entire circuit. The design of analog circuits has hitherto proven difficult to automate due to complex feedback loops and mathematical relationships between different portions / components of the analog circuit.

[0041] Embodiments of the claims relate to a method and system for automating the design of analog circuits that can predict or anticipate parasitic elements in a designed circuit or a portion of a designed circuit so as to enable more efficient circuit design. The inventors have achieved this by developing a computer-implemented model that delegates the responsibility of designing portions or components of an analog circuit to respective units or “blocks”. An example of such a model is shown in FIG. 2. Such a hierarchical model includes the use of a primary design unit called a “parent block” 900 that functions as a control entity, and a number of secondary design units called “child blocks” 950a-d that receive instructions regarding what needs to be designed from the primary design unit or the parent block. Each secondary design unit or child block 950a-d is configured to design respective components or portions of an analog circuit based on the instructions received from the parent 900. The instructions include the technical requirements (“criteria”) that the component or portion should meet (e.g., functional requirements, etc.).

[0042] The indication may also include information related to the context of that component or portion of the circuit, that is, information about what happens when that portion or component of the circuit is placed in situ in the completed circuit (in some examples, the context may be provided as part of the technical criteria, but in other examples may be provided as something in addition to the technical criteria). The context may include parameters and variables that occur during use of the portion or component of the circuit. The context of any given circuit portion or component may be generated based on a simulation of the performance of the circuit portion(s) or component(s) that interact with that given circuit portion or component, or alternatively by simulation of the completed circuit comprising that given circuit portion or component. For example, the parent block 900 may be configured to assemble a circuit from the portions or components designed by each of the child blocks 950a - d and simulate the operation of the assembled circuit. The context of any given circuit portion or component may be generated additionally or alternatively based on mathematical calculations or extraction.

[0043] By designing the analog circuit in this way, parasitic elements that occur in each circuit portion, or in a circuit comprising some of each circuit portion, can be estimated (e.g., by the parent block 900), and if necessary, an adaptation circuit can be created that mitigates the parasitic elements.

[0044] The computer-implemented hierarchical model is iterative. When the parent block 900 instructs each of the child blocks 950a - d to design their respective portions, some redesign of the circuit and its respective portions may be required to account for parasitic elements and / or optionally context that arise from each circuit portion designed by the other child blocks 950a - d.

[0045] In particular, when the initial design of a circuit portion or a completed analog circuit is performed, it may be necessary to adapt the design of one or more circuit portions and / or the completed analog circuit due to estimated parasitic elements that may be caused by a particular circuit portion or the completed analog circuit. Thus, the process of designing a circuit portion may be repeated to adapt the design of one or more circuit portions to account for the estimated parasitic elements in an attempt to mitigate and reduce the parasitic elements. This process of adapting the design of a circuit portion may be repeatedly iterated by sub-blocks 950a-d until, for example, changes in the estimated parasitic elements caused by adjustments to other portions or components of the analog circuit are taken into account. For example, this process may be repeatedly performed until the change in the estimated parasitic elements is less than a selected threshold level of parasitic element change.

[0046] The parasitic elements of any given circuit portion may be generated based on a simulation of the performance of the circuit portion(s) that interact with the given circuit portion or, alternatively, by simulation of the completed circuit that includes the given circuit portion. For example, parent block 900 may be configured to assemble a completed circuit from the portions designed by each of sub-blocks 950a-d and simulate the operation of the assembled circuit. The parasitic elements of any given circuit portion may additionally or alternatively be generated based on mathematical calculations or extraction. Additionally or alternatively, the parasitic elements of any given circuit portion may be obtained by performing a lookup in a database of circuit designs and parasitic elements and / or may be predicted using a machine learning model.

[0047] The inventors have advantageously found that the design of analog circuits can be automated by such an iterative hierarchical model. As a result, it is possible to avoid over-designed analog circuits and circuits with unacceptable parasitic elements and to design and create more efficient circuits.

[0048] As described above, FIG. 1A shows an exemplary analog circuit 1000 that is an analog-to-digital converter (ADC) in this example. Conceptually, the circuit can be divided into functional blocks corresponding to different portions or components of the circuit, for example, based on their respective functionality. For example, the ADC may include a comparator 1001, a digital-to-analog converter (DAC) 1002, a plurality of level shifters 1003, and one or more operational amplifiers 1004. In the example shown in FIG. 1A, the circuit can be conceptually divided into blocks corresponding to these different portions or components. For example, as shown in FIG. 1B, the comparator can be conceptually divided into a first "child block" 950a, the DAC into a second child block 950b, the level shifters into a third child block 950c, and the operational amplifier into a fourth child block 950d. The ADC may, as a whole, be conceptually classified as its own block (labeled "parent" 900 in FIG. 1B). It will be understood that the ADC itself may form a conceptual block within a larger analog circuit.

[0049] As described above, when used in situ, there are interactions between each of the different blocks of the analog circuit. These in-situ interactions between the blocks (which may include parasitic elements that occur in each portion when placed in the completed circuit), and thus the parameters and variables that occur in each block when placed in that circuit, affect the performance of the circuit. For example, the specifications of the operational amplifier used in the circuit may depend on many parameters and variables resulting from the selection and design of the comparator, DAC, and / or level shifters, and the connections between them.

[0050] The inventors have thus recognized that the design and selection of each circuit portion should be done in a way that takes into account the parasitic elements that occur in the completed circuit and / or each circuit portion (optionally, the interactions arising from the context of each circuit portion as well), such that a completed analog with minimized parasitic elements is designed.

[0051] A non-exhaustive list of examples of parameters and variables that may affect the selection and design of these different blocks includes silicon process, temperature range, output load, output impedance, input capacitance, input common-mode range, input differential swing, supply voltage, type of transistors available, output common-mode range, output swing, settling time, noise tolerance, power supply rejection ratio (PSRR), common-mode range - input (input CMR), common-mode range - output (output CMR), linearity, maximum offset, bandwidth, minimum slew rate, intrinsic delay, minimum phase margin, dynamic power consumption, static power consumption, IP3 point, filter center frequency, filter bandwidth, load step response, line step response, output accuracy, noise figure, calibration range, noise floor, SNR, ENOB, SINAD, output frequency range, jitter - ptp, jitter - RMS, output ripple ptp, total harmonic distortion, start-up time, channel isolation, reference voltage, gain error, offset error, gain drift. These parameters and variables may be referred to as the "context" or environment in which the block is placed. To create an optimal analog circuit, knowing this context can improve the circuit design.

[0052] However, it will of course be understood that the design of analog circuits is an iterative process, and that the selection and tuning of one block can affect the context of other blocks, etc. Thus, when the components of one block are selected / tuned to form a circuit portion, the components of another block may need to be adjusted or reselected, taking into account the parasitic elements that occur in the completed circuit / circuit portion and / or optionally the new context in which that block is placed. Such an iterative process is not practical to perform manually, is error-prone, and can only be detected by communication.

[0053] As described above, an example of a computer-implemented model for use in a method of automating the design of analog circuits is shown in FIG. 2. FIG. 2 schematically shows the above-described blocks shown in FIG. 1B and the interactions between the blocks.

[0054] In the example shown in FIG. 2, each block of the model is responsible for the design of the component / functionality represented by that block. In FIG. 2, child 1-950a is responsible for the design of comparator 1001, child 2-950b is responsible for the design of DAC 1002, child 3-950c is responsible for the design of level shifter 1003, and child 4-950d is responsible for the design of op-amp 1004. Parent block 900 is responsible for the overall design of ADC 1000 and delegates the responsibility for the design of the portions / components / functionalities of the ADC to child blocks 950a-d. In some examples, parent block 900 may select how many child blocks 950a-d are needed and the responsibilities assigned to each block. Although child blocks 950a-d are shown in order, it will be understood that this order does not necessarily represent the order in which the portions of the circuit are designed. For example, parent block 900 may instruct the child block 950d responsible for the op-amp to design the portion of the circuit first. In some examples, child blocks 950a-d may be configured to first design the output and work backwards from there.

[0055] Each circuit portion may initially be designed separately by its respective block, but the context in which each circuit portion operates when applied to the entire circuit in place can affect not only each circuit portion but also how the entire circuit operates. This operation includes parasitic elements that occur in the entire circuit during use. Thus, while the parent block can instruct each child block to design its respective portion, if the initial version of the designed circuit is assembled by the parent 900 from the portions or components designed by each of the child blocks 950a-d, it is conceivable that some adaptation or redesign of the circuit 1000 and its portions or components must take into account the parasitic elements obtained and the context generated by the portions designed by the other child blocks 950a-d as options. As described above, this is an iterative process.

[0056] Accordingly, the parent block 900 functions as a controller and is configured to process and handle the design processes executed by each child block. To perform this function, as shown in FIG. 2, the parent block 900 may be composed of a number of different modules each configured to perform a different function as part of the design process. The parent block in FIG. 2 includes an instructor module 901, an assembly module 902, and a verification and simulator module 903.

[0057] The instructor module 901 receives the customer requirements for the circuit to be designed, along with other requirements such as PDK / conditions / control parameters etc. as instructed by the foundry, and is configured to convert these into a set of technical criteria that each of the sub - blocks 950a - d needs to meet when designing the respective components of the circuit. Also, it is configured to create instructions regarding what each of the sub - blocks 950a - d needs to design and the criteria that need to be met when doing so, and send them to each of the sub - blocks 950a - d. The instructions may also include the context of other designed portions of the circuit designed by other sub - blocks and the broader context of the circuit in which the components or portions of the circuit are intended to operate. For example, the technical criteria may be adjusted taking the context into account.

[0058] The assembly module 902 receives and collates all of the respective designed portions or components of the analog circuits provided by each of the sub - blocks 950a - d, and is configured to assemble a complete analog circuit based on the respective designed portions or components. The completed analog circuit may then be tested by the verification and simulator module 903.

[0059] The verification and simulator module 903 receives the designed components from each of the sub - blocks, compares them with a set of technical requirements, and is configured to determine whether the designed portions or components are satisfactory. This may include comparing their performance against the customer requirements, for example, by verifying whether each of the designed circuit portions or components meets the corresponding technical criteria and / or whether the designed analog circuit meets the customer requirements. Additionally or alternatively, it may include verification checks to determine whether the designed circuit is valid in the sense that it is operable within certain technical limitations.

[0060] Also, the verification and simulator module 903 functions as a "test bed" and is configured to simulate the functionality of the assembled components of the circuit. Such simulation can obtain not only parasitic element information but also optional context information. For example, the verification and simulator module 903, in a virtual test bench, by mathematically simulating the performance of at least one of (i) the designed circuit portion and (ii) the complete analog circuit including the designed circuit portion, may be configured to obtain information related to parasitic elements that would occur in the analog circuit if the analog circuit included the designed circuit portion. Additionally or alternatively, the verification and simulator module 903 may be configured to obtain information related to parasitic elements that would occur in the analog circuit if the analog circuit included the designed circuit portion, for example, by performing a lookup in a database of circuit designs and parasitic elements. Additionally or alternatively, the verification and simulator module 903 may be configured to perform a lookup in a database of circuit designs and parasitic elements for at least one of each circuit portion and for each similar circuit portion, and obtain information related to parasitic elements that occur in the design generated based on the values of the parasitic elements obtained through the lookup for at least one of each circuit portion. In other examples, the verification and simulator module 903 is configured to obtain information related to parasitic elements that occur due to the generated design by using a machine learning model to predict the parasitic elements.

[0061] Also, the verification and simulator module 903 may be configured to input parasitic elements and circuit designs into the database, for example, when the instructor module 901 instructs to repeat the process of designing circuit portions based on corresponding (new or adapted) technical criteria for the sub - blocks 950a - d multiple times.

[0062] The verification and simulator module 903 may further compare the simulated function of the circuit with the customer requirements and optionally verify whether the designed circuit portion meets its corresponding technical criteria and / or whether the designed analog circuit meets the customer requirements. In some examples, it will be understood that the simulator module may replace the verification module 903.

[0063] Also, each of the sub-blocks 950a - d includes a number of different modules configured to perform different functions as part of the design process. In the example shown in FIG. 2, each of the sub-blocks 950a - d includes converter modules 951a - d, assembly modules 952a - d, and simulator modules 953a - d. In some examples, it will be understood that each of the sub-blocks 950a - d may further include additional modules for instructing a tertiary design unit or "grandchild" block, similar to the way the parent block 900 of FIG. 2 includes an instructor module and a verification module for instructing and verifying the design process from the sub-blocks 950a - d, as will be described in more detail below with reference to FIGS. 3 - 6.

[0064] The converter modules 951a - d of each of the sub-blocks 950a - d receive the technical criteria received from the parent block 900, and optionally the context of the entire circuit, as well as the context of the other components of the circuit, and are configured to convert these into a set of requirements for designing a portion or component of the analog circuit to meet these criteria. In some examples, it will be understood that the context information may be provided and received as part of the technical criteria, while in other examples it may be provided in addition to (e.g., separately from) the technical criteria.

[0065] The assembly modules 952a - d are configured to select and / or design electronic components to meet the required requirements that satisfy the criteria indicated by the context of the parent block and the overall circuit and / or the context of other components of the circuit.

[0066] Also, the simulator modules 953a - d may be configured to simulate how those components operate in place to confirm / verify whether the design portion or components designed by the assembly module are technically feasible. In some examples, the simulator modules 953a - d may also obtain information related to the parasitic elements of each circuit portion designed by that block in a manner similar to the verification and simulator module 903 of the parent block 900 described above (in such examples, it will be understood that the verification and simulator module 903 of the parent block 900 may not need to obtain information related to parasitic elements since it may already be performed by the simulator modules 953a - d of each sub - block 950a - d).

[0067] In use, the parent block 900 receives a set of requirements for the analog circuit 1000 to be designed. In the example shown in FIG. 2, the parent block 900 receives a set of requirements for an ADC to be designed that has characteristics including performance indicated by the foundry that will manufacture the ADC, for example. The parent block 900 receives these requirements, and the instructor module 901 converts them into a set of technical criteria. These technical criteria are then sent to each of the sub - blocks 950a - d.

[0068] The instructor module 901 may send these technical criteria to each of the sub - blocks 950a - d in parallel (i.e., all at the same time) or in series (e.g., the criteria are sent to child 1 first, then child 2, then child 3, etc.). In some examples, the instructor module 901 may wait until it receives the design circuit from the first child before sending a series of technical criteria to the next child. In some examples, the instructor module may be configured to adjust the technical criteria sent to the next child based on the design circuit received from the previous child - in other words, based on the context of the design circuit received from the previous child.

[0069] In an example where the technical criteria are sent to the sub - blocks 950a - d in series, the technical criteria may include means for distinguishing which part of the technical criteria is relevant to which sub - block 950a - d - for example, the technical criteria may include a header or flag that identifies whether a particular part of the technical criteria is relevant to the sub - blocks 950a - d. These headers or flags are determined by the parent block 900, and the technical criteria may be adjusted as appropriate to incorporate them.

[0070] Each of the sub - blocks 950a - d receives these technical criteria from the parent block 900, and each of the converter modules 951a - d converts them into a set of requirements for designing the analog circuit portions or components to meet these technical criteria. The assembly modules 952a - d receive these requirements and design the components / portions of the circuit that meet these requirements. It will be understood that this design process may include a lookup in a database of known circuit designs (or portions) and finding the circuit design that best matches the technical criteria.

[0071] Next, the simulator modules 953a - d simulate how these components / portions operate in place in order to check whether the designed components / portions of the circuit designed by the assembly module are technically feasible and / or verify whether each corresponding designed circuit portion meets its corresponding technical criteria. If the designed circuit portion meets the corresponding technical criteria, the sub - blocks 950a - d are then configured to send back or output the designed portion or components of the circuit to the parent 900. If the designed circuit portion does not meet its corresponding technical criteria, the sub - blocks 950a - d are then configured to adapt the design of that circuit portion and repeat the process.

[0072] When the parent 900 receives all of the designed portions or all of the components of the circuit from all of the sub - blocks 950a - d, the assembly module 902 of the parent 900 then assembles the completed circuit (in this case, the ADC) from the portions or components designed by each sub - block and verifies, via the verification and simulator module 903, whether the designed circuit meets the technical requirements. This may be done by simulating how the assembled circuit operates and comparing this simulated performance to the customer requirements and / or technical requirements. In some examples, this simulated performance of the completed analog circuit design may be used to obtain parasitic elements and / or any context information (e.g., for another design unit), and it will be understood that the parent 900 may adjust the technical criteria based on the parasitic elements and / or any context information obtained via the simulation of the completed analog circuit design.

[0073] If the simulated performance of the designed circuit does not meet the customer requirements or technical requirements (for example, the parameters of the simulation circuit are different from the parameters specified by the technical requirements by a threshold or more, such as the parasitic elements being above the threshold), the verification module 903 transmits this to the instructor module 901. The instructor module 901 may then adjust the technical criteria based on the difference between the simulated performance of the circuit and the technical requirements, and send these modified technical criteria back to the sub-blocks 950a - d.

[0074] In some examples, the parent block 900 (for example, the verification module 903 / instructor module 901) determines which portion or component of the circuit is the cause of the circuit not meeting the technical requirements (for example, which portion has a large proportion of parasitic elements), and if the sub-block(s) 950a - d can be identified, the parent block 900 may be configured to send the modified technical criteria only to the sub-block responsible for the problematic portion or component of the circuit. However, in other examples, the modified criteria may be sent back to all the sub-blocks 950a - d. Also, in some examples, it will be understood that the parent module 900 may additionally and / or alternatively determine the sub-blocks 950a - d and / or grandchild blocks that may be required to design the relevant portion or component of the circuit in order to meet the modified technical criteria, for example.

[0075] Thereafter, the process continues iteratively, and the converter modules 951a - d of each sub - block 950a - d receive these modified or adapted technical criteria from the parent block 900 and convert them into a new set of requirements for designing the analog circuit portions or components to meet these adapted technical criteria. The assembly modules 952a - d receive these new requirements and design the circuit components / portions that meet these requirements. Next, the simulator modules 953a - d simulate how the components / portions of the redesigned circuit would operate in - situ and may check whether the components / portions of the circuit designed by the assembly module are technically feasible. And the sub - blocks 950a - d are configured to send back the (re)designed components / portions of the circuit to the parent 900.

[0076] When the parent 900 receives all of the (re)designed components / portions of the circuit from all of the sub - blocks 950a - d, the parent 900 then assembles the complete circuit (in this case, the ADC) from the components / portions designed by each sub - block, simulates how the assembled circuit operates, and verifies whether the designed circuit meets the technical requirements via the verification and simulator module 903 that can compare the simulated performance with the technical requirements. If the simulated performance does not meet the technical requirements, the process is repeated by sending back a modified set of criteria to the sub - blocks 950a - d. In some examples, the parent 900 (such as the verification and simulator module 903) may input the designed circuit / circuit portions and their simulated parasitic elements into a database, for example, for use in training a machine - learning model or for estimating future parasitic elements.

[0077] Also, it will be understood that the child blocks 950a - d and / or the parent block 900 may include a loop relaxation module to prevent the occurrence of an endless redesign loop. For example, the loop relaxation module may have a record of a previously designed circuit, and when a component / portion of the redesigned circuit or the completed circuit is identical to a component / portion of the previously designed circuit or the completed circuit, or differs from the component / portion of the previously designed circuit or the completed circuit by less than a selected threshold level, it may be configured to output a loop indication. For example, the parent block 900 may include a loop relaxation module and may be configured to end the design process and accept the last designed circuit as the completed circuit when the loop relaxation module provides a loop indication. Additionally or alternatively, the parent block 900 may be configured to reduce the selected threshold level of the difference, for example, when the design process is repeated for a selected number of iterations. This can have the effect of finding a functional circuit at the "best compromise point" that meets the technical requirements.

[0078] Figure 3 is a functional schematic diagram of another example of a computer - implemented model for designing an analog circuit. The implementation of this model is similar in many respects to the model shown in Figure 2, and the functions described above for the parent block 900 and the child blocks 950a - d with respect to Figure 2 may be attributed to the parent block and the child blocks in Figure 3. Further, some of the functions described with respect to the primary design unit or the parent block 900 in Figure 2 may be attributed to the secondary design unit or the child blocks 950a - d in Figure 3 where the child blocks have tertiary design units or "grandchild" blocks, etc. below them.

[0079] More specifically, as shown in FIG. 3, the model hierarchy includes a core design layer that includes a primary design unit or a parent block. Only one parent block 900 is shown in the core design layer of FIG. 3, but it will be understood that in some examples, there may be multiple parent blocks 900, for example, when each parent block 900 operates in parallel. For example, each parent block 900 may be configured to design different aspects of an analog circuit (e.g., different from each other functionally and / or structurally).

[0080] Below the core design layer is the first design layer. The first design layer includes secondary design units or child blocks 950 coupled to the parent block 900 of the upper layer (in this case, the core design layer). In this example, there are six child blocks, all of which are coupled to the parent block of the core design layer. The child blocks 950 are grouped into a first group consisting of child blocks 1, 2, 3 and a second group consisting of child blocks 3, 4, 5. Each child block 950 is coupled to the parent block 900. The two groups may represent different functional regions or areas of the analog circuit that instruct the parent block 900 to design in parallel.

[0081] In the illustrated example, the child blocks 950 of the first group are coupled in parallel to the parent block 900 of the core design layer, and the child blocks 950 of the second group are coupled in parallel to the parent block 900 of the core design layer. The child blocks 950 may be grouped in this way to design different regions or aspects of the analog circuit (e.g., different from each other functionally and / or structurally). However, it will be understood that in some examples, it is not necessary for all child blocks 950 of the first design layer to be coupled in parallel to the parent block of the core design layer. For example, child blocks 1 and 3 of the first design layer may be coupled to the parent block 900 of the core design layer, and child block 2 of the first design layer may be coupled in series to child blocks 1 and 3 of the first design layer, respectively.

[0082] The grouping of the sub-blocks 950 may be determined by the parent block 900 of the core design layer. For example, the parent block 900 may be configured to group the sub-blocks of the first design layer so as to design different aspects of the analog circuit (e.g., different from each other functionally and / or structurally). The parent block 900 of the core design layer may be configured to do this based on the determination of requirements from the customer specifications.

[0083] Below the first design layer, there is a second design layer. The second design layer includes tertiary design units or great-grandchild blocks 1, 2, 3, 4, 5, 6, 7, 8 - 960. The great-grandchild blocks 960 are coupled to the sub-blocks of the upper layer (the first design layer). Not all of the sub-blocks of the first design layer are coupled to the great-grandchild blocks of the second design layer. In the illustrated example, the great-grandchild blocks 1, 2, 3 of the second design layer are coupled in parallel to the sub-block 2 of the first design layer. However, as described above for the sub-block 950 of the first design layer, it will be understood that in some examples, it is not necessary for all of the great-grandchild blocks of the second design layer to be coupled in parallel to the sub-blocks of the first design layer. For example, the great-grandchild blocks 1 and 3 of the second design layer may be coupled to the sub-block 2 of the first design layer, and the great-grandchild block 2 of the second design layer may be coupled in series to the great-grandchild blocks 1 and 3 of the second design layer, respectively.

[0084] Below the second design layer, another (nth) design layer is arranged. The nth design layer includes great-great-grandchild blocks 1, 2, 3, 4 - 970. The great-great-grandchild blocks 970 are coupled to the great-grandchild blocks 960 of the upper layer (the second design layer) in substantially the same way as the great-grandchild blocks 960 of the second design layer are coupled to the sub-blocks 950 of the first design layer. Thus, it will be understood that below the second design layer, there may be a plurality of additional design layers each having its own blocks coupled to the blocks of the upper layer.

[0085] The block hierarchy structure shown in FIG. 3 is such that blocks of different layers of the model are configured to design analog circuit aspects or portions at different levels of complexity. For example, the parent block 900 is configured to design a complete analog circuit, the child block 950 is configured to design functional components of an analog circuit (operational amplifiers, AC / DC converters, level shifters, comparators, voltage regulators, power switches, etc.), and the grandchild block 960 may be configured to design components of those functional components (e.g., an array of resistors, transistors, capacitors, diodes, inductors, etc. for that component). However, it will be understood that the grandchild block 960 may be configured to design more hierarchical blocks such as operational amplifiers or voltage references or comparators, etc.

[0086] (Of the core design layer) The parent block 900 may be configured to determine the level of complexity that the blocks of the selected layer are configured to design, and / or the blocks of a layer may be configured to determine the level of complexity that the blocks of the lower layer are configured to design.

[0087] Additionally or alternatively, the block hierarchy structure shown in FIG. 3 is such that blocks of different layers of the model are configured to design analog circuit aspects or portions based on different functional or structural requirements. For example, one layer may comprise blocks configured to design an analog circuit aspect or portion based on a certain functional requirement (e.g., size), and another layer may comprise blocks configured to design based on another functional requirement (e.g., current or voltage).

[0088] FIG. 4 shows a functional schematic flowchart of a method for designing an analog circuit using, for example, an example of the computer-implemented hierarchical model of FIG. 2 or FIG. 3.

[0089] More specifically, in step 300, the parent block 900 receives customer requirements. The customer requirements may define, for example, the function of the circuit and specific restrictions required from the circuit such as peak current, voltage, etc. Also, the customer requirements may specify other characteristics such as the PDK / foundry where the circuit is to be manufactured. The parent block 900 is configured to convert the customer requirements 302 into a set of technical criteria. The parent block 900 may be additionally or alternatively configured to determine whether to send these technical criteria to the child blocks 950 in parallel or in series, and / or whether to send a different set of criteria to the lower-level child blocks 950.

[0090] Also, at this stage, the parent block 900 may be configured to determine the number of layers of the model, or alternatively, to determine whether a lower-level block is required when each layer block designs the portion of the circuit that is tasked to be designed by the upper-level block.

[0091] After converting the customer requirements into criteria (302), the parent block 900 then sends this to the first-layer child blocks (304). In the illustrated example, the parent block 900 sends the technical criteria in parallel to Child 1, Child 2, and Child 3 (304).

[0092] In this example, upon receiving the technical criteria, Child 1 determines that it is necessary to involve the lower-level block (grandchild block 960) (306) and instructs Grandchild 1 to design the first portion of the circuit based on those criteria. At the same time, Child 2 designs the first third portion of the circuit based on the technical criteria (307), and Child 3 designs the first fourth portion of the circuit based on the technical criteria (308).

[0093] Grandson 1 designs the first portion of the circuit based on the technical criteria (308), sends the designed first portion back to Child 1 (312), and Child 1 forwards it to the parent (optionally, after performing some simulation / verification first). Next, Child 1 instructs Grandson 2 to design the second portion of the circuit based on the criteria (314). Grandson 2 designs the second portion of the circuit based on the criteria (316), sends it back to Child 1 (318), and Child 1 may forward it to the parent.

[0094] Once Child 1 has designed the first and second portions of the circuit (via Grandson 1 and Grandson 2), Child 1 sends the context information to Child 2 (320). Child 2 may adapt or adjust the technical criteria received from the parent based on the context information obtained from Child 1. Next, Child 2 adapts the initially designed third portion of the circuit based on the context information received from Child 1.

[0095] In the example shown in FIG. 4, when the third portion of the circuit is designed by Child 2, the designed adapted third portion may be sent to the parent, and the context information may be sent to Child 3 (324). The context information may include the context created by the first, second, and third portions of the circuit. Next, Child 3 adapts the initial design of the fourth portion of the circuit based on the received context information (326) and sends the designed fourth portion to the parent block 900 (328).

[0096] When the parent block 900 receives all the designed portions of the circuit, the parent block 900 generates an initial design for the analog circuit based on a series of designs obtained from the child blocks, and checks or verifies (330) whether the designed initial design for the analog circuit meets the customer requirements. As described above, the parent block 900 may do this by employing a verification and simulation module to simulate the performance of the completed circuit. The parent block 900 also obtains information related to parasitic elements that would occur in the analog circuit if the analog circuit included all of the designed circuit portions.

[0097] If the designed completed circuit does not meet the customer requirements, the parent block may directly resend the adjusted criteria to the block responsible for designing the portion of the circuit that caused the failure to meet the requirements, along with additional information about what needs to be adjusted (and optionally by which block) (332) - for example, the criteria may be adjusted taking into account additional information for redesigning the block to meet the customer requirements. In some examples, the parent block 900 may simply send back only the designed portion of the circuit to the block responsible for designing that portion (332) - for example, the parent block 900 may send back, for example, the first portion of the analog circuit to grandchild 1, along with information about what needs to be adjusted and / or the adjusted criteria.

[0098] It will be understood that in the above examples, the first, second, third, and fourth portions of the analog circuit may be independent portions of the circuit and / or may be functionally dependent on each other. In other examples, the first, second, third, and fourth portions of the analog circuit may be a selected subset of the analog circuit. For example, the second portion may constitute part of the first portion, the third portion may constitute part of the first and second portions, and the fourth portion may constitute part of the first, second, and third portions.

[0099] In the example shown in FIG. 4, the parent block obtains information related to parasitic elements only after all child blocks have designed their respective circuit portions. However, in some examples, the parent block 900 may obtain information related to parasitic elements after each child block has designed its portion and before the next child block designs its respective circuit portion.

[0100] FIG. 5 shows a functional schematic flowchart of another exemplary method for designing an analog circuit using, for example, the exemplary computer-implemented hierarchical model of FIG. 2 or FIG. 3. The method of FIG. 5 has many features in common with the method of FIG. 4.

[0101] In step 500, the parent block 900 receives customer requirements. Similar to the method described above in connection with FIG. 4, the customer requirements may define, for example, the functionality of the circuit and specific restrictions required from the circuit such as peak current, voltage, etc. The customer requirements may also specify other characteristics such as the PDK / foundry in which the circuit is to be manufactured. The parent block 900 is configured to convert the customer requirements into a set of criteria (5202). The parent block 900 may be configured to determine, additionally or alternatively, whether to send these criteria to the child blocks 950 in parallel or serially, and / or whether to send a different set of criteria to the lower-level child blocks 950.

[0102] Also, at this stage, the parent block 900 may be configured to determine the number of layers of the model, or alternatively, each layer of blocks may be configured to determine whether a lower-level block is needed when designing the portion of the circuit that is tasked to be designed by the upper-level block.

[0103] After converting the customer requirements into criteria (502), the parent block 900 then sends these to the child block 1 of the first design layer (504). These criteria can specify how many child blocks 950 of this layer are to be used and which child blocks 950 are responsible for designing each portion of the analog circuit.

[0104] Upon receiving a reference, Child 1 designs a first portion of the analog circuit based on the received reference (506). It will be understood that Child 1 may be configured to design a first portion of the analog circuit based on a subset / first portion of the applicable reference determined by the parent block.

[0105] When Child 1 designs a first portion of the analog circuit, the reference received from the parent block 900 may instruct Child 1 to send the first portion of the designed circuit and the reference to a second child (Child 2) in the same layer. Child 2 may design a second portion of the analog circuit based on the received reference, and in some examples, may design the second portion of the analog circuit based on only a subset of the reference (e.g., only the applicable portion thereof) or based on all of the reference.

[0106] Also, Child 2 adapts the design of the second portion of the analog circuit based on the context created by the designed first portion of the analog circuit designed by Child 1. In some examples, this context may be represented in the form of an adjusted set of references - for example, the parent block and / or Child 1 may be configured to adjust the reference based on the context and / or parasitic elements provided by the designed first portion of the circuit designed by Child 1, but in other examples, it will be understood that the context and / or parasitic elements may be provided in addition to / separately from the reference. For example, in an example where the parent block includes a verification and simulator module, the verification and simulator module may simulate the performance of the designed portion or component of the circuit to obtain context and / or parasitic element information. Additionally or alternatively, in an example where each child block includes a verification and simulator module, the verification and simulator module may simulate the performance of the designed portion or component of the circuit to obtain context and / or parasitic element information.

[0107] In some examples, child 2 may determine that it is necessary to use lower-level blocks to design a portion of the circuit for which it is responsible, and / or determine whether to use these lower-level blocks in series and / or in parallel. Additionally or alternatively, the criteria received by child 2 may instruct child 2 to use lower-level blocks to design a portion of the circuit for which it is responsible (and whether to use these blocks in series or in parallel). For example, as shown in FIG. 6, child 2 may optionally instruct grandchild 1 and grandchild 2 to design a subset of the second portion of the analog circuit (512). In such an example, child 2 may optionally verify whether the portion of the circuit designed by the lower-level blocks (grandchild 1 and grandchild 2 in the illustrated example) meets the criteria required of them (513).

[0108] Next, child 2 transmits the designed first portion, the designed second portion, and the criteria to child 3 (514). In some examples, the criteria may be modified by a preceding child. For example, the criteria may be modified by child 1 and / or child 2 before being transmitted to the next child. For example, child 2 may be configured to modify the criteria transmitted to child 3 based on the designed first portion of the circuit and / or the designed second portion of the circuit.

[0109] Next, child 3 additionally or alternatively designs the third portion of the analog circuit based on the received criteria and the designed first portion and / or the designed second portion (516).

[0110] Next, Child 3 sends the completed circuit to the parent block (518), and the parent block generates an initial design of the analog circuit based on a series of respective circuit portion designs, and checks or verifies whether the designed completed circuit meets the customer requirements (520). As described above, the parent block may do this by employing a verification and simulation module to simulate the performance of the completed circuit. Parent block 900 also obtains information related to parasitic elements that would occur in the analog circuit if it included all the circuit portions for which the analog circuit was designed.

[0111] If, hypothetically, the designed completed circuit does not meet the customer requirements, the parent block may resend the designed completed circuit to Child 1, along with additional information regarding what needs to be adjusted (and optionally by which block) (522). Additionally or alternatively, if the designed completed circuit does not meet the customer requirements, the parent block may send back only the portion of the designed circuit to the block responsible for the design of that portion (524) - for example, the parent block may send back the second portion of the analog circuit to Child 2, along with information regarding what needs to be adjusted, for example, and / or along with adjusted criteria. And Child 2 may design that portion of the circuit and send it directly back to the parent block to check whether it meets the customer requirements, or send it to Child 3, which may redesign the third portion of the circuit based on the redesigned second portion of the circuit (and / or optionally based on adjusted criteria).

[0112] It will be understood in the above examples that the first, second, third, and fourth portions of the analog circuit may be independent portions of the circuit and / or may be functionally dependent on each other. In other examples, the first, second, third, and fourth portions of the analog circuit may be a selected subset of the analog circuit. For example, the second portion may constitute a part of the first portion, the third portion may constitute a part of the first and second portions, and the fourth portion may constitute a part of the first, second, and third portions.

[0113] In the example shown in FIG. 5, the parent block acquires information related to parasitic elements only after all child blocks have designed their respective circuit portions. However, in some examples, the parent block 900 may acquire information related to parasitic elements after each child block has designed its portion and before the next child block designs its respective circuit portion.

[0114] FIG. 6A shows an input buffer, a level shifter, a DAC, and a comparator. Each of these may form a portion of a completed analog circuit, such as the completed ADC shown in FIG. 6B.

[0115] The examples shown in FIGS. 6A and 6B are designed using a hierarchical model implemented on a computer as described above. The parent block (or primary design unit) is responsible for the design of the entire ADC, and the child blocks (or secondary design units) are responsible for the input buffer, level shifter, DAC, and comparator, respectively. The parent block receives technical requirements from the user, converts them into technical specifications, and the technical specifications are used by the respective child blocks to design their respective portions of the circuit. The context of the other portions of the circuit is considered and used when the child blocks design their respective portions of the circuit. This model is iterative in that when the parent block 900 instructs each child block 950a - d to design its respective portion or component, some redesign of the circuit and its portions is performed so that the context provided by the other portions of the circuit is used in the design of each circuit portion and the circuit as a whole. As described above, each child block and / or parent block may perform verification / validation to determine whether the designed portion / completed circuit meets the required technical requirements.

[0116] In the designed circuit shown in FIG. 6B, there are two DACs in order to operate the differential ADC. There are multiple input buffers (three in the example shown in the figure), two of which are for buffering two inputs and one is for buffering the reference as an input.

[0117] As described above, the analog circuit design apparatus may estimate parasitic elements for any designed circuit or circuit portion using a machine learning model.

[0118] The machine learning model may include a neural network. The neural network may include at least one of a deep residual network, a highway network, a tightly coupled network, and a capsule network.

[0119] In such a type of network, the network may include a plurality of different neurons and be organized into different layers. Each neuron is configured to receive input data, process this input data, and provide output data. Each neuron may be configured to perform a specific operation on the input, including, for example, mathematically processing the input data. The input data of each neuron may include outputs from a plurality of other preceding neurons. As part of the operation of the neuron on the input data, a weighting is assigned to each stream of the input data (for example, one stream of the input data for each preceding neuron that provides an output to the neuron). Thus, the processing of the input data by the neuron includes applying a weighting to different streams of the input data so that different items of the input data contribute more or less to the overall output of the neuron. As a result of the change in the weighting of the input, when the input value of a certain neuron is adjusted, the output value of that neuron may change. The output data from each neuron may be transmitted to a plurality of subsequent neurons.

[0120] Neurons are arranged in layers. Each layer consists of multiple neurons, which perform operations on the data supplied from the outputs of the neurons in the preceding layer. There are a large number of different neurons in each layer, and each neuron can assign different weights to the input data and perform different operations on the input data. Also, the input data for all the neurons in a certain layer may be the same, and the output from the neurons is passed to the neurons in the subsequent layer.

[0121] The exact routing between neurons in different layers forms a major difference between capsule networks and deep residual networks (including variants such as highway networks and tightly coupled networks).

[0122] In a residual network, the layers are organized into blocks, and the network can have multiple blocks, with each block having at least one layer. In the case of a residual network, the output data from the neurons in one layer may follow multiple different paths. In a conventional neural network (e.g., a convolutional neural network), the output data from a certain layer is passed to the next layer, which continues until the end of the network, and each layer receives input from the layer immediately preceding it and provides output to the layer immediately following it. However, in a residual network, the routing between layers may be different. For example, the output from a certain layer may be passed to multiple different subsequent layers, and the input to a certain layer may be received from multiple different preceding layers.

[0123] In a residual network, the layers of neurons may be organized into different blocks, and each block comprises at least one layer of neurons. The blocks may be arranged by stacking the layers such that the output of a preceding layer (or multiple layers) is supplied as the input to the layer of the next block. The structure of the residual network may be such that the output from one block (or layer) is passed to both the immediately subsequent block (or layer) and at least one other subsequent block (or layer). A shortcut may be introduced into the neural network that bypasses other intermediate layers (or blocks) while passing data from one layer (or block) to another. This may enable more efficient training of the network, for example, to address problems related to degradation when training a very deep network (which will be described in more detail below). The arrangement of the residual neural network may cause a branch such that the same input provided to one layer, or block of layers, is provided to at least one other layer, or block of layers (e.g., such that the other layer can operate on both the input data and the output data from one layer, or block of layers). This arrangement may enable deeper penetration into the network when using the backpropagation algorithm to train the network. For example, during learning, a layer, or block of layers, may be able to take as input both the input and the output of the previous layer / block, and a shortcut may be used to provide deeper penetration when updating the weighting for the network.

[0124] In a capsule network, layers may be nested inside other layers to provide "capsules". Different capsules can be adapted to become proficient at performing different tasks than other capsules. The capsule network may provide dynamic routing between capsules such that, for a given task, the task is assigned to the most capable capsule for handling that task. For example, the capsule network can avoid routing the output from all neurons in one layer to all neurons in the next layer. Lower-level capsules are configured to send their input to the higher-level (subsequent) capsule that is determined to be most likely to process that input. A capsule can predict the activity of capsules in higher layers. For example, a capsule can output a vector that represents the characteristics of an object whose orientation is in question. In response, each subsequent capsule may provide, as an output, the probability that an object trained to be recognized by that capsule is present in the input data. This information (e.g., probability) is fed back to the capsule, and the capsule can dynamically determine routing weights and transfer the input data to the subsequent capsule that is most likely to be the relevant capsule for processing that data.

[0125] Any type of neural network may include a plurality of different layers having different functions. The neural network may include at least one convolutional layer configured to convolve input data across its height and width. The neural network may have a plurality of filtering layers, each of which comprises a plurality of neurons configured to focus on different portions of the input data and apply filters. To process the input data, other layers may be included, such as pooling layers (to introduce non-linearity) like max pooling or global average pooling, rectified linear unit layers (ReLU), loss layers, etc., which may include regularization functions. The final block of the layers may receive input from the last output layer (or more layers if branches exist). The final block may comprise at least one fully connected layer.

[0126] The last output layer may include a classifier such as a softmax classifier, a sigmoid classifier, or a tanh classifier. Different classifiers may be suitable for different types of outputs. For example, when the output is a binary classifier, a sigmoid classifier may be suitable. The neural network of the present disclosure may be configured to predict the binding affinity between a target and a test object. In this case, the output may be a prediction of the value of the equilibrium dissociation constant. The output of the neural network may provide an indication of the probability that the target and the test object match. Also, an indication of whether a more detailed analysis regarding the compatibility of the target and the test object, such as a binary format where the first output indicates "yes" and the second output indicates "no", is guaranteed may be provided as the output. In this case, the network may function as a screen for extracting a small group of compounds that require more detailed inspection.

[0127] FIG. 7 shows an overview of an example of a method for training a machine learning model for estimating parasitic elements. Neural network 700 is configured to take in, as input 710, a designed circuit portion and / or an analog circuit. The designed circuit portion and / or the analog circuit may be stored in a database and may be designed using the hierarchical model of the primary design unit and the secondary design unit using the computer-implemented models described above with reference to FIGS. 1A-6B. The circuit portion and / or the analog circuit may be vectorized and / or encoded, such as by using one-hot encoding to provide a binary format. This input is then fed into a series of 3D layers of the neural network. This network has several characteristics that can be varied as the training of the network progresses. Each neuron has a plurality of weightings, and each weighting is applied to a respective input stream for the output data from the neurons of the preceding layer. These weightings are variables that can be changed to affect the output of the neural network. These weightings can be changed in response to training to provide more accurate data. The changed weightings are referred to as "trained" corresponding to the training of these weightings. Further, the size and connectivity of the layers may depend on the typical input data of the network, but these too may be variables that can be modified and learned during training, including strengthening the connections.

[0128] For the training of the network, for example, to learn the values of the weightings, initial values are assigned to these weightings. These initial values may basically be random, but appropriate initialization of the values, such as Xavier / Glorot initialization, can be applied to improve the training of the network. Such initialization can prevent situations where the initial random weightings are too large or too small and the neural network is not properly trained to overcome these initial biases. This type of initialization may include assigning weightings using a distribution that has zero mean but a fixed variance.

[0129] Once weights are assigned, the learning target data can be supplied (700) or input (710) to the neural network. This may include operating the neural network on a designed known circuit (and / or circuit portion) and corresponding estimation / simulation and / or set of known parasitic elements to output predicted parasitic elements for the input circuit portion / analog circuit (720). Based on this information, for example, backpropagation optimization methods using gradient descent (e.g., stochastic gradient descent) and a loss function are executed on the network to compare the predicted parasitic elements with the expected or known parasitic elements for that circuit portion / analog circuit (730). The expected or known parasitic elements may be obtained, for example, using a virtual test bench. In this process, algorithms such as mini-batch gradient descent, RMSprop, Adam, Adadelta, Nesterov, etc. may be used. This enables identification of how much each different point (neuron) or path (between neurons in subsequent layers) within the network contributes to an inaccurate score determination, and thus enables determination of the weight adjustments that need to be made (740). Then, the weights can be adjusted according to the calculated error (750). For example, to minimize or remove the contribution from neurons that contribute to or most contribute to an inaccurate determination.

[0130] After repeatedly training the network with different sets of parasitic elements corresponding to the designed circuit (and / or circuit portion), the weights can be updated (750), and this process can be repeated a number of times. To suppress the possibility of overtraining the network, training variables such as the learning rate and momentum can be varied and / or controlled to reach selected values. Further, regularization techniques such as L2 and dropout can be used to reduce the likelihood that different layers are overtrained and not generally applicable to other similar data and are too specialized to the training data. Similarly, batch normalization may also be used to aid training and improve accuracy. Generally, the weights are adjusted so that when the network operates again on the same training image, the expected results are obtained. However, how correct this is depends on learning variables such as the learning rate.

[0131] It is understood that increasing the depth of a neural network can cause problems during training, for example due to the vanishing gradient problem, and can also provide a slower network. However, the present disclosure may enable the provision of a network with increased depth and accuracy without sacrificing the ability to properly train the network.

[0132] The depth of the network used may be selected to provide a balance between accuracy and the time required to provide an output. Increasing the depth of the network may increase the accuracy but may also increase the time required for the output. Using a branched structure (in contrast to a convolutional neural network), as the depth of the network increases, sufficient learning of the network becomes possible, and as a result, the accuracy of the network may improve.

[0133] In the context of the present disclosure, a non-exhaustive list of exemplary analog parameters that may form the basis of a criterion includes noise tolerance, power supply rejection ratio (PSRR), common mode range - input (input CMR), common mode range - output (output CMR), linearity, maximum offset, bandwidth, minimum slew rate, inherent delay, minimum phase margin, dynamic power consumption, static power consumption, IP3 point, filter center frequency, filter bandpass range, load step response, line step response, output accuracy, noise figure, calibration range, noise floor, SNR, ENOB, SINAD, output frequency range, jitter - ptp, jitter - RMS, output ripple ptp, total harmonic distortion, startup time, channel separation, reference voltage, gain error, offset error, gain drift.

[0134] Also, it will be understood that the design unit (primary, secondary, tertiary design units, etc.) may be implemented in software or hardware, for example, as a dedicated circuit. For example, the design unit may be implemented as part of a computer system. The computer system may include a bus or other communication mechanism for communicating information data, signals, and information among various components of the computer system. The components may include input / output (I / O) components that process the operations of a user (i.e., sender, receiver, service provider), such as selecting keys from a keypad / keyboard, selecting one or more buttons or links, and sending corresponding signals to the bus. The I / O components may include output components such as a display and cursor control (keyboard, keypad, mouse, etc.). A transceiver or network interface may send and receive signals between the computer system and other devices such as other user devices, merchant servers, or service provider servers via a network. In one embodiment, the transmission is wireless, but other transmission media and methods may also be suitable. A processor, which may be a microcontroller, digital signal processor (DSP), or other processing component, processes these various signals, for example, for display on the computer system or transmission to other devices via a communication link. Also, the processor may control the transmission of information such as cookies and IP addresses to other devices.

[0135] The components of the computer system may include system memory components (e.g., RAM), static storage components (e.g., ROM), and / or disk drives (e.g., solid state drive, hard drive). The computer system executes one or more instruction sequences included in the system memory components to perform specific operations by the processor and other components.

[0136] Logic may be encoded in a computer-readable medium, which may refer to any medium that participates in providing instructions to a processor for execution. Such a medium can take many forms including, but not limited to, non-volatile media, volatile media, and transmission media. In various embodiments, non-volatile media includes optical or magnetic disks, volatile media includes dynamic memory such as system memory components, and transmission media includes coaxial cables, copper wire, and fiber optics. In one embodiment, the logic is encoded in a non-transitory computer-readable medium. In one example, the transmission media may take the form of acoustic or light waves such as those generated during radio wave, optical, and infrared data communications.

[0137] Common forms of computer-readable media include, for example, floppy disks, flexible disks, hard disks, magnetic tape, other magnetic media, CD-ROM, other optical media, punch cards, paper tape, other physical media with patterns of holes, RAM, PROM, EPROM, Flash-EPROM, other memory chips or cartridges, or other media designed to be read by a computer.

[0138] In various embodiments of the present disclosure, the execution of sequences of instructions for practicing the present disclosure may be performed by a computer system. In various other embodiments of the present disclosure, a plurality of computer systems 600 coupled by a communication link to a network (e.g., various other wired or wireless networks including, but not limited to, LAN, WLAN, PTSN, and / or telecommunications, mobile, and cellular phone networks) may cooperate with each other to execute a sequence of instructions for practicing the present disclosure.

[0139] It will also be understood that aspects of the present disclosure may be implemented using hardware, software, or a combination of hardware and software. Also, where applicable, the various hardware components and / or software components defined herein may be combined into composite components consisting of software, hardware, and / or both without departing from the spirit of the present disclosure. Also, where applicable, the various hardware components and / or software components described herein may be separated into sub-components consisting of software, hardware, or both without departing from the scope of the present disclosure. Further, where applicable, software components may be implemented as hardware components and vice versa.

[0140] Software according to the present disclosure, such as program code and / or data, may be stored on one or more computer-readable media. It is also contemplated that the software identified herein may be implemented using one or more networked and / or other general-purpose or special-purpose computers and / or computer systems. Where applicable, the order of the various steps described herein may be changed, combined into composite steps, and / or separated into sub-steps to provide the features described herein.

[0141] The various features and steps described in this specification may be implemented as a system comprising one or more memories that store the various information described in this specification, and one or more processors coupled to the one or more memories and a network, the one or more processors being adapted, when executed by the one or more processors, to cause the one or more processors to execute a method comprising the steps described in this specification, and a non-transitory machine-readable medium comprising a plurality of machine-readable instructions adapted to cause a method performed by one or more devices such as a hardware processor, a user device, a server, and other devices described in this specification to be performed, and to be operable to execute the steps described in this specification.

[0142] In the context of the present disclosure, other examples and variations of the apparatus and methods described in this specification will be apparent to those skilled in the art.

Claims

1. An analog circuit design device, receives information representing technical requirements of an analog circuit, identifies a plurality of circuit portions for forming the analog circuit based on the received information, determines respective technical criteria for each of the plurality of circuit portions with respect to the circuit portion, generates a series of designs including respective designs for each of the circuit portions, for at least one circuit portion design of the series of designs for the plurality of circuit portions, obtains information related to parasitic elements that occur in the analog circuit when the circuit portion design is included in the analog circuit, adapts the design of at least one circuit portion based on the obtained information related to the parasitic elements, outputs a completed circuit design including at least one circuit portion adapted based on the obtained information related to the parasitic elements, and includes at least one design unit configured as such. Analog circuit design device.

2. In the analog circuit design device according to claim 1, the analog circuit design device includes a primary design unit and a plurality of secondary design units, the primary design unit, identifies the plurality of circuit portions for forming the analog circuit based on the received information, determines respective technical criteria for each of the plurality of circuit portions with respect to the circuit portion, and provides the respective technical criteria for each circuit portion to at least one of the plurality of secondary design units, and is configured as such, each of the plurality of secondary design units of the analog circuit design device, (a) Design each of the plurality of circuit portions based on the technical criteria provided by the primary design unit, (b) Output the design as a result of each of the circuit portions, configured as follows, The primary design unit further (c) Obtain a series of designs including the design of each of the circuit portions from each of the plurality of secondary design units, (d) Generate at least an initial design of the analog circuit based on the series of designs, (e) Obtain information related to parasitic elements that will occur in the circuit portions and / or the analog circuit if the analog circuit includes the circuit portions, configured as follows, At least one of the secondary design units is configured to adapt the design of each of the circuit portions based on information related to parasitic elements The primary design unit is configured to output a completed circuit design including at least one adapted circuit portion. Analog circuit design device.

3. In the analog circuit design device according to claim 2, The analog circuit design device is configured to input parasitic elements and circuit designs into a database by repeating the steps (a) to (e) a plurality of times. Each time the steps (a) to (e) are repeated, new technical criteria are provided by the primary design unit. Analog circuit design device.

4. In the analog circuit design device according to any one of claims 1 to 3, The analog circuit design device is configured to obtain information regarding parasitic elements that would occur in the analog circuit when the analog circuit includes the designed circuit portion by mathematically simulating the performance of at least one of (i) the designed circuit portion and (ii) the complete analog circuit including the designed circuit portion in a virtual test bench. Analog circuit design device. **Claim 5** In the analog circuit design device according to any one of claims 1 to 4, the analog circuit design device is configured to obtain information regarding parasitic elements that would occur in the analog circuit when the analog circuit includes the designed circuit portion by performing a lookup in a database regarding circuit design and parasitic elements. Analog circuit design device. **Claim 6** In the analog circuit design device according to any one of claims 1 to 5, the analog circuit design device is configured to obtain information regarding parasitic elements that occur in the generated design by looking up similar generated designs in a database regarding circuit design and parasitic elements. Analog circuit design device. **Claim 7** In the analog circuit design device according to any one of claims 1 to 6, the analog circuit design device is configured to perform a lookup for at least one of each similar circuit portion in a database of circuit design and parasitic elements, and the analog circuit design device is configured to obtain information regarding parasitic elements that occur in the generated design based on the values of the parasitic elements obtained through the lookup for at least one of each of the circuit portions. Analog circuit design device. **Claim 8** In the analog circuit design device according to any one of claims 1 to 7, the analog circuit design device is configured to obtain information related to parasitic elements generated in the generated design by predicting the parasitic elements using a machine learning model. Analog circuit design device.

9. In the analog circuit design device according to any one of claims 1 to 8, the parasitic elements include at least one of a parasitic capacitance, a parasitic resistance, and a parasitic inductance. Analog circuit design device.

10. In the analog circuit design device according to any one of claims 1 to 9, the analog circuit design device is configured to adapt the design of each circuit portion when information regarding parasitic elements generated by the generated design indicates that the parasitic elements are greater than a selected threshold level. Analog circuit design device.

11. In the analog circuit design device according to any one of claims 1 to 10, the analog circuit design device is configured to adapt the design of each circuit portion by adapting the corresponding technical criteria of each circuit portion based on information related to the parasitic elements. Analog circuit design device.

12. A method for training a machine learning model for predicting parasitic elements in a designed analog circuit, the method comprising: in each of a plurality of secondary design units of an analog circuit design device, (a) designing each circuit portion of a plurality of circuit portions based on technical criteria provided by a primary design unit, (b) outputting the design resulting from each said circuit portion, In the primary design unit of the analog circuit design device, (c) obtaining, from at least one of the plurality of secondary design units, a series of designs including the respective designs of the respective circuit portions; (d) generating at least an initial design of the analog circuit based on the series of designs; (e) obtaining information related to at least one of the circuit portions and parasitic elements generated in the generated design by mathematically simulating the performance of the design generated using a virtual test bench, repeating the steps (a) to (e) a plurality of times, and each time the steps (a) to (e) are repeated, a new technical criterion is provided by the primary design unit, method.

13. A method for designing an analog circuit, comprising: The method includes: receiving information representing technical requirements of the analog circuit; identifying a plurality of circuit portions for forming the analog circuit based on the received information; for each of the plurality of circuit portions, determining a respective technical criterion for the circuit portion; generating a series of designs including the respective designs for the respective circuit portions; for the design of at least one of the circuit portions of the series of designs for the plurality of circuit portions, obtaining information related to parasitic elements generated in the analog circuit when the design of the circuit portion is included in the analog circuit; adapting the design of at least one circuit portion based on the obtained information related to the parasitic elements; outputting a completed circuit design including at least one circuit portion adapted based on the obtained information related to the parasitic elements. method.

14. In the method according to claim 13, In a primary design unit of an analog circuit design device, Based on the received information, identify a plurality of circuit portions for forming the analog circuit, For each of the plurality of circuit portions, determine respective technical criteria for the circuit portion, Provide the respective technical criteria for each of the circuit portions to at least one of a plurality of secondary design units, In each of the plurality of secondary design units of the analog circuit design device, (a) Design each of the plurality of circuit portions based on the technical criteria provided by the primary design unit, (b) Output the design resulting from each of the circuit portions, In the primary design unit, further, (c) Obtain a series of designs including the design of each of the circuit portions from each of the plurality of secondary design units, (d) Generate at least an initial design of the analog circuit based on the series of designs, (e) Obtain information related to parasitic elements that would occur in the analog circuit if the analog circuit includes the circuit portions, In at least one of the secondary design units, adapt the design of each of the circuit portions based on the information related to parasitic elements, In the primary design unit, output a completed circuit design having at least one adapted circuit portion. Method.

15. In the analog circuit design method according to claim 14, Further comprising inputting a database of parasitic elements and circuit designs by repeating the steps (a) to (e) a plurality of times, and each time the steps (a) to (e) are repeated, new technical criteria are provided by the primary design unit. Method.

16. In the analog circuit design method according to any one of claims 13, 14, or 15, By mathematically simulating the performance of the generated design with a virtual test bench, obtaining information regarding parasitic elements that would occur in the analog circuit if the analog circuit included the designed circuit portion, Method.

17. In the analog circuit design method according to any one of claims 13 to 16, Obtaining information regarding parasitic elements that would occur in the analog circuit if the analog circuit included the designed circuit portion by performing a lookup in a circuit design and parasitic element database, Method.

18. In the analog circuit design method according to any one of claims 13 to 17, Obtaining information regarding parasitic elements that would occur in the analog circuit if the analog circuit included the designed circuit portion by performing a lookup in the circuit design and parasitic element database for similar generated designs, Method.

19. In the analog circuit design method according to any one of claims 13 to 18, In the circuit design and parasitic element database, performing a lookup for at least one of each similar circuit portion, and based on the values of the parasitic elements obtained through the lookup for at least one of each circuit portion, obtaining information regarding parasitic elements that would occur in the analog circuit if the analog circuit included the designed circuit portion, Method.

20. In the analog circuit design method according to any one of claims 13 to 19, Obtaining information related to parasitic elements that would occur in the analog circuit when the analog circuit includes the designed circuit portion, using a machine learning model for predicting parasitic elements. Method.

21. In the analog circuit design method according to any one of claims 13 to 18, The parasitic elements include at least one of parasitic capacitance, parasitic resistance, and parasitic inductance. Method.

22. In the analog circuit design method according to any one of claims 13 to 21, When the information related to the parasitic elements indicates that the parasitic elements are greater than a selected threshold level, adapting the design of each circuit portion. Method.

23. In the analog circuit design method according to any one of claims 13 to 22, Adapting the design of each circuit portion based on the information related to the parasitic elements includes adapting the corresponding technical criteria of each circuit portion. Method.

24. In the method according to any one of claims 13 to 23, Further comprising fabricating an analog circuit for the output design. Method.

25. A computer-readable non-transitory storage medium comprising a program for a computer configured to cause a processor to execute the method according to any one of claims 13 to 24.

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