Non-volatile memory

Abstract

A non-volatile memory equipped with a memory cell which has a first transistor and a second transistor, a drive circuit for suppling a lead voltage to each gate of the first transistor and the second transistor, and a signal output circuit for outputting a signal associated with a first value or a signal associated with a second value on the basis of each drain current of the first and second transistors during a lead operation in which the lead voltage is supplied. The second transistor is configured from a parallel circuit of a plurality of unit transistors, and the gate width of each unit transistor is greater than the gate width of the first transistor.

Description

Technical Field

[0001] The present disclosure relates to a non-volatile memory.

Background Art

[0002] There is a non-volatile memory that utilizes hot carrier injection into a transistor. This type of non-volatile memory includes first and second transistors with aligned characteristics in an initial state as memory elements, and hot carriers are injected only into one of the transistors to change the characteristics of the transistor. In a subsequent read operation, based on the magnitude relationship of the drain currents when a common gate voltage is supplied to the first and second transistors, it is determined whether "0" data or "1" data is stored. For example, a state where the drain current of the first transistor is smaller (a state where the characteristics of the first transistor have changed) corresponds to a state where "0" data is stored, and a state where the drain current of the second transistor is smaller (a state where the characteristics of the second transistor have changed) corresponds to a state where "1" data is stored.

[0003] However, in the above non-volatile memory, the stored data (stored value) in the initial state is indeterminate. In this case, it is necessary to perform processing to cope with the indeterminate stored data in other peripheral circuits, which may be inconvenient from the perspective of circuit scale and the like. There has also been proposed a non-volatile memory configured such that more drain current flows through the second transistor among the first and second transistors in the initial state so that the stored data in the initial state does not become indeterminate. In this type of non-volatile memory, the stored data can be determined to be "0" in the initial state, and the stored data can be set to "1" through hot carrier injection into the second transistor.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] At this time, in the initial state, it is required to stably read the value of "0" from the non-volatile memory, and after the hot carrier injection, it is required to stably read the value of "1" from the non-volatile memory. In the read operation of reading data from the non-volatile memory, the drain current ratio between the second transistor and the first transistor is represented by N. In order to satisfy the above requirements in consideration of the effects of temperature fluctuations, manufacturing errors, etc., it is necessary to set the drain current ratio N in the initial state to be considerably larger than 1 (for example, "N = 4"), and it is necessary to make the drain current ratio N after hot carrier injection sufficiently smaller than "1". It is not always easy to satisfy these requirements. The development of a configuration that can satisfy these requirements and stably store and read desired values is expected.

[0006] An object of the present disclosure is to provide a non-volatile memory that contributes to the stable storage and reading of desired values.

Means for Solving the Problems

[0007] The non-volatile memory according to the present disclosure includes a memory cell having a first transistor and a second transistor, a drive circuit configured to supply a read voltage to each gate of the first transistor and the second transistor, and in a read operation in which the read voltage is supplied, based on the drain currents of the first and second transistors, a signal output circuit configured to output a signal associated with a first value or a signal associated with a second value, and the second transistor is configured by a parallel circuit of a plurality of unit transistors, and the gate width of each unit transistor is larger than the gate width of the first transistor.

Effects of the Invention

[0008] According to the present disclosure, it is possible to provide a non-volatile memory that contributes to the stable storage and reading of desired values.

Brief Description of the Drawings

[0009]

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Mode for Carrying Out the Invention

[0010] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings to be referred to, the same parts are denoted by the same reference numerals, and redundant descriptions regarding the same parts are omitted in principle. In this specification, for the sake of simplicity of description, the names of information, signals, physical quantities, elements or parts, etc. corresponding to the symbols or reference numerals indicating the information, signals, physical quantities, elements or parts, etc. may be omitted or abbreviated by writing the symbols or reference numerals.

[0011] First, some terms used in the description of the embodiments of the present disclosure will be explained. A line refers to a wiring through which an electrical signal is propagated or applied. A ground refers to a reference conductive part having a reference potential of 0V (zero volts) or the 0V potential itself. The reference conductive part is formed of a conductor such as metal. The 0V potential may also be referred to as a ground potential. In the embodiments of the present disclosure, the voltage shown without particularly setting a reference represents the potential seen from the ground. A level refers to the level of a potential, and for any signal or voltage of interest, the high level has a higher potential than the low level. For any signal or voltage of interest, that the signal or voltage is at a high level means that the level of the signal or voltage is at a high level, and that the signal or voltage is at a low level means that the level of the signal or voltage is at a low level. The level of a signal may be expressed as a signal level, and the level of a voltage may be expressed as a voltage level.

[0012] For any transistor configured as a FET (field effect transistor) including a MOSFET, the on state refers to the state where conduction exists between the drain and source of the transistor, and the off state refers to the state where non-conduction (cut-off state) exists between the drain and source of the transistor. The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-mode MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor".

[0013] The electrical characteristics of a MOSFET include the gate threshold voltage. For any transistor that is an N-channel and enhancement-mode MOSFET, when the gate potential of the transistor is higher than the source potential of the transistor and the magnitude of the gate-source voltage (gate potential as seen from the source potential) of the transistor is equal to or greater than the gate threshold voltage of the transistor, the transistor is in the on state; otherwise, the transistor is in the off state.

[0014] Any switch can be configured with one or more FETs (field effect transistors). When a certain switch is in the on state, conduction exists between both ends of the switch, while when a certain switch is in the off state, non-conduction exists between both ends of the switch. Hereinafter, for any transistor or switch, the on state and the off state may also be simply expressed as on and off.

[0015] <<First Embodiment>> The first embodiment of the present disclosure will be described. FIG. 1 is a configuration diagram showing a main part of a memory circuit 1 according to the first embodiment. The memory circuit 1 is a non-volatile memory that stores 1-bit data, and includes a memory cell 10, a drive circuit 20, a signal output circuit 30, and a control circuit 40. The memory circuit 1 may be configured as a semiconductor integrated circuit. The operation of the drive circuit 20 is controlled by the control circuit 40. The operation of the signal output circuit 30 may also be controlled by the control circuit 40.

[0016] The memory cell 10 includes memory elements M1 and M2, and stores data of "0" or "1" in the memory cell 10. Each of the memory elements M1 and M2 is a transistor. Therefore, the memory elements M1 and M2 are also referred to as transistors M1 and M2 (the first and second transistors). Each of the transistors M1 and M2 is configured as an N-channel type MOSFET.

[0017] The transistor M1 has a gate, an electrode E1a, and an electrode E1b. In the transistor M1, among the electrode E1a and the electrode E1b, the electrode on the high potential side functions as a drain and the electrode on the low potential side functions as a source. The transistor M2 has a gate, an electrode E2a, and an electrode E2b. In the transistor M2, among the electrode E2a and the electrode E2b, the electrode on the high potential side functions as a drain and the electrode on the low potential side functions as a source. However, in the transistor M1, the electrode E1a is fixed as the drain and the electrode E1b is fixed as the source. In the transistor M2, in principle, the electrode E2b functions as a source, but the electrode E2b can function as a drain when the program operation described later is executed.

[0018] In the transistors M1 and M2, the gates are commonly connected by a gate line GL. Each gate of the transistors M1 and M2 is connected to a drive circuit 20 through the gate line GL. The electrode E1b of the transistor M1 and the electrode E2b of the transistor M2 are commonly connected to a line SL. Since the electrodes E1b and E2b basically function as sources, the line SL can be hereinafter referred to as a source line SL. The electrode E1a of the transistor M1 is connected to a line DL1 and is connected to a signal output circuit 30 through the line DL1. The electrode E2a of the transistor M2 is connected to a line DL2 and is connected to a signal output circuit 30 through the line DL2. Since the electrodes E1a and E2a basically function as drains, the lines DL1 and DL2 can be hereinafter referred to as drain lines DL1 and DL2.

[0019] In the memory circuit 1, under the control of the control circuit 40, a read operation for reading the data stored in the memory cell 10 and a program operation (write operation) for rewriting the data (value) stored in the memory cell 10 can be executed. In the present embodiment, the expressions "before the execution of the program operation" and "before the program operation" have the same meaning, and the expressions "after the execution of the program operation" and "after the program operation" have the same meaning (the same applies to other embodiments described later).

[0020] In the memory circuit 1, when the read operation is performed, a precharge period is set prior to the execution of the read operation, and the read operation is performed during the read period after the precharge period. In the read operation, based on the magnitude relationship of the drain currents of the transistors M1 and M2 during the read period, the data stored in the memory cell 10 is read out.

[0021] FIG. 2 and FIG. 3 show the states of voltage or current during the precharge period and the read period. The setting and application of the voltage of each part during the precharge period and the read period are executed under the control of the control circuit 40. During the precharge period and the read period, the voltage of the source line SL is set to 0V, and in the transistor M2, the electrode E2a functions as the drain and the electrode E2b functions as the source. As described above, in the transistor M1, the electrode E1a always functions as the drain and the electrode E1b functions as the source. Let the voltage of the drain line DL1 be represented by the voltage V1, and the voltage of the drain line DL2 be represented by the voltage V2. During the precharge period, while the voltage of each gate of the transistors M1 and M2 is set to 0V by the drive circuit 20, a positive charge is supplied to each of the drain lines DL1 and DL2, so that a common precharge voltage V PC is set for the voltage V1 of the drain line DL1 and the voltage V2 of the drain line DL2. The precharge voltage V PChas a predetermined positive DC voltage value (e.g., 1V). The positive charge may be supplied from the signal output circuit 30 or a circuit not shown. Incidentally, a positive voltage may be supplied to each gate of the transistors M1 and M2 during the precharge period. However, in any case, during the precharge period, the voltages V1 and V2 are maintained at the precharge voltage V PC .

[0022] After the precharge period, a positive read voltage V RD is supplied to each gate of the transistors M1 and M2, and the read period starts. The read voltage V RD may be a constant DC voltage, or may be a voltage that varies slightly with the passage of time during the read period. The read voltage V RD is higher than at least the gate threshold voltage of the transistor M1. The drain currents of the transistors M1 and M2 during the read period are referred to by the symbols "I D1 " and "I D2 ", respectively. Incidentally, during the read period, the input impedances of the signal output circuit 30 as seen from the drain line DL1 and the input impedance of the signal output circuit 30 as seen from the drain line DL2 are set to be sufficiently high. As a result, during the read period, the voltage V1 of the drain line DL1 decreases only when the drain current I D1 flows, and the voltage V2 of the drain line DL2 decreases only when the drain current I D2 flows.

[0023] FIG. 4A schematically shows the behavior of the voltages V1 and V2 during the precharge period and the read period when "I D2 >I D1 " during the read period. FIG. 4B schematically shows the behavior of the voltages V1 and V2 during the precharge period and the read period when "I D2 <I D1 " during the read period. The signal output circuit 30 outputs a signal D OUT corresponding to the value of the data stored in the memory cell 10 based on the magnitude relationship of the drain currents of the transistors M1 and M2 in the read operation.

[0024] In the read operation (in other words, during the read period), the drain current I D2 is larger than the drain current I D1 . This state corresponds to the state in which the first value is stored in the memory cell 10. Therefore, in the read operation, when the drain current I D2 is larger than the drain current I D1 , the signal output circuit 30 outputs a signal D OUT (in other words, the signal D representing the first value OUT ). In the read operation (in other words, during the read period), the drain current I D1 is larger than the drain current I D2 . This state corresponds to the state in which the second value is stored in the memory cell 10. Therefore, in the read operation, when the drain current I D1 is larger than the drain current I D2 , the signal output circuit 30 outputs a signal D OUT (in other words, the signal D representing the second value OUT ). Here, it is assumed that the first value is "0" and the second value is "1".

[0025] In the memory circuit 1, before the execution of the program operation, the first value (0) is stored in the memory cell 10 as the initial value, and after the execution of the program operation, the second value (1) is stored in the memory cell 10. In order to store the first value (0) in the memory cell 10 as the initial value, the structures of the transistors M1 and M2 are made different so that "I D2 >I D1 " in the read operation before the program operation. Therefore, inevitably, the read voltage V RD is not only higher than the gate threshold voltage of the transistor M1, but also higher than the gate threshold voltage of the transistor M2 before the program operation.

[0026] In the program operation, hot carriers are injected only into the transistor M2 among the transistors M1 and M2, whereby the gate threshold voltage of the transistor M2 increases. The program operation is executed so that the gate threshold voltage of the transistor M2 becomes sufficiently higher than the gate threshold voltage of the transistor M1 after the execution of the program operation. The gate threshold voltage of the transistor M2 after the execution of the program operation may be higher than the read voltage V RD Higher is acceptable.

[0027] In the read operation executed before the program operation, as shown in FIG. 4A, "I D2 >I D1 ", and as a result, a signal D OUT representing the first value (0) is output, that is, the data (value) "0" stored in the memory cell 10 is read out. In the read operation executed after the program operation, as the gate threshold voltage of the transistor M2 increases due to the program operation, as shown in FIG. 4B, "I D2 <I D1 ", and as a result, a signal D OUT representing the second value (1) is output, that is, the data (value) "1" stored in the memory cell 10 is read out.

[0028] Here, hereinafter, it is assumed that the low-level signal D OUT represents the first value (0) and the high-level signal D OUT represents the second value (1). Then, for example, after the start of the read period, by specifying the voltage that first becomes equal to or lower than a predetermined voltage among the voltages V1 and V2, the signal output circuit 30 may determine the level of the signal D OUT . If the specified voltage is the voltage V2, it represents that "I D2 >I D1 ", so the low-level signal D OUT (the signal D OUT representing the value "0") is output. If the specified voltage is the voltage V1, it represents that "I D2 <I D1 ", so the high-level signal D OUT (the signal D OUT representing "1") is output.) is output. Alternatively, for example, the read timing is set to the timing when a predetermined time has elapsed since the start of the read period, and the magnitude relationship between the voltages V1 and V2 at the read timing is detected to detect the drain current I D1 and I D2 The magnitude relationship of may also be detected.

[0029] An explanation of the program operation will be added. In the program operation, the memory circuit 1 changes the electrical characteristics of the transistor M2 by injecting hot carriers only into the transistor M2 among the transistors M1 and M2. Due to this change, the gate threshold voltage of the transistor M2 increases (rises). Fig. 5 shows the voltage state of the memory circuit 1 during the program period in which the program operation is performed. The setting and application of the voltages of each part during the program period are executed under the control of the control circuit 40.

[0030] In the program operation (therefore, during the program period), a positive voltage V PRG1 is applied to the line SL, and a positive voltage V PRG2 is applied to each gate of the transistors M1 and M2 by the drive circuit 20. The application of the voltage V PRG1 to the line SL may also be realized by the drive circuit 20. The voltage V PRG2 may have the same voltage value as the read voltage V RD , or may be higher than the read voltage V RD . Whether the voltages V PRG1 and V PRG2 match or not does not matter. In the program operation, as long as the gate threshold voltage of the transistor M2 can be increased by the required amount, the magnitudes of the voltages V PRG1 and V PRG2 are arbitrary.

[0031] Also, although not shown in FIG. 1 and the like, a switch SW2 is inserted between the electrode E2a of the transistor M2 and the ground. The on / off state of the switch SW2 is controlled by the control circuit 40. The switch SW2 may be considered to be incorporated in the drive circuit 20. The switch SW2 is normally off, but is turned on only during the programming period. Therefore, during the programming operation (and thus during the programming period), in the transistor M2, the electrode E2b functions as a drain and the electrode E2a functions as a source, and a current flows from the line SL through the electrodes E2b and E2a and the switch SW2 to the ground. During the flow of this current, hot carriers are injected into the transistor M2, causing the characteristics of the transistor M2 to change, and the gate threshold voltage of the transistor M2 to increase. After maintaining the programming period for a time sufficient to sufficiently increase the gate threshold voltage of the transistor M2, the programming operation is terminated. In order to realize such a programming operation, it is advisable to set the voltage values of the voltages V PRG1 and V PRG2 sufficiently high. Note that the line DL1 is in a high-impedance state during the programming period. It may be considered that a voltage V PRG2 is applied to the line DL1 during the programming period. In any case, no current flows between the electrodes E1a and E1b during the programming period.

[0032] The method of realizing the programming operation is not limited to the above method and is arbitrary. Therefore, for example, during the programming period, while applying a voltage V PRG2 to the gates of the transistors M1 and M2, among the lines DL1 and DL2, a voltage V PRG1By applying [voltage] and applying a ground potential to line SL, the program operation may be realized. At this time, switch SW2 is maintained in the off state, and a ground potential is applied to line DL1 or line DL1 is set to a high impedance state. Also by this, among transistors M1 and M2, hot carriers are injected only into transistor M2. Incidentally, in this case, also in the program operation, similar to the read operation, electrode E2a functions as a drain and electrode E2b functions as a source.

[0033] As shown in FIG. 6, in the read operation (read period) before the program operation, the drain current I D2 and the drain current I D1 The ratio to is expressed as "n: 1". n is a real number greater than 1. n may be an integer or may include a decimal. Considering the effects of temperature fluctuations, manufacturing errors, etc., a value appropriately larger than 1 is set for n so that the initial value (0) can be stably read from memory cell 10 before the program operation. For example, the design value of n is "4".

[0034] Incidentally, in the following description of the first embodiment, in order to prevent complication of the description, unless particularly necessary, the existence of the program operation is ignored, and among the electrodes of transistor M1, it is considered that electrode E1a is a drain and electrode E1b is a source, and among the electrodes of transistor M2, it is considered that electrode E2a is a drain and electrode E2b is a source.

[0035] [First Method] As a method for realizing “n>1”, there is the following first method. Taking “n = 4” as an example, the structures of transistors M1 and M2 according to the first method will be described. In the first method, as shown in FIG. 7, five unit transistors Ma having the same structure as each other are used to form transistors M1 and M2. Each unit transistor Ma is an N-channel type MOSFET. The memory circuit 1 including the five unit transistors Ma is integrated on a semiconductor substrate. When the five unit transistors Ma are referred to as the first to fifth unit transistors Ma, transistor M1 is the first unit transistor Ma itself, and transistor M2 is composed of a parallel circuit of the second to fifth unit transistors Ma. More specifically, the gates of the second to fifth unit transistors Ma are commonly connected to each other to form the gate of transistor M2, the drains of the second to fifth unit transistors Ma are commonly connected to each other to form the drain of transistor M2, and the sources of the second to fifth unit transistors Ma are commonly connected to each other to form the source of transistor M2.

[0036] Regarding a transistor, the structure is a concept including the size of the transistor. Therefore, for any plurality of transistors, the fact that the structures are the same as each other means that the sizes of the plurality of transistors are also the same as each other. When the structures of a plurality of transistors are the same as each other, if hot carrier injection by a program operation is not performed on some or all of the plurality of transistors, the electrical characteristics (including the gate threshold voltage, etc.) of the plurality of transistors will also be the same as each other. However, regarding the structures and electrical characteristics of any plurality of transistors, the fact that the structures or electrical characteristics are the same means that they are the same in design, and actually may include errors (that is, the same is a concept including errors).

[0037] According to the first method shown in FIG. 7, before the program operation, the drain current I D2 and the drain current I D1It is possible to stably set the ratio to “n:1” (here, “n = 4”). That is, although errors are inevitably present, there is an advantage that the current ratio of the drain current I D2 and I D1 before the program operation is easily achieved as designed.

[0038] Fig. 8 shows the relationship between the gate-source voltage of transistor M2 and the drain current I D2 when the first method is adopted. The gate-source voltage of transistor M2 is represented by voltage V GS2 . In Fig. 8, waveform 810[n = 4] represents the relationship between voltage V GS2 and drain current I D2 before the program operation, and waveform 812[n = 4] represents the relationship between voltage V GS2 and drain current I D2 after the program operation. In Fig. 8, waveforms 810[n = 2], 812[n = 2], 810[n = 1], and 812[n = 1] are also shown. Waveforms 810[n = 2] and 812[n = 2] represent the relationship between voltage V GS2 and drain current I D2 before the program operation, and the relationship between voltage V GS2 and drain current I D2 after the program operation, assuming that transistor M2 is composed of a parallel circuit of two unit transistors Ma. Waveforms 810[n = 1] and 812[n = 1] represent the relationship between voltage V GS2 and drain current I D2 before the program operation, and the relationship between voltage V GS2 and drain current I D2 after the program operation, assuming that transistor M2 is composed of one unit transistor Ma.

[0039] The broken lines 814 and 816 in Fig. 9 represent the number of parallel unit transistors Ma constituting transistor M2 and the drain current I D2shows the relationship with. When acquiring data for obtaining the broken line 814, the gate-source voltage of the transistor M2 is fixed at a predetermined voltage (here 5V), and when acquiring data for obtaining the broken line 816, the gate-source voltage of the transistor M2 is fixed at another predetermined voltage (here 4V). When the first method is adopted, since the transistor Ma is formed by the n-parallel circuit of the unit transistor Ma, the drain current I after the program operation increases in proportion to the value of n D2 is found to increase.

[0040] [Second Method] As another method for realizing "n > 1", there is the following second method. In the second method, as shown in FIG. 10, the transistor M1 is formed using one unit transistor Ma, while the transistor M2 is formed using one unit transistor Mb. The unit transistor Mb is an N-channel MOSFET similar to the unit transistor Ma, but the gate width W of the unit transistor Mb is larger than the gate width W of the unit transistor Ma. The gate width W of the unit transistor Mb is particularly referred to as the gate width Wb, and the gate width W of the unit transistor Ma is particularly referred to as the gate width Wa. "Wb > Wa" holds. In FIG. 10, the unit transistor Mb is shown larger than the unit transistor Ma to schematically represent the difference in the gate width W (the same applies to FIGS. 16 and the like described later). In the second method, since the transistor M1 is the unit transistor Ma itself, the gate width W of the transistor M1 is also "Wa", and since the transistor M2 is the unit transistor Mb itself, the gate width W of the transistor M2 is also "Wb".

[0041] The gate width of a MOSFET is defined and recognized as common knowledge in MOSFET technology, but an explanation of the gate width will be added. Fig. 11 schematically shows the structure of a MOSFET. Each circuit element of the memory circuit 1 is formed by being integrated on a semiconductor substrate, and the structure of any transistor formed as a MOSFET on the semiconductor substrate is characterized by a gate width W and a gate length L. Any transistor formed as a MOSFET is provided with a gate electrode GG that functions as a gate. The gate width W and the gate length L represent the size of the gate electrode GG in a direction parallel to the surface (front and back surfaces) of the semiconductor substrate. Among these, the gate length L represents the distance between the drain and the source of the transistor (the length of the gate electrode GG in the direction connecting the drain and the source). The gate width W represents the length of the gate electrode GG in a direction orthogonal to the direction in which the gate length L is defined (the direction connecting the drain and the source) and also orthogonal to the normal direction of the semiconductor substrate (the direction orthogonal to the front and back surfaces of the semiconductor substrate). For any MOSFET, under certain conditions, if the gate width W increases, the drain current increases, and when the gate length L is relatively large, the drain current is generally proportional to the gate width W.

[0042] By setting “Wb > Wa”, in the read operation before the program operation, the drain current I D2 becomes larger than the drain current I D1 . At this time, although it also depends on the gate length L of the unit transistors Ma and Mb, in the read operation before the program operation, the drain current I D2 is about (Wb / Wa) times the drain current I D1 . Note that the gate lengths L of the unit transistors Ma and Mb may be the same as each other.

[0043] Fig. 12 shows the relationship between the gate-source voltage of the transistor M2 and the drain current I D2 when the second method is adopted. As described above, the gate-source voltage of the transistor M2 is represented by the voltage V GS2 . In Fig. 12, waveforms 820 [Wb = W L , 820 [Wb = W M, 820 [Wb = W S respectively represent the voltage V before the program operation and the drain current I under the conditions of "Wb = W L ", "Wb = W M ", "Wb = W S ". In FIG. 12, the waveforms 822 [Wb = W GS2 and the drain current I D2 respectively represent the voltage V after the program operation and the drain current I under the conditions of "Wb = W L ", "Wb = W M ", "Wb = W S ". In FIG. 12, it is difficult to distinguish the waveforms 822 [Wb = W L , 822 [Wb = W M , 822 [Wb = W S because they almost overlap. Here, "W GS2 and the drain current I D2 ". In FIG. 12, although it is difficult to distinguish the waveforms 822 [Wb = W L , 822 [Wb = W M and 822 [Wb = W S , they almost overlap. Here, "W L >W M >W S ". The gate width W M is about 1.5 times the gate width W S , and the gate width W L is about 3.5 times the gate width W S .

[0044] The broken lines 824 and 826 in FIG. 13 show the relationship between the gate width Wb of the transistor M2 and the drain current I D2 after the program operation when the second method is adopted. When obtaining the data for obtaining the broken line 824, the gate-source voltage of the transistor M2 is fixed at a predetermined voltage (here 5V), and when obtaining the data for obtaining the broken line 826, the gate-source voltage of the transistor M2 is fixed at another predetermined voltage (here 4V). When the second method is adopted, assuming that the gate-source voltage of the transistor M2 is constant, the drain current I D2 before the program operation increases with the increase of the gate width Wb of the transistor M2, but the drain current I D2 after the program operationIt can be seen that it hardly depends on the gate width Wb of the transistor M2.

[0045] Referring to FIGS. 14A and 14B, the reason why the drain current I after the program operation D2 hardly depends on the gate width Wb of the transistor M2 will be explained. Note that the specific numerical values related to the current such as 100 unit amount, 20 unit amount, and 400 unit amount used in the explanation of the reason are only for convenience in the concretization of the explanation and are understood to be just for convenience.

[0046] When the second method is adopted, consider the case where a program operation is executed on the transistor M2 having a gate width Wb of "Wb = W S " (see FIG. 14A). In this case, assuming that a current of 100 unit amount flows through the transistor M2 immediately after the start of the program operation, the gate threshold voltage of the transistor M2 increases due to the injection of hot carriers, and accordingly, the current flowing through the transistor M2 gradually decreases from 100 unit amount. Then, when the current flowing through the transistor M2 decreases to 20 unit amount, hot carriers no longer occur, and thereafter, the current flowing through the transistor M2 is maintained at 20 unit amount even if the program operation is continued. It is considered that a current of 20 unit amount or more flowing through the transistor M2 is the generation condition of hot carriers.

[0047] When the second method is adopted, consider the case where a program operation is executed on the transistor M2 having a gate width Wb of "Wb = W L " (see FIG. 14B). Under certain conditions, when "Wb = W L ", then when "Wb = W SWhen it is “[condition]”, more current flows through the channel of transistor M2 than when it is not. In this case, assuming that 400 units of current flow through transistor M2 immediately after the start of the program operation, the gate threshold voltage of transistor M2 increases due to the injection of hot carriers, and accordingly, the current flowing through transistor M2 gradually decreases from 400 units. Even when the current flowing through transistor M2 decreases to 80 units, hot carriers still occur, so the gate threshold voltage of transistor M2 further increases as the program operation continues. Then, when the current flowing through transistor M2 decreases to 20 units, hot carriers no longer occur, and thereafter, the current flowing through transistor M2 is maintained at 20 units even if the program operation is continued.

[0048] Thus, when the second method is adopted, it is found that when a sufficient length is given to the program period, the drain current I D2 after the program operation hardly depends on the gate width Wb of transistor M2 and becomes substantially constant.

[0049] [Achievement of “n:1” and “1 / n:1” by the First Method] Now, in order to stably read the first value (0) from memory cell 10 before the program operation and to stably read the second value (1) from memory cell 10 after the program operation, before the program operation, “I D2 :I D1 ≧n:1” is achieved and after the program operation, “I D2 :I D1 ≦1 / n:1” is achieved. Consider this as a necessary condition imposed on memory circuit 1. For the sake of concretizing the explanation, take the example where “n = 4”.

[0050] When using the configuration of FIG. 7 according to the first method, before the program operation, “I D2 :I D1 = 4:1” (see FIG. 15A). At this time, in order to satisfy the above necessary condition, after the program operation, “I D2 :I D1It is necessary to satisfy ≦1 / 4:1”. That is, if the drain current of each unit transistor Ma of the transistor M2 in the read operation was 1 unit amount before the program operation, it is required to reduce it to 1 / 16 unit amount after the program operation (see FIG. 15B). It is difficult to achieve this requirement. If the gate width W of each unit transistor Ma of the transistor M2 is set to the gate W as shown in the example of FIG. 14B, the reduction to 1 / 16 is possible (“20 / 400 < 1 / 16”), but it is necessary to prepare 5 unit transistors Ma of a large size, which is not practical. L Although it is possible to reduce to 1 / 16 by setting it to the gate W (since “20 / 400 < 1 / 16”), it is necessary to prepare 5 unit transistors Ma of a large size, which is not practical.

[0051] Thus, the first method has the merit that it is easy to realize the current ratio of the drain currents I D2 and I D1 as designed, but there is a difficult aspect in achieving “I D2 :I D1 ≦1 / n:1” after the program operation.

[0052] [Third Method] Therefore, a third method, which is a combination of the first method and the second method, is considered. In the memory circuit 1 according to the first embodiment, actually, the following third method is adopted. In the third method, as shown in FIG. 16, the transistor M1 is constituted by one unit transistor Ma, while the transistor M2 is constituted by a parallel circuit of m unit transistors Mb. Here, m is an arbitrary integer of 2 or more. The m unit transistors Mb constituting the transistor M2 have the same structure as each other. In the third method, each gate of the m unit transistors Mb is commonly connected to each other to constitute the gate of the transistor M2, each drain of the m unit transistors Mb is commonly connected to each other to constitute the drain of the transistor M2, and each source of the m unit transistors Mb is commonly connected to each other to constitute the source of the transistor M2. As already described, the gate width Wb, which is the gate width of each unit transistor Mb, is larger than the gate width Wa, which is the gate width of the unit transistor Ma (therefore, larger than the gate width W of the transistor M1).

[0053] Consider satisfying the above requirements when adopting the third method. As an example, referring to FIGS. 17A and 17B, consider the case where "m = 2". In this case, first, by appropriately designing the gate width Wb of each unit transistor Mb of the transistor M2, "I D2 :I D1 = 4:1" can be achieved in the read operation before the program operation. If the drain currents I D2 , I D1 are 4 unit amounts and 1 unit amount respectively at this time, a drain current of 2 unit amounts flows through each unit transistor Mb of the transistor M2 (see FIG. 17A). And in order to satisfy the above requirements, in the read operation after the program operation, it is sufficient to make the drain current of each unit transistor Mb of the transistor M2 1 / 8 unit amount or less (see FIG. 17B). The reduction from 2 unit amounts to 1 / 8 unit amounts is a reduction of 1 / 16. If the gate width W of each unit transistor Mb of the transistor M2 is set to the gate W L as shown in the example of FIG. 14B, the reduction to 1 / 16 or less is easy.

[0054] According to the memory circuit 1 adopting the third method, while enjoying the merit of the first method that it is easy to realize the current ratio of the drain currents I D2 and I D1 before the program operation as designed, the desired current ratio of the drain currents I D2 and I D1 can also be easily realized after the program operation. As a result, with a relatively small circuit size, it is possible to stably read the first value (0) from the memory cell 10 before the program operation and stably read the second value (1) from the memory cell 10 after the program operation.

[0055] <<Second Embodiment>> A second embodiment of the present disclosure will be described. The second embodiment is based on the first embodiment, and regarding matters not specifically described in the second embodiment, the description of the first embodiment is applicable to the second embodiment as long as there is no contradiction. When interpreting the description of the second embodiment, the description of the second embodiment may take precedence over matters conflicting between the first and second embodiments.

[0056] FIG. 18 is a configuration diagram of a memory array 100 according to the second embodiment. The memory array 100 is a non-volatile memory that stores multi-bit data, includes a data area DR and a history area HR, and also includes a drive circuit 120, a signal output circuit 130, and a control circuit 140. The memory array 100 is configured by a semiconductor integrated circuit. In the memory array 100, first to x-th addresses are defined, and y-bit data can be stored at each address. However, the storage of y-bit data here refers to the storage within the data area DR. The history area HR stores which address in the data area DR the data has been written to. x is an arbitrary integer of 2 or more, for example, x = 32, x = 128, or x = 256. y is also an arbitrary integer of 2 or more, for example, y = 8, y = 16, or y = 32.

[0057] x word lines WL[1] to WL[x] are connected to the drive circuit 120. The signal output circuit 130 includes a total of (y + 1) sense amplifiers SA[1] to SA[y + 1]. Two bit lines are connected to each sense amplifier. The two bit lines connected to the sense amplifier SA[j] are referred to by the symbols "BLa[j]" and "BLb[j]" (j is an integer).

[0058] The data area DR is provided with (x × y) data memory cells. Among the (x × y) data memory cells in the data area DR, the data memory cell assigned to the i-th address and at the j-th bit is referred to by the symbol "CEL[i, j]" (i and j are integers). In the data area DR, data for one word can be stored for each address, and one word consists of y bits. The history area HR is provided with x history memory cells. The x history memory cells in the history area HR are one-to-one associated with the 1st to x-th addresses. Among the x history memory cells, the history memory cell assigned to the i-th address is referred to by the symbol "CEL[i, y + 1]". Note that the word line WL[i] corresponds to the gate line (GL) for the data memory cells CEL[i, 1] to CEL[i, y] and the history memory cell CEL[i, y + 1] (see FIG. 1). The initial value stored in each data memory cell is indeterminate, and data is written and held in the data memory cells CEL[i, 1] to CEL[i, y] by a program operation for the data memory cells CEL[i, 1] to CEL[i, y]. The history memory cell CEL[i, y + 1] stores whether data has been written to the data memory cells CEL[i, 1] to CEL[i, y].

[0059] All the history memory cells in the history area HR have the same configuration as each other, and each history memory cell in the history area HR has the same configuration as the memory cell 10 in which the third method of the first embodiment is adopted. That is, each history memory cell in the history area HR consists of transistors M1 and M2 having the configuration of the third method.

[0060] FIG. 19 shows the configuration of one history memory cell CEL[i, y+1]. The history memory cell CEL[i, y+1] includes a transistor M1 composed of one unit transistor Ma, and a transistor M2 composed of a parallel circuit of m unit transistors Mb. As described in the first embodiment, m may be any integer of 2 or more, but here, it is assumed that m = 2. In the history memory cell CEL[i, y+1], the gates of the m unit transistors Mb are commonly connected to each other to form the gate of the transistor M2, the drains of the m unit transistors Mb are commonly connected to each other to form the drain of the transistor M2, and the sources of the m unit transistors Mb are commonly connected to each other to form the source of the transistor M2. The gate width W(Wb) of each unit transistor Mb is larger than the gate width W(Wa) of the unit transistor Ma, as described in the first embodiment.

[0061] In the history memory cell CEL[i, y+1], the transistor M1 has a gate, an electrode E1a, and an electrode E1b. Among the electrode E1a and the electrode E1b, the electrode on the high potential side functions as a drain and the electrode on the low potential side functions as a source. In the history memory cell CEL[i, y+1], the transistor M2 has a gate, an electrode E2a, and an electrode E2b. Among the electrode E2a and the electrode E2b, the electrode on the high potential side functions as a drain and the electrode on the low potential side functions as a source. However, in the transistor M1, the electrode E1a is fixed as the drain and the electrode E1b is fixed as the source. In the transistor M2, in principle, the electrode E2b functions as a source, but the electrode E2b can function as a drain during the execution of the program operation.

[0062] In the history memory cell CEL[i, y+1], the gates of the transistors M1 (and thus the gates of the unit transistors Ma) and the gates of the transistors M2 (and thus the gates of each of the m unit transistors Mb) are commonly connected to the word line WL[i]. In the history memory cell CEL[i, y+1], the electrodes E1b of the transistor M1 and the electrodes E2b of the transistor M2 are commonly connected to the line SL[i]. Since the electrodes E1b and E2b basically function as sources, the line SL[i] may hereinafter be referred to as the source line SL[i]. In the history memory cell CEL[i, y+1], the electrode E1a of the transistor M1 is connected to the bit line BLa[y+1], and is connected to the sense amplifier SA[y+1] via the bit line BLa[y+1]. In the history memory cell CEL[i, y+1], the electrode E2a of the transistor M2 is connected to the bit line BLb[y+1], and is connected to the sense amplifier SA[y+1] via the bit line BLb[y+1].

[0063] All data memory cells in the data area DR have the same configuration as each other, and each data memory cell in the data area DR consists of transistors M3 and M4. The transistors M3 and M4 are N-channel MOSFETs and have the same structure as each other. Each of the transistors M3 and M4 may be composed of one unit transistor Ma, or may be composed of other unit transistors having a structure different from that of the unit transistors Ma and Mb.

[0064] FIG. 20 shows the configuration of one data memory cell CEL[i, j]. When considering the data memory cell CEL[i, j], i and j represent arbitrary integers satisfying "1 ≦ i ≦ x" and "1 ≦ j ≦ y". The data memory cell CEL[i, j] consists of transistors M3 and M4.

[0065] In data memory cell CEL[i,j], transistor M3 has a gate, electrode E3a, and electrode E3b. Among electrode E3a and electrode E3b, the electrode on the high potential side functions as a drain and the electrode on the low potential side functions as a source. In transistor M3, in principle, electrode E3b functions as a source, but electrode E3b can function as a drain during the execution of a program operation. In data memory cell CEL[i,j], transistor M4 has a gate, electrode E4a, and electrode E4b. Among electrode E4a and electrode E4b, the electrode on the high potential side functions as a drain and the electrode on the low potential side functions as a source. In transistor M4, in principle, electrode E4b functions as a source, but electrode E4b can function as a drain during the execution of a program operation.

[0066] In data memory cell CEL[i,j], each gate of transistors M3 and M4 is commonly connected to word line WL[i]. In data memory cell CEL[i,j], electrode E3b of transistor M3 and electrode E4b of transistor M4 are commonly connected to line SL[i]. In data memory cell CEL[i,j], electrode E3a of transistor M3 is connected to bit line BLa[j] and is connected to sense amplifier SA[j] via bit line BLa[j]. In data memory cell CEL[i,j], electrode E4a of transistor M4 is connected to bit line BLb[j] and is connected to sense amplifier SA[j] via bit line BLb[j].

[0067] In memory array 100, a read operation for reading data stored in the data memory cells and the history memory cells, and a program operation (write operation) for rewriting data (values) stored in the data memory cells and the history memory cells can be executed. The read operation and the program operation are executed for each address.

[0068] [Read Operation] The read operation in the memory array 100 will be described. The read operation is realized by the drive circuit 120 and the signal output circuit 130 under the control of the control circuit 140. When performing the read operation, the control circuit 140 sets one of the first to y addresses as the read target address. The drive circuit 120, in cooperation with the signal output circuit 130, executes the read operation on each data memory cell and history memory cell corresponding to the read target address.

[0069] In the read operation, for each data memory cell corresponding to the read target address, based on the magnitude relationship of the drain currents of the transistors M3 and M4 in the data memory cell during the read period, the data stored in the data memory cell can be read out. In addition, in the read operation, for the history memory cell corresponding to the read target address, based on the magnitude relationship of the drain currents of the transistors M1 and M2 during the read period, the data stored in the history memory cell can be read out. By the read operation, the data stored in the data memory cells CEL[i,1] to CEL[i,y] corresponding to the read target address is output from the sense amplifiers SA[1] to SA[y] as data signals D OUT [1] to D OUT [y], and the data stored in the history memory cell CEL[i,y + 1] corresponding to the read target address is output from the sense amplifier SA[y + 1] as the history signal D OUT [y + 1].

[0070] When the read operation is performed, a precharge period is set prior to the execution of the read operation, and the read operation is performed during the read period after the precharge period.

[0071] Now, consider the case where the read target address is the i TG th address, and the read operation for the i TG th address will be described (i TG is an integer greater than or equal to 1 and less than or equal to x). When the read target address is the i TG th address, the data memory cell CEL[i TG corresponding to the i TG,1] to CEL[i TG ,y] and the history memory cell CEL[i TG ,y + 1] is subjected to a read operation.

[0072] At this time, during the read period and the precharge period, the voltages of all source lines SL[1] to SL[x] are set to 0V (see FIGS. 21 and 22). Therefore, in the transistor M2 of the history memory cell CEL[i TG ,y + 1], the electrode E2a functions as a drain and the electrode E2b functions as a source. In the transistor M1 of the history memory cell CEL[i TG ,y + 1], the electrode E1a always functions as a drain and the electrode E1b functions as a source. Further, in the data memory cells CEL[i TG ,1] to CEL[i TG ,y], the electrodes E3a and E3b of each transistor M3 function as a drain and a source, respectively, and the electrodes E4a and E4b of each transistor M4 function as a drain and a source, respectively. Also, during the precharge period, the voltages of all word lines WL[1] to WL[x] are set to 0V by the drive circuit 120 (see FIG. 21). In addition, during the precharge period, positive charges are supplied to all bit lines BLa[1] to BLa[y + 1] and BLb[1] to BLb[y + 1], so that the voltages of the bit lines BLa[1] to BLa[y + 1] and BLb[1] to BLb[y + 1] are set to a common precharge voltage V PC is set (see FIG. 21). The precharge voltage V PC has a predetermined positive DC voltage value (for example, 1V). The above positive charges may be supplied from the signal output circuit 130.

[0073] After the precharge period, as shown in FIG. 22, a positive read voltage V TG is supplied only to the word line WL[i RD corresponding to the read target address, and the read period starts (however, in FIG. 22, the situation of "i TG = x" is assumed). Thereby, in the read operation (that is, during the read period), the history memory cell CEL[i TG, y + 1], the gates of transistors M1 and M2 (specifically, between the gates and sources of transistors M1 and M2 respectively), and the data memory cell CEL[i assigned to the read target address TG , 1] to [i TG , y], for each of the gates of transistors M3 and M4 (specifically, between the gates and sources of transistors M3 and M4 respectively), the read voltage V RD is supplied. During the read period, the voltage of each word line other than the word line WL[i TG is maintained at 0V. The read voltage V RD may be a constant DC voltage, or may be a voltage that varies slightly with the passage of time during the read period. The read voltage V RD is higher than at least one of the gate threshold voltages of transistors M1 and M2 and higher than at least one of the gate threshold voltages of transistors M3 and M4.

[0074] In this embodiment, as shown in FIG. 23, the drain currents of transistors M1 and M2 during the read period in the history memory cell CEL[i TG , y + 1] are referred to by the symbols "I D1 " and "I D2 " respectively. Further, as shown in FIG. 24, the drain currents of transistors M3 and M4 during the read period in the data memory cell CEL[i TG , 1] to CEL[i TG , y], which is any one of the data memory cells CEL[i TG , j], are referred to by the symbols "I D3 " and "I D4 " respectively.

[0075] Still, during the read period, for any integer j, the input impedance of the signal output circuit 130 as seen from the bit line BLa[j] and the input impedance of the signal output circuit 130 as seen from the bit line BLb[j] are set to be sufficiently high. In addition, during the read period, the word line WL[i TGSince the voltages of the word lines other than [[ID=]]] are maintained at 0V, all the transistors M1 to M4 corresponding to the addresses other than the read target address are maintained in the off state. As a result, during the read period, in the history memory cell CEL[i TG ,y+1], only when the drain current I D1 flows through the transistor M1, the voltage of the bit line BLa[y+1] decreases, and only when the drain current I D2 flows through the transistor M2, the voltage of the bit line BLb[y+1] decreases. Also, in the data memory cell CEL[i TG ,j], only when the drain current I D3 flows through the transistor M3, the voltage of the bit line BLa[j] decreases, and only when the drain current I D4 flows through the transistor M4, the voltage of the bit line BLb[j] decreases.

[0076] In the read operation (in other words, during the read period), the state where the drain current I D2 is larger than the drain current I D1 corresponds to the state where the first value is stored in the history memory cell CEL[i TG ,y+1], and the state where the drain current I D1 is larger than the drain current I D2 corresponds to the state where the second value is stored in the history memory cell CEL[i TG ,y+1].

[0077] Therefore, in the read operation, the sense amplifier SA[y+1] determines the magnitude relationship between the drain currents I TG and I D1 based on the voltages of the bit lines BLa[y+1] and BLb[y+1]. When the drain current I D2 is larger than the drain current I D2 , it outputs the history signal D D1 [y+1] associated with the first value (in other words, the history signal D OUT [y+1] representing the first value), and when the drain current I OUT ​D1 is greater than the drain current I D2 , a history signal D associated with the second value is output when it is greater than the drain current I OUT [y + 1] (in other words, the history signal D representing the second value OUT [y + 1]) is output. Here, it is assumed that the first value is "0" and the second value is "1". Also, the low-level history signal D OUT [y + 1] represents the first value (0) and the high-level history signal D OUT [y + 1] represents the data of the second value (1).

[0078] In the read operation (in other words, during the read period), among the drain currents I TG and I D3 of the data memory cell CEL[i D4 , j], the state where the drain current I D3 is greater than the drain current I D4 corresponds to the state where the third value is stored in the data memory cell CEL[i TG , j], and the state where the drain current I D4 is greater than the drain current I D3 corresponds to the state where the fourth value is stored in the data memory cell CEL[i TG , j].

[0079] Therefore, in the read operation, the sense amplifier SA[1] corresponding to the first bit determines the magnitude relationship between the drain currents I TG and I D3 of the data memory cell CEL[i D4 , 1] based on the voltages of the bit lines BLa[1] and BLb[1], and when the drain current I D3 is greater than the drain current I D4 , it outputs a data signal D OUT [1] (in other words, the data signal D OUT [1] representing the third value), and when the drain current I D4 is greater than the drain current I D3 , it outputs a data signal D OUT[1](In other words, a data signal D representing a fourth value OUT [1]) is output. Similarly, in the read operation, the sense amplifier SA[2] corresponding to the second bit determines, based on the voltages of the bit lines BLa[2] and BLb[2], the drain currents I TG and I D3 of the data memory cell CEL[i D4 ,2], determines the magnitude relationship between them, and when the drain current I D3 is greater than the drain current I D4 , outputs a data signal D OUT [2] associated with a third value (in other words, a data signal D OUT [2] representing the third value), and when the drain current I D4 is greater than the drain current I D3 , outputs a data signal D OUT [2] associated with a fourth value (in other words, a data signal D OUT [2] representing the fourth value).

[0080] The same applies to the sense amplifiers SA[3] to SA[y] corresponding to the third to y-th bits. That is, in the read operation, for each data memory cell of the read target address, a data signal (D D3 and I D4 ) associated with a third value or a fourth value is output based on the magnitude relationship between the drain currents I OUT [j] of the data memory cell. Here, it is assumed that the third value is "0" and the fourth value is "1". Also, for any integer j satisfying "1 ≤ j ≤ y", it is assumed that a low-level data signal D OUT [j] represents the third value (0) and a high-level data signal D OUT [j] represents the fourth value (1).

[0081] For any integer j satisfying “1 ≦ j ≦ y + 1”, the operation of the sense amplifier SA[j] based on the voltages of the bit lines BLa[j] and BLb[j] is the same as the operation of the signal output circuit 30 based on the voltages of the drain lines DL1 and DL2 in FIG. 1. That is, for example, for any integer j satisfying “1 ≦ j ≦ y + 1”, the sense amplifier SA[j] identifies the voltage that first becomes equal to or lower than a predetermined voltage among the voltages of the bit lines BLa[j] and BLb[j] after the start of the read period, thereby determining the level of the data signal or the history signal D OUT [j].

[0082] [Program operation] The program operation in the memory array 100 will be described. The program operation is realized by the drive circuit 120 under the control of the control circuit 140. Therefore, it can be considered that the control circuit 140 performs the program operation using the drive circuit 120. When performing the program operation, the control circuit 140 sets one of the first to y addresses as the write target address (in other words, the program target address). The program operation is executed for each data memory cell and history memory cell corresponding to the write target address.

[0083] Each data memory cell is composed of transistors M3 and M4 having the same structure as each other as described above. For this reason, if a common gate-source voltage is supplied to the transistors M3 and M4 before the program operation, the magnitude relationship of their drain currents is indeterminate, and thus the data (value) read from the data memory cell is also indeterminate. Therefore, in the program operation, hot carriers are injected into either one of the transistors M3 and M4 in each data memory cell at the write target address. On the other hand, in the program operation, hot carriers are always injected into the transistor M2 of the history memory cell at the write target address, thereby writing the second value (1) into the history memory cell at the write target address. As a result, it is stored in the history memory cell at the write target address that data has been written into each data memory cell at the write target address.

[0084] Now, considering the case where the write target address is the i-th TG address, the program operation for the i-th TG address will be described (i TG is an integer greater than or equal to 1 and less than or equal to x). When the write target address is the i-th TG address, for the data memory cells CEL[i TG ,1] to CEL[i TG ,y] and the history memory cell CEL[i TG ,y + 1] corresponding to the i-th TG address, program operations are performed.

[0085] The program operation for the history memory cell CEL[i TG ,y + 1] is the same as the program operation for the memory cell 10 described in the first embodiment. That is, in the program operation for the history memory cell CEL[i TG ,y + 1], among the transistors M1 and M2 of the history memory cell CEL[i TG ,y + 1], hot carriers are injected only into the transistor M2 to change the electrical characteristics of the transistor M2. Due to this change, the gate threshold voltage of the transistor M2 increases. After the execution of the program operation in which the i-th TG address is set as the write target address, in the history memory cell CEL[i TG ,y + 1], the program operation is executed such that the gate threshold voltage of the transistor M2 becomes sufficiently higher than the gate threshold voltage of the transistor M1. At this time, the gate threshold voltage of the transistor M2 after the execution of the program operation may be higher than the read voltage V RD .

[0086] The control circuit 140 outputs write word data representing the y-bit data to be written to the y-bit data memory cells at the write target address (here, the i-th TG address). The write word data may be data generated by the control circuit 140, or may be data supplied from an external circuit (not shown) of the memory array 100 to the control circuit 140. The data memory cells CEL[i TG,1] to CEL[i TG In the program operation for, y], based on the write word data, for each data memory cell of the i-th TG address, hot carriers are injected into one of the transistors M3 and M4.

[0087] That is, for example, when it is indicated by the write word data that the third value (0) should be written to the data memory cell CEL[i TG ,1], in the program operation for the data memory cell CEL[i TG ,1], in the program operation for the data memory cell CEL[i TG ,1], by injecting hot carriers only into the transistor M4 among the transistors M3 and M4 of the data memory cell CEL[i TG ,1], the electrical characteristics of the transistor M4 are changed. Due to this change, the gate threshold voltage of the transistor M4 increases. After the execution of this program operation, in the data memory cell CEL[i RD ,1], the program operation is executed so that the gate threshold voltage of the transistor M4 becomes sufficiently higher than the gate threshold voltage of the transistor M3. At this time, the gate threshold voltage of the transistor M4 after the execution of the program operation may be higher than the read voltage V Also, for example, when it is indicated by the write word data that the fourth value (1) should be written to the data memory cell CEL[i TG ,2], in the program operation for the data memory cell CEL[i TG ,2], in the program operation for the data memory cell CEL[i TG ,2], by injecting hot carriers only into the transistor M3 among the transistors M3 and M4 of the data memory cell CEL[i TG ,2], the electrical characteristics of the transistor M3 are changed. Due to this change, the gate threshold voltage of the transistor M3 increases. After the execution of this program operation, in the data memory cell CEL[i RD ,2], the program operation is executed so that the gate threshold voltage of the transistor M3 becomes sufficiently higher than the gate threshold voltage of the transistor M4. At this time, the gate threshold voltage of the transistor M3 after the execution of the program operation may be higher than the read voltage V Data memory cell CEL[i TG ,3] to CEL[i TG ,y] is the same for the program operation.

[0088] Fig. 25 shows an example of the state of the memory array 100 during the program period. However, in Fig. 25, "i TG =x", and it is assumed that a program operation is executed to write the third value (0), the fourth value (1), and the third value (0) to the data memory cells CEL[i TG ,1], CEL[i TG ,2], and CEL[i TG ,y], respectively.

[0089] The hot carrier injection method may be the same as in the first embodiment. That is, during the program period in which the program operation for the i TG -th address is executed, a positive voltage V TG is applied to the line SL[i PRG1 , and a positive voltage V TG is applied to the word line WL[i PRG2 by the drive circuit 120, and 0V is applied to all word lines except the word line WL[i TG (see Fig. 25; assuming "i TG =x" in Fig. 25). The application of the voltage V TG to the line SL[i PRG1 may also be realized by the drive circuit 120. At this time, the voltage V PRG1 may be applied to all of the lines SL[1] to SL[x], or 0V may be applied to all lines other than the line SL[i TG among the lines SL[1] to SL[x]. The voltages V PRG1 and V PRG2 are as described in the first embodiment.

[0090] Then, during the above program period, while short - circuiting bit line BLb[y + 1] to ground through a switch (the switch is always off outside the program period; the switch is not shown in FIG. 18 etc.), bit line BLa[y + 1] is set to an open state (high - impedance state) without being short - circuited to ground. As a result, in history memory cell CEL[i TG ,y + 1], current flows from line SL[i TG through transistor M2 towards ground (assuming "i TG = x" as shown in FIG. 25 above). During the process of this current flowing, hot carriers are injected into transistor M2, causing the characteristics of transistor M2 to change, and the gate threshold voltage of transistor M2 to increase. After maintaining the program period for a time sufficient to increase the gate threshold voltage of transistor M2 sufficiently, the program operation is terminated.

[0091] Also, for example, when it is indicated by write - word data that a third value (0) should be written to data memory cell CEL[i TG ,1], during the above program period, while short - circuiting bit line BLb[1] to ground through a switch (the switch is always off outside the program period; the switch is not shown in FIG. 18 etc.), bit line BLa[1] is set to an open state (high - impedance state) without being short - circuited to ground. As a result, in data memory cell CEL[i TG ,1], current flows from line SL[i TG through transistor M4 towards ground (assuming "i TG = x" as shown in FIG. 25 above). During the process of this current flowing, hot carriers are injected into transistor M4, causing the characteristics of transistor M4 to change, and the gate threshold voltage of transistor M4 to increase. After maintaining the program period for a time sufficient to increase the gate threshold voltage of transistor M4 sufficiently, the program operation is terminated. Also, for example, when it is indicated by write - word data that a third value (0) should be written to data memory cell CEL[i TGWhen it is indicated that the fourth value (1) should be written to ,2], during the above program period, while short - circuiting bit line BLa[2] to ground via a switch (the switch is always off outside the program period; the switch is not shown in FIG. 18 etc.), bit line BLb[2] is left in an open state (high - impedance state) without being short - circuited to ground. As a result, in data memory cell CEL[i TG ,2], current flows from line SL[i TG through transistor M3 towards ground (assuming i TG = x” in the example of FIG. 25 as described above). During the process of this current flowing, hot carriers are injected into transistor M3, causing the characteristics of transistor M3 to change, and the gate threshold voltage of transistor M3 to increase. After maintaining the program period for a time sufficient to increase the gate threshold voltage of transistor M3 sufficiently, the program operation is terminated. The program operation for data memory cells CEL[i TG ,3] to CEL[i TG ,y] is the same.

[0092] As can be understood from the above description, regarding the read operation and the program operation focused on the i TG th address, the following can be said. When the read operation is executed with the i TG th address set as the read target address before the program operation is executed for the i TG th address, the drain current (I TG ) of transistor M2 in the history memory cell CEL[i D2 ,y + 1] of the read target address is larger than the drain current (I D1 ) of transistor M1. After the i TG th address is set as the write target address and the program operation is executed for the i TG th address, when the read operation is executed with the i TG th address set as the read target address, in the history memory cell CEL[i TG, y + 1], as the gate threshold voltage of transistor M2 increases, the drain current (I D1 ) of transistor M1 becomes larger than the drain current (I D2 ) of transistor M2, and in each of the data memory cells CEL[i TG , 1] to CEL[i TG , y] of the lead target address, as the gate threshold voltage of one of the transistors M3 and M4, which is the target of hot carrier injection, increases, the drain current of the other transistor becomes larger than the drain current of one of the transistors.

[0093] Note that the method for realizing the program operation is not limited to the above-described method, and any method can be used as long as hot carriers can be injected only into the necessary transistors.

[0094] [Usage Examples of History Memory Cells and Memory Arrays] When the first value (0) is stored in the history memory cell CEL[i, y + 1] at the i-th address, the first value (0) means that data has not been written yet to the data memory cells CEL[i, 1] to CEL[i, y]. When the second value (1) is stored in the history memory cell CEL[i, y + 1], the second value (1) means that data has been written to the data memory cells CEL[i, 1] to CEL[i, y].

[0095] Since each data memory cell and each history memory cell correspond to an OTP (One Time Programmable ROM) that can write data only once, the control circuit 140 can set only the address in which the first value (0) is stored in the corresponding history memory cell as the write target address when setting the write target address.

[0096] That is, for example, in a situation where only the second value (1) is stored in the history memory cells CEL[1,y+1] and CEL[2,y+1] corresponding to the first and second addresses among the history memory cells CEL[1,y+1] to CEL[x,y+1], when writing new write word data to the data area DR by a program operation, the control circuit 140 sets any one of the third to x-th addresses as the write target address (usually, the third address may be set as the write target address).

[0097] Therefore, for example, the memory array 100 can be used as follows. In the initial state of the memory array 100, the first value (0) is stored in all of the history memory cells CEL[1,y+1] to CEL[x,y+1], and the stored values of all the data memory cells are indefinite. When writing the first write word data to the data area DR, the control circuit 140 sets the first address as the write target address and performs a program operation to write the first write word data to the data memory cells CEL[1,1] to CEL[1,y] at the first address and simultaneously write the second value (1) to the history memory cell CEL[1,y+1] at the first address.

[0098] Thereafter, when writing the second write word data to the data area DR, the control circuit 140 sets the second address as the write target address and performs a program operation to write the second write word data to the data memory cells CEL[2,1] to CEL[2,y] at the second address and simultaneously write the second value (1) to the history memory cell CEL[2,y+1] at the second address. The same applies when writing the third and subsequent write word data to the data area DR.

[0099] Actually, prior to the execution of the program operation, the control circuit 140 reads all or part of the values stored in the history memory cells CEL[1, y+1] to CEL[x, y+1] by a read operation, and among the history memory cells CEL[1, y+1] to CEL[x, y+1], identifies the history memory cell in which the first value (0) is stored and that corresponds to the youngest address number, and may set the address corresponding to the identified history memory cell as the write target address. Therefore, for example, if only the second value (1) is stored in the history memory cells CEL[1, y+1] and CEL[2, y+1] among the history memory cells CEL[1, y+1] to CEL[x, y+1], the third address corresponding to the history memory cell CEL[3, y+1] may be set as the write target address.

[0100] As a result, memory utilization such that the write word data for y bits can be rewritten x times becomes possible. At this time, each data memory cell in the data area DR can be formed in a small size to the extent that an initial stored value is allowed to be indefinite. The initial value of the history memory cell can be determined, and the effects shown in the first embodiment can be further enjoyed.

[0101] <<Modifications, etc.>> Hereinafter, modifications, application examples, etc. applicable to the first or second embodiment will be described.

[0102] In the above operation example, it is assumed that the first value is "0" and the second value is "1", but as long as the first and second values are different, the first and second values are arbitrary. Also, the signal D OUT (In the second embodiment, the history signal D OUT [y+1]) becomes a high-level signal and the signal D associated with the second value OUT (In the second embodiment, the history signal D OUTThe circuit may be configured such that [y + 1]) becomes a low-level signal. Similarly, in the above operation example, it is assumed that the third value is "0" and the fourth value is "1", but as long as the third and fourth values are different, the third and fourth values are arbitrary. Also, the data signal D associated with the third value OUT [j] becomes a high-level signal and the data signal D associated with the fourth value OUT [j] becomes a low-level signal. Also, the match / mismatch between the first value and the third value or the fourth value is arbitrary, and the match / mismatch between the second value and the third value or the fourth value is also arbitrary.

[0103] The non-volatile memory (memory circuit 1 or memory array 100) according to the present disclosure can be incorporated into any circuit or device that realizes a predetermined functional operation. When a power supply voltage is supplied to the circuit or device in which the non-volatile memory is incorporated and the circuit or device is activated, the circuit or device reads the data stored in the non-volatile memory by a read operation and realizes a predetermined functional operation according to the read data. For example, a non-volatile memory (memory circuit 1 or memory array 100) can be incorporated into an amplifier circuit (not shown) capable of varying the amplification factor according to trimming data, and the amplification factor of the amplifier circuit can be optimally adjusted by supplying one or more data stored in the non-volatile memory as trimming data to the amplifier circuit. Also, the non-volatile memory according to the present disclosure can be incorporated into semiconductor integrated circuits for various applications such as semiconductor integrated circuits for DC / DC converters and semiconductor integrated circuits for motor drivers. The above amplifier circuit is an example of a circuit provided in these semiconductor integrated circuits.

[0104] The type of channel of the FET (field effect transistor) shown in each embodiment is an example, and the configuration of the circuit including the FET can be modified such that the N-channel type FET is changed to a P-channel type FET, or the P-channel type FET is changed to an N-channel type FET.

[0105] Unless there is a problem, any of the above transistors can be any type of transistor. For example, any transistor described as a MOSFET can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor, unless there is a problem. Any transistor has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is a drain and the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector and the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector and the other is an emitter, and the control electrode is a base.

[0106] Embodiments of the present disclosure can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each component are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and of course, they can be changed to various numerical values.

[0107] <<Appendix>> Consider the technical idea embodied in the above embodiment.

[0108] A non-volatile memory according to one aspect of the present disclosure includes a memory cell having a first transistor and a second transistor, a drive circuit configured to supply a read voltage to each gate of the first transistor and the second transistor, and a signal output circuit configured to output a signal associated with a first value or a signal associated with a second value based on each drain current of the first and second transistors in a read operation in which the read voltage is supplied. The second transistor is configured by a parallel circuit of a plurality of unit transistors, and the gate width of each unit transistor is larger than the gate width of the first transistor (a first configuration).

[0109] In the non-volatile memory according to the first configuration, in the read operation, when the drain current of the second transistor is larger than the drain current of the first transistor, the signal output circuit is configured to output a signal associated with the first value, and when the drain current of the first transistor is larger than the drain current of the second transistor, it may be configured to output a signal associated with the second value (second configuration).

[0110] In the non-volatile memory according to the second configuration, it is possible to execute a program operation for increasing the gate threshold voltage of the second transistor by injecting hot carriers into the second transistor. In the read operation executed before the program operation, the drain current of the second transistor is larger than the drain current of the first transistor, and in the read operation executed after the program operation, as the gate threshold voltage of the second transistor increases due to the program operation, the drain current of the first transistor may be larger than the drain current of the second transistor (third configuration).

[0111] Other non-volatile memories according to the present disclosure are non-volatile memories configured to store data of a plurality of bits at each of a plurality of addresses. At each address, a history memory cell having a first transistor and a second transistor is provided, and at each address, a plurality of data memory cells having a third transistor and a fourth transistor are provided. Further, a control circuit configured to set any one of the plurality of addresses as a read target address, a drive circuit configured to supply a read voltage to gates of the first to fourth transistors in the history memory cell and each data memory cell assigned to the read target address, and in a read operation in which the read voltage is supplied for the read target address, a history signal associated with a first value or a second value is output based on drain currents of the first and second transistors in the history memory cell of the read target address, and a data signal associated with a third value or a fourth value is output based on drain currents of the third and fourth transistors of each data memory cell for the data memory cell of the read target address. A signal output circuit configured to do so is provided. In the history memory cell of each address, the second transistor is configured by a parallel circuit of a plurality of unit transistors, and a gate width of each unit transistor is larger than a gate width of the first transistor (fourth configuration).

[0112] In the non-volatile memory according to the fourth configuration, in the read operation for the read target address, for the history memory cell, when the drain current of the second transistor is larger than the drain current of the first transistor, the signal output circuit is configured to output the history signal associated with the first value, and when the drain current of the first transistor is larger than the drain current of the second transistor, the signal output circuit is configured to output the history signal associated with the second value. For each data memory cell of the read target address, when the drain current of the third transistor is larger than the drain current of the fourth transistor, the signal output circuit is configured to output the data signal associated with the third value, and when the drain current of the fourth transistor is larger than the drain current of the third transistor, the signal output circuit is configured to output the data signal associated with the fourth value (a fifth configuration).

[0113] In the non-volatile memory according to the fifth configuration, the control circuit can set any one of the plurality of addresses as a write target address, and can execute a program operation on the write target address using the drive circuit. In the program operation on the write target address, hot carriers are injected into the second transistor in the history memory cell of the write target address to increase the gate threshold voltage of the second transistor, and for each data memory cell of the write target address, hot carriers are injected into one of the third and fourth transistors to increase the gate threshold voltage of the targeted transistor. When the read operation is executed in a state where the specific address is set as the read target address before the program operation is executed on the specific address, the drain current of the second transistor in the history memory cell of the read target address is larger than the drain current of the first transistor. After the specific address is set as the write target address and the program operation is executed on the specific address, when the read operation is executed in a state where the specific address is set as the read target address, in the history memory cell of the read target address, as the gate threshold voltage of the second transistor increases, the drain current of the first transistor is larger than the drain current of the second transistor, and in each data memory cell of the read target address, as the gate threshold voltage of one of the third and fourth transistors that is the target of hot carrier injection increases, the drain current of the other transistor is larger than the drain current of the one transistor (the sixth configuration) may be employed.

[0114] In the non-volatile memory according to any one of the fourth to sixth configurations, in each data memory cell of each address, the third and fourth transistors may have the same structure as each other (the seventh configuration).

[0115] Still another non-volatile memory according to the present disclosure includes a memory cell having a first transistor and a second transistor, a drive circuit configured to supply a read voltage to each gate of the first transistor and the second transistor, and a signal output circuit configured to output a signal associated with a first value or a signal associated with a second value based on each drain current of the first and second transistors in a read operation in which the read voltage is supplied. The second transistor is configured by a parallel circuit of a plurality of unit transistors, and the gate width of each unit transistor is larger than the gate width of the first transistor (eighth configuration).

[0116] Still another non-volatile memory according to the present disclosure is a non-volatile memory configured to store data for a plurality of bits at each of a plurality of addresses. At each address, a history memory cell having a first transistor and a second transistor is provided, and a plurality of data memory cells having a third transistor and a fourth transistor are provided. Further, a control circuit configured to be able to set any one of the plurality of addresses as a read target address, a drive circuit configured to supply a read voltage to each gate of the first to fourth transistors in the history memory cell and each data memory cell assigned to the read target address, and in a read operation in which the read voltage is supplied for the read target address, a history signal associated with a first value or a second value is output based on each drain current of the first and second transistors in the history memory cell of the read target address, and a data signal associated with a third value or a fourth value is output based on each drain current of the third and fourth transistors of each data memory cell for the data memory cell of the read target address. In the history memory cell of each address, the second transistor is configured by a parallel circuit of a plurality of unit transistors, and the gate width of each unit transistor is larger than the gate width of the first transistor (ninth configuration).

Description of Reference Numerals

[0117] 1 Memory circuit 10 Memory cells 20 Driving circuit 30 Signal output circuit 100 Memory array 120 Driving circuit 130 Signal output circuit 140 Control circuit Memory cells CEL[1,1] to CEL[x,y+1] DR Data area HR History area

Claims

1. A memory cell having a first transistor and a second transistor, A drive circuit configured to supply a read voltage to each gate of the first transistor and the second transistor, In a read operation in which the read voltage is supplied, based on drain currents of the first and second transistors, a signal associated with a first value or a signal associated with a second value is output. A signal output circuit configured as described above, The second transistor is configured by a parallel circuit of a plurality of unit transistors, and a gate width of each unit transistor is larger than a gate width of the first transistor , a non-volatile memory.

2. In the read operation, when the drain current of the second transistor is larger than the drain current of the first transistor, the signal output circuit outputs a signal associated with the first value. When the drain current of the first transistor is larger than the drain current of the second transistor, the signal output circuit is configured to output a signal associated with the second value , the non-volatile memory according to claim 1.

3. It is possible to execute a program operation for increasing the gate threshold voltage of the second transistor by injecting hot carriers into the second transistor, In the read operation performed before the program operation, the drain current of the second transistor is larger than the drain current of the first transistor, In the read operation performed after the program operation, as the gate threshold voltage of the second transistor increases due to the program operation, the drain current of the first transistor is larger than the drain current of the second transistor , the non-volatile memory according to claim 2.

4. In a non-volatile memory configured to store data for a plurality of bits at each of a plurality of addresses, For each of the addresses, a history memory cell having a first transistor and a second transistor is provided, and a plurality of data memory cells each having a third transistor and a fourth transistor are provided for each of the addresses, and further, a control circuit configured to set any one of the plurality of addresses as a read target address, a drive circuit configured to supply a read voltage to each of the gates of the first to fourth transistors in the history memory cell and each data memory cell assigned to the read target address, in a read operation in which the read voltage is supplied for the read target address, a history signal associated with a first value or a second value is output based on each drain current of the first and second transistors in the history memory cell of the read target address, and a data signal associated with a third value or a fourth value is output for each data memory cell of the read target address based on each drain current of the third and fourth transistors of the data memory cell, and a signal output circuit configured as such is provided, In the history memory cell of each address, the second transistor is configured by a parallel circuit of a plurality of unit transistors, and the gate width of each unit transistor is larger than the gate width of the first transistor , a non-volatile memory.

5. In the read operation for the read target address, the signal output circuit for the history memory cell, when the drain current of the second transistor is larger than the drain current of the first transistor, the history signal associated with the first value is output, and when the drain current of the first transistor is larger than the drain current of the second transistor, the history signal associated with the second value is output, For each of the data memory cells of the target read address, when the drain current of the third transistor is greater than the drain current of the fourth transistor, the data signal associated with the third value is output, and when the drain current of the fourth transistor is greater than the drain current of the third transistor, it is configured to output the data signal associated with the fourth value. , the non-volatile memory according to claim 4.

6. The control circuit can set any one of the plurality of addresses as a write target address and execute a program operation on the write target address using the drive circuit. In the program operation for the write target address, By injecting hot carriers into the second transistor in the history memory cell of the write target address, the gate threshold voltage of the second transistor is increased, and For each of the data memory cells of the write target address, by injecting hot carriers into one of the third and fourth transistors, the gate threshold voltage of the targeted transistor is increased. When the read operation is executed in a state where the specific address is set as the read target address before the program operation is executed for the specific address, In the history memory cell of the read target address, the drain current of the second transistor is greater than the drain current of the first transistor. When the read operation is executed in a state where the specific address is set as the read target address after the specific address is set as the write target address and the program operation is executed for the specific address, In the history memory cell of the read target address, as the gate threshold voltage of the second transistor increases, the drain current of the first transistor is greater than the drain current of the second transistor, and In each data memory cell of the target read address, as the gate threshold voltage of one of the third and fourth transistors, which is the target of hot carrier injection, increases, the drain current of the other transistor becomes larger than the drain current of the one transistor. , the non-volatile memory according to claim 5.

7. In each data memory cell of each address, the third and fourth transistors have the same structure as each other. , the non-volatile memory according to any one of claims 4 to 6.

8. A memory cell having a first transistor and a second transistor, A drive circuit configured to be able to supply a read voltage to each gate of the first transistor and the second transistor, In a read operation in which the read voltage is supplied, based on the drain currents of the first and second transistors, a signal output circuit configured to be able to output a signal associated with a first value or a signal associated with a second value is provided. The second transistor is configured by a parallel circuit of a plurality of unit transistors, and the gate width of each unit transistor is larger than the gate width of the first transistor. , a non-volatile memory.

9. In a non-volatile memory configured to store data for a plurality of bits at each of a plurality of addresses, each address includes a history memory cell having a first transistor and a second transistor, and each address includes a plurality of data memory cells having a third transistor and a fourth transistor, and further, a control circuit configured to be able to set any one of the plurality of addresses as a target read address, a drive circuit configured to be able to supply a read voltage to each gate of the first to fourth transistors in the history memory cell and each data memory cell assigned to the target read address, In a read operation in which the read voltage is supplied to the read target address, a history signal associated with a first value or a second value is outputtable based on the drain currents of the first and second transistors in the history memory cell of the read target address, and a data signal associated with a third value or a fourth value is outputtable for each data memory cell of the read target address based on the drain currents of the third and fourth transistors of the data memory cell, and a signal output circuit configured to output the data signal; In the history memory cell of each address, the second transistor is configured by a parallel circuit of a plurality of unit transistors, and the gate width of each unit transistor is larger than the gate width of the first transistor , a non-volatile memory.

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