Non-volatile memory

Abstract

In the present invention, a memory cell includes first and second transistors. A driving circuit includes: a boost circuit configured to generate a boosted voltage on a boost line by boosting a prescribed reference voltage; and an adjustment circuit configured to adjust the boosted voltage by letting an adjustment current corresponding to the boosted voltage flow in from the boost line. The driving circuit supplies the adjusted boosted voltage to the respective gates of the first and second transistors as a read voltage. In a read operation, in which the read voltage is supplied, a signal output circuit outputs a signal associated with a first value or a second value on the basis of the respective drain currents of the first and second transistors.

Description

Technical Field

[0001] The present disclosure relates to non-volatile memories.

Background Art

[0002] There is a non-volatile memory that utilizes hot carrier injection into a transistor. This type of non-volatile memory includes first and second transistors (m1 and m2; not shown) whose characteristics are aligned in an initial state as memory elements, and hot carriers are injected only into one of the transistors to change the characteristics of the transistor. In a subsequent read operation, based on the magnitude relationship of the drain currents when a common gate voltage (read voltage) is supplied to the first and second transistors, it is determined whether "0" data or "1" data is stored. For example, a state where the drain current of the first transistor is smaller (a state where the characteristics of the first transistor have changed) corresponds to a state where "0" data is stored, and a state where the drain current of the second transistor is smaller (a state where the characteristics of the second transistor have changed) corresponds to a state where "1" data is stored.

[0003] However, in the above non-volatile memory, the stored data (stored value) in the initial state is indeterminate. There has also been proposed a non-volatile memory configured such that in the initial state, more drain current flows through the second transistor among the first and second transistors so that the stored data in the initial state does not become indeterminate. In this type of non-volatile memory, the stored data can be determined to be "0" in the initial state, and the stored data can be set to "1" through hot carrier injection into the second transistor.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, the gate threshold voltages of the memory elements (m1, m2) in the non-volatile memory are relatively high. In order to surely generate a gate voltage (read voltage) higher than the gate threshold voltage in the read operation, it is considered beneficial to use a charge pump. At this time, from the viewpoint of reducing the circuit size and the like, it is preferable to form a charge pump with a simple configuration. However, in this case, it becomes difficult to accurately apply the read voltage to the gates of the memory elements (m1, m2).

[0006] In addition, the relationship between the gate-source voltage and the drain current in the memory elements (m1, m2) varies greatly depending on element variations and temperature changes. Therefore, even if the read voltage is constant, the drain currents of the memory elements (m1, m2) during the read operation vary variously. The variation in the drain current of the memory elements (m1, m2) during the read operation becomes more prominent if the read voltage varies.

[0007] On the one hand, if the drain current of the memory elements (m1, m2) during the read operation is excessively large, it will lead to an increase in power consumption. From the perspective of power saving, it is preferable to reduce the drain current during the read operation. However, if those drain currents are too small, it becomes difficult to read out the stored data within a limited time. For this reason, during the read operation, it is preferable to pass an appropriate-sized drain current through the memory elements (limiting the variation range of the drain current magnitude) without depending on element variations or temperature changes. If such a requirement can be met (if the drain current of the memory elements during the read operation can be optimized), power saving can be achieved. Also, when there is a large variation in the drain current of the memory elements (m1, m2) during the read operation, the size of the peripheral circuit (for example, the circuit that serves as the current supply source and the switch on the path through which the current flows) needs to be configured considering the maximum value of the drain current in the design. However, by limiting the variation range of the drain current magnitude, it is also possible to reduce the size of the peripheral circuit. Furthermore, when the drain current of the memory elements (m1, m2) during the read operation varies greatly, it has an adverse effect on the characteristics of the non-volatile memory. However, by limiting the variation range of the drain current magnitude (ideally making it constant), an improvement in the characteristics of the non-volatile memory can also be expected.

[0008] An object of the present disclosure is to provide a non-volatile memory that contributes to the optimization of the drain current of a memory element (transistor) during the read operation.

Means for Solving the Problems

[0009] The non-volatile memory according to the present disclosure includes a memory cell having a first transistor and a second transistor, a drive circuit configured to supply a read voltage to each gate of the first transistor and the second transistor, and in a read operation in which the read voltage is supplied, based on the drain current of each of the first and second transistors, a signal output circuit configured to output a signal associated with a first value or a signal associated with a second value. The drive circuit includes a boost circuit configured to generate a boost voltage on a boost line by boosting a predetermined reference voltage, and an adjustment circuit configured to adjust the boost voltage by drawing an adjustment current corresponding to the boost voltage from the boost line. In the read operation, the adjusted boost voltage is supplied as the read voltage to each gate of the first transistor and the second transistor.

Advantages of the Invention

[0010] According to the present disclosure, it is possible to provide a non-volatile memory that contributes to optimizing the drain current of a memory element (transistor) during a read operation.

Brief Description of the Drawings

[0011]

Figure 1

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Figure 5B

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Figure 14A

Figure 14B

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Figure 16

Best Mode for Carrying Out the Invention

[0012] Hereinafter, examples of embodiments of the present disclosure will be specifically described with reference to the drawings. In each of the drawings referred to, the same parts are denoted by the same reference numerals, and redundant descriptions regarding the same parts are omitted as a rule. In this specification, for the sake of simplification of description, by writing symbols or signs referring to information, signals, physical quantities, elements, or parts, etc., the names of the information, signals, physical quantities, elements, or parts, etc. corresponding to the symbols or signs may be omitted or abbreviated. For example, the adjustment transistor referred to by "M" ADJ below (see FIG. 13) may be denoted as the adjustment transistor M ADJ or may be abbreviated as transistor M ADJ , but they all refer to the same thing.

[0013] First, some terms used in the description of the embodiments of the present disclosure will be explained. A line refers to a wiring through which an electrical signal is propagated or applied. A ground refers to a reference conductive part having a reference potential of 0 V (zero volts) or the 0 V potential itself. The reference conductive part is formed of a conductor such as metal. The 0 V potential may also be referred to as the ground potential. In the embodiments of the present disclosure, a voltage shown without particularly setting a reference represents a potential viewed from the ground. A level refers to the level of a potential. For any signal or voltage of interest, the high level has a higher potential than the low level. For any signal or voltage of interest, that the signal or voltage is at the high level means that the level of the signal or voltage is at the high level, and that the signal or voltage is at the low level means that the level of the signal or voltage is at the low level. The level of a signal may be expressed as a signal level, and the level of a voltage may be expressed as a voltage level.

[0014] For any signal of interest, when the signal is at a high level, its inverted signal takes a low level, and when the signal is at a low level, its inverted signal takes a high level. For any signal or voltage of interest, the transition from a low level to a high level is referred to as an up edge (or rising edge), and the transition from a high level to a low level is referred to as a down edge (or falling edge).

[0015] For any transistor configured as a FET (field effect transistor) including a MOSFET, the on state refers to the state where the drain and source of the transistor are conducting, and the off state refers to the state where the drain and source of the transistor are non-conducting (blocked state). The same applies to transistors not classified as FETs. Unless otherwise specified, a MOSFET is understood to be an enhancement-type MOSFET. MOSFET is an abbreviation of "metal-oxide-semiconductor field-effect transistor".

[0016] The electrical characteristics of a MOSFET include the gate threshold voltage. For any transistor that is an N-channel and enhancement-type MOSFET, when the gate potential of the transistor is higher than the source potential of the transistor and the magnitude of the gate-source voltage (gate potential seen from the source potential) of the transistor is equal to or greater than the gate threshold voltage of the transistor, the transistor is in the on state, and otherwise, the transistor is in the off state.

[0017] Any switch can be constituted by one or more FETs (field effect transistors). When a certain switch is in the on state, conduction occurs between both ends of the switch, while when a certain switch is in the off state, non-conduction occurs between both ends of the switch. Hereinafter, for any transistor or switch, the on state and the off state may simply be expressed as on and off. Also, for any signal having a high-level or low-level signal level, the period during which the level of the signal becomes high level is referred to as the high-level period, and the period during which the level of the signal becomes low level is referred to as the low-level period. The same applies to any voltage having a high-level or low-level voltage level.

[0018] <<First Embodiment>> The first embodiment of the present disclosure will be described. FIG. 1 is a configuration diagram showing a main part of a memory circuit 1 according to the first embodiment. The memory circuit 1 is a non-volatile memory that stores data for a predetermined number of bits, and includes a memory cell 10, a drive circuit 20, a signal output circuit 30, and a control circuit 40. In FIG. 1, one memory cell 10 included in the memory circuit 1 is focused on. One memory cell 10 can non-volatily store data for one bit. The memory circuit 1 may have a plurality of memory cells 10, but here only one memory cell 10 is focused on. Note that the memory circuit 1 may be a non-volatile memory having only one memory cell 10 as a memory cell (that is, the above-mentioned predetermined number of bits may be one bit). The memory circuit 1 may be constituted by a semiconductor integrated circuit. The operation of the drive circuit 20 is controlled by the control circuit 40. The operation of the signal output circuit 30 may also be controlled by the control circuit 40.

[0019] The memory cell 10 includes memory elements M1 and M2, and stores data of "0" or "1" in the memory cell 10. Each of the memory elements M1 and M2 is a transistor. Therefore, the memory elements M1 and M2 are also referred to as transistors M1 and M2 (first and second transistors). Each of the transistors M1 and M2 is configured as an N-channel type MOSFET.

[0020] Transistor M1 has a gate, electrode E1a, and electrode E1b. In transistor M1, among electrode E1a and electrode E1b, the electrode on the high potential side functions as a drain and the electrode on the low potential side functions as a source. In transistor M1, in principle, electrode E1b functions as a source, but electrode E1b can function as a drain when the program operation described later is executed. Transistor M2 has a gate, electrode E2a, and electrode E2b. In transistor M2, among electrode E2a and electrode E2b, the electrode on the high potential side functions as a drain and the electrode on the low potential side functions as a source. In transistor M2, in principle, electrode E2b functions as a source, but electrode E2b can function as a drain when the program operation described later is executed.

[0021] In transistors M1 and M2, the gates are commonly connected by gate line LN G Each gate of transistors M1 and M2 is connected to the drive circuit 20 through gate line LN G Electrode E1b of transistor M1 and electrode E2b of transistor M2 are commonly connected to line LN S Since electrodes E1b and E2b basically function as sources, line LN S is hereinafter referred to as source line LN S Electrode E1a of transistor M1 is connected to line LN D1 and is connected to the signal output circuit 30 through line LN D1 Electrode E2a of transistor M2 is connected to line LN D2 and is connected to the signal output circuit 30 through line LN D2 Since electrodes E1a and E2a basically function as drains, line LN D1 and LN D2 are hereinafter referred to as drain lines LN D1 and LN D2 respectively.

[0022] In the memory circuit 1, under the control of the control circuit 40, a read operation for reading the data stored in the memory cell 10 and a program operation (write operation) for writing data (value) to the memory cell 10 or rewriting the data (value) stored in the memory cell 10 can be executed. In the present embodiment, the expression "before execution of the program operation" and the expression "before the program operation" have the same meaning, and the expression "after execution of the program operation" and the expression "after the program operation" have the same meaning (the same applies to other embodiments described later).

[0023] In the memory circuit 1, when the read operation is performed, a precharge period is set prior to the execution of the read operation, and the read operation is performed during the read period after the precharge period. In the read operation, based on the magnitude relationship of the drain currents of the transistors M1 and M2 during the read period, the data stored in the memory cell 10 is read out.

[0024] FIG. 2 and FIG. 3 show the states of voltage or current during the precharge period and the read period. The setting and application of the voltage of each part during the precharge period and the read period are executed under the control of the control circuit 40. During the precharge period and the read period, the voltage of the source line LN S is set to 0V, and the electrodes E1a and E2a function as drains and the electrodes E1b and E2b function as sources. Represent the voltage of the drain line LN D1 by the voltage V1, and represent the voltage of the drain line LN D2 by the voltage V2. During the precharge period, while the voltage of each gate of the transistors M1 and M2 is set to 0V by the drive circuit 20, a positive charge is supplied to each of the drain lines LN D1 and LN D2 so that a common precharge voltage V D1 is set for the voltage V1 of the drain line LN D2 and the voltage V2 of the drain line LN PC The precharge voltage V PChas a predetermined positive DC voltage value (e.g., 1V). The positive charge may be supplied from the signal output circuit 30 or a circuit not shown. Incidentally, a positive voltage may be supplied to each gate of the transistors M1 and M2 during the precharge period. However, in any case, during the precharge period, the voltages V1 and V2 are maintained at the precharge voltage V PC is maintained.

[0025] After the precharge period, a positive read voltage V RD is supplied to each gate of the transistors M1 and M2, and the read period starts. The read voltage V RD may be a constant DC voltage, or may be a voltage that varies slightly with the passage of time during the read period. The read voltage V RD is higher than at least one of the gate threshold voltages of the transistor M1 and the gate threshold voltage of the transistor M2. Let the drain currents of the transistors M1 and M2 during the read period be referred to by the symbols "I D1 " and "I D2 ", respectively. Incidentally, during the read period, the input impedance of the signal output circuit 30 as seen from the drain line LN D1 and the input impedance of the signal output circuit 30 as seen from the drain line LN D2 are set to be sufficiently high. As a result, during the read period, the voltage V1 of the drain line LN D1 decreases only when the drain current I D1 flows, and the voltage V2 of the drain line LN D2 decreases only when the drain current I D2 flows.

[0026] Fig. 4A schematically shows the behavior of the voltages V1 and V2 during the precharge period and the read period when "I D2 >I D1 " during the read period. Fig. 4B shows "I D2 <I D1Schematically shows the behavior of voltages V1 and V2 during the precharge period and the read period when it becomes “”. The signal output circuit 30 outputs a signal D corresponding to the value of the data stored in the memory cell 10 based on the magnitude relationship of the drain currents of the transistors M1 and M2 in the read operation. OUT is output.

[0027] In the read operation (in other words, during the read period), the state where the drain current I D2 is greater than the drain current I D1 corresponds to the state where the first value is stored in the memory cell 10. Therefore, in the read operation, when the drain current I D2 is greater than the drain current I D1 , the signal output circuit 30 outputs a signal D associated with the first value (in other words, the signal D OUT representing the first value). In the read operation (in other words, during the read period), the state where the drain current I OUT is greater than the drain current I D1 corresponds to the state where the second value is stored in the memory cell 10. Therefore, in the read operation, when the drain current I D2 is greater than the drain current I D1 , the signal output circuit 30 outputs a signal D associated with the second value (in other words, the signal D D2 representing the second value). Here, it is assumed that the first value is “0” and the second value is “1”. OUT (In other words, the signal D OUT representing the second value).

[0028] In the memory circuit 1 according to the first embodiment, the transistors M1 and M2 have the same structure as each other. Therefore, in the initial state of the memory circuit 1, the magnitude relationship between the drain currents I D1 and I D2 is indefinite, and thus the value stored in the memory cell 10 is also indefinite. The initial state of the memory circuit 1 corresponds to the state where the program operation described later is not executed.

[0029] Regarding a transistor, the structure is a concept that includes the size of the transistor. Therefore, for any plurality of transistors, if the structures are the same as each other, it means that the sizes of the plurality of transistors are also the same as each other. When the structures of a certain plurality of transistors are the same as each other, if hot carrier injection by a program operation is not performed on some or all of the plurality of transistors, the electrical characteristics (including the gate threshold voltage, etc.) of the plurality of transistors will also be the same as each other. However, regarding the structures and electrical characteristics of any plurality of transistors, if the structures or electrical characteristics are the same, it means that they are the same in design, and actually may include errors (that is, the same is understood as a concept including errors).

[0030] In the memory circuit 1, only one of the first and second program operations is alternatively executed as the program operation.

[0031] In the first program operation, hot carriers are injected only into the transistor M1 among the transistors M1 and M2, whereby the gate threshold voltage of the transistor M1 increases. The first program operation is executed so that the gate threshold voltage of the transistor M1 becomes sufficiently higher than the gate threshold voltage of the transistor M2 after the execution of the first program operation. The gate threshold voltage of the transistor M1 after the execution of the first program operation may be higher than the lead voltage V RD . Therefore, in the read operation executed after the first program operation, as shown in FIG. 4A, with the increase in the gate threshold voltage of the transistor M1 due to the first program operation, “I D2 >I D1 ” occurs, and as a result, a signal D OUT representing the first value (0) is output, that is, the data (value) “0” stored in the memory cell 10 is read out.

[0032] In the second program operation, hot carriers are injected only into transistor M2 among transistors M1 and M2, thereby increasing the gate threshold voltage of transistor M2. The second program operation is executed so that the gate threshold voltage of transistor M2 becomes sufficiently higher than the gate threshold voltage of transistor M1 after the execution of the second program operation. The gate threshold voltage of transistor M2 after the execution of the second program operation may be higher than the read voltage V RD . Therefore, in the read operation executed after the second program operation, as the gate threshold voltage of transistor M2 increases due to the second program operation, as shown in FIG. 4B, "I D2 <I D1 ", and as a result, a signal D OUT representing the second value (1) is output, that is, the data (value) "1" stored in the memory cell 10 is read out.

[0033] Here, hereinafter, it is assumed that a low-level signal D OUT represents the first value (0) and a high-level signal D OUT represents the second value (1). Then, for example, after the start of the read period, by specifying the voltage that first becomes equal to or lower than a predetermined voltage among the voltages V1 and V2, the signal output circuit 30 may determine the level of the signal D OUT . If the specified voltage is the voltage V2, it represents "I D2 >I D1 ", so a low-level signal D OUT (a signal D OUT representing the value "0") is output. If the specified voltage is the voltage V1, it represents "I D2 <I D1 ", so a high-level signal D OUT (a signal D OUT representing "1") is output. Alternatively, for example, the timing when a predetermined time has elapsed since the start of the read period is set as the read timing, and the magnitude relationship between the drain currents I D1 and I D2 may be detected by detecting the magnitude relationship between the voltages V1 and V2 at the read timing.

[0034] Add an explanation of the program operation. The period during which the program operation is performed is referred to as the program period. The setting and application of the voltages of each part during the program period are executed under the control of the control circuit 40.

[0035] FIG. 5A shows the state of the memory circuit 1 during the program period in which the first program operation is performed. In the first program operation, the memory circuit 1 changes the electrical characteristics of the transistor M1 by injecting hot carriers only into the transistor M1 among the transistors M1 and M2. Due to this change, the gate threshold voltage of the transistor M1 increases (rises). FIG. 5B shows the state of the memory circuit 1 during the program period in which the second program operation is performed. In the second program operation, the memory circuit 1 changes the electrical characteristics of the transistor M2 by injecting hot carriers only into the transistor M2 among the transistors M1 and M2. Due to this change, the gate threshold voltage of the transistor M2 increases (rises).

[0036] In the first and second program operations (therefore, during the program period), a positive voltage V S is applied to the line LN PRG1 , and a positive voltage V PRG2 is applied to each gate of the transistors M1 and M2 by the drive circuit 20. The voltage V PRG2 may have the same voltage value as the read voltage V RD , or may be higher than the read voltage V RD . Whether the voltages V PRG1 and V PRG2 match or not does not matter. As long as the gate threshold voltage of the transistor M1 can be increased as required in the first program operation and the gate threshold voltage of the transistor M2 can be increased as required in the second program operation, the magnitudes of the voltages V PRG1 and V PRG2 are arbitrary.

[0037] Also, although not shown in FIG. 1 and the like, the memory circuit 1 is provided with switches SW1 and SW2. The switch SW1 is inserted between the electrode E1a of the transistor M1 and the ground, and the switch SW2 is inserted between the electrode E2a of the transistor M2 and the ground. The on and off of the switches SW1 and SW2 are individually controlled by the control circuit 40. In principle, both the switches SW1 and SW2 are off. However, the switch SW1 is turned on only during the program period of the first program operation, and the switch SW2 is turned on only during the program period of the second program operation. The switch SW2 is off during the program period of the first program operation, and the switch SW1 is off during the program period of the second program operation.

[0038] Therefore, in the first program operation (during the program period of the first program operation), in the transistor M1, the electrode E1b functions as a drain and the electrode E1a functions as a source, and a current flows from the line LN S towards the ground through the electrodes E1b and E1a and the switch SW1. During the process of this current flowing, hot carriers are injected into the transistor M1, and the characteristics of the transistor M1 change, and the gate threshold voltage of the transistor M1 increases. After maintaining the program period for a time sufficient to sufficiently increase the gate threshold voltage of the transistor M1, the first program operation ends. In order to realize the first program operation that brings about such an effect, it is advisable to set the voltage values of the voltages V PRG1 and V PRG2 to be sufficiently high. Incidentally, the line LN D2 is in a high impedance state during the program period of the first program operation. It may be considered that a voltage V D2 is applied to the line LN PRG2 during the program period of the first program operation. In any case, no current flows between the electrodes E2a and E2b during the program period of the first program operation.

[0039] Similarly, in the second program operation (during the program period of the second program operation), in transistor M2, electrode E2b functions as the drain and electrode E2a functions as the source, and current flows from line LN S towards ground through electrodes E2b and E2a and switch SW2. During the process of this current flowing, hot carriers are injected into transistor M2, causing the characteristics of transistor M2 to change, and the gate threshold voltage of transistor M2 to increase. After maintaining the program period for a time sufficient to increase the gate threshold voltage of transistor M2 sufficiently, the second program operation ends. In order to realize the second program operation that brings about such an effect, it is advisable to set the voltage values of voltage V PRG1 and V PRG2 to be sufficiently high. Incidentally, during the program period of the second program operation, line LN D1 is in a high-impedance state. It is also possible to consider that voltage V D1 is applied to line LN PRG2 during the program period of the second program operation. In any case, no current flows between electrodes E1a and E1b during the program period of the second program operation.

[0040] The method for realizing the first or second program operation is not limited to the above method and is arbitrary. Therefore, for example, during the program period of the first program operation, while applying voltage V PRG2 to the gates of transistors M1 and M2, among lines LN D1 and LN D2 , applying voltage V D1 only to line LN PRG1 , and applying the ground potential to line LN S can also be used to realize the first program operation. At this time, switch SW1 is maintained in the off state, and the ground potential is applied to line LN D2 or line LN D2is set to a high impedance state. Also due to this, hot carriers are injected only into the transistor M1 among the transistors M1 and M2. Similarly, for example, during the program period of the second program operation, while applying the voltage V PRG2 to each gate of the transistors M1 and M2, among the lines LN D1 and LN D2 , applying the voltage V D2 to only the line LN PRG1 and giving the ground potential to the line LN S may also be used to realize the second program operation. At this time, the switch SW2 is maintained off, and the ground potential is given to the line LN D1 or the line LN D1 is set to a high impedance state. Also due to this, hot carriers are injected only into the transistor M2 among the transistors M1 and M2.

[0041] By the way, since the gate threshold voltages of the memory elements (M1, M2) in the non-volatile memory are relatively high, when using a relatively low power supply voltage, it is beneficial to use a charge pump to generate the read voltage V RD . At this time, from the viewpoint of reducing the circuit size, etc., a simple configuration without a diode or a large output capacitor is used to form the charge pump. Then, it becomes difficult to accurately apply the read voltage V RD to the gates of the memory elements (M1, M2).

[0042] Also, the relationship between the gate-source voltage and the drain current in the memory elements (M1, M2) varies greatly depending on element variations and temperature changes. Therefore, even if the read voltage V RD is constant, the drain currents of the memory elements (M1, M2) during the read operation vary widely. The variation in the drain currents of the memory elements (M1, M2) during the read operation becomes more prominent if the read voltage V RD varies.

[0043] On the other hand, if the drain current of the memory elements (M1, M2) during the read operation is excessively large, it will lead to an increase in power consumption. From the perspective of power saving, it is preferable to reduce the drain current during the read operation. However, if those drain currents are too small, it becomes difficult to read out the stored data of the memory cell 10 within a limited time. For this reason, during the read operation, it is required to pass an appropriate-sized drain current through the transistor M1 or M2 (limit the fluctuation range of the drain current magnitude) without depending on device variations or temperature changes. By satisfying this requirement, power saving can be achieved. Also, when there is a large variation in the drain current of the transistor M1 or M2 during the read operation, the size of the peripheral circuit (for example, the circuit serving as the current supply source or the switch on the path through which the current flows) needs to be configured considering the maximum value of the designed drain current, so the size of the peripheral circuit becomes large. However, by limiting the fluctuation range of the drain current magnitude, it is also possible to reduce the size of the peripheral circuit. Furthermore, when the drain current of the transistor M1 or M2 during the read operation varies greatly, it has an adverse effect on the characteristics of the non-volatile memory. However, by limiting the fluctuation range of the drain current magnitude (ideally making it constant), an improvement in the characteristics of the non-volatile memory can also be expected.

[0044] Therefore, a circuit configuration for appropriately setting the drain current of the memory elements (M1, M2) during the read operation is considered.

[0045] Fig. 6 shows the internal configuration of the drive circuit 20 and a plurality of memory cells connected to the drive circuit 20. In Fig. 1, attention was focused only on one memory cell 10 provided in the memory circuit 1, but the memory circuit 1 may be a non-volatile memory that stores data for a plurality of bits as described above. Hereinafter, it is assumed that first to Nth addresses are defined in the memory circuit 10, and a memory cell 10 is provided for each address. N is an arbitrary integer of 2 or more. However, a modification with "N = 1" is also possible (in this case, the total number of addresses is "1").

[0046] The memory cell 10 assigned to the i-th address is particularly referred to as the memory cell 10[i] (i is an integer). In the memory circuit 1, by providing a plurality of memory cells 10 for each address, it is possible to non-volatilely store data for a plurality of bits for each address. However, in FIG. 6, only the memory cell 10[i] for 1 bit for each address is illustrated. The memory cells 10[1] to 10[N] have the same configuration as each other.

[0047] The gate line LN for the memory cell 10 of the i-th address (i.e., the memory cell 10[i]) G is particularly referred to by the symbol "LN G [i]". The gate line LN G [i] is commonly connected to the gates of the transistors M1 and M2 in the memory cell 10[i]. The drive circuit 20 supplies gate voltages to the transistors M1 and M2 for each address by outputting gate voltages V G [1] to LN G [N], respectively. The gate voltage V OTPG [1] to V OTPG [N]. The gate voltage V OTPG [i] is the voltage applied to the gate line LN G [i] and is supplied to the gates of the transistors M1 and M2 in the memory cell 10[i].

[0048] The drive circuit 20 includes a boost circuit 21, an adjustment circuit 22, and a gate voltage supply circuit 23.

[0049] The boost circuit 21 generates a boosted voltage V REG by boosting a predetermined reference voltage V REG generated within the drive circuit 20. The boosted voltage V BST is a boosted voltage of the reference voltage V BST and is generated on the boost line LN BST . The reference voltage V REG has a positive predetermined DC voltage value (for example, 1.6V). A specific example of the boost circuit 21 will be described later, but the boost circuit 21 may be a charge pump circuit configured using one or more capacitors and one or more switches. At this time, the boosted voltage VBST varies in conjunction with the operation of the charge pump circuit, and at least the boost voltage V BST during the process of the variation has a maximum voltage higher than the reference voltage V REG . The power supply voltage VDD corresponds to the power supply voltage of the memory circuit 1 and has a predetermined positive DC voltage value.

[0050] The adjustment circuit 22 is connected to the boost line LN BST and draws a regulation current I BST corresponding to the boost voltage V ADJ from the boost line LN BST to adjust the boost voltage V BST . A specific example of the adjustment circuit 22 will be described later, but the adjustment circuit 22 adjusts the boost voltage V BST to an appropriate voltage level for the read operation.

[0051] The gate voltage supply circuit 23 supplies gate voltages to the transistors in the memory cells 10[1] to 10[N]. The gate voltage supply circuit 23 includes gate drivers provided for each address. The gate driver corresponding to the i-th address is referred to by the symbol "DRV[i]". Then, the gate voltage supply circuit 23 is composed of the gate drivers DRV[1] to DRV[N]. Each gate driver consists of a first and a second buffer. The first and second buffers provided in the gate driver DRV[i] are referred to by the symbols "23a[i]" and "23b[i]" respectively. From the control circuit 40 (see FIG. 1), address selection signals SEL ADD [1] to SEL ADD [N] are input to the gate drivers DRV[1] to DRV[N] respectively. Each address selection signal is a digital signal having a signal level of high level or low level. In each address selection signal, the high level substantially has the potential of the power supply voltage VDD, and the low level substantially has the ground potential.

[0052] Since the gate drivers DRV[1] to DRV[N] have the same configuration as each other, the configuration and operation of the gate driver DRV[i], which is one of the gate drivers DRV[1] to DRV[N] (the configuration and operation of the buffers 23a[i] and 23b[i]) will be described.

[0053] The buffer 23a[i] has an input terminal and an output terminal. The address selection signal SEL ADD [i] is input to the input terminal of the buffer 23a[i]. The buffer 23a[i] outputs a high-level signal and a low-level signal from its output terminal when the address selection signal SEL ADD [i] is at a high level and a low level, respectively. The buffer 23a[i] is a buffer that uses the power supply voltage VDD as the high-potential-side power supply voltage and the ground voltage as the low-potential-side power supply voltage. Therefore, in the output signal of the buffer 23a[i], the high level has substantially the potential of the power supply voltage VDD, and the low level has substantially the ground potential.

[0054] The buffer 23b[i] has an input terminal and an output terminal, and the output terminal of the buffer 23a[i] is connected to the input terminal of the buffer 23b[i]. The buffer 23b[i] outputs a high-level signal and a low-level signal from its output terminal when the output signal of the buffer 23a[i] is at a high level and a low level, respectively. The buffer 23b[i] is a buffer that uses the boost voltage V BST as the high-potential-side power supply voltage and the ground voltage as the low-potential-side power supply voltage. Therefore, in the output signal of the buffer 23b[i], the high level has substantially the potential of the boost voltage V BST , and the low level has substantially the ground potential. The output signal of the buffer 23b[i] is output as the gate voltage V OTPG [i] to the gate line LN G [i].

[0055] Fig. 7 shows a configuration example of any one of the memory cells 10[1] to 10[N] and its peripheral circuit among the memory cells 10[1] to 10[N]. Fig. 7 also shows a circuit example of the boost circuit 21.

[0056] The boost circuit 21 shown in FIG. 7 will be described. The boost circuit 21 in FIG. 7 is constituted by a charge pump circuit including an inverter 101, level shifters 102 and 103, a transistor 104, and capacitors 105 and 106. The transistor 104 is a P-channel type MOSFET and functions as a switch in the charge pump circuit.

[0057] The inverter 101 receives the clock signal CLK_N and outputs a clock signal CLK which is an inverted signal of the clock signal CLK_N. Therefore, when the clock signal CLK_N is at a high level or a low level, the clock signal CLK is at a low level or a high level, respectively. The inverter 101 is driven based on the power supply voltage VDD, and in each of the clock signals CLK_N and CLK, the high level has a potential substantially equal to the power supply voltage VDD, and the low level has a ground potential. The clock signal CLK_N is output from a clock supply circuit (not shown) provided inside or outside the memory circuit 1.

[0058] The level shifter 102 uses the power supply voltage VDD and the boost voltage V BST to shift the potential on the high level side of the clock signal CLK output from the inverter 101 to the potential of the boost voltage V BST The output signal OUT 102 of the level shifter 102 obtained by this shift is supplied to the gate of the transistor 104. When the clock signal CLK is at a high level or a low level, the output signal OUT 102 of the level shifter 102 also becomes a high level or a low level, respectively. However, the high level of the output signal OUT 102 substantially has the potential of the boost voltage V BST The low level of the output signal OUT 102 substantially has a ground potential. A first buffer that uses the power supply voltage VDD as the high potential side power supply voltage and the ground voltage as the low potential side power supply voltage, and the boost voltage V BSTThe level shifter 102 can be configured by a series circuit with a second buffer that uses the power supply voltage on the high potential side and the ground voltage as the power supply voltage on the low potential side.

[0059] The level shifter 103 uses the power supply voltage VDD and the reference voltage V REG to shift the potential on the high level side of the clock signal CLK output from the inverter 101 to the potential of the reference voltage V REG . The output signal OUT 103 of the level shifter 103 obtained by this shift is applied to one end of the capacitor 106. The other end of the capacitor 106 is connected to the boost line LN BST . When the clock signal CLK is at the high level and the low level, the output signal OUT 103 of the level shifter 103 also becomes the high level and the low level, respectively. However, the high level of the output signal OUT 103 substantially has the potential of the reference voltage V REG . The low level of the output signal OUT 103 substantially has the ground potential. The level shifter 103 can be configured by a series circuit with a third buffer that uses the power supply voltage VDD as the power supply voltage on the high potential side and the ground voltage as the power supply voltage on the low potential side, and a fourth buffer that uses the reference voltage V REG as the power supply voltage on the high potential side and the ground voltage as the power supply voltage on the low potential side.

[0060] Note that the inverter 101 may be omitted in the boost circuit 21, and the clock signal CLK may be directly supplied to the level shifters 102 and 103.

[0061] The source of the transistor 104 is connected to the boost line LN BST . The drain of the transistor 104 and one end of the capacitor 105 are commonly connected at a line to which the reference voltage V REG is applied. The other end of the capacitor 105 is connected to the ground.

[0062] As a peripheral circuit of the memory cell 10[i], the memory circuit 1 is provided with switches SW1 to SW6, a charge circuit 51, and a discharge circuit 52. The sense amplifier SAMP is a component of the signal output circuit 30 and corresponds to the signal output circuit 30 for the memory cell 10[i]. In the read operation for the memory cell 10[i], the sense amplifier SAMP outputs a signal D representing the stored data of the memory cell 10[i]. OUT The switches SW1 to SW6 are individually controlled to be on or off by the control circuit 40. In FIG. 7, a state where all the switches SW1 to SW6 are off is illustrated.

[0063] The switches SW1 to SW6, the charge circuit 51, and the discharge circuit 52 may be shared for the memory cells 10[1] to 10[N]. However, in FIG. 7, only the relationship between one memory cell 10[i] and the switches SW1 to SW6, the charge circuit 51, and the discharge circuit 52 is illustrated. It is also possible to provide the switches SW1 to SW6, the charge circuit 51, and the discharge circuit 52 individually for each of the memory cells 10[1] to 10[N].

[0064] In the memory cell 10[i], the electrode E1b of the transistor M1 and the electrode E2b of the transistor M2 are commonly connected to the source line LN. S The source line LN is connected to one end of the switch SW5 and one end of the switch SW6. The other end of the switch SW5 is connected to the ground, and the other end of the switch SW6 is connected to the line to which the power supply voltage VDD is applied. S

[0065] In the memory cell 10[i], the electrode E1a of the transistor M1 is connected to the drain line LN. D1 The drain line LN is connected to one end of the switch SW3, and the other end of the switch SW3 is connected to the first input terminal of the sense amplifier SAMP. Also, a switch SW1 is inserted in series between the connection node between the drain line LN and one end of the switch SW3 and the ground. D1 D1 ​​​

[0066] In memory cell 10[i], the electrode E2a of transistor M2 is the drain line LN D2 is connected to, and the drain line LN D2 is connected to one end of switch SW4, and the other end of switch SW4 is connected to the second input terminal of sense amplifier SAMP. Also, switch SW2 is inserted in series between the connection node of drain line LN D2 and one end of switch SW4, and ground.

[0067] In memory cell 10[i], the gates of transistors M1 and M2 are commonly connected to gate line LN G [i], and receive the gate voltage V OTPG [i] from gate driver DRV[i].

[0068] Charge circuit 51 is individually connected to drain lines LN D1 and LN D2 via two different lines. Discharge circuit 52 is individually connected to the first and second input terminals of sense amplifier SAMP via two other different lines. Charge circuit 51 can supply a charge (positive charge) based on power supply voltage VDD at a necessary timing under the control of control circuit 40 to drain lines LN D1 and LN D2 . Discharge circuit 52 can extract a charge (positive charge) from drain lines LN D1 and LN D2 at a necessary timing under the control of control circuit 40 (assuming that switches SW3 and SW4 are on).

[0069] An enable signal EN SAMP is input to sense amplifier SAMP. When enable signal EN SAMP is at a low level, sense amplifier SAMP is in a reset state and sense amplifier SAMP does not output a significant signal. When enable signal EN SAMPWhen it is at a high level, the reset state of the sense amplifier SAMP is released, and the sense amplifier SAMP can output a signal D representing the stored data of the memory cell 10[i]. OUT It becomes possible to output

[0070] In FIG. 8, together with the waveforms of the clock signal CLK_N, the boost voltage V BST and the enable signal EN SAMP the waveforms of the address selection signal and the gate voltage for three addresses are shown. As the waveforms of the address selection signal and the gate voltage for three addresses, FIG. 8 shows the address selection signal SEL ADD [i] and the gate voltage V OTPG [i], the waveforms of the address selection signal SEL ADD [i + 1] and the gate voltage V OTPG [i + 1], and the waveforms of the address selection signal SEL ADD [i + 2] and the gate voltage V OTPG [i + 2] are shown (in FIG. 8, it is assumed that i is a natural number less than or equal to (N - 2)).

[0071] Based on the clock signal CLK_N (or a clock signal corresponding to the inverted signal of the clock signal CLK_N), the control circuit 40 sequentially sets the address selection signals SEL ADD [1] to SEL ADD [N] to a high level one by one for each period of the clock signal CLK_N. More specifically, a period having a length of one cycle of the clock signal CLK_N is defined as a unit period. In the first unit period, among the address selection signals SEL ADD [1] to SEL ADD [N], only the address selection signal SEL ADD [1] is set to a high level and all other address selection signals are set to a low level. In the second unit period, among the address selection signals SEL ADD [1] to SEL ADD [N], the address selection signal SEL ADDSet only [2] to the high level and set all other address selection signals to the low level. The same applies to the third unit period. That is, in the i-th unit period, among the address selection signals SEL ADD [1] to SEL ADD [N], set only the address selection signal SEL ADD [i] to the high level and set all other address selection signals to the low level. However, each unit period shall start from the rising edge timing (transition timing from low level to high level) of the clock signal CLK_N.

[0072] During the high level period of the clock signal CLK_N, the low level output signal OUT 102 (signal of the ground potential) is supplied to the gate of the transistor 104, so the transistor 104 is turned on. Therefore, during the high level period of the clock signal CLK_N, the boost voltage V BST is consistent with the reference voltage V REG , and at this time, the output signal OUT of the ground potential from the level shifter 103 103 is supplied to one end (low potential end) of the capacitor 106, and the capacitor 106 is charged with the boost voltage V BST .

[0073] When the clock signal CLK_N switches from high level to low level, the high level output signal OUT from the level shifter 102 102 (signal having the potential of the boost voltage V BST ) is supplied to the gate of the transistor 104, so the transistor 104 is turned off. Also, at this time, since the output signal OUT of the level shifter 103 103 switches from low level to high level, the boost voltage V BST rises through the capacitor 106. If there is no circuit that draws current from the boost line LN BST during the low level period of the clock signal CLK_N, ideally, the boost voltage V BST rises up to twice the reference voltage V REG . Since the unit period visits repeatedly, the boost voltage VBST varies between the reference voltage V REG and a voltage higher than the reference voltage V REG during the repetition of the unit period.

[0074] The enable signal EN SAMP is set to a high level when the boost voltage V BST is equal to or higher than a predetermined determination voltage, and is set to a low level when the boost voltage V BST is lower than the determination voltage. The determination voltage is set to a voltage higher than the reference voltage V REG and lower than twice the reference voltage V REG . A boost voltage detection circuit (not shown) is provided in the memory circuit 1, and the enable signal EN BST is generated based on the comparison of the boost voltage V SAMP and the determination voltage. Hysteresis characteristics may be imparted to this comparison.

[0075] As understood from the above description, in the i-th unit period corresponding to the high level period of the address selection signal SEL ADD [i], among the gate voltages V OTPG [1] to V OTPG [N], only the gate voltage V OTPG [i] substantially coincides with the boost voltage V BST , and the other gate voltages become 0V. Then, as shown in FIG. 8, during the high level period of the clock signal CLK_N in the i-th unit period, the gate voltage V OTPG [i] coincides with the reference voltage V REG , and during the low level period of the clock signal CLK_N in the i-th unit period, the gate voltage V OTPG [i] becomes higher than the reference voltage V REG . Similarly, during the high level period of the clock signal CLK_N in the (i + 1)-th unit period, the gate voltage V OTPG [i + 1] coincides with the reference voltage V REG , and during the low level period of the clock signal CLK_N in the (i + 1)-th unit period, the gate voltage V OTPG [i + 1] coincides with the reference voltage V REGIt becomes higher. The same applies to other unit periods. Hereinafter, the high-level period and the low-level period of the clock signal CLK_N during the i-th unit period are particularly referred to by the symbols "Pa" and "Pb", respectively.

[0076] [Read operation] This is the same as the read operation described above with reference to FIGS. 2 and 3. Referring to FIGS. 9 and 10, the read operation performed on the memory cell 10[i] will be described. During any period (including the precharge period and the read period) except for the program period in which the program operation is performed, the switches SW1, SW2, and SW6 are maintained off and the switches SW3 to SW5 are maintained on. Therefore, during the precharge period and the read period, the voltage of the source line LN S is set to 0V, and the electrodes E1a and E2a function as drains and the electrodes E1b and E2b function as sources. The precharge period and the read period for the memory cell 10[i] are set within the i-th unit period. Specifically, for example, the periods Pa and Pb shown in FIG. 8 can be set as the precharge period and the read period for the memory cell 10[i], respectively.

[0077] During the precharge period, positive charges are supplied to each of the drain lines LN D1 and LN D2 by the charge circuit 51, so that a common precharge voltage V D1 is set for the voltage V1 of the drain line LN D2 and the voltage V2 of the drain line LN PC as shown in FIG. 9. When the precharge period for the memory cell 10[i] is the period Pa, since "V OTPG [i]=V BST =V REG >0", during this precharge period, a corresponding drain current can flow through at least one of the transistors M1 and M2, but the voltages V1 and V2 are maintained at the precharge voltage V PC . Note that the discharge circuit 52 does not function significantly during the precharge period and the read period (the discharge circuit 52 can be considered non-existent).

[0078] After the precharge period, when reaching the period Pb shown in FIG. 8, the read period of the memory cell 10[i] starts. The gate voltage V OTPG [i] corresponds to the above-described read voltage V RD (see FIG. 3). The gate voltage V OTPG [i] is higher than at least one of the gate threshold voltages of transistor M1 and transistor M2. During the read period, the input impedances of circuits 51 and 52 and sense amplifier SAMP as seen from drain lines LN D1 and LN D2 are set to be sufficiently high. As a result, during the read period of the memory cell 10[i], the voltage V1 of the drain line LN D1 decreases only when the drain current I D1 flows through the transistor M1 of the memory cell 10[i], and the voltage V2 of the drain line LN D2 decreases only when the drain current I D2 flows through the transistor M2 of the memory cell 10[i] (see FIG. 10).

[0079] The operation of the sense amplifier SAMP based on the drain currents I D1 and I D2 of the memory cell 10[i] is the same as the operation of the signal output circuit 30 based on the drain currents I D1 and I D2 of the memory cell 10 described above with reference to FIG. 3 and the like. Therefore, in the read operation for the memory cell 10[i], the sense amplifier SAMP detects the magnitude relationship between the drain currents I D1 and I D2 based on the voltages of its first and second input terminals (and thus based on the voltages V1 and V2), and when "I D2 >I D1 ", outputs a signal D OUT (in other words, a signal D OUT representing the first value), and when "I D2 <I D1 ", outputs a signal D OUT(In other words, a signal D representing the second value OUT ) is output. However, a significant signal D OUT is output only during the high-level period of the enable signal EN SAMP . As described above, a low-level signal D OUT represents the first value (0) and a high-level signal D OUT represents the second value (1). Then, for example, after the start of the read period, by identifying the voltage that first becomes below a predetermined voltage among the voltages V1 and V2, the sense amplifier SAMP may determine the level of the signal D OUT .

[0080] [Program Operation] The program operation is the same as the program operation described above with reference to FIGS. 5A and 5B. Referring to FIGS. 11 and 12, the program operation executed on the memory cell 10[i] will be described. As described above, there are a first program operation and a second program operation as program operations.

[0081] In each of the first and second program operations, the switches SW3 to SW5 are turned off and the switch SW6 is turned on. As a result, the power supply voltage VDD is applied to the electrodes E1b and E2b of the transistors M1 and M2, and those electrodes function as drains. At this time, the power supply voltage VDD functions as the voltage V PRG1 shown in FIGS. 5A and 5B. The adjustment circuit 22 is a circuit that functions effectively in the read operation. When the program operation is executed, the adjustment circuit 22 shall not draw the adjustment current I ADJ . Also, when the first or second program operation is executed on the memory cell 10[i], the address selection signal SEL ADD [i] is maintained at a high level during the program period.

[0082] And, during the program period in the first program operation, as shown in FIG. 11, the switch SW1 is turned on and the switch SW2 is maintained off, and the line LN SA current flows from [the relevant source] through electrodes E1b and E1a and switch SW1 towards the ground. During the process of this current flowing, hot carriers are injected into transistor M1, causing the characteristics of transistor M1 to change and the gate threshold voltage of transistor M1 to increase. After maintaining the programming period for a time sufficient to sufficiently increase the gate threshold voltage of transistor M1, the first programming operation ends. Incidentally, during the programming period of the first programming operation, line LN D2 is in a high-impedance state, and no current flows between electrodes E2a and E2b.

[0083] On the other hand, during the programming period in the second programming operation, as shown in FIG. 12, switch SW1 is turned off and switch SW2 is maintained in the on state, and line LN S A current flows from [the relevant source] through electrodes E2b and E2a and switch SW2 towards the ground. During the process of this current flowing, hot carriers are injected into transistor M2, causing the characteristics of transistor M2 to change and the gate threshold voltage of transistor M2 to increase. After maintaining the programming period for a time sufficient to sufficiently increase the gate threshold voltage of transistor M2, the second programming operation ends. Incidentally, during the programming period of the second programming operation, line LN D1 is in a high-impedance state, and no current flows between electrodes E1a and E1b.

[0084] After performing the first programming operation on memory cell 10[i], when a read operation is performed on memory cell 10[i], along with the increase in the gate threshold voltage of transistor M1 due to the first programming operation, in the read operation, "I D2 >I D1 ", and as a result, a signal D OUT representing the first value (0) is output, that is, the data (value) "0" stored in memory cell 10[i] is read out. After performing the second programming operation on memory cell 10[i], when a read operation is performed on memory cell 10[i], along with the increase in the gate threshold voltage of transistor M2 due to the second programming operation, in the read operation, "I D2 <ID1 ” and as a result, a signal D representing the second value (1) OUT is output, that is, the data (value) of “1” stored in the memory cell 10[i] is read out.

[0085] [Adjustment circuit] FIG. 13 shows a configuration example of the adjustment circuit 22. The adjustment circuit 22 in FIG. 13 includes an adjustment transistor M ADJ and transistors 121 to 126 and transistors 131 to 134. The adjustment transistor M ADJ , transistors 123, 124, 131, and 132 are composed of N-channel MOSFETs, and transistors 121, 122, 125, 126, 133, and 134 are composed of P-channel MOSFETs.

[0086] The adjustment transistor M ADJ is composed of the same element as the memory element. That is, the adjustment transistor M ADJ is composed of a MOSFET having the same structure as the MOSFET constituting the transistor M1 or the MOSFET constituting the transistor M2.

[0087] When paying attention to one transistor M1 and one transistor M2, the first to third unit transistors Mu having the same structure as each other are formed on the semiconductor substrate on which the memory circuit 1 is integrated. As shown in FIG. 14A, the first and second unit transistors Mu are used as the transistors M1 and M2, respectively, and the third unit transistor Mu is used as the adjustment transistor M ADJ and may be used. Alternatively, the first to k-th unit transistors Mu having the same structure as each other are formed on the semiconductor substrate on which the memory circuit 1 is integrated (k is an arbitrary integer of 4 or more). As shown in FIG. 14B, the first and second unit transistors Mu are used as the transistors M1 and M2, respectively, and the parallel circuit of the third to k-th unit transistors Mu is used as the adjustment transistor M ADJ and may be used.

[0088] Therefore, after the first program operation (thus, when hot carriers are not injected into the transistor M2), when a common gate-source voltage is supplied to the transistors M2 and M ADJ a drain current corresponding to the drain current of the adjustment transistor M ADJ flows through the transistor M2. Similarly, after the second program operation (thus, when hot carriers are not injected into the transistor M1), when a common gate-source voltage is supplied to the transistors M1 and M ADJ a drain current corresponding to the drain current of the adjustment transistor M ADJ flows through the transistor M1.

[0089] The connection relationships of the elements in the adjustment circuit 22 will be described. Note that the line to which the power supply voltage VDD is applied may be referred to as the power supply voltage line LN VDD The sources of the transistors 121, 122, 125, 126, 133, and 134 are connected to the power supply voltage line LN VDD The gate and drain of the transistor 121, the gate of the transistor 122, and the drains of the transistors 126, 133, and 131 are commonly connected at the node ND1. The source of the transistor 131 is connected to the drain of the adjustment transistor M ADJ In the adjustment transistor M ADJ the gate is connected to the boost line LN BST and the source is connected to the line LN S The drain of the transistor 122 is connected to the drain and gate of the transistor 123 and the gate of the transistor 124. The sources of the transistors 123 and 124 are connected to the line LN S The drain of the transistor 124 is connected to the source of the transistor 132, and the drain of the transistor 132 is connected to the boost line LN BST The drains and gates of the transistors 125, the gate of the transistor 126, and the drain of the transistor 134 are connected to each other.

[0090] The input signal and input voltage for the adjustment circuit 22 in FIG. 13, and the operation of the adjustment circuit 22 in FIG. 13 will be described. The above-described adjustment current I ADJ (see FIGS. 6 and 7) flows through each channel (between drain and source) of transistors 132 and 124. An enable signal EN ADJ is input to each gate of transistors 132 to 134. ADJ The enable signal EN ADJ is output from the control circuit 40. The high level of the enable signal EN ADJ has the potential of the power supply voltage VDD, and the low level has the ground potential. The control circuit 40 may set the enable signal EN ADJ to the low level during the programming period, and to the high level during any other period (including the precharge period and the read period). The adjustment circuit 22 functions effectively only during the high level period of the enable signal EN ADJ . That is, during the high level period of the enable signal EN ADJ , the transistor 132 can conduct a non-zero adjustment current I ADJ through its channel, and both transistors 133 and 134 functioning as switches are turned off. During the low level period of the enable signal EN ADJ , the transistor 132 is turned off and the adjustment current I BST does not flow regardless of the boost voltage V ADJ , and the constant current I CC described later is not generated. Hereinafter, unless otherwise specified, it is assumed that the enable signal EN ADJ is at the high level.

[0091] A predetermined positive voltage Vp1 is applied to the gate of the transistor 131. If an excessive drain voltage is applied to the transistor M ADJ when the gate voltage of the transistor M ADJ is sufficiently high, hot carriers are generated in the adjustment transistor M ADJ , causing a change in the characteristics of the transistor M ADJ . The adjustment transistor M ADJTo prevent an excessive drain voltage from being applied, a transistor 131 is inserted between node ND1 and the adjustment transistor M ADJ A predetermined positive voltage Vp2 lower than the power supply voltage VDD is applied to each gate of transistors 125 and 126 and each drain of transistors 125 and 134 (however, the output of the voltage Vp2 may be stopped during the low level period of the enable signal EN ADJ ).

[0092] Transistors 125 and 126 form a current mirror circuit, and the current mirror circuit functions as a constant current circuit CC. That is, a constant current I CC is output from the drain of transistor 126 toward node ND1. The value of the voltage Vp2 is set so that the constant current I CC has a predetermined current value (for example, 10 μA). Since node ND1 is connected to the drain of the adjustment transistor M ADJ via transistor 131, it can be said that the constant current circuit CC outputs the constant current I CC toward the drain of the adjustment transistor M ADJ .

[0093] Transistors 121 and 122 form a current mirror circuit CM1. Transistors 123 and 124 form a current mirror circuit CM2. The drain current of transistor 121 is referred to as current Ia, and the drain current of transistor 122 is referred to as current Ib. The drain current of transistor 124 is the adjustment current I ADJ . Then, current Ia, current Ib, and the adjustment current I ADJ are in a proportional relationship with each other. The current ratio between current Ia and Ib may be 1 or other than 1. The current ratio between current Ib and I ADJ may be 1 or other than 1. A line connecting the drain of transistor 122 and the drain of transistor 123 to each other is particularly referred to as line LN11.

[0094] The current mirror circuit CM1 adjusts the current Ia to the adjustment transistor M ADJWhile outputting towards the drain, a current Ib proportional to the current Ia is generated on the line LN11. The current mirror circuit CM2 generates a current for adjustment I ADJ as a current proportional to the current Ib flowing through the line LN11 and generates the adjustment current I ADJ is drawn from the boost line LN BST .

[0095] The drain current of the adjustment transistor M ADJ is the sum of the current Ia (first current) and the constant current I CC (second current). The drain current flowing through the adjustment transistor M ADJ is proportional to the boost voltage V BST . The higher the boost voltage V BST , the larger the drain current of the adjustment transistor M ADJ . The larger the drain current of the adjustment transistor M ADJ , the larger the adjustment current I ADJ accompanied by the increase in the currents Ia and Ib.

[0096] The operation of the adjustment circuit 22 will be described starting from the state where the boost voltage V BST has risen to a sufficiently high voltage. When the boost voltage V BST is sufficiently high, the drain current of the adjustment transistor M ADJ increases, causing the current Ia to increase. As a result, the currents Ib and I ADJ also increase. The large adjustment current I ADJ causes the boost voltage V BST to decrease. The draw of the adjustment current I BST from the boost line LN ADJ causes the boost voltage V BST to decrease, resulting in a decrease in the drain current of the adjustment transistor M ADJ . As the potential of the node ND1 rises, the current Ia (first current) decreases by the amount of the decrease in the drain current of the adjustment transistor M ADJ . As a result, the adjustment current I ADJ also decreases. Finally, the currents Ia, Ib, and I ADJ become zero, and the constant current I CCOnly the adjustment transistor M ADJ reaches the state of flowing therethrough.

[0097] In addition, in FIG. 8, the boost voltage V BST changes in a substantially rectangular wave synchronously with the clock signal CLK_N. However, actually, as shown in FIG. 15, the boost voltage V BST rises from the reference voltage V REG to a voltage higher than the voltage V BST_ADJ and then converges to the voltage V ADJ after pulling in the adjustment current I BST through the adjustment transistor M. The state of "V BST_ADJ =V BST " corresponds to the state where the drain current of the adjustment transistor M BST_ADJ coincides with the constant current I ADJ (i.e., the state of "I CC =0"). The voltage V ADJ corresponds to the boost voltage V BST_ADJ after being adjusted by the adjustment circuit 22. BST

[0098] Thus, in this embodiment, the adjustment current I BST corresponding to the boost voltage V ADJ is pulled in from the boost line LN BST to adjust the boost voltage V BST , and in the read operation, the adjusted boost voltage V BST is supplied as the read voltage V RD to the gates of the transistors M1 and M2. Focusing on the memory cell 10[i], during the period Pb (see FIG. 8) corresponding to the read period for the memory cell 10[i], the boost voltage V REG higher than the reference voltage V BST is adjusted by the adjustment circuit 22, and the adjusted boost voltage V BST is supplied as the gate voltage V OTPG [i] and as the read voltage V RD to the gates of the transistors M1 and M2 in the memory cell 10[i]. As a result, the drain current I D1 or ID2 Optimization is achieved, leading to power saving, and by extension, size reduction of the peripheral circuit and improvement of the characteristics of the non-volatile memory.

[0099] In particular, an adjustment transistor M composed of the same elements as the constituent elements of transistor M1 or M2 ADJ is provided in the adjustment circuit 22, and with a boost voltage V ADJ applied between the gate and source of the adjustment transistor M BST in a state where the adjustment transistor M ADJ is adjusted such that a constant current I CC flows. Thereby, against element variations, temperature changes, etc., optimization of the drain current I BST or I D1 or I D2 in the lead operation is achieved. That is, for example, when the configuration of FIG. 14A is adopted, in the transistor M1 or M2 that receives the adjusted boost voltage V BST at the gate, a drain current of the same magnitude as the constant current I CC flows (ignoring errors). That is, against element variations, temperature changes, etc., the magnitude of the drain current I D1 or I D2 in the lead operation can always be made the same as that of the constant current I CC . Therefore, the value of the constant current I CC can be set to the appropriate value of the drain current I D1 or I D2 in the lead operation. The same applies when the configuration of FIG. 14B is adopted. However, when the configuration of FIG. 14B is adopted, considering that a constant current I CC flows through the parallel circuit of a plurality of unit transistors Mu, the value of the constant current I CC is set. Compared with the case where the configuration of FIG. 14A is adopted, if the configuration of FIG. 14B is adopted, the boost voltage V BST quickly converges to the stable voltage V BST_ADJ during the period Pb.

[0100] <<Second Embodiment>> The second embodiment of the present disclosure will be described. The second embodiment is based on the first embodiment, and regarding matters not specifically described in the second embodiment, the description of the first embodiment is applied to the second embodiment as long as there is no contradiction. When interpreting the description of the second embodiment, the description of the second embodiment may be given priority for matters conflicting between the first and second embodiments.

[0101] In the second embodiment, in the initial state of the memory cell 10 or 10[i] (i.e., the state where no program operation has been executed at all), the memory cell 10 or 10[i] is made to store an initial value of "0". To achieve this, in the second embodiment, the configurations of the transistor M1 and the transistor M2 are made different.

[0102] A configuration example of the memory cell 10[i] according to the second embodiment is shown in FIG. 16. In the memory cell 10[i], the transistor M1 is constituted by one unit transistor Mu, and the transistor M2 is constituted by a parallel circuit of n unit transistors Mu. Here, n is an arbitrary integer of 2 or more. However, in FIG. 16, a configuration example in the case of "n = 4" is shown. The total (n + 1) unit transistors Mu included in the memory cell 10[i] in FIG. 16 are N-channel type MOSFETs having the same structure as each other. In the case of "n = 4", when the five unit transistors Mu included in the memory cell 10[i] are referred to as the first to fifth unit transistors Mu, the transistor M1 is the first unit transistor Mu itself, and the transistor M2 is constituted by a parallel circuit of the second to fifth unit transistors Mu. More specifically, the gates of the second to fifth unit transistors Mu are commonly connected to each other to constitute the gate of the transistor M2, the drains of the second to fifth unit transistors Mu are commonly connected to each other to constitute the drain of the transistor M2, and the sources of the second to fifth unit transistors Mu are commonly connected to each other to constitute the source of the transistor M2.

[0103] According to such a configuration, in the initial state of the memory cell 10[i] (i.e., the state where no program operation has been executed at all), when a read operation is performed, the drain current I of the transistor M2 D2 becomes n times the drain current I of the transistor M1 D1 (ignoring errors), and a value of "0" is read from the memory cell 10[i] in the read operation (i.e., a signal D representing the value of "0" is output from the sense amplifier SAMP OUT ).

[0104] In the second embodiment, the first program operation (see FIG. 11) is not executed as the program operation, and the program operation is limited to the second program operation (see FIG. 12). Therefore, the switch SW1 is removed from the memory circuit 1, or the switch SW1 is fixed to the off state.

[0105] In the memory circuit 1 according to the second embodiment, when the second program operation is executed in the switch state shown in FIG. 12, a current flows from the line LN S towards the ground through the electrodes E2b and E2a and the switch SW2. During the process of this current flowing, hot carriers are injected into the transistor M2 and the characteristics of the transistor M2 (the characteristics of each unit transistor Mu constituting the transistor M2) change, and the gate threshold voltage of the transistor M2 increases. After maintaining the program period for a time sufficient to sufficiently increase the gate threshold voltage of the transistor M2, the second program operation is terminated. Note that during the program period of the second program operation, the line LN D1 is in a high-impedance state, and no current flows between the electrodes E1a and E1b. After performing the second program operation on the memory cell 10[i], when a read operation is performed on the memory cell 10[i], along with the increase in the gate threshold voltage of the transistor M2 due to the second program operation, in the read operation, "I D2 <I D1 ", and as a result, a signal D representing the second value (1) OUT is output, that is, the data (value) of "1" stored in the memory cell 10[i] is read.

[0106] The configuration of the adjustment circuit 22 in the second embodiment is the same as that in the first embodiment, and the adjustment transistor M ADJ is composed of one unit transistor Mu or a parallel circuit of a plurality of unit transistors Mu. Therefore, the operations and effects shown in the first embodiment can also be obtained in the second embodiment.

[0107] Note that instead of configuring the transistor M2 as a parallel circuit of n unit transistors Mu, the following method may also be used. That is, for example, while configuring the transistor M1 with the unit transistor Mu, by making the gate width of the MOSFET as the transistor M2 larger than the gate width of the MOSFET as the transistor M1 (therefore the MOSFET as the unit transistor Mu), "I D2 >I D1 " may be ensured in the lead operation in the initial state.

[0108] <<Modifications, etc.>> Hereinafter, modifications, application examples, etc. applicable to the first or second embodiment will be described.

[0109] In the above operation example, it is assumed that the first value is "0" and the second value is "1". However, as long as the first and second values are different, the first and second values are arbitrary. Also, the signal D associated with the first value OUT is a high-level signal and the signal D associated with the second value OUT is a low-level signal, the circuit may be configured.

[0110] The non-volatile memory (memory circuit 1) according to the present disclosure can be incorporated into any circuit or device that realizes a predetermined functional operation. When a power supply voltage is supplied to the circuit or device in which the non-volatile memory is incorporated and the circuit or device is activated, the circuit or device reads the data stored in the non-volatile memory by a read operation and realizes a predetermined functional operation according to the read data. For example, the non-volatile memory (memory circuit 1) can be incorporated into an amplifier circuit (not shown) capable of varying the amplification factor according to trimming data, and the amplification factor of the amplifier circuit can be optimally adjusted by supplying one or more data stored in the non-volatile memory as trimming data to the amplifier circuit. Further, the non-volatile memory according to the present disclosure can be incorporated into semiconductor integrated circuits for various applications, such as a semiconductor integrated circuit for a DC / DC converter and a semiconductor integrated circuit for a motor driver. The amplifier circuit is an example of a circuit provided in these semiconductor integrated circuits.

[0111] The type of the channel of the FET (field effect transistor) shown in each embodiment is an example, and the configuration of the circuit including the FET can be modified so that the N-channel type FET is changed to the P-channel type FET, or the P-channel type FET is changed to the N-channel type FET.

[0112] Unless otherwise inconvenient, any of the above transistors can be any type of transistor. For example, any of the transistors described above as MOSFETs can be replaced with a junction FET, an IGBT (Insulated Gate Bipolar Transistor), or a bipolar transistor unless otherwise inconvenient. Any transistor has a first electrode, a second electrode, and a control electrode. In an FET, one of the first and second electrodes is a drain and the other is a source, and the control electrode is a gate. In an IGBT, one of the first and second electrodes is a collector and the other is an emitter, and the control electrode is a gate. In a bipolar transistor that does not belong to an IGBT, one of the first and second electrodes is a collector and the other is an emitter, and the control electrode is a base.

[0113] Embodiments of the present disclosure can be appropriately modified in various ways within the scope of the technical idea shown in the claims. The above embodiments are merely examples of the embodiments of the present disclosure, and the meanings of the terms of the present disclosure or each constituent element are not limited to those described in the above embodiments. The specific numerical values shown in the above description are merely examples, and of course, they can be changed to various numerical values.

[0114] <<Supplementary Note>> Consider the technical idea embodied in the above embodiments.

[0115] The non-volatile memory according to the present disclosure includes a memory cell having a first transistor and a second transistor, a drive circuit configured to supply a read voltage to each gate of the first transistor and the second transistor, and a signal output circuit configured to output a signal associated with a first value or a signal associated with a second value based on the drain current of each of the first and second transistors in a read operation in which the read voltage is supplied. The drive circuit includes a boost circuit configured to generate a boost voltage on a boost line by boosting a predetermined reference voltage, and an adjustment circuit configured to adjust the boost voltage by drawing an adjustment current corresponding to the boost voltage from the boost line. In the read operation, the adjusted boost voltage is supplied as the read voltage to each gate of the first transistor and the second transistor (a first configuration).

[0116] In the non-volatile memory according to the first configuration, the adjustment circuit may include an adjustment transistor having a gate connected to the boost line, a drain current corresponding to the boost voltage flowing through the adjustment transistor, and the adjustment current having a magnitude corresponding to the drain current of the adjustment transistor (a second configuration).

[0117] In the non-volatile memory according to the second configuration, the higher the boost voltage, the larger the drain current of the adjustment transistor, and the larger the drain current of the adjustment transistor, the larger the adjustment current (third configuration) may be.

[0118] In the non-volatile memory according to the third configuration, the adjustment circuit is configured such that the sum of a first current proportional to the adjustment current and a predetermined second current is supplied to the drain of the adjustment transistor, and when the drain current of the adjustment transistor decreases based on the decrease in the boost voltage accompanying the drawing-in of the adjustment current from the boost line, the first current decreases by the amount of the decrease, and as a result, the adjustment current also decreases (fourth configuration) may be.

[0119] In the non-volatile memory according to the fourth configuration, the adjustment circuit includes a first current mirror circuit configured to output the first current toward the drain of the adjustment transistor while generating a current proportional to the first current in a predetermined line, a second current mirror circuit configured to generate a current proportional to the current flowing in the predetermined line as the adjustment current and draw in the adjustment current from the boost line, and a constant current circuit configured to output the second current as a constant current toward the drain of the adjustment transistor (fifth configuration) may be.

[0120] In the non-volatile memory according to any one of the second to fifth configurations, the adjustment transistor may be configured by a MOSFET that constitutes the first transistor or the two transistors and a MOSFET having the same structure (sixth configuration).

[0121] In the non-volatile memory according to any one of the first to sixth configurations, the boost circuit may be configured by a charge pump circuit configured to boost the reference voltage using a capacitor and a switch (seventh configuration).

[0122] In the non-volatile memory according to any one of the first to seventh configurations, in the read operation, when the drain current of the second transistor is larger than the drain current of the first transistor, the signal output circuit outputs a signal associated with the first value, and when the drain current of the first transistor is larger than the drain current of the second transistor, it may be configured to output a signal associated with the second value (eighth configuration).

[0123] In the non-volatile memory according to the eighth configuration, it is possible to execute a program operation that increases the gate threshold voltage of the targeted transistor by injecting hot carriers into one of the first and second transistors. In the read operation executed after the program operation, with the increase in the gate threshold voltage of the one transistor that was the target of hot carrier injection among the first and second transistors, a configuration (ninth configuration) in which the drain current of the other transistor is larger than the drain current of the one transistor may be adopted.

[0124] In the non-volatile memory according to the eighth configuration, it is possible to execute a program operation that increases the gate threshold voltage of the second transistor by injecting hot carriers into the second transistor. In the read operation executed before the program operation, the drain current of the second transistor is larger than the drain current of the first transistor, and in the read operation executed after the program operation, with the increase in the gate threshold voltage of the second transistor due to the program operation, a configuration (tenth configuration) in which the drain current of the first transistor is larger than the drain current of the second transistor may be adopted.

[0125] Other non-volatile memories according to the present disclosure include a memory cell having a first transistor and a second transistor, a drive circuit configured to supply a read voltage to each gate of the first transistor and the second transistor, and in a read operation in which the read voltage is supplied, based on the drain current of each of the first and second transistors, a signal output circuit configured to output a signal associated with a first value or a signal associated with a second value. The drive circuit includes a boost circuit configured to generate a boost voltage on a boost line by boosting a predetermined reference voltage, and an adjustment circuit configured to adjust the boost voltage by drawing an adjustment current corresponding to the boost voltage from the boost line. When the read operation is performed, in the read operation, the adjusted boost voltage is supplied as the read voltage to each gate of the first transistor and the second transistor (a first configuration).

Explanation of Signs

[0126] 1 Storage circuit 10, 10[i] Memory cell 20 Drive circuit 30 Signal output circuit 40 Control circuit 21 Boost circuit 22 Adjustment circuit 23 Gate voltage supply circuit M1 Transistor (first transistor) M2 Transistor (second transistor) M ADJ Adjustment transistor V REG Reference voltage V BST Boost voltage LN BST Boost line

Claims

1. A memory cell having a first transistor and a second transistor, A drive circuit configured to supply a read voltage to each gate of the first transistor and the second transistor, In a read operation in which the read voltage is supplied, based on the drain current of each of the first and second transistors, a signal associated with a first value or a signal associated with a second value is output. And a signal output circuit configured as described above, The drive circuit includes a boost circuit configured to generate a boost voltage on a boost line by boosting a predetermined reference voltage, and a boost voltage is obtained by drawing an adjustment current corresponding to the boost voltage from the boost line. And an adjustment circuit configured to adjust the boost voltage, and in the read operation, the adjusted boost voltage is used as the read voltage to be applied to each gate of the first transistor and the second transistor. Configured to supply , a non-volatile memory.

2. The adjustment circuit has an adjustment transistor having a gate connected to the boost line, A drain current corresponding to the boost voltage flows through the adjustment transistor, The adjustment current has a magnitude corresponding to the drain current of the adjustment transistor , the non-volatile memory according to claim 1.

3. The higher the boost voltage, the greater the drain current of the adjustment transistor, The greater the drain current of the adjustment transistor, the greater the adjustment current , the non-volatile memory according to claim 2.

4. The adjustment circuit is configured such that the sum of a first current proportional to the adjustment current and a predetermined second current is supplied to the drain of the adjustment transistor, When the drain current of the adjustment transistor decreases based on the decrease in the boost voltage accompanying the drawing-in of the adjustment current from the boost line, the first current decreases by the amount of the decrease, and as a result, the adjustment current also decreases. The non-volatile memory according to claim 3.

5. The adjustment circuit A first current mirror circuit configured to output the first current toward the drain of the adjustment transistor while generating a current proportional to the first current in a predetermined line; A second current mirror circuit configured to generate a current proportional to the current flowing in the predetermined line as the adjustment current and draw in the adjustment current from the boost line; A constant current circuit configured to output the second current as a constant current toward the drain of the adjustment transistor, and has The non-volatile memory according to claim 4.

6. The adjustment transistor is composed of a MOSFET that constitutes the first transistor or the two transistors, and a MOSFET having the same structure. The non-volatile memory according to any one of claims 2 to 5.

7. The boost circuit is composed of a charge pump circuit configured to boost the reference voltage using a capacitor and a switch. The non-volatile memory according to any one of claims 1 to 6.

8. In the read operation, when the drain current of the second transistor is greater than the drain current of the first transistor, the signal output circuit is configured to output a signal associated with the first value, and when the drain current of the first transistor is greater than the drain current of the second transistor, the signal output circuit is configured to output a signal associated with the second value. The non-volatile memory according to any one of claims 1 to 7.

9. It is possible to execute a program operation that increases the gate threshold voltage of a targeted transistor by injecting hot carriers into one of the first and second transistors. In the read operation executed after the program operation, as the gate threshold voltage of one of the first and second transistors that is the target of hot carrier injection increases, the drain current of the other transistor is greater than the drain current of the one transistor. The non-volatile memory according to claim 8.

10. It is possible to execute a program operation that increases the gate threshold voltage of the second transistor by injecting hot carriers into the second transistor. In the read operation executed before the program operation, the drain current of the second transistor is greater than the drain current of the first transistor. In the read operation executed after the program operation, as the gate threshold voltage of the second transistor increases due to the program operation, the drain current of the first transistor is greater than the drain current of the second transistor. The non-volatile memory according to claim 8.

11. A memory cell having a first transistor and a second transistor. A drive circuit configured to be able to supply a read voltage to each gate of the first transistor and the second transistor. In a read operation in which the read voltage is supplied, a signal output circuit configured to be able to output a signal associated with a first value or a signal associated with a second value based on each drain current of the first and second transistors. The drive circuit includes a boost circuit configured to generate a boost voltage on a boost line by boosting a predetermined reference voltage, and an adjustment circuit configured to adjust the boost voltage by drawing an adjustment current corresponding to the boost voltage from the boost line. When the lead operation is performed, in the lead operation, the adjusted boost voltage is supplied as the lead voltage to the gates of the first transistor and the second transistor. , a non-volatile memory.

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