Memory system combining a high-density low-bandwidth memory and a low-density high-bandwidth memory

Abstract

To provide a memory system having DRAMs of different types.SOLUTION: A memory system according to the present invention has at least two kinds of DRAMs each of which has at least one different characteristic. DRAM types 16A to 16D are a high-density DRAM, and the other DRAM type 18 has lower density as compared with those of the first DRAM types but has lower latency and higher bandwidth as compared with those. The first DRAM type may be disposed in one or more first integrated circuits, and the second DRAM type may be disposed in one or more second integrated circuits. The first integrated circuit and the second integrated circuit can be connected to each other in a stack. The second integrated circuit may have a physical layer circuit 60B connected to other circuit (e.g., an integrated circuit having a memory controller such as system-on-chip (SOC)) which can be shared by the DRAMs of the first integrated circuit.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The embodiments described herein relate to an electronic system including a dynamic random access memory (DRAM).

Background Art

[0002] As DRAM continues to evolve, the design of DRAM has become more complex due to different ideal objectives of DRAM, such as high bandwidth, large capacity, and high density storage with low power consumption (high energy efficiency). Design choices to improve density / capacity tend to reduce (or at least not increase) bandwidth. Design choices that can increase bandwidth tend to reduce (or at least not increase) capacity and energy efficiency.

Summary of the Invention

[0003] In one embodiment, a memory system can include at least two types of DRAM with at least one different characteristic. For example, one DRAM type can be a high-density DRAM, while the other DRAM type can have a lower density than the one DRAM type but also have a lower latency and a higher bandwidth. The first type of DRAM can be in one or more first integrated circuits, and the second type of DRAM can be in one or more second integrated circuits. By providing a memory system with two types of DRAM (e.g., one high density and one low latency, high bandwidth), a very energy-efficient operation can be enabled, thereby fabricating a memory system suitable for portable devices and other devices where energy efficiency and performance per unit of energy consumed are important attributes.

[0004] In one embodiment, the first integrated circuit and the second integrated circuit can be connected to each other in a stack. The second integrated circuit can include a physical layer circuit for connecting to other circuits (e.g., an integrated circuit having a memory controller such as a system on a chip (SOC)), and this physical layer circuit can be shared by the DRAM of the first integrated circuit. In some embodiments, this memory can be used to achieve high energy efficiency, large capacity, and low latency. The following detailed description refers to the accompanying drawings briefly described below.

Brief Description of the Drawings

[0005]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

Figure 11

Figure 12

Figure 13

Figure 14

DETAILED DESCRIPTION OF THE INVENTION

[0006] While there may be scope for various modifications and alternative forms in the embodiments described in this disclosure, specific embodiments thereof are shown in the drawings by way of example and will be described in detail herein. However, it should be understood that the drawings and the detailed description thereof are not intended to limit the embodiments to the particular forms disclosed, but rather the intention is to cover all modifications, equivalents, and alternative forms included within the spirit and scope of the appended claims. The headings used herein are for purposes of organization only and are not intended to limit the scope of the description. As used throughout this application, the term "may" is used in a permissive sense (i.e., having the possibility of doing something) rather than in an obligatory sense (i.e., meaning that one must do something). Similarly, the terms "include," "including," and "includes" mean "including but not limited to."

[0007] Within the present disclosure, various entities (which may be variously referred to as "units", "circuits", other components, etc.) may be described or claimed as being "configured" to perform one or more tasks or operations. This explicit phrase "entity configured to perform [one or more tasks]" is used herein to refer to a structure (i.e., something physical such as an electronic circuit). More specifically, this explicit phrase is used to indicate that the structure is arranged to perform one or more tasks during operation. A structure may be described as being "configured" to perform some task even when the structure is not currently operating. For example, a "clock circuit configured to generate an output clock signal" is intended to encompass a circuit that performs this function during operation even if the circuit is not currently in use (e.g., the power supply is not connected to the circuit). Thus, an entity described or recited as being "configured" to perform some task refers to something physical such as a device, circuit, memory storing program instructions, etc. that is executable to implement that task. This phrase is not used herein to refer to something intangible. Generally, a circuit forming a structure corresponding to "configured to" may include a hardware circuit. The hardware circuit may include any combination of combinational logic circuits, clocked storage devices such as flops, registers, latches, finite state machines, memories such as static random access memories or embedded dynamic random access memories, custom designed circuits, analog circuits, programmable logic arrays, etc. Similarly, various units / circuits / components may be described as performing a task(s) for simplicity of explanation. Such explanations should be construed as including the phrase "configured to".

[0008] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA may be "configurable to" perform some particular function, but would not be considered "configured to" perform that function. After appropriate programming, the FPGA may then be configured to perform that function.

[0009] The description in the appended claims of a unit / circuit / component or other structure configured to perform one or more tasks is expressly intended not to invoke the interpretation of 35 U.S.C. § 112(f) with respect to the claim elements. Accordingly, none of the claims in the present application as filed is intended to be construed as having means-plus-function elements. If Applicant wishes to invoke 35 U.S.C. § 112(f) during prosecution, it will be by reciting claim elements using the construct "means for" performing the function.

[0010] In one embodiment, the hardware circuit according to the present disclosure may be implemented by coding a circuit description in a hardware description language (HDL) such as Verilog or VHDL. The HDL description may be synthesized against a library of cells designed for a given integrated circuit manufacturing technology and modified for timing, power, and other reasons to result in a final design database that can be sent to a foundry to generate masks and ultimately manufacture an integrated circuit. Some hardware circuits or portions thereof may also be custom designed with a circuit diagram editor and incorporated into the integrated circuit design along with the synthesized circuits. The integrated circuit may include transistors and may further include other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.) and the interconnections between the transistors and the circuit elements. Some embodiments may implement a plurality of integrated circuits connected together to realize the hardware circuit, and / or in some embodiments, individual elements may be used. Alternatively, the HDL design may be integrated into a programmable logic array such as a field programmable gate array (FPGA) or implemented on an FPGA.

[0011] As used herein, the terms "based on" or "depending on" are used to describe one or more factors that affect a determination. This term does not exclude the possibility that additional factors may affect the determination. That is, the determination may be based on only the specified factors or on the specified factors as well as other unspecified factors. Consider the phrase "determine A based on B". This phrase specifies that B is a factor used to determine A or that affects the determination of A. This phrase does not exclude the possibility that the determination of A may also be based on some other factor, such as C. This phrase is intended to cover embodiments in which A is determined based on only B. As used herein, the phrase "based on" is synonymous with the phrase "at least partially based on".

[0012] The present disclosure is not intended to refer to a particular implementation form, but rather to indicate that it is intended to refer to the scope of implementation forms within the spirit of the present disclosure, including the appended claims, this specification includes references to various implementation forms. Specific features, structures, or characteristics may be combined in any suitable manner consistent with the present disclosure.

[0013] Referring now to FIG. 1, a block diagram of an embodiment of a system including a memory system 10 and an integrated circuit 12 is shown. In the illustrated embodiment, the integrated circuit 12 is a system-on-chip (SOC), and in other embodiments of the present disclosure, the SOC is used as an example. However, any integrated circuit can be used in various embodiments. In the embodiment of FIG. 1, the memory 10 includes a plurality of main DRAM chips (DRAMs) 16A to 16D and a cache DRAM 18. The main DRAMs 16A to 16D include a physical layer circuit (PHY) 60A, and the cache DRAM 18 includes a PHY 60B. The PHY 60A is connected to the PHY 60C in the SOC 12, and the PHY 60B is connected to the PHY 60D in the SOC 12. More specifically, the PHY 60C may be connected to the main memory controller (MC) block 28A, and the PHY 60D may be connected to the cache controller block (CC) 28B, and both of them may be part of the memory controller 28 (Mem) in FIG. 1.

[0014] Memory system 10 can include two different types of DRAM, and for those DRAMs, the memory controller 28 of SOC 12 can independently control main DRAMs 16A - 16D and cache DRAM 18. The combination of main DRAMs 16A - 16D and cache DRAM 18 provides high bandwidth to the memory agent of SOC 12 and can also provide a large overall storage capacity and low power. The storage capacity can be provided by main DRAMs 16A - 16D which can have memory designed for density and capacity. High bandwidth can be provided by the wide interface between cache DRAM 18 and SOC 12. As the interface becomes wider, it becomes possible to clock control at a slower clock speed, saving power compared to the fast and narrow interfaces of conventional synchronous DRAMs. In one embodiment, the interfaces between cache DRAM 18 and SOC 12, and between main DRAMs 16A - 16D and SOC 12 may have different widths (e.g., cache DRAM 18 may have an interface more than twice as wide as main DRAMs 16A - 16D, and in some embodiments, it may be 2 - 4 times wider). Further, cache DRAM 18 can include a relatively small memory array that has a lower density but can achieve a higher bandwidth with less energy. For example, the memory array can have more banks, a smaller page size, lower latency, more channels, etc. compared to conventional DRAM or DRAMs 16A - 16D. In some embodiments, the memory array can include one or more of fewer memory cells per bit line, fewer memory cells per word line, and / or smaller banks compared to the similar characteristics of DRAMs 16A - 16D to reduce power. More specifically, in one embodiment, the memory array of cache DRAM 18 can trade off a lower density compared to main DRAMs 16A - 16D to reduce energy consumption.A lower density can be achieved in the cache DRAM 18 by one or more of fewer memory cells per bit line (compared to the main DRAMs 16A to 16D), fewer memory cells per word line, a larger number of banks, and / or smaller banks. In one embodiment, the cache DRAM 18 can have a memory array that is 4 to 16 times lower density, preferably 6 to 8 times lower density, than the memory arrays of the main DRAMs 16A to 16D. The data path design within the bank and the data path design from the bank to the PHY 60B can be optimized. Further, the data path from the cache DRAM 18 to the SOC 12 can be a point-to-point, low capacitance, low voltage connection.

[0015] When two types of DRAM form a memory system, in some embodiments, one of them can be optimized for bandwidth, the other can be optimized for capacity, and both the purpose of increasing bandwidth and the purpose of increasing capacity can be achieved. Further, energy efficiency can be managed in the high-bandwidth portion of the memory (which is smaller in capacity / smaller in size and thus can have a lower density). The portion of the memory optimized for capacity can have the purpose of lower bandwidth and a gentle (longer) latency. Because these purposes can be achieved by the portion optimized for bandwidth. Similarly, the portion of the memory optimized for bandwidth can have the purpose of lower area efficiency, but can improve latency and energy efficiency. In some embodiments, overall, a high-bandwidth, low-latency, energy-efficient, and large-capacity memory system can be realized at low cost. In particular, by implementing the high-density portion (main DRAM 16A to 16D) and the high-bandwidth, low-latency portion (cache DRAM 18) on separate chips that together form the main memory system 10, it becomes possible to improve the energy efficiency for each of the memories 16A to 16D and 18, thereby providing a memory solution that is both high-performance and high-bandwidth and very energy-efficient. Specific optimizations that can be performed on each memory in various embodiments will be described in more detail below with respect to FIGS. 12 to 14.

[0016] In one embodiment, the cache DRAM 18 can implement a simplified command set to reduce the number of commands sent to the cache DRAM 18 per access. For example, the main DRAMs 16A - 16D can include an active command, a column address strobe (CAS) command for each read or write access, and optionally a recharge command. On the other hand, the cache DRAM 18 can support a read command for read access and a write command for write access. Inside the cache DRAM 18, a read or write command can cause multiple internal operations such as activation, one or more CAS reads or writes respectively, and precharge. Since only a small number of commands are sent through the interface for a given access, the energy consumption for the access can be reduced.

[0017] As shown in the figure, the memory controller 28 controls the main DRAMs 16A to 16D and the cache DRAM 18 independently. In particular, in one embodiment, a main memory controller block 28A and a cache controller block 28B are shown. The main memory controller block 28A can control the main DRAMs 16A to 16D, and the cache controller block 28B can control the cache DRAM 18. Caching of data from the main DRAMs 16A to 16D to the cache DRAM 18 is under the control of the memory controller 28 and can be performed by moving data from the main DRAMs 16A to 16D through the SOC 12 to the cache DRAM 18. That is, the caching policy, allocation, and deallocation of cache lines, etc., can be determined by the memory controller 28. By storing frequently accessed data in the high-bandwidth low-power cache DRAM 18, the effective memory bandwidth can be increased to be higher than the memory bandwidth of the main DRAMs 16A to 16D, and at the same time, the large capacity of the main DRAMs 16A to 16D can also be enjoyed. In addition to the main memory controller block 28A and the cache controller block 28B, additional circuits of the memory controller 28 can coordinate the caching policy, data transfer, etc., or the blocks 28A to 28B can interact directly to perform the caching operation.

[0018] Figure 2 is a block diagram of another embodiment of the main DRAMs 16A to 16D and the cache DRAM 18 connected to the SOC 12. In the embodiment of Figure 2, a single PHY 60D can be implemented in the SOC 12, and the SOC 12 is connected to a single PHY 60B of the cache DRAM 18. There may be logic capable of decoding operations directed to the main DRAMs 16A to 16D, and this decoded operation can be transferred to the DRAMs 16A to 16D through the PHYs 60C and 60A as shown in Figure 2.

[0019] FIG. 3 is a block diagram of a third embodiment of main DRAMs 16A to 16D and cache DRAM 18 connected to SOC 12. In the embodiment of FIG. 3, separate PHYs 60D and 60C can be implemented for cache controller block 28B to communicate with cache DRAM 18 (PHY 60B) and for main memory controller block to communicate with main DRAMs 16A to 16B (PHY 60A), respectively. However, cache DRAM 18 can operate as a host to the transport layer to main DRAMs 16A to 16D that communicates with PHYs 60F of main DRAMs 16A to 16D via PHY 60E, as shown in FIG. 3.

[0020] As shown in FIGS. 1 to 3, in some embodiments, the PHY protocol for cache DRAM 18 may be different from the PHY protocol for main DRAMs 16A to 16D, and both protocols can be supported in various configurations. In other embodiments, the same PHY protocol can be used.

[0021] Figures 4 to 7 illustrate the scalability of the memory system 10 for various application examples based on various embodiments of packaging the cache DRAM 18 and the main DRAMs 16A to 16D with the SOC 12. For example, in FIGS. 4 and 6, the main DRAMs 16A to 16D and the cache DRAM 18 (i.e., the main memory 10) are packaged separately from the SOC 12. For small form factor devices such as mobile phones, a system such as that in FIG. 4 can be used, having the memory system 10 on one side of the SOC 12. On the other hand, for larger form factor devices such as tablet computers, laptops, or desktop computers, an embodiment such as that in FIG. 6 can be used, where the memory system 10 is formed from a plurality of portions on various sides of the SOC 12 (e.g., portions 10A, 10B, 10C, and 10D in FIG. 6). Any number of portions can be used in various embodiments. FIGS. 5 and 7 show embodiments in which the SOC 12 and the cache DRAM 18 are packaged together and interface with the main DRAMs 16A to 16D. FIG. 5 is similar to FIG. 4 and shows the main DRAMs 16A to 16D on one side of the SOC 12 / cache DRAM 18, for example, for small form factor devices such as mobile phones. On the other hand, for larger form factor devices, an embodiment such as that in FIG. 7 can be used. In FIG. 7, a plurality of instances of the main DRAMs 16A to 16D are shown on various sides of the SOC 12 and the cache DRAM 18. The cache DRAM 18 packaged with the SOC 12 is also scalable in different implementation forms as needed. For example, see FIGS. 8 and 9 below. Any number of instances can be used in various embodiments. As described above, each of the main DRAMs 16A to 16D shown in FIGS. 4 to 7 can be one DRAM or a plurality of DRAMs as needed in various embodiments.

[0022] FIG. 8 is a block diagram of one embodiment of a system showing a package 50 including SOC 12 and cache DRAM 18. Optionally, in some embodiments, multiple instances of cache DRAM 18 can be included (e.g., a second cache DRAM 18 is shown in dotted lines in FIG. 8). The package may include a connection layer 14 including relatively short interconnects to cache DRAM 18 (see, e.g., FIGS. 12 and the description below for further details). One or more main DRAMs 16A-16D can be assembled with the SOC 12 / cache DRAM 18 in a package-on-package (POP) configuration using a POP substrate 52 and can be connected between the main DRAMs 16A-16D and the connection layer 14 (and further to the SOC 12, to the wiring in the connection layer 14 and POP substrate 52 not shown in FIG. 8). FIG. 9 is another example of POP packaging using one or more main DRAMs 16A-16D and the SOC 12 / cache DRAM 18. In the embodiment of FIG. 9, one cache DRAM 18 (or multiple cache DRAMs 18 in some embodiments) is mounted on the SOC 12 using any desired technique. For example, chip on wafer (COW) packaging, wafer on wafer (WOW) packaging, chip on chip (COC) packaging, etc. can be used.

[0023] In other embodiments, the main DRAMs 16A-16D may be packaged separately from the SOC 12 and the cache DRAM 18. For example, FIGS. 10 and 11 show the SOC 12 / cache DRAM 18 as shown in FIGS. 8 and 9, respectively, but the main DRAMs 16A-16D packaged separately are connected to a system substrate or main board 54. In some implementations, the embodiments of FIGS. 10 and 11 may be a multi-chip module (MCM), and the substrate 54 may be an MCM substrate. In other embodiments, the main board 54 may be various types of circuit boards, such as a printed circuit board (PCB). Two sets of main DRAMs 16A-16D are shown, but each DRAM may be one or more DRAMs, and there may be one DRAM / DRAM set or multiple DRAM sets as shown in FIGS. 6 and 7.

[0024] FIGS. 12-14 show various exemplary 2.5-dimensional (D) and 3D configurations of the SOC 12, the cache DRAM 18, and the main DRAMs 16A-16D. However, note that in other embodiments, any packaging solution including various other 2.5D and / or 3D solutions can also be used.

[0025] Next, referring to FIG. 12, a block diagram of an embodiment of a system including a memory system 10 and an SOC 12 connected through a connection layer 14 is shown. In the embodiment of FIG. 1, the memory 10 includes a plurality of main DRAM chips (DRAMs) 16A-16D and a cache DRAM 18. Each main DRAM 16A-16B includes one or more memory arrays 20A-20H as shown in FIG. 1. The cache DRAM 18 includes a memory array 22 and a physical layer interface circuit (PHY circuit 24). The PHY circuit 24 is connected to the connection layer 14 through a pin of the cache DRAM 18, connected to a pin of the SOC 12 through the connection layer 14, and then connected to a corresponding PHY circuit 26 of the SOC 12. The PHY 26 is connected to a memory controller 28 of the SOC 12, and the memory controller 28 further includes various other circuits 30 (such as a processor, peripherals, etc.). The other circuits 30 are connected to the opposite side of the connection layer 14 through other pins of the SOC 12 and can be connected to other components of the system.

[0026] As described above, the memory system 10 can include two different types of DRAMs, and for those DRAMs, the memory controller 28 of the SOC 12 can independently control the main DRAMs 16A-16D and the cache DRAM 18. Although one PHY circuit 24 and one PHY circuit 26 are shown in the embodiment of FIG. 1, in other embodiments, it should be noted that, as described above with respect to PHY circuits 60A-60D (and 60E and 60F in the embodiment of FIG. 3), there can be independent PHY circuits 24 and 26 for the cache DRAM 18 and for the main DRAMs 16A-16D.

[0027] As described above, the memory arrays 20A to 20H can be designed for density in order to provide a high storage capacity per unit area of the DRAMs 16A to 16D. The DRAMs 16A to 16D can implement, for example, a larger page size compared to the cache DRAM 18. The DRAMs 16A to 16D can include fewer banks compared to the cache DRAM 18. In order to further increase the density, some control logic for the DRAMs 16A to 16D, such as a test circuit, redundancy control, an error correction code (ECC) mechanism, a reference voltage logic, a temperature control reference logic, etc., can be placed on the cache DRAM 18.

[0028] The smaller the page size of the cache DRAM 18 becomes (and the larger the number of open pages becomes due to the increase in the number of banks of the cache DRAM 18), the more frequent small accesses can be promoted by a large number of memory agents of the SOC 12 (compared to its page size). For example, the processor tends to read only one or a few cache lines of data, where the conventional page size of the DRAM can be 2 to 4 kilobytes in size. Each time a page is opened, the entire page of data is read from the memory array and can be captured in a sense amplifier and / or a register for access. When that page is closed and a new page is opened, the entire new page of that data is read. On the other hand, reading a smaller page proportionally consumes less power. When a large number of agents are competing for access to the memory, page contention and page open / close can become more frequent, and a reduction in power consumption per page can lead to a reduction in the overall power consumption.

[0029] Therefore, when data can be reused, the memory controller 28 can be configured to write data read from the main DRAMs 16A to 16D to the cache DRAM 18. Various caching methods can be used. However, since the cache DRAM 18 is denser than the on-SOC static RAM (SRAM) on the SOC, a larger cache can be implemented than is possible using SRAM. Further, DRAM includes fewer transistors per bit of stored data than SRAM (e.g., one transistor per bit versus six transistors per bit), and thus, DRAM has lower leakage power per bit than SRAM. Further, in some embodiments, reducing the on-chip memory cache can save the silicon die area of the SOC 12, which can offset the expense of the cache DRAM 18 to some extent.

[0030] To reduce the length and capacitance of the interconnections, the main DRAMs 16A - 16D can employ through-silicon-via (TSV) interconnections (e.g., TSV 32 shown in FIG. 12). TSV 32 can be formed, for example, using known TSV manufacturing techniques. TSV 32 can be connected to each other when the DRAMs 16A - 16D are stacked between memories through pins. The DRAM 16D (the main DRAM at the bottom of the stack) can be connected to the cache DRAM 18 through pins, and the cache DRAM 18 can route signals to the PHY circuit 24. The PHY circuit 24 may have output terminals to the PHY circuit 26 and / or input terminals from the PHY circuit 26 physically arranged along the edge of the cache DRAM 18, and the input / output terminals of the PHY circuit 26 can be similarly physically arranged along the edge of the SOC 12. In this way, a short wiring path through the connection layer 14 can be used to connect the PHY circuits 24 / 26. The PHY circuit 24 and the PHY circuit 26 can be designed to communicate through a relatively short interconnection with a fixed small load and through the connection layer 14. A small low-power driver can be used compared to conventional DRAM interfaces that have longer interconnections and multiple DRAM loads.

[0031] Furthermore, since the cache DRAM 18 routes the TSV interconnection to a desired position at the edge of this cache DRAM 18, the TSVs can be positioned more freely within the main DRAMs 16A - 16D. In some embodiments, congestion can be reduced and more interconnections can be provided than possible in conventional DRAMs.

[0032] In the illustrated embodiment, TSVs are used, but in other embodiments, silicon interposer interconnects or fanout technologies such as integrated fanout (InFO) available from Taiwan Semiconductor Manufacturing Company (trademark) (TSMC) can be used. The pins referred to in this specification can be any form of inter-chip interconnect. For example, the pins can be "microbumps", or solder balls or other pin-forming materials. Although other embodiments explicitly show solder balls, other pin configurations can equally be used in those embodiments.

[0033] The connection layer 14 can be any form of inter-chip interconnect. For example, the connection layer 14 can be a silicon interposer, a redistribution layer, ceramic, organic, or a printed circuit board-like substrate, etc.

[0034] FIG. 13 is a block diagram of another embodiment of the memory system 10 on the SOC 12. In the embodiment of FIG. 2, since the package is directly connected rather than connected through the connection layer 14, the pins connecting the PHY circuit 24 to the PHY circuit 26 do not need to be on one edge. Pins (not shown) on the bottom surface of the SOC 12 can be used to connect the SOC to the rest of the system. As described above, other embodiments can have separate PHY circuits 24 for the cache DRAM 18 and for the main DRAMs 16A - 16D.

[0035] FIG. 14 is a block diagram of a third embodiment of the memory system in which the cache DRAM 18 is implemented in a stack with the SOC 12 and the main DRAMs 16A - 16D are connected to the SOC 12 through the connection layer 14. In this embodiment, the main DRAMs 16A - 16D are stacked on the base die 40, and the base die 40 routes the signals from the TSVs 32 to the PHY circuit 24 and then to the PHY 26 of the SOC 12 through short interconnects (near the edge).

[0036] DRAM 18 and SOC 12 can be connected using various packaging technologies. Either DRAM 18 or SOC 12 may be the "upper" chip (where "upper" is based on the orientation in FIG. 14). Any 3D chip packaging technology can be used. For example, in various embodiments, one or more of TSV connection, COW packaging, WOW packaging, POP packaging, etc. can be used.

[0037] Many variations and modifications will be apparent to those skilled in the art if the above disclosure is well understood. The following "claims" are intended to be construed to cover all such variations and modifications.

Claims

1. 1. A system comprising: at least one first integrated circuit including a first type of dynamic random access memory (DRAM); at least one second integrated circuit including a second type of DRAM, a second memory array in the second type of DRAM being less dense than a first memory array in the first type of DRAM, one or more accesses to the second memory array in the second type of DRAM consuming less energy than accesses to the first memory array in the first type of DRAM, the first memory array including a first number of banks and the second memory array including a second number of banks, the first number being less than the second number; a third integrated circuit including a memory controller configured to control access to a memory including the first type of DRAM and the second type of DRAM.

2. 2. The system of claim 1, wherein the first number of banks support a first amount of bandwidth from the first memory array and the second number of banks support a second amount of bandwidth from the second memory array, the first amount being less than the second amount.

3. 2. The system of claim 1, wherein the second integrated circuit includes the first type of DRAM and the second type of DRAM and comprises a physical layer circuit configured to communicate for the memory.

4. 2. The system of claim 1 further comprising a plurality of said first integrated circuits including a plurality of said first type of DRAMs.

5. The system of claim 4 , wherein the first integrated circuits are connected in a stack by through-silicon via (TSV) interconnects.

6. 6. The system of claim 5, wherein the stack of the plurality of first integrated circuits is connected to the second integrated circuit, and the TSV interconnect is connected to a physical layer circuit of the second integrated circuit.

7. 7. The system of claim 6, wherein the second integrated circuit is coupled to the physical layer circuit, the physical layer circuit including a communication line for the first type of DRAM from the plurality of first integrated circuits to the third integrated circuit, and a communication line for the second type of DRAM from the second integrated circuit to the third integrated circuit.

8. The system of claim 1 , wherein the second integrated circuit and the third integrated circuit are packaged using chip-on-wafer packaging techniques.

9. The system of claim 1 , wherein the second integrated circuit and the third integrated circuit are packaged using wafer-on-wafer packaging techniques.

10. The system of claim 1 , wherein the second integrated circuit and the third integrated circuit are packaged using chip-on-chip packaging techniques.

11. The system of claim 1 , wherein the first integrated circuit is stacked on a package of the second integrated circuit and the third integrated circuit.

12. 12. The system of claim 11, wherein the first integrated circuit is packaged in a package-on-package configuration with the package containing the second integrated circuit and the third integrated circuit.

13. 10. The system of claim 1, wherein the first integrated circuit is disposed on a side of a package that contains the third integrated circuit and the second integrated circuit.

14. 2. The system of claim 1, wherein the first integrated circuit is one of a plurality of first integrated circuits, the plurality of first integrated circuits being disposed on multiple sides of a package that contains the second integrated circuit and the third integrated circuit.

15. 2. The system of claim 1, wherein the memory controller is configured to cache data from a plurality of DRAMs, the first type of DRAM, in at least one second DRAM of the second type of DRAM.

16. 2. The system of claim 1, wherein said second type of DRAM is between 4 and 16 times less dense than said first type of DRAM.

17. 2. The system of claim 1, wherein the third integrated circuit is packaged with the second integrated circuit to reduce a length and coupling capacitance between the third integrated circuit and the second integrated circuit as compared to a coupling between the first integrated circuit and the third integrated circuit.

18. 1. A method comprising:

1. A method in a system comprising at least one first integrated circuit, at least one second integrated circuit, and a third integrated circuit, comprising: controlling accesses to a first memory comprising a first type of dynamic random access memory (DRAM) and a second type of DRAM using a memory controller; the first integrated circuit comprising the first type of DRAM; the second integrated circuit comprising the second type of DRAM; a second memory array in the second type of DRAM having a lower density than a first memory array in the first type of DRAM; one or more accesses to the second memory array in the second type of DRAM consume less energy than accesses to the first memory array in the first type of DRAM; the first memory array comprises a first number of banks; the second memory array comprises a second number of banks; the first number is less than the second number; and the third integrated circuit comprises the memory controller.

19. 20. The method of claim 18, wherein the first number of banks support a first amount of bandwidth from the first memory array and the second number of banks support a second amount of bandwidth from the second memory array, the first amount being less than the second amount.

20. A memory, at least one first integrated circuit including a first type of dynamic random access memory (DRAM); and at least one second integrated circuit including a second type of DRAM, a second memory array in the second type of DRAM being less dense than a first memory array in the first type of DRAM, one or more accesses to the second memory array in the second type of DRAM consuming less energy than accesses to the first memory array in the first type of DRAM, the first memory array including a first number of banks and the second memory array including a second number of banks, the first number being less than the second number.

Images