Semiconductor device and method of manufacturing the same

Abstract

This semiconductor device comprises: a substrate including a first principal surface and having a circuit pattern; a semiconductor chip disposed on the circuit pattern; a frame body which extends in a direction that intersects the first principal surface, and which surrounds the outer periphery of the substrate; and a resin part which is disposed in a space surrounded by the frame body, and which covers the substrate and the semiconductor chip. The resin part includes: a first region positioned on the semiconductor chip and in contact with the semiconductor chip; and a second region which is positioned, with respect to the first region, on the side opposite from the side where the semiconductor chip is positioned, which has the same volume as the first region, and which has a projection surface that is projected in the same shape as the first region when seen in the thickness direction of the substrate. The amount of air bubbles included in the resin part disposed in the first region is less than the amount of air bubbles included in the resin part disposed in the second region.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

[0002] This application claims priority based on Japanese Application No. 2020-138402 filed on August 19, 2020, and incorporates by reference all the descriptions set forth in the Japanese application.

Background Art

[0003] A semiconductor device in which semiconductor elements are mounted on an insulating substrate is known (see, for example, Patent Document 1). The semiconductor device disclosed in Patent Document 1 includes an electrode bonded to an insulating substrate, a semiconductor element mounted on the upper surface of the electrode, a flow control member, and an insulating resin.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

[0005] A semiconductor device according to the present disclosure includes a substrate including a first main surface and having a circuit pattern, a semiconductor chip disposed on the circuit pattern, a frame extending in a direction intersecting the first main surface and surrounding the outer periphery of the substrate, and a resin portion disposed in a space surrounded by the frame and covering the substrate and the semiconductor chip. The resin portion includes a first region that contacts the semiconductor chip and is located on the semiconductor chip, and a second region that is located on the side opposite to the side where the semiconductor chip is located with respect to the first region, has the same volume as the first region, and has a projection surface that is projected in the same shape as the first region when viewed in the thickness direction of the substrate. The amount of bubbles contained in the resin portion disposed in the first region is less than the amount of bubbles contained in the resin portion disposed in the second region.

Brief Description of the Drawings

[0006]

Figure 1

Figure 2

Figure 3

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Figure 8

[0007] [Problems to be Solved by the Present Disclosure] According to Patent Document 1, the flow control member is disposed along the upper surface end of the electrode. The insulating resin is provided so as to cover a part of the flow control member, the side surface of the electrode, and a part of the insulating substrate. However, with such a configuration, processes such as the arrangement of the flow control member and the application of the insulating resin are required, resulting in a decrease in productivity. In addition, since interfaces between members with different linear expansion coefficients increase, such as an interface between the silicone gel encapsulated in the housing as a sealing material and the insulating resin, peeling at the interface is likely to occur. Then, air may enter the peeled portion, and partial discharge starting from the peeled portion may occur. As a result, the breakdown voltage may decrease, leading to possible damage to the semiconductor element. That is, the reliability is reduced.

[0008] Therefore, one of the objectives is to provide a semiconductor device that can improve productivity while enhancing reliability.

[0009] [Effects of the Present Disclosure] According to the above semiconductor device, it is possible to improve productivity while enhancing reliability.

[0010] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. The semiconductor device according to the present disclosure includes a substrate having a first main surface and a circuit pattern, a semiconductor chip disposed on the circuit pattern, a frame body extending in a direction intersecting the first main surface and surrounding the outer periphery of the substrate, and a resin portion disposed in a space surrounded by the frame body and covering the substrate and the semiconductor chip. The resin portion includes a first region that contacts the semiconductor chip and is located on the semiconductor chip, and a second region that is located on the side opposite to the side where the semiconductor chip is located with respect to the first region, has the same volume as the first region, and has a projection surface that is projected in the same shape as the first region when viewed in the thickness direction of the substrate. The amount of bubbles contained in the resin portion disposed in the first region is less than the amount of bubbles contained in the resin portion disposed in the second region.

[0011] According to the semiconductor device of the present disclosure, the amount of bubbles contained in the resin portion disposed in the first region is located on the side opposite to the side where the semiconductor chip is located with respect to the first region, has the same volume as the first region, and is projected in the same shape as the first region when viewed in the thickness direction of the substrate. It is less than the amount of bubbles contained in the resin portion disposed in the second region having a projection surface. By doing so, when a high voltage is applied to the semiconductor chip, it is possible to reduce the risk of partial discharge starting from the portion where bubbles are disposed in the first region disposed on the semiconductor chip. Therefore, a decrease in breakdown voltage can be suppressed. Therefore, the risk of damage to the semiconductor chip can be reduced, and the reliability can be improved. Further, in the second region where the amount of bubbles is larger than in the first region, in the manufacturing process, the resin can be injected without making the viscosity lower than necessary. Therefore, productivity can be improved. The second region is located on the side opposite to the side where the semiconductor chip is located with respect to the first region, and is located farther from the semiconductor chip than the first region. Therefore, the influence on the decrease in breakdown voltage due to the bubbles contained in this region can be reduced. From the above, according to the semiconductor device, while improving the reliability, the productivity can be improved.

[0012] In the semiconductor device, a conductive member connected to the semiconductor chip may be further provided in the first region. The thickness of the first region and the thickness of the second region may be equal to or greater than the height of the conductive member connected to the semiconductor chip and equal to or less than 50% of the total thickness of the resin portion. Since the thickness of the first region and the thickness of the second region are equal to or greater than the height of the conductive member connected to the semiconductor chip, the resin between the conductive member and the semiconductor chip is included in the first region. In particular, since the resin located between the conductive member and the semiconductor chip in the first region, which is the region where partial discharge is likely to occur, is the resin contained in the first region, by making the amount of bubbles contained in the resin in the first region less than the amount of resin in the second region, destruction due to partial discharge as described above is less likely to occur, and while improving the reliability, productivity can be improved. Note that the thickness of the first region and the thickness of the second region may each be equal to or greater than the thickness of the semiconductor chip.

[0013] In the semiconductor device described above, the semiconductor chip may be a wide bandgap semiconductor chip. A wide bandgap semiconductor chip refers to a semiconductor chip having a semiconductor layer made of a material with a larger bandgap than silicon as an operating layer. The wide bandgap semiconductor chip has, for example, a semiconductor layer made of silicon carbide, gallium nitride, or gallium oxide as an operating layer. Such a wide bandgap semiconductor chip has a high breakdown voltage and can achieve further improvement in reliability.

[0014] In the semiconductor device described above, the resin constituting the resin portion may be silicone gel, epoxy resin, or urethane resin. Such a resin has high insulation properties and can achieve further improvement in reliability.

[0015] In the semiconductor device described above, when viewed in the thickness direction of the substrate, the first region may have a projection surface projected in the same shape as the semiconductor chip. By doing so, the occurrence of partial discharge in the region on the semiconductor chip can be further suppressed. Therefore, the improvement in reliability can be achieved more reliably.

[0016] In the semiconductor device described above, the semiconductor chip and the first region may each be rectangular. The center of the projection surface of the semiconductor chip may overlap with the center of the projection surface of the first region. The length of one side of the projection surface of the first region may be equal to or less than twice the length of one side of the projection surface of the semiconductor chip corresponding to one side of the projection surface of the first region. By doing so, the occurrence of partial discharge in the region on the semiconductor chip and the surrounding region can be suppressed. Therefore, the improvement in reliability can be achieved even more reliably.

[0017] The manufacturing method of the semiconductor device of the present disclosure includes a substrate including a first main surface and having a circuit pattern, a semiconductor chip disposed on the circuit pattern, a frame extending in a direction intersecting the first main surface and surrounding the outer periphery of the substrate, and a resin portion disposed in a space surrounded by the frame and covering the substrate and the semiconductor chip. The manufacturing method of the semiconductor device includes a step of disposing the frame so as to surround the substrate, a step of injecting, at a first speed, a resin that constitutes the resin portion into the space surrounded by the frame after the disposing step, and a step of injecting, at a second speed higher than the first speed, the resin that constitutes the resin portion into the space surrounded by the frame after the step of injecting the resin portion at the first speed.

[0018] According to the manufacturing method of the semiconductor device of the present disclosure, for example, by injecting the resin into the space surrounded by the frame over a relatively long time as the first speed, it is possible to suppress the entrapment of air bubbles during injection. Therefore, the amount of air bubbles in the first region that contacts the semiconductor chip and is disposed on the semiconductor chip can be reduced. Next, the resin is injected into a second region that is farther from the semiconductor chip than the first region. Here, for the resin disposed in the second region that is farther from the semiconductor chip than the first region, the resin is injected into the second region at a second speed higher than the first speed. By doing so, the production time can be shortened and the productivity can be improved. At this time, since the injection speed is high, there is a possibility that the amount of air bubbles contained in the resin disposed in the second region is larger than that of the resin disposed in the first region. However, since the resin disposed in the second region functions as a barrier layer for preventing oxidation from the atmosphere or the like, partial discharge starting from the portion of the air bubbles contained in the resin disposed in the second region is less likely to occur. As a result, according to such a manufacturing method of the semiconductor device, it is possible to improve the productivity while improving the reliability. Note that the step of injecting the resin at the first speed and the step of injecting the resin at the second speed may have a constant temperature, for example, the first temperature, or the temperature may be changed during the injection of the resin.

[0019] The manufacturing method of the semiconductor device of the present disclosure includes a substrate including a first main surface and having a circuit pattern, a semiconductor chip disposed on the circuit pattern, a frame extending in a direction intersecting the first main surface and surrounding the outer periphery of the substrate, and a resin portion disposed in a space surrounded by the frame and covering the substrate and the semiconductor chip. The manufacturing method of the semiconductor device includes a step of disposing the frame so as to surround the substrate, a step of injecting, after the disposing step, a resin that forms the resin portion at a first temperature into the space surrounded by the frame, and a step of injecting, after the step of injecting the resin portion at the first temperature, a resin that forms the resin portion at a second temperature lower than the first temperature into the space surrounded by the frame.

[0020] According to the manufacturing method of the semiconductor device of the present disclosure, for example, by injecting a resin having a low viscosity state as the first temperature into the space surrounded by the frame, even if air bubbles are entrained during injection, the air bubbles can easily rise in the resin and reach the surface of the resin. Therefore, the amount of air bubbles in the first region that comes into contact with the semiconductor chip and is disposed on the semiconductor chip can be reduced. Next, a resin having a high viscosity state as a second temperature lower than the first temperature is injected into the space surrounded by the frame. At this time, the resin in the second region is located on the side opposite to the side where the semiconductor chip is located with respect to the first region, has the same volume as the first region, and has a projection surface that is projected in the same shape as the first region when viewed in the thickness direction of the substrate. Since the resin in the first region injected at the first temperature can be cooled, it is possible to suppress the reduction of the pot life of the resin. Here, for the resin disposed in the second region, which is a position farther from the semiconductor chip than the first region, since the viscosity is relatively high, the air entrained during the injection of the resin cannot escape completely, and there is a possibility that the amount of air bubbles contained therein becomes larger than that of the resin disposed in the first region. However, since the resin disposed in the second region functions as a barrier layer for preventing oxidation from the atmosphere or the like, partial discharge starting from the portion of the air bubbles contained in the resin disposed in the second region is less likely to occur. In addition, when injecting the resin at the second temperature, the temperature rise of the resin can be simplified. As a result, according to such a manufacturing method of the semiconductor device, it is possible to improve the productivity while improving the reliability.

[0021] [Details of Embodiments of the Present Disclosure] Next, an embodiment of the semiconductor device of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals and their descriptions will not be repeated.

[0022] (Embodiment 1) The configuration of the semiconductor device in Embodiment 1 of the present disclosure will be described. FIG. 1 is a schematic perspective view of the semiconductor device in Embodiment 1. FIG. 2 is a schematic plan view when the semiconductor device shown in FIG. 1 is viewed in the thickness direction of the heat sink. FIG. 2 is a schematic perspective view of the semiconductor device shown in FIG. 1. FIG. 3 is a schematic cross-sectional view showing a part of the semiconductor device shown in FIG. 1 enlarged. FIG. 3 is a cross-sectional view when cut along a plane parallel to the X-Z plane and including the semiconductor chip. In FIGS. 1 and 2, the illustration of the resin part included in the semiconductor device is omitted. Also, in FIG. 3, the first region 41a to be described later is indicated by a one-dot chain line, and the second region 42a is indicated by a two-dot chain line. For ease of understanding, the illustration of the hatching of the resin part in FIG. 3 is omitted, and a wire to be described later extending in the Y direction is illustrated.

[0023] Referring to FIGS. 1, 2, and 3, the semiconductor device 11a in Embodiment 1 includes a heat sink 12, a frame 13 disposed on the heat sink 12, substrates 17a, 17b disposed on the heat sink 12, plate-shaped electrodes (bus bars) 19a, 19b, 19c, 19d, terminals 18a, 18b, 18c, 18d, semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, 22f, and a resin part 40. The heat sink 12 and the frame 13 constitute a case 20 provided in the semiconductor device 11a.

[0024] The heat sink 12 is made of metal. The heat sink 12 is made of, for example, copper. The surface of the heat sink 12 may be subjected to a plating treatment such as nickel plating. The outer shape of the heat sink 12 is a rectangle with the side extending in the X direction as the long side and the side extending in the Y direction as the short side when viewed in the thickness direction. The substrate 17a is joined onto one main surface 12a of the heat sink 12 by solder (not shown) or the like. On the other main surface 12b of the heat sink 12, for example, heat dissipation fins (not shown) for efficiently dissipating heat may be attached. The thickness direction of the heat sink 12 and the thickness direction of the substrate 17a are the Z direction.

[0025] The substrate 17a includes an insulating plate 14a having insulation properties and a circuit pattern 16a having conductivity. The substrate 17a has a first main surface 31a. The first main surface 31a is the main surface located on the opposite side of the heat sink 12 in the thickness direction of the insulating plate 14a. The circuit pattern 16a is disposed on the insulating plate 14a. The substrate 17a has a configuration in which the circuit pattern 16a is laminated on the insulating plate 14a. The circuit pattern 16a is composed of a plurality of circuit boards. In the present embodiment, the circuit pattern 16a includes a first circuit board 15a, a second circuit board 15b, a third circuit board 15c, and a fourth circuit board 15d. In the present embodiment, the circuit pattern 16a is a copper wiring. Similar to the substrate 17a, the substrate 17b includes an insulating plate 14b having insulation properties and a circuit pattern 16b which is a copper wiring. The substrate 17b has a first main surface 31b. The circuit pattern 16b includes a fifth circuit board 15e, a sixth circuit board 15f, and a seventh circuit board 15g.

[0026] The semiconductor chips 21a, 21b, 21c, 22a, 22b, and 22c are arranged on the first circuit board 15a. The semiconductor chips 21d, 21e, 21f, 22d, 22e, and 22f are arranged on the fifth circuit board 15e. The semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, and 22f are wide-bandgap semiconductor chips. A wide-bandgap semiconductor chip refers to a semiconductor chip having a semiconductor layer made of a material with a larger bandgap than silicon as an operating layer. A wide-bandgap semiconductor chip has, for example, a semiconductor layer made of silicon carbide, gallium nitride, or gallium oxide as an operating layer. Specifically, the semiconductor chips 21a to 21f, 22a to 22f have a semiconductor layer made of silicon carbide as an operating layer. Such wide-bandgap semiconductor chips have a high breakdown voltage and can achieve higher reliability. Also, since wide-bandgap semiconductor chips have high heat resistance, they can be used as semiconductor devices (power modules) that can be used even in an environment exceeding, for example, 175°C. When used in such a high-temperature environment, it is required to use a resin having a high glass transition temperature for the resin constituting the resin part 40 described later. A resin with a high glass transition temperature inevitably has a high curing temperature. If the curing temperature becomes high, the time required until cooling and removal after curing becomes long. Therefore, for semiconductor devices using wide-bandgap semiconductor chips, improvement in productivity such as shortening of production time during manufacturing is particularly required. The semiconductor chips 21a, 21b, 21c, 21d, 21e, and 21f are, for example, Schottky barrier diodes (SBDs). The semiconductor chips 22a, 22b, 22c, 22d, 22e, and 22f are, for example, metal-oxide-semiconductor field-effect transistors (MOSFETs). Note that the semiconductor chips 21a, 21b, 21c, 22a, 22b, and 22c are rectangular when viewed in the thickness direction of the substrates 17a and 17b.

[0027] The frame body 13 extends from one main surface 12a of the heat sink 12 and is attached to the heat sink 12 so as to surround the substrates 17a and 17b when viewed in the thickness direction of the substrates 17a and 17b. In the present embodiment, the frame body 13 is formed so as to rise from one main surface 12a of the heat sink 12. The frame body 13 is fixed to the heat sink 12 by, for example, an adhesive. The frame body 13 is made of, for example, an insulating resin. The frame body 13 includes a first wall portion 13a, a second wall portion 13b, a third wall portion 13c, and a fourth wall portion 13d. The first wall portion 13a and the second wall portion 13b are arranged to face each other in a direction (Y direction) corresponding to the short side of the heat sink 12 when viewed in the thickness direction of the heat sink 12. The third wall portion 13c and the fourth wall portion 13d are arranged to face each other in a direction (X direction) corresponding to the long side of the heat sink 12 when viewed in the thickness direction of the heat sink 12. The inner wall surfaces 27a, 27b, 27c, and 27d of the frame body 13 are rectangular when viewed in the thickness direction of the heat sink 12. Specifically, the frame body 13 includes an inner wall surface 27a, an inner wall surface 27b facing the inner wall surface 27a, an inner wall surface 27c continuous with the inner wall surfaces 27a and 27b, and an inner wall surface 27d continuous with the inner wall surfaces 27a and 27b and facing the inner wall surface 27c. The frame body 13 rises in a direction intersecting the first main surfaces 31a and 31b. Specifically, the inner wall surfaces 27a, 27b, 27c, and 27d rise perpendicular to the first main surfaces 31a and 31b.

[0028] The resin portion 40 is disposed in the space 30 surrounded by the frame body 13. The resin portion 40 covers the substrates 17a and 17b and the semiconductor chips 21a to 21f and 22a to 22f. In the present embodiment, the resin constituting the resin portion 40 is an epoxy resin. Note that, in the present embodiment, the resin constituting the resin portion 40 is of one type.

[0029] The electrodes 19a, 19b, 19c, and 19d are each plate-shaped and made of metal. The electrodes 19a and 19b are attached to the third wall portion 13c. The electrodes 19c and 19d are attached to the fourth wall portion 13d. The electrodes 19a, 19b, 19c, and 19d each have a bent strip shape. In the present embodiment, the electrodes 19a, 19b, 19c, and 19d are each formed, for example, by bending a strip-shaped copper plate. The semiconductor device 11a ensures electrical connection to the outside through the electrodes 19a, 19b, 19c, and 19d. Note that the terminals 18a, 18b, 18c, and 18d are also provided to ensure electrical connection to the outside. The terminals 18a and 18b are attached to the fourth wall portion 13d. The terminals 18c and 18d are attached to the third wall portion 13c.

[0030] The electrode 19a and the first circuit board 15a are connected by a wire 23a. The electrode 19b and the second circuit board 15b are connected by a wire 23b. The electrode 19c and the fifth circuit board 15e are connected by a wire 23c. The electrode 19d and the fifth circuit board 15e are connected by a wire 23d. The semiconductor chip 21a and the semiconductor chip 22a are connected by a wire 24a. The semiconductor chip 21b and the semiconductor chip 22b are connected by a wire 24b. The semiconductor chip 21c and the semiconductor chip 22c are connected by a wire 24c. The semiconductor chip 21d and the semiconductor chip 22d are connected by a wire 24d. The semiconductor chip 21e and the semiconductor chip 22e are connected by a wire 24e. The semiconductor chip 21f and the semiconductor chip 22f are connected by a wire 24f. The semiconductor chip 22a and the fourth circuit board 15d are connected by a wire 25a. The semiconductor chip 22b and the fourth circuit board 15d are connected by a wire 25b. The semiconductor chip 22c and the fourth circuit board 15d are connected by a wire 25c. The semiconductor chip 22d and the sixth circuit board 15f are connected by a wire 25d. The semiconductor chip 22e and the sixth circuit board 15f are connected by a wire 25e. The semiconductor chip 22f and the sixth circuit board 15f are connected by a wire 25f. Each of the wires 24a~24f, 25a~25f as conductive members is connected to each of the semiconductor chips 21a~21f, 22a~22f within the first region 41a described later. Note that each of the wires 24a etc. may be connected by wire bonding. Also, each of the wires 24a etc. may be connected by stitch bonding.

[0031] The second circuit board 15b and the sixth circuit board 15f are connected by a wire 29a. The fourth circuit board 15d and the fifth circuit board 15e are connected by a wire 29b. The terminal 18a and the third circuit board 15c are connected by a wire 26a. The terminal 18b and the fourth circuit board 15d are connected by a wire 26b. The terminal 18c and the sixth circuit board 15f are connected by a wire 26c. The terminal 18d and the seventh circuit board 15g are connected by a wire 26d. Also, the semiconductor chips 22a, 22b, 22c and the third circuit board 15c are each connected by a wire, and the semiconductor chips 22d, 22e, 22f and the seventh circuit board 15g are each connected by a wire. As the wire, a thick aluminum wire may be adopted, or a ribbon wire may be adopted.

[0032] Here, the resin portion 40 includes a first region 41a located on the semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, 22f, and a second region 42a located on the side opposite to the side where the semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, 22f are located with respect to the first region 41a, having the same volume as the first region 41a and having a projection plane that is projected in the same shape as the first region 41a when viewed in the thickness direction of the substrate 17b (see FIG. 3 in particular). Specifically, the first region 41a is disposed on the semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, 22f. In the present embodiment, among the resin portion 40 covering the circuit pattern 16a and the insulating plate 14a, the region on the semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, 22f becomes the first region 41a. That is, when viewed in the thickness direction of the substrates 17a and 17b, the first region 41a has a projection plane that is projected in the same shape as each of the semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, 22f. In the present embodiment, in a state where the substrate 17a is disposed on the lower side in the Z direction, the second region 42a is disposed above the first region 41a. Specifically, the second region 42a is disposed on the first region 41a. In the present embodiment, both the first region 41a and the second region 42a are rectangular parallelepiped-shaped. The first region 41a and the second region 42a have the same volume. The projection planes in the first region 41a and the second region 42a are, for example, the surfaces facing the semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, 22f. When viewed in the thickness direction of the substrates 17a and 17b, the projection plane of the first region 41a and the projection plane of the second region 42a have the same shape. The thickness D1 of the first region 41a and the thickness D2 of the second region 42a are not less than the height D3 of the wires 24a~24f, 25a~25f which are conductive members connected to the semiconductor chips 21a~21f, 22a~22f, and not more than 50% of the entire thickness D3 of the resin portion 40. Note that the thickness direction of the first region 41a and the thickness direction of the second region 42a are each the same as the thickness direction of the substrate 17a.Also, here, the entire thickness Da of the resin portion 40 is the distance from the upper surfaces of the semiconductor chips 21a to 21f and 22a to 22f to the upper surface of the resin. Further, the height D3 is the height from the upper surfaces of the semiconductor chips 21a to 21f and 22a to 22f to the wires 24a to 24f and 25a to 25f which are conductive members. In the present embodiment, the thickness D1 of the first region 41a and the thickness D2 of the second region 42a are each the thickness D of the resin portion 40. a is 50% of the whole. In the present embodiment, the thickness D of the resin portion 40 a is, for example, 12 mm. The thickness D1 of the first region 41a and the thickness D2 of the second region 42a are each, for example, 6 mm. Note that as the height D3 of the wires 24a to 24f and 25a to 25f, for example, 1 to 2 mm is selected. Also, when a copper plate (copper clip) is used as the conductive member, as the height of the conductive member, for example, 0.3 to 1 mm is selected.

[0033] Here, the amount of the air bubbles 43 contained in the resin portion 40 disposed in the first region 41a is less than the amount of the air bubbles 43 contained in the resin portion 40 disposed in the second region 42a. The measurement of the amount of the air bubbles 43 is performed as follows. In this case, it is carried out by ultrasonic flaw detection inspection (SAT (Scanning Acoustic Tomograph) observation). The amount of the air bubbles 43 is defined by the void ratio, that is, the ratio of the void volume per unit volume.

[0034] Next, a method for manufacturing the semiconductor device 11a will be briefly described. FIG. 4 is a flowchart showing typical steps of the method for manufacturing the semiconductor device shown in FIG. 1. Referring to FIG. 4, in the method for manufacturing the semiconductor device 11a in Embodiment 1, first, as a step (S10), a substrate mounting step is performed. In this step (S10), substrates 17a and 17b, on which semiconductor chips 21a to 21f and 22a to 22f are attached to circuit patterns 16a and 16b of insulating plates 14a and 14b, are mounted on the heat sink 12. In this case, the substrates 17a and 17b are joined to the heat sink 12 by solder or the like. Next, as a step (S20), a frame attaching step is performed. In this step (S20), the frame 13 is attached to the heat sink 12 by an adhesive or the like so as to surround the substrates 17a and 17b. Then, as a step (S30) of electrically connecting the respective members, a wire bonding step is performed. In this step (S30), using wire bonding or the like, the electrode 19a and the first circuit board 15a are joined by a wire 23a to electrically connect the electrode 19a and the first circuit board 15a. In addition, the respective members are joined by wires 23b and the like.

[0035] Next, as step (S40), a first resin injection step is performed. Here, an epoxy resin with a curing temperature of 120°C is used. Specifically, for example, a two-component epoxy resin can be used. FIG. 5 is a schematic perspective view showing the injection state of the resin in the first resin injection step. Referring to FIG. 5, uncured epoxy resin is prepared, and using the hole 45 formed in the discharge portion 44, the epoxy resin is injected into the space 30 surrounded by the frame body 13 from the hole 45 at a first speed. At this time, the temperature of the epoxy resin is set to 80°C as the first temperature. Then, the epoxy resin is injected so that the thickness in the final first region 41a becomes 5.5 mm as the thickness D1. At this time, the injected epoxy resin flows horizontally on the substrates 17a and 17b (while spreading along the X-Y plane) and accumulates on the substrates 17a and 17b. Here, by injecting the resin into the space 30 surrounded by the frame body 13 relatively slowly (taking a relatively long time) as the first speed, it is possible to suppress the entrapment of air bubbles 43 during injection. Also, the temperature of the epoxy resin is 80°C, which is a relatively high temperature and has a low viscosity. Therefore, even if air bubbles 43 are entrapped during injection, the air bubbles 43 rise in the resin and easily reach the surface of the resin. Thus, the amount of air bubbles contained in the first region 41a can be reduced.

[0036] Thereafter, as step (S50), a second resin injection step is performed. FIG. 6 is a schematic perspective view showing the injection state of the resin in the second resin injection step. Referring to FIG. 6, in the present embodiment, the same type of epoxy resin as that used in the first resin injection step is used. Then, continuing from the hole 45 at the same first temperature, the epoxy resin is injected into the space 30 surrounded by the frame body 13 at a second speed faster than the first speed. At this time, the injected epoxy resin flows horizontally on the first region 41a and accumulates on the first region 41a. Then, the epoxy resin is injected so that the thickness in the final second region 42a becomes 6 mm as the thickness D2.

[0037] Next, as step (S60), a resin curing step is performed. The resin curing step is performed in two stages. After the completion of the second resin injection step, the temperature is raised and maintained at 90°C, and primary curing, which is the first-stage curing with a curing time of 2 hours, is performed. Then, the temperature is raised and maintained at 150°C, and secondary curing, which is the second-stage curing with a curing time of 3 hours, is performed. By using the epoxy resin and curing it in two stages in this way, the inner layer of the resin portion 40 can be sufficiently cured. After the curing is completed, the semiconductor device 11a in Embodiment 1 is obtained.

[0038] According to such a semiconductor device 11a, the amount of air bubbles 43 contained in the resin part 40 disposed in the first regions 41a and 41b is located on the side opposite to the side where the semiconductor chips 21a to 21f and 22a to 22f are positioned with respect to the first region 41a, has the same volume as the first region 41a, and is disposed in the resin part 40 disposed in the second region 42a having a projection surface projected in the same shape as the first region 41a when viewed in the thickness direction of the substrates 17a and 17b. Then, when a high voltage is applied to the semiconductor chips 21a to 21f and 22a to 22f, it is possible to reduce the risk of causing partial discharge starting from the portion where the air bubbles 43 are disposed in the first region 41a disposed on the semiconductor chips 21a to 21f and 22a to 22f. Therefore, a decrease in the breakdown voltage can be suppressed. Accordingly, the risk of damage to the semiconductor chips 21a to 21f and 22a to 22f can be reduced, and the reliability can be improved. Also, in the second region 42a where the amount of air bubbles 43 is larger than that in the first region 41a, in the manufacturing process, the resin can be injected without making the viscosity lower than necessary. Therefore, the productivity can be improved. The second region 42a is located on the side opposite to the side where the semiconductor chips 21a to 21f and 22a to 22f are positioned with respect to the first region 41a, and is located farther from the semiconductor chips than the first region 41a. Therefore, the influence on the decrease in the breakdown voltage due to the air bubbles 43 contained in this region can be reduced. From the above, according to the semiconductor device 11a, while improving the reliability, the productivity can be improved. In the above embodiment, the temperature of the resin in the step of injecting the resin at the first speed and the step of injecting the resin at the second speed is the same, but it is not limited to this, and different temperatures are also possible.

[0039] In the semiconductor device 11a, when viewed in the thickness direction of the substrate 17b, the first region 41a has a projection plane projected in the same shape as the semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, 22f. By doing so, it is possible to further suppress the occurrence of partial discharge in the regions on the semiconductor chips 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, 22f. Therefore, such a semiconductor device 11a is a semiconductor device that can more reliably improve reliability.

[0040] In this embodiment, the resin constituting the resin portion 40 is only one type. Therefore, no interface where different resins come into contact occurs. Therefore, peeling starting from this portion does not occur, and reliability can be further improved.

[0041] In the semiconductor device 11a, the semiconductor chips 21a to 21f, 22a to 22f are wide-bandgap semiconductor chips having a semiconductor layer made of silicon carbide as an operating layer. Such semiconductor chips 21a to 21f, 22a to 22f have a high breakdown voltage and can further improve reliability. Also, even if a resin with a high glass transition point is used, the overall resin injection speed can be increased. Therefore, the production time can be shortened and productivity can be improved.

[0042] In this embodiment, the thickness D1 of the first region 41a and the thickness D2 of the second region 42a are not less than the height D3 of the wires 24a to 24f, 25a to 25f connected to the semiconductor chips 21a to 21f, 22a to 22f and the thickness D of the resin portion 40 aIt is 50% or less of the whole. The thickness D1 of the first region 41a and the thickness D2 of the second region 42a are not less than the height D3 of the wires 24a to 24f, 25a to 25f which are conductive members connected to the semiconductor chips 21a to 21f, 22a to 22f. Therefore, the first region 41a contains the resin between the wires 24a to 24f, 25a to 25f which are conductive members and the semiconductor chips 21a to 21f, 22a to 22f. Particularly, partial discharge is likely to occur in the resin located between the wires 24a to 24f, 25a to 25f which are in the first region 41a and the semiconductor chips 21a to 21f, 22a to 22f. Therefore, by making the amount of bubbles contained in the resin in the first region 41a less than the amount of resin in the second region 42a, destruction due to the above partial discharge is less likely to occur, and while improving reliability, productivity can be improved. Incidentally, if the thickness D2 of the second region 42a is increased, for example, by making the thickness D2 of the second region 42a thicker than the thickness D1 of the first region 41a, the overall resin injection speed can be increased. Therefore, the production time can be shortened, and productivity can be further improved.

[0043] Also, according to the manufacturing method of such a semiconductor device 11a, for example, by injecting resin into the space 30 surrounded by the frame 13 over a relatively long time as the first speed, it is possible to suppress the entrapment of air bubbles 43 during injection. Therefore, the amount of air bubbles 43 in the first region 41a that comes into contact with the semiconductor chips 21a to 21f, 22a to 22f and is disposed on the semiconductor chips 21a to 21f, 22a to 22f can be reduced. Next, resin is injected into the second region 42a, which is a position farther from the semiconductor chips 21a to 21f, 22a to 22f than the first region 41a. Here, with respect to the resin disposed in the second region 42a, which is a position farther from the semiconductor chips 21a to 21f, 22a to 22f than the first region 41a, the resin is injected into the second region 42a at a second speed that is faster than the first speed. By doing so, the production time can be shortened and productivity can be improved. At this time, since the injection speed is fast, there is a possibility that the amount of air bubbles 43 contained in the resin disposed in the second region 42a becomes larger than that of the resin disposed in the first region 41a. However, since the resin disposed in the second region 42a functions as a barrier layer to prevent oxidation from the atmosphere or the like, partial discharge starting from the portion of the air bubbles 43 contained in the resin disposed in the second region 42a is less likely to occur. As a result, according to the manufacturing method of such a semiconductor device 11a, it is possible to improve productivity while improving reliability.

[0044] Regarding the manufacturing method of the semiconductor device 11a, it may also be as follows. That is, the manufacturing method of the semiconductor device 11a includes substrates 17a, 17b including first main surfaces 31a, 31b and having circuit patterns 16a, 16b, semiconductor chips 21a to 21f, 22a to 22f disposed on the circuit patterns 16a, 16b, a frame body 13 extending in a direction intersecting the first main surfaces 31a, 31b and surrounding the outer periphery of the substrates 17a, 17b, and a resin portion 40 disposed in a space 30 surrounded by the frame body 13 and covering the substrates 17a, 17b and the semiconductor chips 21a to 21f, 22a to 22f. The manufacturing method of the semiconductor device 11a includes a step of disposing the frame body 13 so as to surround the substrates 17a, 17b, a step of injecting a resin that constitutes the resin portion 40 at a first temperature into the space 30 surrounded by the frame body 13 after the disposing step, and a step of injecting a resin that constitutes the resin portion 40 at a second temperature lower than the first temperature into the space 30 surrounded by the frame body 13 after the step of injecting the resin at the first temperature. Specifically, for example, in the first resin injection step, the temperature of the resin is set to 80°C, and in the second resin injection step, the temperature of the resin is set to 50°C. Also, the injection rate of the resin in the first resin injection step is made the same as the injection rate of the resin in the second resin injection step.

[0045] According to the manufacturing method of such a semiconductor device 11a, for example, by injecting a resin in a state with low viscosity as the first temperature into the space 30 surrounded by the frame 13, even if air bubbles 43 are entrained during injection, the air bubbles 43 can easily rise in the resin and reach the surface of the resin. Therefore, the amount of air bubbles 43 in the first region 41a that comes into contact with the semiconductor chips 21a to 21f, 22a to 22f and is disposed on the semiconductor chips 21a to 21f, 22a to 22f can be reduced. Next, a resin in a state with high viscosity as the second temperature lower than the first temperature is injected into the space 30 surrounded by the frame 13. At this time, the resin in the second region 42a is located on the side opposite to the side where the semiconductor chips 21a to 21f, 22a to 22f are located with respect to the first region 41a, has the same volume as the first region 41a, and has a projection surface that is projected in the same shape as the first region 41a when viewed in the thickness direction of the substrate 17a. Since the resin in the first region 41a injected at the first temperature can be cooled by the resin in the second region 42a, it is possible to suppress the reduction of the pot life of the resin. Here, for the resin disposed in the second region 42a, which is a position farther from the semiconductor chips 21a to 21f, 22a to 22f than the first region 41a, since the viscosity is relatively high, the air entrained during the injection of the resin cannot escape completely, and there is a possibility that the amount of air bubbles 43 contained therein becomes larger than that of the resin disposed in the first region 41a. However, since the resin disposed in the second region 42a functions as a barrier layer for preventing oxidation from the atmosphere or the like, partial discharge starting from the portion of the air bubbles 43 contained in the resin disposed in the second region 42a is less likely to occur. Also, when injecting the resin at the second temperature, the temperature rise of the resin can be simplified. As a result, according to the manufacturing method of such a semiconductor device 11a, it is possible to improve productivity while improving reliability.

[0046] Regarding the manufacturing method of the semiconductor device 11a, in the first resin injection step and the second resin injection step, the temperature and the speed may be changed respectively to inject the resin. That is, the manufacturing method of the semiconductor device 11a includes a step of arranging the frame 13 so as to surround the substrates 17a and 17b, and after the arranging step, a step of injecting the resin constituting the resin portion 40 at the first temperature into the space 30 surrounded by the frame 13 at the first speed, and after the step of injecting the resin at the first temperature and the first speed, a step of injecting the resin constituting the resin portion 40 at the second temperature lower than the first temperature into the space 30 surrounded by the frame 13 at the second speed faster than the first speed. Also by such a manufacturing method of the semiconductor device 11a, it is possible to improve the productivity while improving the reliability.

[0047] (Embodiment 2) Next, Embodiment 2 which is another embodiment will be described. FIG. 7 is a schematic perspective view showing an enlarged view of a region including the semiconductor chip 21f in the semiconductor device 11b in Embodiment 2. In FIG. 7, the first region 41b is indicated by a dashed line, and the second region 42b is indicated by a two-dot chain line. FIG. 8 is a schematic plan view of the semiconductor chip 21f and the first region 41b viewed in the thickness direction of the substrate 17b. In FIG. 7, for ease of understanding, the illustration of the wire 24f connecting the semiconductor chip 21f and the semiconductor chip 22f and the wire 24e connecting the semiconductor chip 21e and the semiconductor chip 22e is omitted. The semiconductor device of Embodiment 2 is different from that of Embodiment 1 in that the shapes of the first region and the second region are different.

[0048] Referring to FIGS. 7 and 8, in the semiconductor device 11b of the second embodiment, the semiconductor chip 21f is rectangular when viewed in the thickness direction of the substrate 17b. The first region 41b that contacts the semiconductor chip 21f and is disposed on the semiconductor chip 21f is rectangular when viewed in the thickness direction of the substrate 17b. Note that the second region 42b disposed on the first region 41b is also rectangular when viewed in the thickness direction of the substrate 17b. When viewed in the thickness direction of the substrate 17b, the center O of the semiconductor chip 21f and the center O of the first region 41b overlap. The length of one side of the projection plane of the first region 41b is equal to or less than twice the length of one side of the projection plane of the semiconductor chip 21f corresponding to one side of the projection plane of the first region 41b. Specifically, the length of one side of the projection plane of the first region 41b is twice the length of one side of the projection plane of the semiconductor chip 21f corresponding to one side of the projection plane of the first region 41b. That is, assuming that the length of one side of the projection plane, which is the length of the semiconductor chip 21f in the X direction, is L1, and the length of one side of the projection plane, which is the length of the first region 41b in the X direction, is S1, then S1 = 2 × L1. Also, assuming that the length of one side of the projection plane, which is the length of the semiconductor chip 21f in the Y direction, is L2, and the length of one side of the projection plane, which is the length of the first region 41b in the Y direction, is S2, then S2 = 2 × L2. Note that when the semiconductor chip 21f has a square shape when viewed in the thickness direction of the substrate 17b, L1 = L2.

[0049] In such a semiconductor device 11b, it is possible to suppress the occurrence of partial discharge in the regions on the semiconductor chips 21a to 21f, 22a to 22f and the peripheral regions thereof. Therefore, the semiconductor device 11b is a semiconductor device that can further surely improve reliability.

[0050] Note that in the above embodiment, the length of one side of the projection plane of the first region 41b may be equal to or less than twice the length of one side of the projection plane of the semiconductor chip 21f corresponding to one side of the projection plane of the first region 41b. That is, the first region 41b, and further the second region 42b may be configured to have a relationship of S1 ≦ 2 × L1. Also, the first region 41b, and further the second region 42b may be configured to have a relationship of S2 ≦ 2 × L2.

[0051] (Other Embodiments) In the above embodiment, an epoxy resin was used as the resin constituting the resin portion 40. However, the present invention is not limited to this, and a silicone gel or a urethane resin may be used as the resin constituting the resin portion 40. That is, the resin constituting the resin portion 40 may be a silicone gel, an epoxy resin, or a urethane resin. Such a resin has high insulation properties and can improve reliability.

[0052] In the above embodiment, the second region is located on the side opposite to the side where the semiconductor chip is located with respect to the first region, and the second region and the first region are in contact with each other. However, the present invention is not limited to this, and the second region and the first region may not be in contact with each other. The second region may be located on the side opposite to the side where the semiconductor chip is located with respect to the first region and may be spaced apart from the first region.

[0053] It should be understood that the embodiments disclosed this time are illustrative in all respects and not restrictive in any way. The scope of the present disclosure is defined by the claims rather than the above description, and it is intended that all modifications within the meaning and scope equivalent to the claims be included.

Explanation of Reference Numerals

[0054] 11a, 11b semiconductor devices, 12 heat sink, 12a, 12b main surfaces, 13 frame, 13a, 13b, 13c, 13d wall portions, 14a, 14b insulating plates, 15a, 15b, 15c, 15d, 15e, 15f, 15g circuit boards, 16a, 16b circuit patterns, 17a, 17b substrates, 18a, 18b, 18c, 18d terminals, 19a, 19b, 19c, 19d terminals, 20 case, 21a, 21b, 21c, 21d, 21e, 21f, 22a, 22b, 22c, 22d, 22e, 22f semiconductor chips, 23a, 23b, 23c, 23d, 24a, 24b, 24c, 24d, 24e, 24f, 25a, 25b, 25c, 25d, 25e, 25f, 26a, 26b, 26c, 26d, 29a, 29b wires, 27a, 27b, 27c, 27d inner wall surfaces, 30 space, 31a, 31b first main surfaces, 40 resin portion, 41a, 41b first regions, 42a, 42b second regions, 43 bubbles, 44 discharge portion, 45 holes, D1, D2, D a Thickness, D3 Height, L1, L2, S1, S2 Lengths, O Center

Claims

1. A substrate including a first main surface and having a circuit pattern, A semiconductor chip disposed on the circuit pattern, A frame extending in a direction intersecting the first main surface and surrounding the outer periphery of the substrate, A resin portion disposed in a space surrounded by the frame and covering the substrate and the semiconductor chip, and comprising: The resin portion is A first region in contact with the semiconductor chip and located on the semiconductor chip; A second region located on the side opposite to the side where the semiconductor chip is located with respect to the first region, having the same volume as the first region, and having a projection surface that is projected in the same shape as the first region when viewed in the thickness direction of the substrate; and The amount of bubbles contained in the resin portion disposed in the first region is less than the amount of bubbles contained in the resin portion disposed in the second region, The semiconductor device further includes a conductive member connected to the semiconductor chip in the first region, The thickness of the first region and the thickness of the second region are each not less than the height of the conductive member and not more than 50% of the total thickness of the resin portion.

2. The semiconductor device according to claim 1, wherein the semiconductor chip is a wide bandgap semiconductor.

3. The resin constituting the resin portion is a silicone gel, an epoxy resin, or a urethane resin. The semiconductor device according to claim 1 or claim 2.

4. When viewed in the thickness direction of the substrate, The semiconductor device according to any one of claims 1 to 3, wherein the first region has a projection surface that is projected in the same shape as the semiconductor chip.

5. When viewed in the thickness direction of the substrate, The semiconductor chip and the first region are each rectangular, The center of the projection surface of the semiconductor chip overlaps with the center of the projection surface of the first region, The semiconductor device according to any one of claims 1 to 3, wherein the length of one side of the projection surface of the first region is not more than twice the length of one side of the projection surface of the semiconductor chip corresponding to one side of the projection surface of the first region.

6. A method of manufacturing a semiconductor device, comprising a substrate including a first main surface and having a circuit pattern, A semiconductor chip disposed on the circuit pattern, A frame extending in a direction intersecting the first main surface and surrounding the outer periphery of the substrate, A resin portion disposed in a space surrounded by the frame and covering the substrate and the semiconductor chip, the method comprising: A step of disposing the frame so as to surround the substrate, After the step of arranging, a step of injecting a resin that forms the resin portion into the space surrounded by the frame at a first rate; After the step of injecting the resin at the first rate, a step of injecting a resin that forms the resin portion into the space surrounded by the frame at a second rate higher than the first rate, the method for manufacturing a semiconductor device including these steps.

7. A substrate including a first main surface and having a circuit pattern; A semiconductor chip disposed on the circuit pattern; A frame extending in a direction intersecting the first main surface and surrounding the outer periphery of the substrate; A resin portion disposed in the space surrounded by the frame and covering the substrate and the semiconductor chip, the method for manufacturing a semiconductor device including: A step of arranging the frame so as to surround the substrate; After the step of arranging, a step of injecting a resin that forms the resin portion at a first temperature into the space surrounded by the frame; After the step of injecting the resin at the first temperature, a step of injecting a resin that forms the resin portion at a second temperature lower than the first temperature into the space surrounded by the frame, the method for manufacturing a semiconductor device including these steps.

8. A substrate including a first main surface and having a circuit pattern; A semiconductor chip disposed on the circuit pattern; A frame extending in a direction intersecting the first main surface and surrounding the outer periphery of the substrate; A resin portion disposed in the space surrounded by the frame and covering the substrate and the semiconductor chip, wherein the resin portion includes a first region that contacts the semiconductor chip and is located on the semiconductor chip; a second region that is located on the side opposite to the side where the semiconductor chip is located with respect to the first region, has the same volume as the first region, and has a projection surface that is projected in the same shape as the first region when viewed in the thickness direction of the substrate; the amount of air bubbles included in the resin portion disposed in the first region is less than the amount of air bubbles included in the resin portion disposed in the second region; when viewed in the thickness direction of the substrate, the first region has a projection surface that is projected in the same shape as the semiconductor chip, a semiconductor device.

9. A substrate including a first main surface and having a circuit pattern; A semiconductor chip disposed on the circuit pattern; A frame extending in a direction intersecting the first main surface and surrounding the outer periphery of the substrate; A resin portion disposed in the space surrounded by the frame and covering the substrate and the semiconductor chip, wherein the resin portion A first region that contacts the semiconductor chip and is located on the semiconductor chip; A second region that is located on the side opposite to the side where the semiconductor chip is located with respect to the first region, has the same volume as the first region, and has a projection surface that is projected in the same shape as the first region when viewed in the thickness direction of the substrate; and The amount of air bubbles contained in the resin portion disposed in the first region is less than the amount of air bubbles contained in the resin portion disposed in the second region; When viewed in the thickness direction of the substrate, The semiconductor chip and the first region are each rectangular; The center of the projection surface of the semiconductor chip overlaps with the center of the projection surface of the first region; A semiconductor device, wherein the length of one side of the projection surface of the first region is not more than twice the length of one side of the projection surface of the semiconductor chip corresponding to one side of the projection surface of the first region.

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