Semiconductor device

Abstract

This semiconductor device comprises: a substrate; a circuit pattern including a first circuit board, a second circuit board, a third circuit board and a fourth circuit board which are positioned apart from one another; a plate-shaped first electrode connected to the first circuit board; a plate-shaped second electrode connected to the second circuit board and the third circuit board; a plate-shaped third electrode connected to the fourth circuit board; a first semiconductor chip; a second semiconductor chip; a first electroconductive member; and a second electroconductive member. The second electrode includes a first portion, which is arranged parallel to the third electrode with a gap therebetween, and / or a second portion, which is arranged parallel to the first electrode with a gap therebetween.

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device.

[0002] This application claims priority based on Japanese Application No. 2021-8835 filed on January 22, 2021, and incorporates by reference all the descriptions set forth in the above-mentioned Japanese application.

Background Art

[0003] A semiconductor device in which semiconductor elements are arranged on a substrate is known (see, for example, Patent Document 1). The semiconductor device disclosed in Patent Document 1 is a power semiconductor module and includes a positive power supply terminal, a negative power supply terminal, and an output terminal.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

[0005] A semiconductor device according to the present disclosure includes a substrate including a first main surface, a first circuit board, a second circuit board, a third circuit board, and a fourth circuit board that are separately located, a circuit pattern disposed on the first main surface, a plate-shaped first electrode disposed on the circuit pattern and connected to the first circuit board, a plate-shaped second electrode disposed on the circuit pattern and connected to the second circuit board and the third circuit board, a plate-shaped third electrode disposed on the circuit pattern and connected to the fourth circuit board, a first semiconductor chip disposed on the first circuit board, a second semiconductor chip disposed on the third circuit board, a first conductive member that electrically connects the first semiconductor chip and the second circuit board, and a second conductive member that electrically connects the second semiconductor chip and the fourth circuit board. The second electrode includes at least one of a first portion disposed in parallel with a space from the third electrode or a second portion disposed in parallel with a space from the first electrode.

Brief Description of the Drawings

[0006]

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Embodiments for Carrying Out the Invention

[0007] [Problems to be Solved by the Present Disclosure] In a semiconductor device such as a power semiconductor module disclosed in Patent Document 1, from the viewpoint of suppressing surge voltage, it is required to reduce inductance.

[0008] Therefore, one of the objects is to provide a semiconductor device capable of reducing inductance.

[0009] [Effects of the Present Disclosure] According to the above semiconductor device, inductance can be reduced.

[0010] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described. The semiconductor device according to the present disclosure includes a substrate including a first main surface, a first circuit board, a second circuit board, a third circuit board, and a fourth circuit board that are separately located, a circuit pattern disposed on the first main surface, a plate-shaped first electrode disposed on the circuit pattern and connected to the first circuit board, a plate-shaped second electrode disposed on the circuit pattern and connected to the second circuit board and the third circuit board, a plate-shaped third electrode disposed on the circuit pattern and connected to the fourth circuit board, a first semiconductor chip disposed on the first circuit board, a second semiconductor chip disposed on the third circuit board, a first conductive member that electrically connects the first semiconductor chip and the second circuit board, and a second conductive member that electrically connects the second semiconductor chip and the fourth circuit board. The second electrode includes at least one of a first portion disposed in parallel with a space from the third electrode or a second portion disposed in parallel with a space from the first electrode.

[0011] In the semiconductor device, a capacitor such as a smoothing capacitor may be connected in parallel with the first semiconductor chip and the second semiconductor chip. At this time, a closed circuit is formed between the first semiconductor chip and the second semiconductor chip and the capacitor. In the semiconductor device, the path of this closed circuit is a path from the first electrode to the first circuit board, the first semiconductor chip, the first conductive member, the second circuit board, the second electrode, the third circuit board, the second semiconductor chip, the second conductive member, the fourth circuit board, and then to the third electrode. In this closed circuit, a high di / dt occurs when the first semiconductor chip and the second semiconductor chip are switched. In the surge voltage derived from the value obtained by multiplying di / dt and L (inductance), when the inductance is large, a high surge voltage occurs when a high di / dt occurs and is applied to the first semiconductor chip and the second semiconductor chip. Such a state may cause damage to the first semiconductor chip and the second semiconductor chip. Therefore, suppression of the surge voltage is required. If the inductance can be reduced in the current path from the first electrode to the third electrode, the surge voltage can be suppressed.

[0012] In the semiconductor device shown in Patent Document 1, since the members corresponding to the second circuit board and the members corresponding to the third circuit board are composed only of circuit patterns and wire wirings, the inductance becomes large. In the semiconductor device of the present disclosure, the second circuit board and the third circuit board are connected to the plate-shaped second electrode. Here, the second electrode includes at least one of a first portion arranged in parallel with a space from the third electrode or a second portion arranged in parallel with a space from the first electrode. Therefore, in this portion arranged in parallel, by making the direction of the current flowing through at least one of the first electrode or the third electrode opposite to the direction of the current flowing through the second electrode, the magnetic flux generated when the current flows through the electrode is canceled, and the inductance of the current path is subtracted by the mutual inductance. Therefore, compared with the semiconductor device described in Patent Document 1, the inductance can be reduced. Further, since the cross-sectional area is increased by the electrode, a reduction in wiring resistance can be achieved compared with wirings such as circuit patterns and wires. Here, for parallel, it does not have a geometrically exact parallel relationship. For example, the other may be inclined within a range of about several degrees, specifically within 30 degrees, with respect to one side.

[0013] In the above semiconductor device, the first electrode may include a third portion arranged in parallel with a space from the third electrode. By doing so, in the portion arranged in parallel, by making the direction of the current flowing through the first electrode opposite to the direction of the current flowing through the third electrode, the magnetic flux generated when the current flows through the first electrode and the third electrode is canceled, and the inductance of the path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device can be further reduced.

[0014] In the semiconductor device described above, the third electrode may include a first flat plate portion and a second flat plate portion that are arranged in parallel with a gap therebetween. The second electrode may include a third flat plate portion that is between the first flat plate portion and the second flat plate portion and is arranged with a gap from each of the first flat plate portion and the second flat plate portion. By doing so, between each of the third flat plate portion arranged in parallel and the first flat plate portion and the second flat plate portion, by making the direction of the current flowing through the third electrode opposite to the direction of the current flowing through the second electrode, the magnetic flux generated when current flows through the third electrode and the second electrode is canceled out, and the inductance of the path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device can be further reduced.

[0015] In the semiconductor device described above, the first flat plate portion, the second flat plate portion, and the third flat plate portion may be perpendicular to the first main surface. There may be a case where a sealing material is filled to insulate the space on the base plate and seal the first semiconductor chip, the second semiconductor chip, the first conductive member, and the second conductive member. By making the first flat plate portion, the second flat plate portion, and the third flat plate portion perpendicular to the first main surface, it is possible to avoid bubbles being caught in the sealing material and accumulating in the lower regions of the first flat plate portion, the second flat plate portion, and the third flat plate portion when filling the sealing material. Therefore, it is possible to avoid the risk of bubbles accumulating in the sealing material and suppress a decrease in insulation performance, thereby improving the reliability of the semiconductor device. Here, regarding perpendicularity, it does not have a geometrically strict perpendicular relationship. For example, one may be inclined with respect to the other by about several degrees with respect to 90 degrees, specifically within a range of 30 degrees.

[0016] In the above semiconductor device, the first electrode may include a fourth flat plate portion and a fifth flat plate portion that are arranged in parallel with a gap therebetween. The second electrode may include a sixth flat plate portion that is between the first flat plate portion and the second flat plate portion and is arranged with a gap from each of the first flat plate portion and the second flat plate portion. By doing so, between the sixth portion arranged in parallel and each of the fourth flat plate portion and the fifth flat plate portion, by making the direction of the current flowing through the first electrode and the direction of the current flowing through the second electrode opposite to each other, the magnetic flux generated when the current flows through the first electrode and the second electrode is canceled out, and the inductance of the path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device can be further reduced.

[0017] In the above semiconductor device, the fourth flat plate portion, the fifth flat plate portion, and the sixth flat plate portion may be perpendicular to the first main surface. By making the fourth flat plate portion, the fifth flat plate portion, and the sixth flat plate portion perpendicular to the first main surface, it is possible to avoid air bubbles being caught in the sealing material and accumulating in the lower regions of the fourth flat plate portion, the fifth flat plate portion, and the sixth flat plate portion when filling the sealing material. Therefore, it is possible to avoid the risk of air bubbles accumulating in the sealing material and suppress a decrease in insulation performance, and improve the reliability of the semiconductor device.

[0018] In the above semiconductor device, the first electrode may include a seventh flat plate portion. The third electrode may include an eighth flat plate portion arranged in parallel with the seventh flat plate portion. By doing so, between the seventh flat plate portion and the eighth flat plate portion arranged in parallel, by making the direction of the current flowing through the first electrode and the direction of the current flowing through the third electrode opposite to each other, the magnetic flux generated when the current flows through the first electrode and the third electrode is canceled out, and the inductance of the path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device can be further reduced.

[0019] In the semiconductor device described above, the seventh flat plate portion and the eighth flat plate portion may be perpendicular to the first main surface. By making the seventh flat plate portion and the eighth flat plate portion perpendicular to the first main surface, when encapsulating the encapsulant, it is possible to avoid voids that are bitten in during the encapsulation of the encapsulant from accumulating in the lower regions of the seventh flat plate portion and the eighth flat plate portion. Therefore, it is possible to avoid the risk of voids accumulating in the encapsulant and suppress a decrease in insulation performance, thereby improving the reliability of the semiconductor device.

[0020] In the semiconductor device described above, at least any one of the first circuit board, the second circuit board, the third circuit board, and the fourth circuit board may be divided into a plurality of circuit boards that are electrically connected. By doing so, the degree of freedom in designing the shape of the circuit pattern can be increased. Note that depending on the current flowing through the semiconductor device, there may be a plurality of first semiconductor chips and second semiconductor chips, respectively.

[0021] [Details of Embodiments of the Present Disclosure] Next, an embodiment of the semiconductor device of the present disclosure will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals and their descriptions will not be repeated.

[0022] (Embodiment 1) The configuration of the semiconductor device in Embodiment 1 of the present disclosure will be described. FIG. 1 is a schematic perspective view of the semiconductor device in Embodiment 1. FIG. 2 is a schematic cross-sectional view when the semiconductor device shown in FIG. 1 is cut along II-II in FIG. 1. FIG. 3 is a schematic cross-sectional view when the semiconductor device shown in FIG. 1 is cut along III-III in FIG. 1. FIG. 4 is a schematic perspective view of the semiconductor device shown in FIG. 1 with the illustration of the lid portion described later omitted. For ease of understanding, the nut described later is illustrated in FIG. 4. FIG. 5 is a schematic perspective view of the semiconductor device shown in FIG. 1 with the illustrations of the lid portion, the sealing material, and the frame body described later omitted. FIG. 6 is a schematic side view of the semiconductor device shown in FIG. 5. FIG. 7 is a schematic cross-sectional view when the semiconductor device shown in FIG. 6 is cut along VII-VII in FIG. 6. FIG. 7 is a view seen in the thickness direction of the substrate described later. Note that FIG. 7 illustrates the case where the cross-section is taken in a region where the sealing material described later is not located. FIG. 8 is a schematic cross-sectional view of the semiconductor device shown in FIG. 7 with the illustrations of the first electrode, the second electrode, and the third electrode described later omitted. Note that FIG. 2 corresponds to the cross-section when cut along the plane including the dashed line in FIG. 7. Also, FIG. 3 corresponds to the cross-section when cut along the plane including the two-dot chain line in FIG. 7. FIG. 9 is a schematic cross-sectional view of the semiconductor device shown in FIG. 7 with only the first electrode, the second electrode, and the third electrode illustrated. FIG. 10 is a diagram schematically showing a part of the circuit diagram of the semiconductor device shown in FIG. 1. Note that in FIG. 10, for ease of understanding, a capacitor having a configuration not included in the semiconductor device of the present disclosure, which is connected in parallel with the first semiconductor chip and the second semiconductor chip described later, is also illustrated. FIG. 11 is a schematic perspective view of the frame body included in the semiconductor device shown in FIG. 1. FIG. 12 is a schematic cross-sectional view schematically showing a part of the semiconductor device shown in FIG. 1. FIG. 13 is a schematic cross-sectional view schematically showing a part of the semiconductor device shown in FIG. 1. FIG. 12 shows the case when cut in the X-Y plane, and FIG. 13 shows the case when cut in the X-Z plane.

[0023] Referring to FIGS. 1 to 13, the semiconductor device 10a in Embodiment 1 includes a plate-shaped base plate 11a as a base portion, a substrate 12a, a circuit pattern 13a, a frame 14a, a sealing material 15a, a lid portion 16a, a first electrode 17a, a second electrode 18a, a third electrode 19a, first semiconductor chips 21a, 21b, 21c, 21d, second semiconductor chips 22a, 22b, 22c, 22d, third semiconductor chips 23a, 23b, 23c, 23d, fourth semiconductor chips 24a, 24b, 24c, 24d, fifth semiconductor chips 21e, 21f, sixth semiconductor chips 22e, 22f, seventh semiconductor chips 23e, 23f, eighth semiconductor chips 24e, 24f, a first control terminal 25a, a second control terminal 25b, a third control terminal 25c, a fourth control terminal 25d, first conductive members 26a, 26b, 26c, 26d, second conductive members 27a, 27b, 27c, 27d, third conductive members 26e, 26f, fourth conductive members 27e, 27f, and wires 28a, 28b, 28c, 28d, 28e.

[0024] In the present embodiment, the base plate 11a has a rectangular shape in which the length in the X direction is longer than the length in the Y direction when viewed in the thickness direction (Z direction). The base plate 11a is made of, for example, metal. The base plate 11a includes a first main surface 11b located on one side in the thickness direction and a second main surface 11c located on the other side in the thickness direction. Through holes 11d, 11e, 11f, 11g penetrating in the thickness direction are formed in portions near the four corners of the base plate 11a. The through holes 11d, 11e, 11f, 11g are effectively used together with through holes 14h, 14i, 14j, 14k described later when attaching the semiconductor device 10a to a predetermined installation location.

[0025] On the first main surface 11b, a substrate 12a is disposed. In the present embodiment, the substrate 12a has a rectangular shape in which the length in the X direction is longer than the length in the Y direction when viewed in the thickness direction (Z direction). The substrate 12a has insulating properties. The substrate 12a is made of, for example, ceramic. The substrate 12a includes a first main surface 12b located on one side in the thickness direction and a second main surface 12c located on the other side in the thickness direction. The second main surface 12c of the substrate 12a is joined to the first main surface 11b of the base plate 11a by a joining material.

[0026] On the first main surface 12b of the substrate 12a, a circuit pattern 13a is disposed. The circuit pattern 13a is a conductive member, specifically, for example, composed of a copper plate. The circuit pattern 13a includes a first circuit board 13b, a second circuit board 13c, a third circuit board 13d, and a fourth circuit board 13e that are respectively spaced apart. The circuit pattern 13a further includes a fifth circuit board 13f, a sixth circuit board 13g, a seventh circuit board 13h, an eighth circuit board 13i, a ninth circuit board 13j, a tenth circuit board 13k, an eleventh circuit board 13l, and a twelfth circuit board 13m that are respectively spaced apart. The first circuit board 13b and the fourth circuit board 13e are each separated and arranged in the Y direction. Between the first circuit board 13b and the fourth circuit board 13e separated in the Y direction, the second circuit board 13c is disposed. Among the first circuit board 13b, the second circuit board 13c, the third circuit board 13d, and the fourth circuit board 13e, the first circuit board 13b and the fourth circuit board 13e are divided into a plurality of circuit boards that are electrically connected, specifically, two circuit boards (see FIG. 8 in particular). Note that the fifth circuit board 13f and the seventh circuit board 13h are also divided into a plurality of circuit boards that are electrically connected, specifically, two circuit boards. In the present embodiment, the fifth circuit board 13f and the seventh circuit board 13h are each separated and arranged in the Y direction.

[0027] The region where the first circuit board 13b and the second circuit board 13c are arranged, the region where the third circuit board 13d and the fourth circuit board 13e are arranged, and the region where the fifth circuit board 13f, the sixth circuit board 13g, and the seventh circuit board 13h are arranged are arranged side by side in the X direction. Specifically, in the X direction, the region where the first circuit board 13b and the second circuit board 13c are arranged is arranged at a position close to the first control terminal 25a. Next, the region where the fifth circuit board 13f, the sixth circuit board 13g, and the seventh circuit board 13h are arranged is arranged. Next, the region where the third circuit board 13d and the fourth circuit board 13e are arranged is arranged. That is, in the X direction, between the region where the first circuit board 13b and the second circuit board 13c are arranged and the region where the third circuit board 13d and the fourth circuit board 13e are arranged, the region where the fifth circuit board 13f, the sixth circuit board 13g, and the seventh circuit board 13h are arranged is arranged.

[0028] During the operation of the semiconductor device 10a, the first circuit board 13b, the second circuit board 13c, the third circuit board 13d, the fourth circuit board 13e, the fifth circuit board 13f, the sixth circuit board 13g, and the seventh circuit board 13h constitute a current path together with the first electrode 17a, the second electrode 18a, and the third electrode 19a. The eighth circuit board 13i, the ninth circuit board 13j, the tenth circuit board 13k, the eleventh circuit board 13l, and the twelfth circuit board 13m are used for controlling the first semiconductor chip 21a, etc. by the first control terminal 25a, the second control terminal 25b, the third control terminal 25c, and the fourth control terminal 25d.

[0029] The frame body 14a is attached to the base plate 11a. Specifically, it is attached to the first main surface 11b of the base plate 11a by an adhesive (not shown). In the present embodiment, the frame body 14a has a rectangular shape in which the length in the X direction is longer than the length in the Y direction when viewed in the thickness direction of the substrate 12a. The frame body 14a includes four side wall portions 14b, 14c, 14d, and 14e that surround the outer periphery of the substrate 12a. The side wall portions 14b, 14c, 14d, and 14e are arranged such that the inner wall surface 14l of the side wall portion 14b faces the inner wall surface 14m of the side wall portion 14c, and the inner wall surface 14n of the side wall portion 14d faces the inner wall surface 14o of the side wall portion 14e. The substrate 12a is disposed in a space 14f surrounded by the four side wall portions 14b, 14c, 14d, and 14e of the frame body 14a. Four through holes 14h, 14i, 14j, and 14k that penetrate in the Z direction are formed in portions near the four corners of the frame body 14a. The through holes 14h, 14i, 14j, and 14k are arranged to align with the positions of the four through holes 11d, 11e, 11f, and 11g of the base plate 11a when the frame body 14a is attached to the base plate 11a. The first control terminal 25a, the second control terminal 25b, the third control terminal 25c, and the fourth control terminal 25d are inserted into the side wall portion 14d of the frame body 14a.

[0030] As the material of the frame body 14a, a material with high insulation and strength is used. Specifically, for example, PPS (Polyphenylenesulfide) resin is adopted. Such a resin is a thermoplastic resin with good moldability, excellent insulation, moisture resistance, heat resistance, and high strength. In addition, PBT (Poly Butylene Terephtalate) resin may be used as the material of the frame body 14a. The frame body 14a includes ribs 41a. The specific configuration of the frame body 14a will be described in detail later.

[0031] The sealing material 15a covers the substrate 12a. The sealing material 15a fills a part of the space 14f within the frame 14a. The sealing material 15a is arranged at a distance from the lid portion 16a. The sealing material 15a is in contact with the side surface of the substrate 12a and a part of the first main surface 12b. Specifically, the sealing material 15a is in contact with the side surface of the substrate 12a and the first main surface 12b in a portion where the semiconductor chips 21a, etc. are not arranged. The sealing material 15a electrically insulates the space on the side surface side of the substrate 12a and the space on the substrate 12a within the region surrounded by the frame 14a. A part of the first electrode 17a, a part of the second electrode 18a, a part of the third electrode 19a, and the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f are covered by the sealing material 15a. Specifically, the sealing material 15a is used to seal each component arranged on the substrate 12a, that is, a part of the first electrode 17a, a part of the second electrode 18a, a part of the third electrode 19a, the first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the third semiconductor chips 23a, 23b, 23c, 23d, the fourth semiconductor chips 24a, 24b, 24c, 24d, the fifth semiconductor chips 21e, 21f, the sixth semiconductor chips 22e, 22f, the seventh semiconductor chips 23e, 23f, the eighth semiconductor chips 24e, 24f, the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, the fourth conductive members 27e, 27f, and the wires 28a, 28b, 28c, 28d, 28e. The members on the base plate 11a are fixed by the sealing material 15a. As the material of the sealing material 15a, for example, a resin with high insulation and heat resistance is adopted. Specifically, an epoxy resin, a phenol resin, a silicone resin, etc., which are thermosetting resins, are adopted as the sealing material 15a.

[0032] The lid portion 16a is plate-shaped. In the present embodiment, the lid portion 16a is rectangular in shape with the length in the X direction being longer than the length in the Y direction when viewed in the thickness direction of the substrate 12a, and has a shape with four notches provided at portions near the four corners. The lid portion 16a is adhered to the frame body 14a by an adhesive (not shown). The lid portion 16a is arranged to cover the opening 14g of the above-described frame body 14a. Three terminal blocks 16b, 16c, and 16d are formed on the lid portion 16a at intervals in the longitudinal direction. The terminal blocks 16b, 16c, and 16d are arranged at intervals in the X direction. Further, three through holes 16e, 16f, and 16g penetrating in the thickness direction (Z direction) are formed in the lid portion 16a. The three through holes 16e, 16f, and 16g are respectively formed at positions where the three terminal blocks 16b, 16c, and 16d are provided. When the lid portion 16a is attached to the frame body 14a, the three through holes 16e, 16f, and 16g are respectively arranged at positions where a part of the first electrode 17a, the second electrode 18a, and the third electrode 19a in a state where the third regions 17d, 18d, and 19d (described later) are not bent penetrate. Nuts 16h, 16i, and 16j as fastening members used to electrically connect the first electrode 17a, the second electrode 18a, and the third electrode 19a to an external electrode (not shown) are outserted or press-fitted at the positions where the terminal blocks 16b, 16c, and 16d are provided on the lid portion 16a. For ease of understanding, the nuts 16h, 16i, and 16j are shown in FIG. 4. As the material of the lid portion 16a, for example, the same material as that of the frame body 14a, specifically, PPS resin or PBT resin is adopted.

[0033] The first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the third semiconductor chips 23a, 23b, 23c, 23d, the fourth semiconductor chips 24a, 24b, 24c, 24d, the fifth semiconductor chips 21e, 21f, the sixth semiconductor chips 22e, 22f, the seventh semiconductor chips 23e, 23f and the eighth semiconductor chips 24e, 24f are each wide-bandgap semiconductor chips. Specifically, the first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the third semiconductor chips 23a, 23b, 23c, 23d, the fourth semiconductor chips 24a, 24b, 24c, 24d, the fifth semiconductor chips 21e, 21f, the sixth semiconductor chips 22e, 22f, the seventh semiconductor chips 23e, 23f and the eighth semiconductor chips 24e, 24f each include a semiconductor layer made of SiC (silicon carbide). Note that the semiconductor layer may be made of, for example, Si (silicon) or GaN (gallium nitride).

[0034] The first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the fifth semiconductor chips 21e, 21f and the sixth semiconductor chips 22e, 22f are each metal-oxide-semiconductor field-effect transistors (MOSFETs). In the present embodiment, the first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the fifth semiconductor chips 21e, 21f and the sixth semiconductor chips 22e, 22f are each vertical transistor chips. That is, the first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the fifth semiconductor chips 21e, 21f and the sixth semiconductor chips 22e, 22f are each transistor chips through which current flows in the thickness direction (Z direction). The first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the fifth semiconductor chips 21e, 21f and the sixth semiconductor chips 22e, 22f are each switching elements.

[0035] The first semiconductor chips 21a, 21b, 21c, 21d are arranged on the first circuit board 13b. Specifically, the first semiconductor chips 21a, 21b are arranged on the first circuit board 13b that is closer to the side wall portion 14b among the divided first circuit boards 13b. Also, the first semiconductor chips 21c, 21d are arranged on the first circuit board 13b that is closer to the side wall portion 14c among the divided first circuit boards 13b. The first semiconductor chips 21a, 21b are arranged at intervals in the X direction. The first semiconductor chips 21c, 21d are arranged at intervals in the X direction. The first semiconductor chips 21a, 21c are arranged at intervals in the Y direction. The first semiconductor chips 21b, 21d are arranged at intervals in the Y direction. The first semiconductor chips 21a, 21b, 21c, 21d are joined to the first circuit board 13b by a conductive bonding material (not shown), whereby the respective drain electrode pads of the first semiconductor chips 21a, 21b, 21c, 21d and the first circuit board 13b are electrically connected.

[0036] The second semiconductor chips 22a, 22b, 22c, 22d are arranged on the third circuit board 13d. Specifically, the second semiconductor chips 22a, 22b are arranged at positions closer to the side wall portion 14b of the third circuit board 13d. Also, the second semiconductor chips 22c, 22d are arranged at positions closer to the side wall portion 14c of the third circuit board 13d. The second semiconductor chips 22a, 22b are arranged at intervals in the X direction. The second semiconductor chips 22c, 22d are arranged at intervals in the X direction. The second semiconductor chips 22a, 22c are arranged at intervals in the Y direction. The second semiconductor chips 22b, 22d are arranged at intervals in the Y direction. The second semiconductor chips 22a, 22b, 22c, 22d are joined to the third circuit board 13d by a conductive bonding material (not shown), whereby the respective drain electrode pads of the second semiconductor chips 22a, 22b, 22c, 22d and the third circuit board 13d are electrically connected.

[0037] The fifth semiconductor chips 21e and 21f are arranged on the fifth circuit board 13f. Specifically, the fifth semiconductor chip 21e is arranged on the fifth circuit board 13f that is closer to the side wall portion 14b among the divided fifth circuit boards 13f. The fifth semiconductor chip 21f is arranged on the fifth circuit board 13f that is closer to the side wall portion 14c among the divided fifth circuit boards 13f. The fifth semiconductor chips 21e and 21f are arranged at intervals in the Y direction. The fifth semiconductor chips 21e and 21f are joined to the fifth circuit board 13f by a joining material (not shown) having conductivity, whereby the respective drain electrode pads of the fifth semiconductor chips 21e and 21f and the fifth circuit board 13f are electrically connected. The sixth semiconductor chips 22e and 22f are arranged on the sixth circuit board 13g. Specifically, the sixth semiconductor chip 22e is arranged at a position closer to the side wall portion 14b in the sixth circuit board 13g. The sixth semiconductor chip 22f is arranged at a position closer to the side wall portion 14c in the sixth circuit board 13g. The sixth semiconductor chips 22e and 22f are arranged at intervals in the Y direction. The sixth semiconductor chips 22e and 22f are joined to the sixth circuit board 13g by a joining material (not shown) having conductivity, whereby the respective drain electrode pads of the sixth semiconductor chips 22e and 22f and the sixth circuit board 13g are electrically connected.

[0038] The third semiconductor chips 23a, 23b, 23c, 23d, the fourth semiconductor chips 24a, 24b, 24c, 24d, the seventh semiconductor chips 23e, 23f, and the eighth semiconductor chips 24e, 24f are each a Schottky barrier diode (SBD). In the present embodiment, the third semiconductor chips 23a, 23b, 23c, 23d, the fourth semiconductor chips 24a, 24b, 24c, 24d, the seventh semiconductor chips 23e, 23f, and the eighth semiconductor chips 24e, 24f are each diode chips through which current flows in the thickness direction (Z direction).

[0039] The third semiconductor chips 23a, 23b, 23c, 23d are arranged on the first circuit board 13b. Specifically, the third semiconductor chips 23a, 23b are arranged on the first circuit board 13b that is closer to the side wall portion 14b among the divided first circuit boards 13b. Also, the third semiconductor chips 23c, 23d are arranged on the first circuit board 13b that is closer to the side wall portion 14c among the divided first circuit boards 13b. Further, the third semiconductor chips 23a, 23b are respectively arranged between the side wall portion 14b and the first semiconductor chips 21a, 21b in the Y direction. The third semiconductor chips 23c, 23d are respectively arranged between the side wall portion 14c and the first semiconductor chips 21c, 21d in the Y direction. The third semiconductor chips 23a, 23b are arranged at intervals in the X direction. The third semiconductor chips 23c, 23d are arranged at intervals in the X direction. The third semiconductor chips 23a, 23c are arranged at intervals in the Y direction. The third semiconductor chips 23b, 23d are arranged at intervals in the Y direction. The third semiconductor chips 23a, 23b, 23c, 23d are joined to the first circuit board 13b by a joining material (not shown) having conductivity, whereby the respective cathode electrode pads of the third semiconductor chips 23a, 23b, 23c, 23d and the first circuit board 13b are electrically connected.

[0040] The fourth semiconductor chips 24a, 24b, 24c, and 24d are arranged on the third circuit board 13d. Specifically, the fourth semiconductor chips 24a and 24b are arranged at positions close to the side wall portion 14b on the third circuit board 13d. Also, the fourth semiconductor chips 24c and 24d are arranged at positions close to the side wall portion 14c on the third circuit board 13d. Further, the fourth semiconductor chips 24a and 24b are respectively arranged between the side wall portion 14b and the second semiconductor chips 22a and 22b in the Y direction. The fourth semiconductor chips 24c and 24d are respectively arranged between the side wall portion 14c and the second semiconductor chips 22c and 22d in the Y direction. The fourth semiconductor chips 24a and 24b are arranged at intervals in the X direction. The fourth semiconductor chips 24c and 24d are arranged at intervals in the X direction. The fourth semiconductor chips 24a and 24c are arranged at intervals in the Y direction. The fourth semiconductor chips 24b and 24d are arranged at intervals in the Y direction. The fourth semiconductor chips 24a, 24b, 24c, and 24d are joined to the third circuit board 13d by a joining material (not shown) having conductivity, whereby the respective cathode electrode pads of the fourth semiconductor chips 24a, 24b, 24c, and 24d and the third circuit board 13d are electrically connected.

[0041] The seventh semiconductor chips 23e and 23f are arranged on the fifth circuit board 13f. Specifically, the seventh semiconductor chip 23e is arranged on the fifth circuit board 13f that is closer to the side wall portion 14b among the divided fifth circuit boards 13f. The seventh semiconductor chip 23f is arranged on the fifth circuit board 13f that is closer to the side wall portion 14c among the divided fifth circuit boards 13f. Also, the seventh semiconductor chip 23e is arranged between the side wall portion 14b and the fifth semiconductor chip 21e in the Y direction. The seventh semiconductor chip 23f is arranged between the side wall portion 14c and the fifth semiconductor chip 21f in the Y direction. The seventh semiconductor chips 23e and 23f are arranged at intervals in the Y direction. The seventh semiconductor chips 23e and 23f are joined to the fifth circuit board 13f by a joining material (not shown) having conductivity, whereby the respective cathode electrode pads of the seventh semiconductor chips 23e and 23f and the fifth circuit board 13f are electrically connected. The eighth semiconductor chips 24e and 24f are arranged on the sixth circuit board 13g. Specifically, the eighth semiconductor chip 24e is arranged at a position closer to the side wall portion 14b among the sixth circuit boards 13g. The eighth semiconductor chip 24f is arranged at a position closer to the side wall portion 14c among the sixth circuit boards 13g. Also, the eighth semiconductor chip 24e is arranged between the side wall portion 14b and the sixth semiconductor chip 22e in the Y direction. The eighth semiconductor chip 24f is arranged between the side wall portion 14c and the sixth semiconductor chip 22f in the Y direction. The eighth semiconductor chips 24e and 24f are arranged at intervals in the Y direction. The eighth semiconductor chips 24e and 24f are joined to the sixth circuit board 13g by a joining material (not shown) having conductivity, whereby the respective cathode electrode pads of the eighth semiconductor chips 24e and 24f and the sixth circuit board 13g are electrically connected.

[0042] In this embodiment, the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f are each solid cylindrical aluminum wires having conductivity. The first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, the fourth conductive members 27e, 27f, and the wires 28a, 28b, 28c, 28d, 28e are each joined to the respective members by wire bonding using a bonding tool. Note that the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f may be copper wires having conductivity, or may be plate-shaped conductive members made of aluminum or copper. Note that aluminum and copper may be pure aluminum or pure copper, or may be aluminum alloys or copper alloys. In the case of plate-shaped members, they are joined, for example, by solder.

[0043] The first conductive members 26a, 26b, 26c, 26d electrically connect the first semiconductor chips 21a, 21b, 21c, 21d and the second circuit board 13c. Specifically, the first conductive members 26a, 26b, 26c, 26d electrically connect the source electrode pads of the first semiconductor chips 21a, 21b, 21c, 21d and the second circuit board 13c. Note that the first conductive members 26a, 26b, 26c, 26d electrically connect the source electrode pads of the first semiconductor chips 21a, 21b, 21c, 21d and the anode electrode pads of the third semiconductor chips 23a, 23b, 23c, 23d.

[0044] The second conductive members 27a, 27b, 27c, 27d electrically connect the second semiconductor chips 22a, 22b, 22c, 22d and the fourth circuit board 13e. Specifically, the second conductive members 27a, 27b, 27c, 27d electrically connect the source electrode pads of the second semiconductor chips 22a, 22b, 22c, 22d and the fourth circuit board 13e. Note that the second conductive members 27a, 27b, 27c, 27d electrically connect the source electrode pads of the second semiconductor chips 22a, 22b, 22c, 22d and the anode electrode pads of the fourth semiconductor chips 24a, 24b, 24c, 24d.

[0045] The third conductive members 26e, 26f electrically connect the fifth semiconductor chips 21e, 21f and the sixth circuit board 13g. Specifically, the third conductive members 26e, 26f electrically connect the source electrode pads of the fifth semiconductor chips 21e, 21f and the sixth circuit board 13g. Note that the third conductive members 26e, 26f electrically connect the source electrode pads of the fifth semiconductor chips 21e, 21f and the anode electrode pads of the seventh semiconductor chips 23e, 23f. The fourth conductive members 27e, 27f electrically connect the sixth semiconductor chips 22e, 22f and the seventh circuit board 13h. Specifically, the fourth conductive members 27e, 27f electrically connect the source electrode pads of the sixth semiconductor chips 22e, 22f and the seventh circuit board 13h. Note that the fourth conductive members 27e, 27f electrically connect the source electrode pads of the sixth semiconductor chips 22e, 22f and the anode electrode pads of the eighth semiconductor chips 24e, 24f.

[0046] Also, the first control terminal 25a and the eighth circuit board 13i are connected by a wire 28a. The second control terminal 25b and the ninth circuit board 13j are connected by a wire 28b. The third control terminal 25c and the tenth circuit board 13k are connected by a wire 28c. The fourth control terminal 25d and the eleventh circuit board 13l are connected by a wire 28d. The eleventh circuit board 13l and the twelfth circuit board 13m are connected by a wire 28e.

[0047] Note that the gate electrode pads of the first semiconductor chips 21a, 21b, 21c, 21d and the fifth semiconductor chips 21e, 21f are electrically connected to the eighth circuit board 13i by wires. The source electrode pads of the first semiconductor chips 21a, 21b, 21c, 21d and the fifth semiconductor chips 21e, 21f are electrically connected to the ninth circuit board 13j by wires. The gate electrode pads of the second semiconductor chips 22a, 22b, 22c, 22d and the sixth semiconductor chips 22e, 22f are electrically connected to the tenth circuit board 13k by wires. The source electrode pads of the second semiconductor chips 22a, 22b, 22c, 22d and the sixth semiconductor chips 22e, 22f are electrically connected to the eleventh circuit board 13l or the twelfth circuit board 13m by wires.

[0048] Next, the configurations of the first electrode 17a, the second electrode 18a, and the third electrode 19a will be described. The first electrode 17a, the second electrode 18a, and the third electrode 19a are each plate-shaped. The first electrode 17a, the second electrode 18a, and the third electrode 19a have conductivity. In the present embodiment, the first electrode 17a, the second electrode 18a, and the third electrode 19a are each composed of a bent copper plate. The first electrode 17a, the second electrode 18a, and the third electrode 19a are each disposed on the circuit pattern 13a. In the present embodiment, the first electrode 17a, the second electrode 18a, and the third electrode 19a are each disposed away from the side wall portions 14b, 14c, 14d, 14e that form the frame body 14a. Through holes 17e, 18e, 19e that penetrate in the thickness direction are formed in portions of the first electrode 17a, the second electrode 18a, and the third electrode 19a that are exposed from the lid portion 16a. In the present embodiment, the first electrode 17a is a so-called P terminal, the second electrode 18a is a so-called O terminal, and the third electrode 19a is a so-called N terminal.

[0049] The first electrode 17a is connected to the first circuit board 13b of the circuit pattern 13a. The first electrode 17a includes a first region 17b connected to the first circuit board 13b, a second region 17c that extends in a direction intersecting the first main surface 12b, which is the Z direction in this embodiment, and is continuous with the first region 17b, and a third region 17d that extends in a direction intersecting the extending direction of the second region 17c and is continuous with the second region 17c and is exposed from the sealing material 15a. In this embodiment, the third region 17d includes a portion extending in the X direction. The first region 17b is joined to the first circuit board 13b by a joining material having conductivity, such as solder. A part of the first region 17b and the second region 17c is located inside the sealing material 15a. The third region 17d includes a region exposed to the outside, that is, a region exposed from the lid portion 16a. The above-described through hole 17e is formed in the third region 17d. Note that the first electrode 17a is also connected to the fifth circuit board 13f. In this way, the first electrode 17a is electrically connected to the first circuit board 13b and the fifth circuit board 13f.

[0050] The second electrode 18a is connected to the second circuit board 13c and the third circuit board 13d of the circuit pattern 13a. The second electrode 18a includes a first region 18b connected to the second circuit board 13c and the third circuit board 13d, a second region 18c that extends in a direction intersecting the first main surface 12b, which is the Z direction in this embodiment, and is continuous with the first region 18b, and a third region 18d that extends in a direction intersecting the extending direction of the second region 18c and is continuous with the second region 18c and is exposed from the sealing material 15a. In this embodiment, the third region 18d includes a portion extending in the X direction. The first region 18b is joined to each of the second circuit board 13c and the third circuit board 13d by a joining material having conductivity, such as solder. A part of the first region 18b and the second region 18c is located inside the sealing material 15a. The third region 18d includes a region exposed to the outside, that is, a region exposed from the lid portion 16a. The above-described through hole 18e is formed in the third region 18d. Note that the second electrode 18a is also connected to the sixth circuit board 13g. In this way, the second electrode 18a is electrically connected to the second circuit board 13c, the third circuit board 13d, and the sixth circuit board 13g.

[0051] Here, the second circuit board 13c and the third circuit board 13d are electrically connected by the plate-shaped second electrode 18a. Therefore, in the electrical path between the second circuit board 13c and the third circuit board 13d, a reduction in wiring resistance can be achieved as compared with the case where the second circuit board 13c and the third circuit board 13d are connected by wiring such as a wire or a circuit pattern 13a.

[0052] The third electrode 19a is connected to the fourth circuit board 13e of the circuit pattern 13a. The third electrode 19a includes a first region 19b connected to the fourth circuit board 13e, a second region 19c that extends in the Z direction in the present embodiment in a direction that is continuous with the first region 19b and intersects the first main surface 12b, and a third region 19d that extends in a direction intersecting the extending direction of the second region 19c and is exposed from the sealing material 15a. In the present embodiment, the third region 19d includes a portion extending in the X direction. The first region 19b is joined to the fourth circuit board 13e by a joining material having conductivity, such as solder. A part of the first region 19b and the second region 19c is located inside the sealing material 15a. The third region 19d includes a region exposed to the outside, that is, a region exposed from the lid portion 16a. The above-described through hole 19e is formed in the third region 19d. Note that the third electrode 19a is also connected to the seventh circuit board 13h. In this way, the third electrode 19a is electrically connected to the fourth circuit board 13e and the seventh circuit board 13h.

[0053] Here, the specific configurations of the first electrode 17a, the second electrode 18a, and the third electrode 19a will be described (see FIGS. 6 to 9 in particular).

[0054] The third electrode 19a includes a first flat plate portion 19f and a second flat plate portion 19g that are arranged in parallel with a space therebetween. The first flat plate portion 19f and the second flat plate portion 19g are provided with a space therebetween in the Y direction. The first flat plate portion 19f and the second flat plate portion 19g are perpendicular to the first main surface 12b. The first flat plate portion 19f and the second flat plate portion 19g are each parallel to the X-Z plane.

[0055] The second electrode 18a includes a third flat plate portion 18f. The third flat plate portion 18f is perpendicular to the first main surface 12b. The third flat plate portion 18f is parallel to the X-Z plane. The third flat plate portion 18f is between the first flat plate portion 19f and the second flat plate portion 19g, and is arranged at intervals from each of the first flat plate portion 19f and the second flat plate portion 19g. That is, the first flat plate portion 19f, the second flat plate portion 19g, and the third flat plate portion 18f constitute parallel flat plates.

[0056] The second electrode 18a includes a first portion 18g that is arranged in parallel with a space from the third electrode 19a. In the present embodiment, the first portion 18g is the third flat plate portion 18f.

[0057] Further, the first electrode 17a includes a seventh flat plate portion 17f (see FIG. 6 in particular). The seventh flat plate portion 17f is perpendicular to the first main surface 12b. The seventh flat plate portion 17f is parallel to the Y-Z plane.

[0058] The third electrode 19a includes an eighth flat plate portion 19h. The eighth flat plate portion 19h is perpendicular to the first main surface 12b. In the present embodiment, the eighth flat plate portion 19h is parallel to the Y-Z plane. That is, the seventh flat plate portion 17f and the eighth flat plate portion 19h constitute parallel flat plates.

[0059] The first electrode 17a includes a third portion 17g that is arranged in parallel with a space from the third electrode 19a. In the present embodiment, the third portion 17g is the seventh flat plate portion 17f.

[0060] Note that the second electrode 18a includes a ninth flat plate portion 18h. The ninth flat plate portion 18h is perpendicular to the first main surface 12b. The ninth flat plate portion 18h is parallel to the Y-Z plane.

[0061] Next, the arrangement of the first conductive members 26a, etc. will be described. There are gaps between the electrodes located inside the sealing material 15a when viewed in the thickness direction of the substrate 12a, here, the first electrode 17a, the second electrode 18a, and the third electrode 19a, and the conductive members, here, the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f. That is, as shown in FIG. 7, when viewed in the thickness direction of the substrate 12a, each of the first electrode 17a, the second electrode 18a, and the third electrode 19a and the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f do not have overlapping regions and are arranged at intervals.

[0062] FIG. 14 is an enlarged view of the region R indicated by the dashed line in FIG. 7. Referring to FIG. 14, when viewed in the thickness direction of the substrate 12a, there is a gap 29a between the third electrode 19a covered by the sealing material 15a and the second conductive member 27b. Specifically, the gap 29a between the first region 19b of the third electrode 19a and the second conductive member 27b, more specifically, the gap 29a between the Y-direction end 29b of the second conductive member 27b and the Y-direction end 29c of the first region 19b is indicated by D1 in FIG. 14. The gap D1 is 1 mm or more in this embodiment. More specifically, the gap D1 is 5 mm or more.

[0063] Next, the specific configuration of the frame body 14a will be described (see FIGS. 11 and 12 in particular). The frame body 14a includes ribs 41a. The ribs 41a project from the inner wall surfaces 14n and 14o of the side wall portions 14d and 14e. Specifically, the ribs 41a are provided so as to extend in the X direction from the inner wall surface 14n of the side wall portion 14d toward the opposing inner wall surface 14o. The ribs 41a are provided across the side wall portion 14d to the side wall portion 14e. That is, the ribs 41a are provided in the frame body 14a so as to be in a beam shape connecting the side wall portion 14d and the side wall portion 14e. By providing such beam-shaped ribs 41a, the frame body 14a has a configuration that is less likely to sway, and the vibration resistance can be improved. In the present embodiment, the ribs 41a are integral with the side wall portions 14d and 14e. The ribs 41a are also made of the above-described thermoplastic resin. By doing so, the ribs 41a can be easily manufactured. Further, since the frame body 14a can be molded with a single mold, it can be configured at low cost.

[0064] The rib 41a includes a first protruding portion 42a connected to the inner wall surface 14n of the side wall portion 14d and extending straight in the X direction, a second protruding portion 43a connected to the inner wall surface 14o of the side wall portion 14e and extending straight in the X direction, and a central portion 44a connected to each of the first protruding portion 42a and the second protruding portion 43a. The central portion 44a is not in contact with each of the inner wall surface 14l of the side wall portion 14b and the inner wall surface 14m of the side wall portion 14c. The central portion 44a includes a first support portion 45a that supports the first electrode 17a and the third electrode 19a, and a second support portion 46a that supports the second electrode 18a and the third electrode 19a. The first support portion 45a is connected to the first protruding portion 42a. The second support portion 46a is connected to the second protruding portion 43a. The first support portion 45a and the second support portion 46a are arranged side by side in the X direction.

[0065] The first support portion 45a is formed with a first guide hole 47a and a second guide hole 48a. The first guide hole 47a and the second guide hole 48a each penetrate in the thickness direction (Z direction) of the substrate 12a. The first guide hole 47a and the second guide hole 48a are arranged at intervals in the X direction. The wall surfaces constituting the first guide hole 47a and the second guide hole 48a are each rectangular along the outer shape of the first electrode 17a and the third electrode 19a when viewed in the thickness direction of the substrate 12a. The first guide hole 47a is configured to be able to penetrate the third region 17d before the first electrode 17a is bent. The second guide hole 48a is configured to be able to penetrate the third region 19d before the third electrode 19a is bent. The portion located between the first guide hole 47a and the second guide hole 48a becomes an entry portion 49a that enters between the first electrode 17a and the third electrode 19a.

[0066] The second support portion 46a is formed with a first guide groove 51a and a second guide groove 52a. The first guide groove 51a is formed to be recessed in the Z direction. The second support portion 46a includes an eleventh flat plate portion 53a, a twelfth flat plate portion 54a, and a first connection portion 55a. The eleventh flat plate portion 53a and the twelfth flat plate portion 54a are arranged in parallel at intervals in the Y direction. The first connection portion 55a is provided to connect the end portion in the Z direction of the eleventh flat plate portion 53a and the end portion in the Z direction of the twelfth flat plate portion 54a. The first guide groove 51a is formed between the eleventh flat plate portion 53a and the twelfth flat plate portion 54a that are arranged at intervals in the Y direction. A part of the third flat plate portion 18f of the second electrode 18a is arranged in the first guide groove 51a. On the side of the opposing surface 56a of the eleventh flat plate portion 53a that faces the inner wall surface 14m of the side wall portion 14c, the first flat plate portion 19f of the third electrode 19a is arranged. The eleventh flat plate portion 53a becomes an entry portion 58a that enters between the second electrode 18a and the third electrode 19a. On the side of the opposing surface 57a of the twelfth flat plate portion 54a that faces the inner wall surface 14l of the side wall portion 14b, the second flat plate portion 19g of the third electrode 19a is arranged. The twelfth flat plate portion 54a becomes an entry portion 59a that enters between the second electrode 18a and the third electrode 19a.

[0067] The second guide groove 52a is formed to be recessed in the Y direction. The second support portion 46a includes a 13th flat plate portion 61a, a 14th flat plate portion 62a, and a second connection portion 63a. The 13th flat plate portion 61a and the 14th flat plate portion 62a are arranged in parallel with a space therebetween in the X direction. The second connection portion 63a is provided so as to connect the end portion in the Y direction of the 13th flat plate portion 61a and the end portion in the Y direction of the 14th flat plate portion 62a. The second guide groove 52a is formed between the 13th flat plate portion 61a and the 14th flat plate portion 62a which are arranged with a space therebetween in the X direction. A part of the 9th flat plate portion 18h is arranged in the second guide groove 52a.

[0068] In the present embodiment, the entry portions 49a, 58a, 59a included in the rib 41a are each configured to reach the position where the sealing material 15a is disposed. That is, the entry portions 49a, 58a, 59a are each in contact with the sealing material 15a as shown in FIG. 13.

[0069] Next, the current path flowing during the operation of the semiconductor device 10a will be described. The current path when current flows in the semiconductor device 10a reaches from the first electrode 17a to the first circuit board 13b, the first semiconductor chips 21a, 21b, 21c, 21d, the first conductive members 26a, 26b, 26c, 26d, the second circuit board 13c, and the second electrode 18a. Further, it reaches from the second electrode 18a, the third circuit board 13d, the second semiconductor chips 22a, 22b, 22c, 22d, the second conductive members 27a, 27b, 27c, 27d, the fourth circuit board 13e, and then the third electrode 19a. Also, as a current path, it reaches from the first electrode 17a to the fifth circuit board 13f, the fifth semiconductor chips 21e, 21f, the third conductive members 26e, 26f, the sixth circuit board 13g, and the second electrode 18a, and further, there is a path that reaches from the second electrode 18a, the seventh circuit board 13h, the fourth conductive members 27e, 27f, the sixth semiconductor chips 22e, 22f, the sixth circuit board 13g, and then the third electrode 19a.

[0070] Here, consider the current path from the first electrode 17a to the third electrode 19a. In the semiconductor device 10a, as shown in FIG. 10, a capacitor 101 such as a smoothing capacitor may be connected in parallel with the first semiconductor chips 21a, 21b, 21c, 21d and the second semiconductor chips 22a, 22b, 22c, 22d. At this time, a closed circuit is formed between the first semiconductor chips 21a, 21b, 21c, 21d and the second semiconductor chips 22a, 22b, 22c, 22d and the capacitor 101. In the semiconductor device 10a, the path of this closed circuit is from the first electrode 17a to the first circuit board 13b, the first semiconductor chips 21a, 21b, 21c, 21d, the first conductive members 26a, 26b, 26c, 26d, the second circuit board 13c, the second electrode 18a, the third circuit board 13d, the second semiconductor chips 22a, 22b, 22c, 22d, the second conductive members 27a, 27b, 27c, 27d, the fourth circuit board 13e, and then to the third electrode 19a. A high di / dt is generated during switching in this closed circuit. In the case of a surge voltage, when the inductance is large, a high surge voltage is generated when a high di / dt occurs and is applied to the first semiconductor chips 21a, 21b, 21c, 21d and the second semiconductor chips 22a, 22b, 22c, 22d. Such a state may cause damage to the first semiconductor chips 21a, 21b, 21c, 21d and the second semiconductor chips 22a, 22b, 22c, 22d. Therefore, suppression of the surge voltage is required. If the inductance can be reduced in the current path from the first electrode 17a to the third electrode 19a, the surge voltage can be suppressed.

[0071] As shown in FIG. 10, the fifth semiconductor chips 21e, 21f can be arranged in parallel with the first semiconductor chips 21a, 21b, 21c, 21d. Also, the sixth semiconductor chips 22e, 22f can be arranged in parallel with the second semiconductor chips 22a, 22b, 22c, 22d.

[0072] Here, within the second electrode 18a, the current flows from the first region 18b through the second region 18c to the third region 18d. In the third flat plate portion 18f, which is the first portion 18g in the second region 18c as shown in FIG. 9, the current flows in the direction of arrow X as indicated by arrow V1. On the other hand, within the third electrode 19a, the current flows from the first region 19b through the second region 19c to the third region 19d. In the first flat plate portion 19f and the second flat plate portion 19g in the second region 19c, the current flows in the direction opposite to arrow X as indicated by arrow V2.

[0073] Also, within the first electrode 17a, the current flows from the third region 17d through the second region 17c to the first region 17b. In the second region 17c, the current flows in the direction opposite to arrow Z as indicated by arrow V3. On the other hand, within the third electrode 19a, the current flows from the first region 19b through the second region 19c to the third region 19d. In the eighth flat plate portion 19h in the second region 19c, the current flows in the direction of arrow Z as indicated by arrow V4.

[0074] In the semiconductor device 10a of the present disclosure, the second electrode 18a includes a first portion 18g that is arranged in parallel with a gap from the third electrode 19a. Therefore, in this parallel arrangement portion, by making the direction of the current flowing through the third electrode 19a opposite to the direction of the current flowing through the second electrode 18a, the magnetic flux generated when the current flows through the second electrode 18a and the third electrode 19a is canceled out, and the inductance of the current path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device 10a can be reduced.

[0075] In this embodiment, the third electrode 19a includes a first flat plate portion 19f and a second flat plate portion 19g that are arranged in parallel with a gap therebetween. The second electrode 18a includes a third flat plate portion 18f that is between the first flat plate portion 19f and the second flat plate portion 19g and is arranged with a gap from each of the first flat plate portion 19f and the second flat plate portion 19g. In this embodiment, the third flat plate portion 18f serves as the first portion 18g. Therefore, by making the direction of the current flowing through the third electrode 19a opposite to the direction of the current flowing through the second electrode 18a between the third flat plate portion 18f arranged in parallel and each of the first flat plate portion 19f and the second flat plate portion 19g, the magnetic flux generated when the current flows through the third electrode 19a and the second electrode 18a is cancelled out, and the inductance of the path is subtracted by the mutual inductance. Thus, the inductance of the semiconductor device 10a can be further reduced.

[0076] In this embodiment, the first electrode 17a includes a third portion 17g that is arranged in parallel with the third electrode 19a with a gap therebetween. Therefore, by making the direction of the current flowing through the first electrode 17a opposite to the direction of the current flowing through the third electrode 19a in the parallel arranged portions, the magnetic flux generated when the current flows through the first electrode 17a and the third electrode 19a is cancelled out, and the inductance of the path is subtracted by the mutual inductance. Thus, the inductance of the semiconductor device 10a can be further reduced.

[0077] In this embodiment, the first electrode 17a includes a seventh flat plate portion 17f. The third electrode 19a includes an eighth flat plate portion 19h that is arranged in parallel with the seventh flat plate portion 17f. In this embodiment, the seventh flat plate portion 17f serves as the third portion 17g. Therefore, by making the direction of the current flowing through the first electrode 17a opposite to the direction of the current flowing through the third electrode 19a between the seventh flat plate portion 17f and the eighth flat plate portion 19h arranged in parallel, the magnetic flux generated when the current flows through the first electrode 17a and the third electrode 19a is cancelled out, and the inductance of the path is subtracted by the mutual inductance. Thus, the inductance of the semiconductor device 10a can be further reduced.

[0078] In the semiconductor device 10a of the present disclosure, the frame body 14a includes insulating ribs 41a protruding from the inner wall surfaces 14n and 14o of the side wall portions 14d and 14e. The ribs 41a include portions arranged in parallel, specifically, entry portions 58a and 59a that enter between the second electrode 18a and the third electrode 19a and secure the creepage distance between the second electrode 18a and the third electrode 19a arranged in parallel. Further, the rib 41a includes an entry portion 49a that enters between the first electrode 17a and the third electrode 19a and secures the creepage distance between the first electrode 17a and the third electrode 19a arranged in parallel. Therefore, the insulation between the portions arranged in parallel can be enhanced by the entry portions 49a, 58a, and 59a. In this case, since the rib 41a protruding from the inner wall surfaces 14l and 14o is included in the frame body 14a, the rib 41a can be arranged when the frame body 14a is attached to the base plate 11a. Thus, it is possible to easily ensure high insulation between the electrodes.

[0079] In the present embodiment, the entry portions 58a and 59a enter between the first flat plate portion 19f and the third flat plate portion 18f and between the second flat plate portion 19g and the third flat plate portion 18f. Therefore, the entry portions 58a and 59a can easily ensure high insulation between the second electrode 18a and the third electrode 19a between the first flat plate portion 19f and the third flat plate portion 18f and between the second flat plate portion 19g and the third flat plate portion 18f.

[0080] In the present embodiment, the entry portion 49a is arranged between the seventh flat plate portion 17f and the eighth flat plate portion 19h. Therefore, the entry portion 49a that enters between the seventh flat plate portion 17f of the first electrode 17a and the eighth flat plate portion 19h of the third electrode 19a arranged in parallel can be easily arranged. Thus, it is possible to easily ensure high insulation between the first electrode 17a and the third electrode 19a.

[0081] Next, a manufacturing method of the semiconductor device 10a having the above configuration will be briefly described. First, a base plate 11a is prepared. Next, using a conductive bonding material such as a plate solder or a paste solder, the substrate 12a is bonded to the base plate 11a, and semiconductor chips such as a first electrode 17a, a second electrode 18a, a third electrode 19a, and a first semiconductor chip 21a are bonded to the circuit pattern 13a. Here, as the first electrode 17a, the second electrode 18a, and the third electrode 19a, those in a state where the third regions 17d, 18d, and 19d are not bent are used. FIG. 15 is a schematic perspective view showing a state in which the substrate 12a is bonded to the base plate 11a, and semiconductor chips such as a first electrode 17a, a second electrode 18a, a third electrode 19a, and a first semiconductor chip 21a are bonded to the circuit pattern 13a.

[0082] Thereafter, the frame body 14a is attached to the base plate 11a using an adhesive. Note that a first control terminal 25a, a second control terminal 25b, a third control terminal 25c, and a fourth control terminal 25d are attached to the frame body 14a in advance. The frame body 14a is attached to the base plate 11a such that the seventh flat plate portion 17f of the first electrode 17a is accommodated in the first guide hole 47a, the eighth flat plate portion 19h of the third electrode 19a is accommodated in the second guide hole 48a, the third flat plate portion 18f of the second electrode is accommodated in the first guide groove 51a, and the ninth flat plate portion 18h of the second electrode is accommodated in the second guide groove 52a. At this time, the opposing surface 56a is arranged to oppose the first flat plate portion 19f of the third electrode 19a, and the opposing surface 57a is arranged to oppose the second flat plate portion 19g of the third electrode 19a.

[0083] In the present embodiment, the first flat plate portion 19f, the second flat plate portion 19g, and the third flat plate portion 18f are perpendicular to the first main surface 12b. Therefore, when the frame body 14a is attached to the base plate 11a, the entry portions 58a and 59a can be easily arranged between the first flat plate portion 19f and the third flat plate portion 18f and between the second flat plate portion 19g and the third flat plate portion 18f. Thus, it is possible to more easily ensure high insulation between the second electrode 18a and the third electrode 19a.

[0084] In the present embodiment, the seventh flat plate portion 17f and the eighth flat plate portion 19h are perpendicular to the first main surface 12b. Therefore, when attaching the frame body 14a to the base plate 11a, the entry portion 49a can be easily disposed between the seventh flat plate portion 17f and the eighth flat plate portion 19h. Thus, it is possible to more easily ensure high insulation between the first electrode 17a and the third electrode 19a.

[0085] Next, each member is electrically connected by the first conductive member 26a or the like. In this case, a bonding tool is used and each member is connected by wire bonding. FIG. 16 is a schematic perspective view showing a state where the frame body 14a is attached to the base plate 11a and the first conductive member 26a or the like is joined.

[0086] Here, according to the semiconductor device 10a of the present disclosure, when viewed in the thickness direction of the substrate 12a, there is a gap 29a between the first electrode 17a, the second electrode 18a, and the third electrode 19a covered by the sealing material 15a and the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f. Such a semiconductor device 10a is configured such that, when viewed in the thickness direction of the substrate 12a, the first electrode 17a, the second electrode 18a, and the third electrode 19a covered by the sealing material 15a do not overlap with the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f. Therefore, the bonding of the circuit pattern 13a to the first semiconductor chips 21a, 21b, 21c, 21d, the second semiconductor chips 22a, 22b, 22c, 22d, the third semiconductor chips 23a, 23b, 23c, 23d, the fourth semiconductor chips 24a, 24b, 24c, 24d, the fifth semiconductor chips 21e, 21f, the sixth semiconductor chips 22e, 22f, the seventh semiconductor chips 23e, 23f, and the eighth semiconductor chips 24e, 24f and the bonding of the circuit pattern 13a to the first electrode 17a, the second electrode 18a, and the third electrode 19a can be performed simultaneously. Further, in the semiconductor device 10a having such a configuration, when wiring is performed by the first conductive members 26a, 26b, 26c, 26d, the second conductive members 27a, 27b, 27c, 27d, the third conductive members 26e, 26f, and the fourth conductive members 27e, 27f using a bonding tool, the possibility of the bonding tool interfering with the first electrode 17a, the second electrode 18a, and the third electrode 19a can be reduced. Therefore, productivity can be improved.

[0087] Thereafter, the liquid sealing material 15a is filled into the space 14f surrounded by the frame body 14a from the opening 14g side. The sealing material 15a is filled so that the sealing material 15a contacts the entry portions 49a, 58a, 59a even after the sealing material 15a is cured.

[0088] In this embodiment, the rib 41a is integral with the side wall portions 14d and 14e. Therefore, when the sealing material 15a is encapsulated, it is possible to suppress the rib 41a from moving due to buoyancy. Thus, reliable insulation can be achieved.

[0089] In this embodiment, the first flat plate portion 19f, the second flat plate portion 19g, and the third flat plate portion 18f are perpendicular to the first main surface 12b. Therefore, when filling the sealing material 15a, it is possible to avoid air bubbles being caught in the sealing material 15a and accumulating in the lower regions of the first flat plate portion 19f, the second flat plate portion 19g, and the third flat plate portion 18f. Thus, it is possible to avoid the risk of air bubbles accumulating in the sealing material 15a and suppress a decrease in insulation performance, thereby improving the reliability of the semiconductor device 10a.

[0090] In this embodiment, the seventh flat plate portion 17f and the eighth flat plate portion 19h are perpendicular to the first main surface 12b. Therefore, when encapsulating the sealing material 15a, it is possible to avoid voids being caught during the encapsulation of the sealing material 15a and accumulating in the lower regions of the seventh flat plate portion 17f and the eighth flat plate portion 19h. Thus, it is possible to avoid the risk of voids accumulating in the sealing material 15a and suppress a decrease in insulation performance, thereby improving the reliability of the semiconductor device 10a.

[0091] After the filled sealing material 15a has cured, the lid portion 16a is attached to the frame body 14a. FIG. 17 is a schematic perspective view showing a state in which the lid portion 16a is attached to the frame body 14a. Referring to FIG. 17, the first electrode 17a, the second electrode 18a, and the third electrode 19a, specifically, the non-folded third region 17d of the first electrode 17a, the non-folded third region 18d of the second electrode 18a, and the non-folded third region 19d of the third electrode 19a respectively pass through the through holes 16e, 16f, and 16g of the lid portion 16a, and the lid portion 16a is attached to the frame body 14a.

[0092] Thereafter, the portions of the first electrode 17a, the second electrode 18a, and the third electrode 19a that are exposed from the lid portion 16a are bent 90 degrees in the X direction. In this way, the exposed portions of the first electrode 17a, the second electrode 18a, and the third electrode 19a are along the outer shapes of the terminal blocks 16b, 16c, 16d, and the opening portions of the through holes 17e, 18e, 19e are configured to coincide with the respective screw holes of the nuts 16h, 16i, 16j. In this way, the semiconductor device 10a shown in FIG. 1 is manufactured.

[0093] (Embodiment 2) Next, Embodiment 2, which is another embodiment, will be described. FIG. 18 is a schematic perspective view showing a part of the semiconductor device in Embodiment 2. In the semiconductor device shown in FIG. 18, the lid portion, the sealing material, and the frame body are not shown. FIG. 19 is a schematic side view of the semiconductor device shown in FIG. 18. FIG. 20 is a schematic cross-sectional view of the semiconductor device shown in FIG. 19 when cut along XX-XX in FIG. 19. FIG. 21 is a schematic cross-sectional view of the semiconductor device shown in FIG. 20 when the first electrode, the second electrode, and the third electrode are not shown. FIG. 22 is a schematic cross-sectional view of the semiconductor device shown in FIG. 20 when only the first electrode, the second electrode, and the third electrode are shown. The semiconductor device of Embodiment 2 is different from that of Embodiment 1 in that the configurations of the first electrode, the second electrode, and the third electrode are different. Also, in Embodiment 2, the fourth circuit board 13e and the seventh circuit board 13h are not divided.

[0094] Referring to FIGS. 18 to 22, the semiconductor device 10b of Embodiment 2 includes a first electrode 17j, a second electrode 18j, and a third electrode 19j.

[0095] The first electrode 17j includes a fourth flat plate portion 17k and a fifth flat plate portion 17l that are arranged in parallel with each other with a gap therebetween. The fourth flat plate portion 17k and the fifth flat plate portion 17l are provided with a gap in the Y direction. The fourth flat plate portion 17k and the fifth flat plate portion 17l are perpendicular to the first main surface 12b. The fourth flat plate portion 17k and the fifth flat plate portion 17l are each parallel to the X-Z plane.

[0096] The second electrode 18j includes a sixth flat plate portion 18k. The sixth flat plate portion 18k is perpendicular to the first main surface 12b. The sixth flat plate portion 18k is parallel to the X-Z plane. The sixth flat plate portion 18k is located between the fourth flat plate portion 17k and the fifth flat plate portion 17l and is arranged at intervals from each of the fourth flat plate portion 17k and the fifth flat plate portion 17l. That is, the fourth flat plate portion 17k, the fifth flat plate portion 17l, and the sixth flat plate portion 18k constitute parallel flat plates.

[0097] The second electrode 18j includes a second portion 18l that is arranged in parallel with a space from the first electrode 17j. In the present embodiment, the second portion 18l is the sixth flat plate portion 18k.

[0098] Further, the first electrode 17j includes a seventh flat plate portion 17m (see particularly FIG. 19). The seventh flat plate portion 17m is perpendicular to the first main surface 12b. The seventh flat plate portion 17m is parallel to the Y-Z plane.

[0099] The third electrode 19j includes an eighth flat plate portion 19k. The eighth flat plate portion 19k is perpendicular to the first main surface 12b. In the present embodiment, the eighth flat plate portion 19k is parallel to the Y-Z plane. That is, the seventh flat plate portion 17m and the eighth flat plate portion 19k constitute parallel flat plates.

[0100] The first electrode 17j includes a third portion 17n that is arranged in parallel with a space from the third electrode 19j. In the present embodiment, the third portion 17n is the seventh flat plate portion 17m.

[0101] Note that the second electrode 18j includes a ninth flat plate portion 18m. The ninth flat plate portion 18m is perpendicular to the first main surface 12b. The ninth flat plate portion 18m is parallel to the Y-Z plane.

[0102] Regarding the frame 14a included in the semiconductor device 10b in the present embodiment, a frame 14a including ribs provided with a first guide hole, a second guide hole, a first guide groove, and a second guide groove is used according to the configurations of the first electrode 17j, the second electrode 18j, and the third electrode 19j.

[0103] In this embodiment, the second electrode 18j includes a second portion 18l that is arranged in parallel with a gap from the first electrode 17j. Therefore, in this portion arranged in parallel, by making the direction of the current flowing through the third electrode 19j opposite to the direction of the current flowing through the second electrode 18j, the magnetic flux generated when the current flows through the second electrode 18j and the third electrode 19j is canceled out, and the inductance of the current path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device 10b can be reduced.

[0104] In this embodiment, the first electrode 17j includes a fourth flat plate portion 17k and a fifth flat plate portion 17l that are arranged in parallel with a gap therebetween. The second electrode 18j includes a sixth flat plate portion 18k that is between the fourth flat plate portion 17k and the fifth flat plate portion 17l and is arranged with a gap from each of the fourth flat plate portion 17k and the fifth flat plate portion 17l. In this embodiment, the sixth flat plate portion 18k serves as the second portion 18l. Therefore, between the sixth flat plate portion 18k arranged in parallel and each of the fourth flat plate portion 17k and the fifth flat plate portion 17l, the magnetic flux generated when the current flows through the second electrode 18j and the first electrode 17j is canceled out, and the inductance of the path is subtracted by the mutual inductance. Thus, the inductance of the semiconductor device 10b can be further reduced.

[0105] In this embodiment, the fourth flat plate portion 17k, the fifth flat plate portion 17l, and the sixth flat plate portion 18k are perpendicular to the first main surface 12b. Therefore, it is possible to avoid air bubbles that have bitten into the sealing material 15a when filling the sealing material 15a from accumulating in the lower regions of the fourth flat plate portion 17k, the fifth flat plate portion 17l, and the sixth flat plate portion 18k. Therefore, it is possible to avoid the risk of air bubbles accumulating in the sealing material 15a and suppress a decrease in insulation performance, thereby improving the reliability of the semiconductor device 10b. Further, when attaching the frame body 14a to the base plate 11a, the entry portions 58a, 59a can be easily arranged between the fourth flat plate portion 17k and the sixth flat plate portion 18k and between the fifth flat plate portion 17l and the sixth flat plate portion 18k. Therefore, it is possible to more easily ensure high insulation between the second electrode 18j and the third electrode 19j.

[0106] In this embodiment, the first electrode 17j includes the seventh flat plate portion 17m. The third electrode 19j includes an eighth flat plate portion 19k arranged in parallel with the seventh flat plate portion 17m. Therefore, between the seventh flat plate portion 17m and the eighth flat plate portion 19k arranged in parallel, by making the direction of the current flowing through the first electrode 17j opposite to the direction of the current flowing through the third electrode 19j, the magnetic flux generated when current flows through the first electrode 17j and the third electrode 19j is canceled out, and the inductance of the path is subtracted by the mutual inductance. Therefore, the inductance of the semiconductor device 10b can be further reduced.

[0107] In this embodiment, the seventh flat plate portion 17m and the eighth flat plate portion 19k are perpendicular to the first main surface 12b. Therefore, when filling the sealing material 15a, it is possible to avoid air bubbles being caught in the sealing material 15a and accumulating in the lower regions of the seventh flat plate portion 17m and the eighth flat plate portion 19k. Therefore, it is possible to avoid the risk of air bubbles accumulating in the sealing material 15a, suppress a decrease in insulation performance, and improve the reliability of the semiconductor device 10b. Also, when attaching the frame body 14a to the base plate 11a, the entry portion 49a can be easily arranged between the seventh flat plate portion 17m and the eighth flat plate portion 19k. Thus, it is possible to more easily ensure high insulation between the first electrode 17j and the third electrode 19j.

[0108] (Other embodiments) In addition, in the above embodiment, in each of the third regions of the first electrode, the second electrode, and the third electrode, the portion exposed from the lid portion was bent by 90 degrees. However, the present invention is not limited to this, and the portion exposed from the lid portion may be left as it is without being bent, for example, configured to extend in a direction perpendicular to the first main surface. Also, in the third region, other members may be attached by welding or the like to form the first electrode or the like.

[0109] In addition, in the above embodiment, at least one of the first circuit board 13b, the second circuit board 13c, the third circuit board 13d, and the fourth circuit board 13e may be divided into a plurality of circuit boards that are electrically connected. By doing so, the degree of freedom in designing the shape of the circuit pattern 13a can be increased.

[0110] It should be understood that the embodiments disclosed this time are illustrative in all respects and not restrictive in any way. The scope of the present disclosure is defined not by the above description but by the claims, and it is intended that all modifications within the meaning and scope equivalent to the claims be included.

Explanation of reference numerals

[0111] 10a, 10b semiconductor devices, 11a base plate, 11b, 12b first main surface, 11c, 12c second main surface, 11d, 11e, 11f, 11g, 14h, 14i, 14j, 14k, 16e, 16f, 16g, 17e, 18e, 19e through holes, 12a substrate, 13a circuit pattern, 13b first circuit board, 13c second circuit board, 13d third circuit board, 13e fourth circuit board, 13f fifth circuit board, 13g sixth circuit board, 13h seventh circuit board, 13i eighth circuit board, 13j ninth circuit board, 13k tenth circuit board, 13l eleventh circuit board, 13m twelfth circuit board, 14a frame, 14b, 14c, 14d, 14e side wall portions, 14f space, 14g opening, 14l, 14m, 14n, 14o inner wall surfaces, 15a sealing material, 16a lid portion, 16b, 16c, 16d terminal blocks, 16h, 16i, 16j nuts, 17a, 17j first electrodes, 17b, 18b, 19b first regions, 17c, 18c, 19c second regions, 17d, 18d, 19d third regions, 17f, 17m seventh flat portions, 17g, 17n third portions, 17k fourth flat portion, 17l fifth flat portion, 18a, 18j second electrodes, 18f third flat portion m18g first portion, 18h ninth flat portion, 18k sixth flat portion, 18l second portion, 19a, 19j third electrodes, 19f first flat portion, 19g second flat portion, 19h, 19k eighth flat portion, 21a, 21b, 21c, 21d first semiconductor chips, 21e, 21f fifth semiconductor chips, 22a, 22b, 22c, 22d second semiconductor chips, 22e, 22f sixth semiconductor chips, 23a, 23b, 23c, 23d third semiconductor chips, 23e, 23f seventh semiconductor chips, 24a, 24b, 24c, 24d fourth semiconductor chips, 24e, 24f eighth semiconductor chips, 25a first control terminal, 25b second control terminal, 25c third control terminal, 25d fourth control terminal, 26a, 26b, 26c, 26d first conductive members, 26e, 26f third conductive members, 27a, 27b, 27c, 27d second conductive members, 27e, 27f fourth conductive members, 28a, 28b, 28c, 28d, 28e wires, 29a gap, 29b, 29c ends, 41a rib, 42a first protrusion, 43a second protrusion, 44a central portion, 45a first support portion, 46a second support portion, 47a first guide hole, 48a second guide hole, 49a, 58a,59a entrance part, 51a first guide groove, 52a second guide groove, 53a eleventh flat part, 54a twelfth flat part, 55a first connection part, 56a, 57a opposing surfaces, 61a thirteenth flat part, 62a fourteenth flat part, 63a second connection part, 101 capacitor, D1 gap, R region, V1, V2, V3, V4 arrows

Claims

1. A substrate including a first main surface, including a first circuit board, a second circuit board, a third circuit board, and a fourth circuit board that are respectively located apart from each other, and a circuit pattern disposed on the first main surface, a plate-shaped first electrode disposed on the circuit pattern and connected to the first circuit board, a plate-shaped second electrode disposed on the circuit pattern and connected to the second circuit board and the third circuit board, a plate-shaped third electrode disposed on the circuit pattern and connected to the fourth circuit board, a first semiconductor chip disposed on the first circuit board, a second semiconductor chip disposed on the third circuit board, a first conductive member that electrically connects the first semiconductor chip and the second circuit board, a second conductive member that electrically connects the second semiconductor chip and the fourth circuit board, and the second electrode includes at least one of a first portion disposed in parallel with a space from the third electrode or a second portion disposed in parallel with a space from the first electrode, a semiconductor device.

2. The semiconductor device according to claim 1, wherein the first electrode includes a third portion disposed in parallel with a space from the third electrode.

3. The third electrode includes a first flat plate portion and a second flat plate portion that are disposed in parallel with a space from each other, The semiconductor device according to claim 1 or claim 2, wherein the second electrode includes a third flat plate portion that is between the first flat plate portion and the second flat plate portion and is disposed with a space from each of the first flat plate portion and the second flat plate portion.

4. The semiconductor device according to claim 3, wherein the first flat plate portion, the second flat plate portion, and the third flat plate portion are perpendicular to the first main surface.

5. The first electrode includes a fourth flat plate portion and a fifth flat plate portion that are disposed in parallel with a space from each other, The semiconductor device according to claim 3 or claim 4, wherein the second electrode includes a sixth flat plate portion that is between the first flat plate portion and the second flat plate portion and is disposed with a space from each of the first flat plate portion and the second flat plate portion.

6. The semiconductor device according to claim 5, wherein the fourth flat plate portion, the fifth flat plate portion, and the sixth flat plate portion are perpendicular to the first main surface.

7. The first electrode includes a seventh flat plate portion, The semiconductor device according to any one of claims 2 to 6, wherein the third electrode includes an eighth flat plate portion disposed in parallel with the seventh flat plate portion.

8. The semiconductor device according to claim 7, wherein the seventh flat plate portion and the eighth flat plate portion are perpendicular to the first main surface.

9. The semiconductor device according to any one of claims 1 to 8, wherein at least one of the first circuit board, the second circuit board, the third circuit board, and the fourth circuit board is divided into a plurality of circuit boards that are electrically connected.

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