Semiconductor device and method of manufacturing the same

Abstract

A first heat transport structure (109) formed as passing through a mold resin layer (106) is connected to a first extension (104a) of a first heat transport layer (104) and to a first heatsink (107) formed upon the mold resin layer (106). A second heat transport structure (110) formed as passing through the mold resin layer (106) is connected to a second extension (105a) of a second heat transport layer (105) and to a second heatsink (108) formed upon the mold resin layer (106).

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same.

Background Art

[0002] In recent years, electronic devices such as smartphones have been rapidly developing, and along with this, the demand for miniaturization and high performance of electronic devices has been increasing. Against this backdrop, FOWLP (fan-out wafer level package) has attracted attention.

[0003] The FOWLP technology is a packaging technology that integrates semiconductor chips, passive components, etc. with a molding resin. The advantage of this packaging technology is that since a package substrate is not required, the thickness can be reduced, enabling miniaturization. Also, the wiring length between semiconductor chips can be shortened, enabling high-speed transmission of signals. Furthermore, by making the package area larger than the semiconductor chip area, terminals can be extended to the outside of the chip, and a large number of input / output terminals can be secured.

[0004] However, in the FOWLP structure, since the semiconductor chip is sealed with a molding resin, there is a problem with heat dissipation. The thermal conductivity of the molding resin used for FOWLP is typically around 1 W / mK, which is small compared to the value of about 170 W / mK for Si, which is typical for semiconductor chips, and the value of about 400 W / mK for copper, which is typical for the material of a heat sink. When a semiconductor chip is sealed with such a molding resin having a low thermal conductivity, the heat generated in the semiconductor chip cannot diffuse, and the temperature of the semiconductor chip may exceed the allowable upper limit temperature.

[0005] In response to the above problems, studies have been conducted on the heat dissipation characteristics of FOWLP (see, for example, Non-Patent Document 1 and Non-Patent Document 2). As a typical technique for improving the heat dissipation of FOWLP, there is a technique of attaching a heat sink to a semiconductor chip. This will be described with reference to FIG. 3. In this semiconductor device, two semiconductor chips 302 and 303 with different thicknesses are encapsulated by a mold resin layer 305 on a wiring layer 301.

[0006] Since the thickness of the mold resin layer 305 is equal to that of the thickest semiconductor chip 302, the thickest semiconductor chip 302 is exposed from the mold resin layer 305. The heat sink 307 is disposed directly above the mold resin layer 305 and the thickest semiconductor chip 302. Also, the heat sink 307 and the semiconductor chip 303 are connected via a heat transfer plate 306 composed of a heat transfer medium.

[0007] The integrated circuit 302a of the semiconductor chip 302 and the integrated circuit 303a of the semiconductor chip 303 are electrically connected via a wiring 301a formed in the wiring layer 301. Also, terminals 301b are disposed under the wiring layer 301, and the wiring layer 301 is connected (mounted) to a printed circuit board 308 via the terminals 301b.

[0008] According to the above structure, the heat generated in the semiconductor chip 302 and the semiconductor chip 303 is transmitted to the heat sink 307 and diffused from the heat sink 307 into the atmosphere. Also, part of the heat is transmitted to the printed circuit board 308 via the wiring layer 301 and diffused from the printed circuit board 308 into the atmosphere. By these means, the heat dissipation of FOWLP can be improved.

Prior Art Documents

Non-Patent Documents

[0009]

Non-Patent Document 1

[0010] However, in the semiconductor device described above, for example, when a semiconductor chip 302 with a large heat generation amount and a semiconductor chip 303 with a small heat generation amount are mounted, heat is transferred from the semiconductor chip 302 to the semiconductor chip 303 via the heat sink 307 and the heat transfer plate 306. In such a state, the temperature of the semiconductor chip 303 may rise excessively, which may cause malfunction or failure.

[0011] In order to prevent such heat transfer, it is also conceivable to connect individual heat sinks directly above each semiconductor chip. However, in FOWLP, considering that the distance between semiconductor chips is reduced to shorten the wiring length in order to achieve high-speed transmission signals, it is not easy to arrange a plurality of heat sinks of sizes corresponding to the heat generation amounts of the respective semiconductor chips on the molding resin.

[0012] In addition, heat dissipation from the printed circuit board to the atmosphere through the wiring layer is also considered. In the case of a semiconductor chip with a large heat generation amount, it is difficult to obtain a sufficient heat dissipation amount only with the wiring that electrically connects the semiconductor chip and the printed circuit board. In contrast, in addition to the wiring for electrical connection, by forming wiring for heat dissipation purposes in the wiring layer, the heat dissipation amount can be improved. However, when wiring for heat dissipation purposes is provided in this way, although the heat dissipation amount is improved, the area of the wiring layer increases, leading to an increase in the size of the package. This is contrary to the requirement for miniaturization of electronic devices. In addition, since the wiring layer contains wiring for electrical connection and wiring for heat dissipation purposes, the degree of freedom in chip layout and wiring is restricted.

[0013] The present invention has been made to solve the above problems, and aims to improve the heat dissipation performance without increasing the size of the package, without restricting the degree of freedom in chip layout and wiring, and without causing malfunction or failure.

Means for Solving the Problems

[0014] The semiconductor device according to the present invention includes a wiring layer in which wiring is formed, a semiconductor chip disposed on the wiring layer, an integrated circuit formed on a main surface of the semiconductor chip facing the side of the wiring layer and connected to the wiring, and a heat transport layer formed of a heat transport body formed on a surface of the semiconductor chip where the integrated circuit is not formed and further extending on the wiring layer. The semiconductor device also includes a mold resin layer formed of a mold resin that molds the semiconductor chip covered with the heat transport layer on the wiring layer, a heat sink formed on the mold resin layer, and a heat transport structure formed of a heat transport body that penetrates the mold resin layer and thermally connects the extending portion of the heat transport layer and the heat sink.

[0015] Also, a method for manufacturing a semiconductor device according to the present invention includes a first step of fixing a semiconductor chip having an integrated circuit formed on a main surface onto a support substrate on the surface where the integrated circuit is formed; a second step of forming a layer made of a heat transfer body on the support substrate on which the semiconductor chip is fixed; a third step of molding the semiconductor chip with a molding resin to form a molding resin layer on the support substrate after forming the layer made of the heat transfer body; a fourth step of separating the support substrate from the molding resin layer; a fifth step of removing a part of the layer formed to cover the back surface of the molding resin layer on the side where the integrated circuit is formed, and forming a heat transfer layer provided with an extending portion formed on a surface of the semiconductor chip other than the surface on the side where the integrated circuit is formed and further extending on the back surface of the molding resin layer; a sixth step of forming a heat transfer structure made of a heat transfer body that is thermally connected to the extending portion of the heat transfer layer in a state of being molded in the molding resin layer; a seventh step of arranging the semiconductor chip on a wiring layer provided with wiring, connecting the integrated circuit to the wiring, and forming the semiconductor chip in a state of being molded with the molding resin layer on the wiring layer; and an eighth step of forming a heat sink that is thermally connected to the heat transfer structure on the molding resin layer.

Advantages of the Invention

[0016] As described above, according to the present invention, since a heat transfer layer is formed on the surface of the semiconductor chip, and the heat sink formed on the molding resin layer and the extending portion of the heat transfer layer are connected by a heat transfer structure penetrating the molding resin layer, heat dissipation can be improved without increasing the size of the package, without suppressing the degree of freedom of chip layout and wiring, and without causing malfunction or failure.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 2D

Figure 2E

Figure 2F

Figure 2G

Figure 2H

Figure 2I

Figure 3

Embodiments for Carrying Out the Invention

[0018] Hereinafter, a semiconductor device according to an embodiment of the present invention will be described with reference to FIG. 1. This semiconductor device includes a wiring layer 101, a first semiconductor chip 102 disposed on the wiring layer 101, and a second semiconductor chip (other semiconductor chip) 103. The second semiconductor chip 103 may be made of a material different from that of the first semiconductor chip 102. For example, the first semiconductor chip 102 may be made of a compound semiconductor, and the second semiconductor chip 103 may be made of silicon.

[0019] In the wiring layer 101, a wiring 101a made of metal is formed. On the main surface of the first semiconductor chip 102 facing the wiring layer 101, a first integrated circuit 102a electrically connected to the wiring 101a is formed. On the main surface of the second semiconductor chip 103 facing the wiring layer 101, a second integrated circuit (other integrated circuit) 103a electrically connected to the wiring 101a is formed. The first integrated circuit 102a and the second integrated circuit 103a are connected by the wiring 101a.

[0020] In addition, this semiconductor device includes a first heat transport layer 104 formed on the first semiconductor chip 102 on the wiring layer 101. The first heat transport layer 104 is formed on the surface of the first semiconductor chip 102 where the first integrated circuit 102a is not formed. Further, the first heat transport layer 104 includes a first extending portion 104a extending on the wiring layer 101. The first heat transport layer 104 can be formed on a part of the surface of the first semiconductor chip 102 where the first integrated circuit 102a is not formed. Alternatively, the first heat transport layer 104 can be formed to cover the entire surface of the first semiconductor chip 102 where the first integrated circuit 102a is not formed. By forming to cover the entire area, the effect of heat transport by the first heat transport layer 104 can be enhanced more than forming to cover a part.

[0021] The first heat transfer layer 104 is composed of a heat transfer medium. The heat transfer medium constituting the first heat transfer layer 104 can be made of a material having a higher thermal conductivity than the first semiconductor chip 102, and can be made of, for example, a metal such as aluminum, copper, or gold. For example, when the first semiconductor chip 102 is made of GaN, the heat transfer medium can be Cu.

[0022] Similarly, the second semiconductor chip 103 also includes a second heat transfer layer (other heat transfer layer) 105 formed on the wiring layer 101 and on the second semiconductor chip 103. The second heat transfer layer 105 is formed on the surface of the second semiconductor chip 103 where the second integrated circuit 103a is not formed. Further, the second heat transfer layer 105 includes a second extending portion (other extending portion) 105a extending on the wiring layer 101. The second heat transfer layer 105 can be formed on a part of the surface of the second semiconductor chip 103 where the second integrated circuit 103a is not formed. Alternatively, the second heat transfer layer 105 can be formed to cover the entire surface of the second semiconductor chip 103 where the second integrated circuit 103a is not formed. By forming to cover the entire area, the heat transfer effect by the second heat transfer layer 105 can be enhanced compared to forming to cover a part.

[0023] The second heat transfer layer 105 is composed of a heat transfer medium. The heat transfer medium constituting the second heat transfer layer 105 can be made of a material having a higher thermal conductivity than the second semiconductor chip 103, and can be made of, for example, a metal such as aluminum, copper, or gold. For example, when the second semiconductor chip 103 is made of Si, the heat transfer medium can be Cu.

[0024] Also, the first heat transfer layer 104 and the second heat transfer layer 105 are formed separately (without contacting) on the wiring layer 101 and are formed in insulation separation from each other.

[0025] Further, the first semiconductor chip 102 covered by the first heat transport layer 104 and the second semiconductor chip 103 covered by the second heat transport layer 105 are molded by a mold resin layer 106 made of a mold resin on the wiring layer 101. Note that passive components such as resistors, capacitors, or inductances can be molded by the mold resin layer 106 together with the first semiconductor chip 102 and the second semiconductor chip 103.

[0026] Also, this semiconductor device includes, on the mold resin layer 106, a first heat sink 107 and a second heat sink (other heat sink) 108 formed separately from the first heat sink 107. The first heat sink 107 and the second heat sink 108 can be made of an insulating material such as silicon carbide, aluminum nitride, beryllium oxide, or diamond. Alternatively, the first heat sink 107 and the second heat sink 108 can be made of a metal such as aluminum, copper, or gold.

[0027] Also, a columnar first heat transport structure 109 formed through the mold resin layer 106 is thermally connected (in contact) to the first heat sink 107. The first heat transport structure 109 is thermally connected (in contact) to the first extending portion 104a on the side of the wiring layer 101.

[0028] The first heat transport structure 109 is composed of a heat transport body. This heat transport body can be made of a material having a higher thermal conductivity than the first semiconductor chip 102. This heat transport body can be made of, for example, an insulating material such as silicon carbide, aluminum nitride, beryllium oxide, or diamond, or a metal such as aluminum, copper, or gold. For example, when the first semiconductor chip 102 is made of GaN, the heat transport body can be Cu.

[0029] Similarly, a columnar second heat transport structure (other heat transport structure) 110 formed through the mold resin layer 106 is thermally connected (in contact) to the second heat sink 108. The second heat transport structure 110 is thermally connected (in contact) to the second extending portion 105a on the side of the wiring layer 101.

[0030] The second heat transport structure 110 is composed of a heat transport medium. This heat transport medium can be composed of a material with a higher thermal conductivity than that of the second semiconductor chip 103. This transport structure can be composed of, for example, insulating materials such as silicon carbide, aluminum nitride, beryllium oxide, diamond, and metals such as aluminum, copper, and gold. For example, when the second semiconductor chip 103 is made of Si, the heat transport medium can be Cu.

[0031] According to the semiconductor device according to the above-described embodiment, the heat generated in the first semiconductor chip 102 is transmitted to the first heat sink 107 through the first heat transport layer 104 and the first heat transport structure 109 and diffused into the atmosphere. Further, the heat generated in the second semiconductor chip 103 is transmitted to the second heat sink 108 through the second heat transport layer 105 and the second heat transport structure 110 and diffused into the atmosphere.

[0032] In addition, the first semiconductor chip 102, the first heat transport layer 104, the first heat transport structure 109, and the first heat sink 107, and the second semiconductor chip 103, the second heat transport layer 105, the second heat transport structure 110, and the second heat sink 108 are thermally separated by a mold resin. As a result, while preventing thermal interference between the semiconductor chips, the heat dissipation performance is improved.

[0033] In addition, although the first heat sink 107 and the second heat sink 108 are attached to the first semiconductor chip 102 and the second semiconductor chip 103, respectively, the distance between the chips can be determined regardless of the size of each heat sink in plan view. In addition, it is not necessary to form wiring for heat dissipation in the wiring layer 101. Therefore, there are no increases in the package area, chip layout, or wiring constraints caused by wiring for heat dissipation.

[0034] Note that in this semiconductor device, a terminal 101b is formed under the wiring layer 101, and the wiring layer 101 is electrically connected (mounted) to the printed circuit board 111 via the terminal 101b. In this example, the face-down method of FOWLP and the secondary mounting on the printed circuit board 111 are illustrated, but the effects of the present invention can also be obtained for other methods such as the face-up method of FOWLP and designs without secondary mounting.

[0035] According to the above-described embodiments, without increasing the size of the package and without suppressing the degree of freedom of chip layout and wiring, heat dissipation can be improved without thermal interference between semiconductor chips with different heat generation amounts and without causing malfunction or failure.

[0036] Next, a method for manufacturing a semiconductor device according to the present invention will be described with reference to FIGS. 2A to 2I. First, as shown in FIG. 2A, the formation surface of the first integrated circuit 102a of the first semiconductor chip 102 cut out into chips is attached and fixed to the adhesive layer 122 fixed on the support substrate 121. Also, the formation surface of the second integrated circuit 103a of the second semiconductor chip 103 cut out into chips is attached and fixed to the adhesive layer 122. As described above, the material of the first semiconductor chip 102 may be different from the material of the second semiconductor chip 103. Note that in FIG. 2A, a set of the first semiconductor chip 102 and the second semiconductor chip 103 is shown, but a plurality of sets can be simultaneously fixed (mounted) on the support substrate 121.

[0037] The support substrate 121 only needs to have a size corresponding to a semiconductor manufacturing apparatus used when forming the wiring layer 101 described later. The material of the support substrate 121 can be composed of, for example, a semiconductor such as silicon, glass, resin, metal, or the like. The adhesive layer 122 uses a resin material whose adhesive force weakens by a specific operation. For example, a method that does not deteriorate the characteristics of each integrated circuit, such as a laser peeling method, a thermal peeling method, a mechanical peeling method, or a solvent peeling method, can be selected. The adhesive layer 122 can be composed of a material that can withstand the temperature in the formation of the mold resin layer described later.

[0038] Next, as shown in FIG. 2B, a layer 123 made of a heat transporter is formed on a support substrate 121 (adhesive layer 122) to which a first semiconductor chip 102 and a second semiconductor chip 103 are fixed (second step). For example, a layer 123 made of a heat transporter can be formed on the support substrate 121 (adhesive layer 122) in a state of covering the first semiconductor chip 102 and the second semiconductor chip 103. The layer 123 can be formed, for example, by a known sputtering method or the like.

[0039] Note that, with a lift-off mask formed in advance, the layer 123 is formed by a sputtering method or the like, and then the lift-off mask is removed (lift-off), so that a part of the surface of the first semiconductor chip 102 where the first integrated circuit 102a is not formed and a part of the surface of the second semiconductor chip 103 where the second integrated circuit 103a is not formed are in a state where the layer 123 is formed.

[0040] Next, as shown in FIG. 2C, after the layer 123 is formed, on the support substrate 121 (adhesive layer 122), the first semiconductor chip 102 is molded with a molding resin to form a molding resin layer 106 (third step). The molding resin layer 106 can be formed, for example, by forming a layer of the molding resin by a known compression molding method, a transfer molding method, or the like and curing the formed layer of the molding resin.

[0041] Next, the molding resin layer 106 is separated from the support substrate 121 (fourth step), and as shown in FIG. 2D, the integrated circuit formation surface is exposed. For example, the molding resin layer 106 can be separated from the support substrate 121 by peeling the adhesive layer 122. For example, a method that does not deteriorate the characteristics of each integrated circuit, such as a laser peeling method, a thermal peeling method, a mechanical peeling method, or a solvent peeling method, can be selected.

[0042] Next, after separating the support substrate 121 and the mold resin layer 106, as shown in FIG. 2E, a first heat transport layer 104 including a first extending portion 104a and a second heat transport layer 105 including a second extending portion 105a are formed. For example, the first heat transport layer 104 can be in a state of covering the surface of the first semiconductor chip 102 other than the surface on which the first integrated circuit 102a is formed. Also, the second heat transport layer 105 can be in a state of covering the surface of the second semiconductor chip 103 other than the surface on which the second integrated circuit 103a is formed.

[0043] In addition, when the layer 123 is formed on a part of the surface of the first semiconductor chip 102 where the first integrated circuit 102a is not formed, the first heat transport layer 104 is formed on a part of the surface of the first semiconductor chip 102 where the first integrated circuit 102a is not formed. Similarly, when the layer 123 is formed on a part of the surface of the second semiconductor chip 103 where the second integrated circuit 103a is not formed, the second heat transport layer 105 is formed on a part of the surface of the second semiconductor chip 103 where the second integrated circuit 103a is not formed.

[0044] For example, by performing a selective (partial) etching process using a mask pattern formed by a known photolithography technique to remove a part of the layer 123 formed to cover the back surface of the mold resin layer 106 on the side where the first integrated circuit 102a is formed, the first heat transport layer 104 including the first extending portion 104a can be formed. Also, by performing a selective etching process using a mask pattern to remove a part of the layer 123 formed to cover the back surface of the mold resin layer 106 on the side where the second integrated circuit 103a is formed, the second heat transport layer 105 including the second extending portion 105a can be formed.

[0045] Next, as shown in FIG. 2F, a first heat transport structure 109 made of a heat transport body that is thermally connected to the first extending portion 104a of the first heat transport layer 104 is formed in a state of being molded in the mold resin layer 106. Also, a second heat transport structure 110 made of a heat transport body that is thermally connected to the second extending portion 105a of the second heat transport layer 105 is formed in a state of being molded in the mold resin layer 106 (sixth step).

[0046] For example, holes are formed in the mold resin layer 106 by a laser or the like, and metals such as copper are filled into the formed holes by a plating method or the like, whereby the first heat transport structure 109 and the second heat transport structure 110 can be formed.

[0047] When insulating materials such as silicon carbide, aluminum nitride, beryllium oxide, and diamond are used as the heat transport body, the above-described plating method cannot be applied. In this case, at the stage of attaching and fixing the formation surface of the first integrated circuit 102a of the first semiconductor chip 102 and attaching and fixing the formation surface of the second integrated circuit 103a of the second semiconductor chip 103 on the support substrate 121, the first heat transport structure 109 and the second heat transport structure 110 are formed (attached). In this state, the layer 123 is formed, the mold resin layer 106 is formed, the support substrate 121 is separated, and the first heat transport layer 104 and the second heat transport layer 105 are formed. As a result, in a state of being molded in the mold resin layer 106, the first heat transport structure 109 can be connected (contacted) to the first extending portion 104a, and the second heat transport structure 110 can be connected (contacted) to the second extending portion 105a.

[0048] Next, as shown in FIG. 2G, the first semiconductor chip 102 and the second semiconductor chip 103 are formed (mounted) on the wiring layer 101 including the wiring 101a. The first integrated circuit 102a and the second integrated circuit 103a are connected to the wiring 101a. Further, on the wiring layer 101, the first semiconductor chip 102 and the second semiconductor chip 103 are molded with the mold resin layer 106 (seventh step).

[0049] For example, on the first semiconductor chip 102 and the second semiconductor chip 103 molded by the molding resin layer 106, the wiring layer 101 can be formed by the build-up method. For example, after molding the first semiconductor chip 102 and the second semiconductor chip 103 with the molding resin layer 106, a metal layer is formed on the molding resin layer 106 by, for example, vapor deposition or plating method, and the wiring 101a can be formed by patterning this metal layer to obtain the wiring layer 101. Further, a terminal 101b connected to the wiring 101a is formed on the wiring layer 101 by, for example, solder bumps or the like.

[0050] Next, as shown in FIG. 2H, the molding resin layer 106 is thinned so that the upper surfaces of the first heat transport structure 109 and the second heat transport structure 110 are exposed. For example, by mechanically polishing (grinding and polishing) the surface of the molding resin layer 106 with a grinder or the like, the upper surfaces of the first heat transport structure 109 and the second heat transport structure 110 are exposed.

[0051] Next, as shown in FIG. 2I, a first heat sink 107 thermally connected to the first heat transport structure 109 and a second heat sink 108 thermally connected to the second heat transport structure 110 are formed on the thinned molding resin layer 106 (eighth step). For example, a layer of a metal such as aluminum, copper, or gold is formed on the thinned molding resin layer 106 by a plating method or the like. Then, the formed metal layer is patterned by known photolithography technology and etching technology to form the first heat sink 107 and the second heat sink 108.

[0052] Thereafter, using a dicing device, the first semiconductor chip 102 and the second semiconductor chip 103 are singulated for each set. Thereafter, by mounting on the printed circuit board 111 via the terminals 101b of the package formed by the set of the singulated first semiconductor chip 102 and the second semiconductor chip 103, the semiconductor device shown in FIG. 1 is obtained. For example, when using solder bumps, it can be mounted by known reflow technology.

[0053] As described above, according to the present invention, a heat transport layer is formed on the surface of the semiconductor chip, and the heat sink formed on the mold resin layer and the extending portion of the heat transport layer are connected by a heat transport structure penetrating the mold resin layer. Therefore, without increasing the size of the package, and without restricting the degree of freedom of chip layout and wiring, the heat dissipation can be improved without causing malfunction or failure.

[0054] It should be noted that the present invention is not limited to the embodiments described above, and it is obvious that many modifications and combinations can be implemented by those having ordinary knowledge in the art within the technical idea of the present invention.

Explanation of Reference Numerals

[0055] 101... Wiring layer, 101a... Wiring, 101b... Terminal, 102... First semiconductor chip, 102a... First integrated circuit, 103... Second semiconductor chip (other semiconductor chips), 103a... Second integrated circuit (other integrated circuits), 104... First heat transport layer, 104a... First extending portion, 105... Second heat transport layer (other heat transport layers), 105a... Second extending portion (other extending portions), 106... Mold resin layer, 107... First heat sink, 108... Second heat sink (other heat sinks), 109... First heat transport structure, 110... Second heat transport structure (other heat transport structures), 111... Printed circuit board.

Claims

1. A wiring layer on which wirings are formed, a semiconductor chip disposed on the wiring layer, an integrated circuit formed on a main surface of the semiconductor chip facing the wiring layer side and connected to the wiring, a heat transport layer formed of a heat transport body formed on a surface of the semiconductor chip where the integrated circuit is not formed and further having an extending portion extending on the wiring layer, a mold resin layer made of a mold resin that molds the semiconductor chip covered by the heat transport layer on the wiring layer, a heat sink formed on the mold resin layer, a heat transport structure formed of a heat transport body that penetrates the mold resin layer and thermally connects the extending portion of the heat transport layer and the heat sink and comprising another semiconductor chip different from the semiconductor chip disposed on the wiring layer, another integrated circuit formed on a main surface of the other semiconductor chip facing the wiring layer side and connected to the wiring, another heat transport layer formed of a heat transport body formed on a surface of the other semiconductor chip where the other integrated circuit is not formed and further having another extending portion extending on the wiring layer, the mold resin layer that molds the other semiconductor chip covered by the other heat transport layer on the wiring layer, another heat sink formed on the mold resin layer and spaced apart from the heat sink, another heat transport structure formed of a heat transport body that penetrates the mold resin layer and thermally connects the other extending portion of the other heat transport layer and the other heat sink and further comprising a semiconductor device.

2. The semiconductor device according to claim 1, wherein a material of the semiconductor chip is different from a material of the other semiconductor chip.

3. A first step of fixing a semiconductor chip having an integrated circuit formed on a main surface on a support substrate with the surface on which the integrated circuit is formed, a second step of forming a layer made of a heat transport body on the support substrate on which the semiconductor chip is fixed, a third step of molding the semiconductor chip with a mold resin to form a mold resin layer after forming a layer made of a heat transport body on the support substrate, a fourth step of separating the support substrate and the mold resin layer After separating the support substrate and the mold resin layer, a part of the layer formed to cover the back surface of the mold resin layer on the side where the integrated circuit is formed is removed, and a heat transport layer is formed on a surface of the semiconductor chip other than the surface on the side where the integrated circuit is formed and further including an extending portion extending on the back surface of the mold resin layer. The fifth step is as follows: The sixth step is to form a heat transport structure made of a heat transport body that is thermally connected to the extending portion of the heat transport layer in a state of being molded in the mold resin layer. The seventh step is to dispose the semiconductor chip on a wiring layer provided with wiring, connect the integrated circuit to the wiring, and form the semiconductor chip in a state of being molded by the mold resin layer on the wiring layer. The eighth step is to form a heat sink on the mold resin layer that is thermally connected to the heat transport structure. A method for manufacturing a semiconductor device including the above steps.

4. In the method for manufacturing a semiconductor device according to claim 3, The first step includes a step of fixing another semiconductor chip having another integrated circuit formed on a main surface on the support substrate with the surface on which the other integrated circuit is formed. The second step includes a step of forming the layer made of a heat transport body on the support substrate on which the semiconductor chip and the other semiconductor chip are fixed. The third step includes a step of molding the semiconductor chip and the other semiconductor chip with a mold resin to form the mold resin layer. The fifth step includes, after separating the support substrate and the mold resin layer, removing a part of the layer formed to cover the back surface of the mold resin layer on the side where the other integrated circuit is formed, forming an other heat transport layer on a surface of the other semiconductor chip other than the surface on the side where the other integrated circuit is formed, and further including an other extending portion extending on the back surface of the mold resin layer. The sixth step includes a step of forming an other heat transport structure made of a heat transport body that is thermally connected to the other extending portion of the other heat transport layer in a state of being molded in the mold resin layer. The seventh step includes a step of disposing the other semiconductor chip on the wiring layer, connecting the other integrated circuit to the wiring, and forming the other semiconductor chip in a state of being molded by the mold resin layer on the wiring layer. The eighth step includes a step of forming another heat sink that is thermally connected to the other heat transport structure on the mold resin layer and spaced apart from the heat sink. A method for manufacturing a semiconductor device, characterized by the above.

5. In the method for manufacturing a semiconductor device according to claim 4, A method for manufacturing a semiconductor device, characterized in that the material of the semiconductor chip is different from the material of the other semiconductor chip.

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