User-configurable SLC memory size

Abstract

An embodiment of an electronic device may include one or more substrates; and a controller coupled to the one or more substrates, where the controller includes logic to control access to a NAND based storage medium including a first region of cells having a first number of levels and a second region having a second number of levels different than the first number of levels, determine a logical block address location corresponding to a user configurable capacity placeholder, and adjust a size of each of the first region of cells and the second region of cells at run time based on the logical block address location. Other embodiments are disclosed and claimed.

Description

Background Art

[0001] [Cross - Reference to Related Applications] This application claims the benefit of U.S. Patent Application No. 17 / 231,893, filed on April 15, 2021, which is hereby incorporated by reference in its entirety.

[0002] A single - level cell (SLC) buffer may include a NAND - type flash memory (NAND memory) composed of a plurality of cells, and each cell contains 1 bit of data. A triple - level cell (TLC) memory may include a NAND memory composed of a plurality of cells, and each cell contains 3 bits of data. A quad - level cell (QLC) memory may include a NAND memory composed of a plurality of cells, and each cell contains 4 bits of data. The number of bits per cell may generally depend on how many distinct voltage levels are used during program operations related to writing to the cell, reading from the cell, and / or erasing the cell. Thus, in the case of TLC memory, to support 3 bits per cell, 8 voltage levels are used to distinguish 8 possible combinations of 1s and 0s (e.g., 000, 001, 010, 011, 100, 101, 110, 111) that can be written to the cell.

[0003] Some storage systems include techniques for determining a programmable erasure rate associated with a storage device and converting a portion of the SLC area within the storage device to a multi - level cell (MLC) area according to this programmable erasure rate. Examples of MLC may include TLC (e.g., 3 - bit or 8 - level MLC), QLC (e.g., 4 - bit or 16 - level MLC), etc. For example, the amount of the portion converted to the MLC area gradually changes according to the percentage of the capacity satisfied in the storage device.

[0004] Some storage systems may include dynamic SLC memory controller technology. For example, the controller can determine the amount of valid data in the dynamic portion of the SLC area at runtime and adjust the size of the dynamic portion of the SLC area at runtime based on the determined amount of valid data in the dynamic portion of the SLC area.

[0005] Some storage systems may include multi-level memory repurposing technology. For example, the memory controller can reprovision the persistent storage medium in response to a request to change the settings of the persistent storage medium.

Brief Description of the Drawings

[0006] The subject matter described herein is illustrated by way of example and not as a limitation in the accompanying drawings. For the sake of brevity and clarity, the elements shown in the drawings are not necessarily drawn to scale. For example, the dimensions of some elements may be exaggerated relative to other elements for clarity. Further, reference numerals may be repeated between the drawings to indicate corresponding or similar elements where appropriate. The drawings are as follows.

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[0015] With reference to the accompanying drawings, one or more embodiments or implementation examples are described herein. It should be understood that the description of specific configurations and arrangements is for illustrative purposes only. Those skilled in the art will recognize that other configurations and arrangements may be used without departing from the spirit and scope of this specification. It will be apparent to those skilled in the art that the methods and / or arrangements described herein can also be used in various other systems and applications other than those described herein.

[0016] In the following description, various implementation examples that may be manifested in architectures such as, for example, a system-on-chip (SoC) architecture are described. However, the implementation of the techniques and / or arrangements described herein is not limited to a particular architecture and / or computing system, and may be implemented by any architecture and / or computing system for similar purposes. For example, the techniques and / or arrangements described herein may be implemented by various architectures using, for example, multiple integrated circuit (IC) chips and / or packages, and / or various computing devices and / or consumer electronics (CE) devices such as set-top boxes, smartphones, and the like. Further, the following description may describe a number of specific details, such as, for example, implementation examples of logic, types and interrelationships of system components, selection of logic partitioning / integration, etc. However, the claimed subject matter can be practiced even without such specific details. In other instances, some topics, such as, for example, control structures and complete software instruction sequences, may not be shown in detail so as not to obscure the subject matter disclosed herein.

[0017] The subject matter disclosed herein may be implemented in hardware, firmware, software, or any combination thereof. The subject matter disclosed herein may also be implemented as instructions stored on a machine-readable medium, which can be read and executed by one or more processors. A machine-readable medium may include any medium and / or mechanism for storing or transmitting information in a form readable by a machine (e.g., a computing device). For example, a machine-readable medium may include read-only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory devices; electrical, optical, acoustic, or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.), and others.

[0018] References to "one implementation example", "an implementation example", "an exemplary implementation example", etc. in this specification indicate that the described implementation example may include certain features, structures, or characteristics, but not every embodiment necessarily includes such specific features, structures, or characteristics. Further, such language does not necessarily refer to the same implementation example. Additionally, when a particular feature, structure, or characteristic is described in relation to one embodiment, it is stated that it is within the knowledge of those skilled in the art to bring such feature, structure, or characteristic in relation to other embodiments, whether or not explicitly described herein.

[0019] The various embodiments described herein may include memory components and / or interfaces to memory components. Such memory components may include volatile and / or non-volatile (NV) memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored thereon. Non-limiting examples of volatile memory may include various types of RAM such as dynamic RAM (DRAM) or static RAM (SRAM). A particular type of DRAM may be used in a memory module, which is synchronous dynamic RAM (SDRAM). NV memory (NVM) may be a storage medium that does not require power to maintain the state of data stored thereon. In one embodiment, the memory device may include a block-addressable memory device, for example, based on NAND technology. In one embodiment, the memory device may or may not include a NAND flash memory having multiple threshold levels or other memory using memory devices. The memory device may refer to the die itself and / or the packaged memory product.

[0020] Referring to FIG. 1, one embodiment of an electronic storage system 10 may include a NAND-based storage medium 12 including a first cell region 12a having a first number of levels and a second region 12b having a second number of levels different from the first number of levels, and a controller 11 communicatively coupled to the NAND-based storage medium 12. The controller 11 may include logic 13 that determines a logical block address (LBA) position corresponding to a user-configurable capacity placeholder and adjusts the respective sizes of the first cell region 12a and the second cell region 12b at runtime based on the LBA position. In some embodiments, the logic 13 may further be configured to enable a function of user-configuring the size of the first cell region 12a in response to a command. For example, the logic 13 may be configured to reserve a range of LBAs to manage the capacity conversion between the first cell region 12a and the second cell region 12b.

[0021] In some embodiments, the logic 13 may further be configured to store user data in the NAND-based storage medium 12 when this function is enabled. For example, the logic 13 may be configured to convert blocks of the second cell region 12b into blocks of the first cell region 12a and move the data of the second cell region 12b to the converted blocks of the first cell region 12a. In any of the embodiments herein, the controller 11 and the NAND-based storage medium 12 may be incorporated into a solid state drive (SSD).

[0022] Embodiments for each of the system components such as the above-described controller 11, NAND-based storage medium 12, logic 13, etc. may be implemented in hardware, software, or any suitable combination thereof. For example, hardware implementation examples may include configurable logic such as, by way of example, programmable logic arrays (PLAs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), or fixed-function logic hardware using circuit technologies such as, by way of example, application specific integrated circuits (ASICs), complementary metal oxide semiconductors (CMOS), or transistor-transistor logic (TTL) technologies, or any combination thereof. Embodiments of the controller 11 may include general-purpose controllers, special-purpose controllers, memory controllers, storage controllers, microcontrollers, general-purpose processors, special-purpose processors, central processing unit (CPU), execution units, etc. In some embodiments, the NAND-based storage medium 12, logic 13, and / or other system memories may be disposed within various components including the controller 11, or may be disposed in the same location (e.g., on the same die) as it.

[0023] Alternatively, or in addition, all or some of these components may be implemented as a set of logic instructions stored in a machine-readable or computer-readable storage medium (e.g., RAM, ROM, programmable ROM (PROM), firmware, flash memory, etc.) executed by a processor or computing device. For example, the computer program code for executing the operations of the components may be written in any combination of one or more programming languages applicable / appropriate to the operating system (OS), including object-oriented programming languages such as Python®, Perl, Java®, Smalltalk®, C++, C#, etc., and conventional procedural programming languages such as the "C" programming language or similar programming languages. For example, a NAND-based storage medium 12, another NAND-based storage medium, or other system memory may store the instruction set, and when executed by the controller 11, the instruction set causes the system 10 to implement one or more components, features, or aspects of the system 10 (e.g., logic 13, determining the LBA position corresponding to the user-configurable capacity placeholder, adjusting the respective sizes of the first cell region 12a and the second cell region 12b at runtime based on the LBA position, etc.).

[0024] Referring now to FIG. 2, one embodiment of the electronic device 14 may include one or more substrates 15 and a controller 16 coupled to the one or more substrates 15. The controller 16 may include logic 17 that controls access to a NAND-based storage medium that includes a first cell region having a first level count and a second region having a second level count different from the first level count, determines LBA positions corresponding to user-configurable capacity holders, and adjusts the respective sizes of the first cell region and the second cell region at runtime based on the LBA positions. In some embodiments, the logic 17 may further be configured to enable a function of user-configuring the size of the first cell region in response to a command. For example, the logic 17 may be configured to reserve a range of LBAs to manage capacity conversion between the first cell region and the second cell region.

[0025] In some embodiments, the logic 17 may further be configured to store user data in the NAND-based storage medium when this function is enabled. For example, the logic 17 may be configured to convert blocks of the second cell region into blocks of the first cell region and move data of the second cell region to the converted blocks of the first cell region. In any of the embodiments herein, the controller 16 and the NAND-based storage medium may be incorporated into an SSD.

[0026] Embodiments of logic 17 may be implemented in, for example, a system, apparatus, computer, device, etc. as described herein. More specifically, examples of hardware implementations of logic 17 may include configurable logic such as PLA, FPGA, CPLD, or fixed-function logic hardware using circuit technologies such as ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively, or in addition, logic 17 may be implemented in one or more modules as a set of logic instructions executed by a processor or computing device stored in a machine-readable or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc. For example, the computer program code for executing the operations of the components may be described in any combination of one or more programming languages applicable / appropriate to the OS, including object-oriented programming languages such as Python®, Perl, Java®, Smalltalk®, C++, C#, etc., and conventional procedural programming languages such as the "C" programming language or similar programming languages.

[0027] For example, logic 17 may be implemented in a semiconductor device, which may include one or more substrates 15, and logic 17 may be coupled to the one or more substrates 15. In some embodiments, logic 17 may be at least partially implemented in one or more of configurable logic and fixed-function hardware logic on a semiconductor substrate (e.g., silicon, sapphire, gallium arsenide, etc.). For example, logic 17 may include a transistor array and / or other integrated circuit components coupled to a substrate 15 having a channel region of a transistor disposed within the substrate 15. The interface between logic 17 and substrate 15 may not be a step junction. Logic 17 may be considered to include an epitaxial layer grown on the initial wafer of substrate 15.

[0028] Referring now to FIG. 3, one embodiment of a method 20 for controlling storage may include a step of controlling access to a NAND-based storage medium including a first cell region having a first level number and a second region having a second level number different from the first level number in block 21, a step of determining an LBA position corresponding to a user-configurable capacity placeholder in block 22, and a step of adjusting the respective sizes of the first cell region and the second cell region at runtime based on the LBA position in block 23. In some embodiments of method 20, further, in block 24, it may include a step of enabling a function of user-configuring the size of the first cell region in response to a command. For example, method 20 may include a step of reserving a range of LBAs in block 25 to manage capacity conversion between the first cell region and the second cell region.

[0029] In some embodiments, method 20 may further include, in block 26, a step of storing user data in the NAND-based storage medium when this function is enabled. For example, method 20 may include a step of converting blocks of the second cell region into blocks of the first cell region in block 27, and a step of moving data of the second cell region to the converted blocks of the first cell region in block 28. In any of the embodiments herein, the NAND-based storage medium may be incorporated into an SSD in block 29.

[0030] Embodiments of method 20 may be implemented, for example, in a system, apparatus, computer, device, etc. as described herein. More specifically, hardware implementation examples of method 20 may include configurable logic such as PLA, FPGA, CPLD, coarse-grained reconfigurable fabric (CGRA), or fixed-function logic hardware using circuit technologies such as ASIC, CMOS, or TTL technology, or any combination thereof. Alternatively, or in addition, method 20 may be implemented as a set of logic instructions executed by a processor or computing device stored in a machine-readable or computer-readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc. For example, the computer program code for executing the operations of the components may be described in any combination of one or more programming languages applicable / appropriate to the OS, including object-oriented programming languages such as Python®, Perl, Java®, Smalltalk®, C++, C#, etc., and conventional procedural programming languages such as the "C" programming language or similar programming languages.

[0031] For example, method 20 may be implemented in a computer-readable medium as described in Examples 22-28 below. Embodiments of method 20 or portions thereof may be implemented in firmware, an application (e.g., through an application programming interface (API)), or driver software operating in an operating system (OS). Further, the logic instructions may include assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, state setting data, integrated circuit setting data, and other structural components specific to an electronic circuit and / or hardware (e.g., a host processor, a central processing unit / CPU, a microcontroller, etc.), and may include state information for individuating them.

[0032] In some embodiments, advantageously, a technique can be provided that enables user configuration of the SLC buffer / cache size while storing user data for a NAND storage device. Typically, when provisioning a NAND storage device that has multiple bits per cell, an SLC cache or buffer may be provisioned to improve the performance of the device. However, since each cell dedicated to the SLC buffer has only one bit, the overall capacity of the drive is reduced. In a file system and a partitioning system, a portion of its data structure is placed depending on the drive capacity. Since the overall capacity of the device is determined based on the size of the SLC buffer, the user cannot resize the amount of SLC according to their own needs without risking data loss and file system corruption. User selections regarding the trade-off between performance (e.g., SLC size) and overall capacity (e.g., QLC size, TLC size, etc.) can be made at the time of provisioning. To change the trade-off selected by the user, the contents of the drive must be erased.

[0033] In a storage system with a dynamic SLC buffer, the size of the SLC buffer can be adjusted at runtime. However, this adjustment is not user-configurable. The user cannot select how the drive trades off performance and capacity, and the user cannot reserve a certain amount of SLC on the drive. In a storage system with a multi-level memory repurposing technique (e.g., just-in-time block repurposing), the storage medium may be reconfigured based on user requests, but generally, the drive needs to be taken offline to change the reported capacity of the drive, which disrupts the operation of the file system. In some embodiments, it is advantageous because a technique is provided that overcomes one or more of the aforementioned problems.

[0034] In some embodiments, host software components such as storage drivers can be utilized to create files in the file system of a storage device. The created files will not contain data. After the LBA positions associated with the created files are communicated to the SSD's firmware, the SSD can increase the SLC buffer of the SSD by a corresponding amount based on the NAND erase block (EB) characteristics of individual devices. In an SLC-QLC device, for example, that increase will correspond to a ratio of 4:1.

[0035] It is advantageous for the user to control the configurability of SLC. For example, if the user has a QLC-based SSD and realizes that the applications use less than one-quarter (1 / 4) of the SSD's capacity, in some embodiments, the user can configure the storage system to be 100% SLC without losing the user data already on the drive. Later, if the user needs more capacity, again without losing or corrupting the data currently on the device, the user can revert this operation or provision a drive with a different ratio as needed.

[0036] Reclaimed SLC may be utilized for any useful storage needs. For example, in one embodiment, an application may utilize the freed SLC for an intelligent caching solution (not just as a write buffer, for example). It is advantageous for the SSD device to be shipped with the ability to utilize its maximum capacity (e.g., corresponding to a preferred cost / gigabyte (GB) value). The user can, at deployment, while saving user data, reconfigure the trade-off between performance and capacity at runtime as needed.

[0037] In some embodiments, a mechanism can be provided that utilizes a host software driver and a file system to enable a user to make seamless trade-offs between capacity and performance. For example, to make certain LBA ranges of an SSD inaccessible from the rest of the system (e.g., the OS, other applications, etc.) and instead reserve them for firmware (FW) management of capacity conversion between QLC and SLC, a capacity placeholder or padding file can be created to achieve the desired trade-off. For example, since SLC access provides better performance than QLC, the user may choose the trade-off of increasing the SLC capacity.

[0038] In some embodiments, the padding file is created when the corresponding feature is enabled. For example, the LBA range may be sent to the SSD via vendor-specific commands, and then the padding file will be opened for exclusive access reserved by some daemon service every time the OS is initialized. After the SSD's FW receives the LBA range and determines how many new SLC blocks need to be created, the FW creates additional SLCs by moving data from the current QLC blocks to the new SLC blocks as needed. The padding file will exist if the corresponding feature is enabled.

[0039] Referring to FIG. 4, one embodiment of process flow 40 shows how a user can reconfigure a 1 terabyte (TB) drive. Before enabling the function to user-configure the SLC capacity, the entire 1TB of the drive may be available to the OS and file system. After the user enables this function and requests the maximum SLC capacity, 100% of the drive is converted to SLC storage. In a QLC drive, this results in a 256GB SLC capacity with much better read and write access performance (e.g., a 4:1 capacity reduction from 1024GB of the drive converted from QLC to SLC). A 768GB padding file is created as a capacity placeholder to occupy the remaining portion of the original 1TB. It is advantageous for the padding file to make the drive appear to the OS and file system as if the SSD has not changed. Even though the drive has been reconfigured, the system can continue to operate normally without the need for hardware reprovisioning to account for the physical change in capacity.

[0040] Referring to FIG. 5, one embodiment of process flow 50 shows another example of how a user can reconfigure a 1TB drive. Before enabling the function to user-configure the SLC capacity, the entire 1TB of the drive may be available to the OS and file system. After the user enables this function and requests 50% SLC capacity, 50% of the drive is converted to SLC storage. In a QLC drive, this results in a 128GB SLC capacity with much better read and write access performance (e.g., a 4:1 capacity reduction from 512GB of the drive converted from QLC to SLC). A 384GB padding file is created as a capacity placeholder to occupy the remaining portion of the original 512GB converted to SLC. It is advantageous for the padding file to make the drive appear to the OS and file system as if the SSD has not changed. Even though the drive has been reconfigured, the system can continue to operate properly without the need for hardware reprovisioning to account for the physical change in capacity.

[0041] In some embodiments, the actual split of the specified ratio may be set by the user in a graphical user interface (GUI). For example, in this interface, specific NAND cell characteristics of the drive can be queried. In this interface, the capacity trade-off can also be determined and communicated to the user. As illustrated in FIGS. 4 and 5, in a QLC SSD, this function requires reserving 4 bits for each bit of reclaimed SLC. In a NAND-type SSD that supports multiple formats in addition to SLC and QLC, embodiments of this function may be configured to perform conversions between other supported formats (e.g., multi-level cell (MLC), TLC, etc.).

[0042] Referring to FIG. 6, an embodiment of the storage system 60 may include a file system with a plurality of files. The file system creates a file that is converted to an LBA position. The LBA position is then converted to a NAND cell position using a logical-to-physical (L2P) table by the SSD's FW. The SSD may include a certain amount of SLC that is utilized as a buffer / cache by the SSD's FW. In some embodiments, when the user-configurable function is enabled, the SSD's FW creates an L2P entry for locations that are not mapped to a physical NAND position (e.g., identified as reclaimed LBA in FIG. 6). Such locations are assigned to padding files, so the SSD's FW recognizes that these locations cannot be mapped to valid data. Thus, the SSD's FW can create more SLC (e.g., identified as reclaimed SLC in FIG. 6) to improve the performance of the storage device. For example, if the SSD has sufficient QLC blocks for 1TB but 512GB of that space is reserved when the user enables the user-configurable function, the SSD's FW can safely use the QLC capacity corresponding to that 512GB for 128GB SLC blocks. Since these embodiments utilize the SSD's L2P indirect table to indicate locations associated with padding files, fragmentation of the padding files is not a problem.

[0043] In some embodiments, when using a padding file as a capacity placeholder to secure space in this way, there is a certain risk that the LBA position assigned to the padding file will be changed. In some embodiments, a change to the LBA position assigned to padding is detected by the SSD's FW itself through a fail-safe function, and the function can be automatically rolled back. In some embodiments, the fail-safe function refers to detecting a write that occurs at the secured LBA and then correcting the mapping back of the SLC to the QLC. If the SSD's FW ever receives a write (or, for example, TRIM) request to any LBA within the secured LBA range, the SSD's FW immediately cancels this function internally (e.g., disables the user-configured function), converts any valid SLC data within that range to QLC, and can return to a NAND setting that does not use any reclaimed SLC (e.g., the setting before the user enabled this function, or the original setting). Note that since the SSD can return zeros (e.g., similar to what the SSD does when reading a trimmed location), safe reads can be issued to the padding file on the host system.

[0044] For example, if the file system is mounted as a data drive on an OS that does not recognize this function and the LBAs previously reserved by the FW are erased or overwritten, write requests for LBAs within the reserved range may occur. Another possibility for activating the fail-safe function is file system corruption. In the process of restoring this function, the NAND garbage collection process of the SSD that converts SLC to QLC may be activated, resulting in a temporary performance degradation but no data loss. For example, this conversion process can be performed by utilizing appropriate operation codes (e.g., opcode) or function sets that can set the entire NAND die to the desired format (e.g., SLC, MLC, TLC, QLC, etc.). The FW of the SSD identifies the target block and the target format. The FW of the SSD first converts the NAND die to the target format and issues specific operations (e.g., erase, program, or read) to the target block. The conversion process can be performed for each target block, and the FW of the SSD maintains the target format for each target block.

[0045] In addition to enabling and disabling the user-set function, the associated host software should minimize the situations in which the fail-safe function is activated as much as possible and play a role in recovering from the fail-safe function when the fail-safe function occurs. To facilitate this, it is necessary to assign padding files to the most restrictive file system access properties to prevent the most problematic programs or users from activating the fail-safe function. Host file system functions such as file system compression that may interfere with the user-set function need to be disabled, and problematic operations such as writes, moves, file creations, or file deletions must be captured and processed by appropriate host file system filters.

[0046] For the system to function properly, the LBA position of the padding file in the file system must match what is designated as reclaimed in the L2P of the SSD firmware. To ensure this, at power-on, the host software manually requests this information from the SSD and checks for any differences. If the SSD's FW detects a mismatch, the SSD's FW notifies the host driver.

[0047] Based on the mismatch notification, the host driver can either completely disable this function or attempt to correct the mismatch. Correction of the mismatch is possible only if there is still enough unused capacity to create a padding file of the desired size. For example, if a user deletes a 512GB padding file in a system without protective host SW for this function and then fills the SSD so that the free space is less than 512GB, it is not possible to create a 512GB padding file. In this case, the function simply becomes disabled.

[0048] In some embodiments, a driver component of the pre-OS or Unified Extensible Firmware Interface (UEFI) is not required because there is no need to access the padding file before the OS boots and operates (e.g., host SW components for user-configured functions are not required until OS initialization).

[0049] In an alternative embodiment, a separate padding partition may be used in place of a padding file as a capacity placeholder for the reclaimed portion of the SSD's capacity. Using a padding partition as a capacity placeholder may be similar to using a padding file, except when a user desires to consume capacity to create more SLCs. In this situation, the original data partition may span into larger LBA space where its file is, and there may not be enough free capacity at the beginning or end of the partition to shrink the data partition sufficiently. In the case of certain files, such as a paging file, it may not even be possible to move the file during runtime. Thus, an "offline" environment such as UEFI may be required to move these types of protection files. In any embodiment, the data layout of the SSD's LBA space is used to ensure that there are places recognized as unused and unmapped so that the SSD can allocate faster SLCs than those set by the user.

[0050] The techniques described herein may be provided to various computing systems (including non-portable computing devices such as desktop, workstation, server, rack systems, etc., portable computing devices such as smartphones, tablets, ultra-mobile personal computers (UMPCs), laptop computers, Ultrabook computing devices, smartwatches, smart glasses, smart bracelets, etc., and / or client / edge devices such as Internet of Things (IoT) devices (e.g., sensors, cameras, etc.)).

[0051] Referring now to FIG. 7, one embodiment of computing system 100 may include one or more processors 102-1 through 102-N (herein generally referred to as "the plurality of processors 102" or "processor 102"). The plurality of processors 102 can communicate via an interconnect or bus 104. Each processor 102 may include various components, and for clarity, only a portion of them will be described with reference to processor 102-1. Thus, each of the remaining processors 102-2 through 102-N may include the same or similar components as those described with reference to processor 102-1.

[0052] In some embodiments, processor 102-1 may include one or more processor cores 106-1 through 106-M (herein referred to as "the plurality of cores 106" or more generally "core 106"), a cache 108 (which may be a shared cache or a private cache in various embodiments), and / or a router 110. The processor cores 106 may be implemented on one integrated circuit (IC) chip. Further, the chip may include one or more shared caches and / or private caches (such as cache 108), a bus or interconnect (such as bus or interconnect 112), logic 170, a memory controller, or other components.

[0053] In some embodiments, router 110 may be used to communicate between processor 102-1 and / or various components of system 100. Further, processor 102-1 may include more than one router 110. Further, multiple routers 110 may communicate to enable data routing between various components internal or external to processor 102-1.

[0054] Cache 108 may store data (e.g., including instructions) used by one or more components (such as core 106) of processor 102-1. For example, cache 108 may locally cache data stored in memory 114 so that components of processor 102 can access it more quickly. As shown in FIG. 7, memory 114 can communicate with processor 102 via interconnect 104. In some embodiments, cache 108 (which may be shared) may have various levels. For example, cache 108 may be an intermediate-level cache and / or a last-level cache (LLC). Also, each of cores 106 may include a level 1 (L1) cache (116-1), which is generally referred to herein as "L1 cache 116". Various components of processor 102-1 can communicate directly with cache 108 through a bus (e.g., bus 112) and / or a memory controller or hub.

[0055] As shown in FIG. 7, memory 114 may be coupled to other components of system 100 through memory controller 120. Memory 114 may include volatile memory and may sometimes be referred to indistinguishably as main memory or system memory. Although memory controller 120 is shown as being coupled between interconnect 104 and memory 114, memory controller 120 may be located elsewhere in system 100. For example, in some embodiments, memory controller 120 or a portion thereof may be provided in one of the plurality of processors 102.

[0056] System 100 can communicate with other devices / systems / networks via a network interface 128 that communicates with a computer network and / or cloud 129 (e.g., via a wired or wireless interface). For example, network interface 128 may include an antenna (not shown) for communicating wirelessly (e.g., via Institute of Electrical and Electronics Engineers (IEEE) 802.11 interface (including IEEE 802.11a / b / g / n / ac, etc.), cellular interface, 3G, 4G, LTE, Bluetooth® etc.) with network / cloud 129.

[0057] System 100 may also include a storage device such as SSD 130 connected to interconnect 104 via SSD controller logic 125. Thus, logic 125 can control access to SSD 130 by various components of system 100. Further, even though logic 125 is shown in FIG. 7 as being directly connected to interconnect 104, logic 125 may alternatively communicate with one or more other components of system 100 via a storage bus / interconnect (e.g., Serial Advanced Technology Attachment (SATA) bus, Peripheral Component Interconnect (PCI) (or PCI Express (PCIe) interface), Non-Volatile Memory Express (NVMe), etc.) (e.g., if the storage bus is connected to interconnect 104 via some other logic such as a bus bridge, chipset, etc.). Further, logic 125 may be incorporated into memory controller logic (e.g., as described with reference to FIG. 8), or may be provided in the same integrated circuit (IC) device in various embodiments (e.g., on the same circuit board device as SSD 130, or within the same housing as SSD 130).

[0058] Furthermore, logic 125 and / or SSD 130 may be connected to one or more sensors (not shown) to receive the status of the values detected by the one or more sensors or information indicating the values (e.g., in the form of one or more bits or signals). These sensors may be provided in proximity to components of system 100 (or other computing systems described herein), including core 106, interconnects 104 or 112, components external to processor 102, SSD 130, SSD bus, SATA bus, logic 125, logic 160, logic 170, etc., to detect various factors that affect the power / thermal behavior of the system / platform, such as variations in temperature, operating frequency, operating voltage, power consumption, and / or communication activity between cores.

[0059] FIG. 8 illustrates a block diagram of various components of SSD 130 in accordance with one embodiment. As shown in FIG. 8, logic 160 may be located in various locations, such as inside SSD 130 or controller 382, and may include similar techniques described in connection with FIG. 7. SSD 130 includes controller 382 (which further includes one or more processor cores or processors 384 and memory controller logic 386), cache 138, RAM 388, firmware storage 390, and one or more memory devices 392-1 to 392-N (collectively memory 392, which may include NAND media or other types of non-volatile memory). Memory 392 is connected to memory controller logic 386 via one or more memory channels or buses. Also, SSD 130 communicates with logic 125 via an interface (such as an interface such as SATA, SAS, PCIe, NVMe, etc.). Processor 384 and / or controller 382 can compress / decompress data written to or read from memory devices 392-1 to 392-N.

[0060] As shown in FIGS. 7 and 8, SSD 130 may include logic 160, which may be within the same housing as SSD 130 and / or may be fully integrated on the printed circuit board (PCB) of SSD 130. System 100 may further include logic 170 that is external to SSD 130. One or more of the features / aspects / operations described with reference to FIGS. 1-6 may be performed by one or more of the components of FIGS. 7 and / or 8. Also, one or more of the features / aspects / operations of FIGS. 1-6 may be programmed into firmware 390. Further, SSD controller logic 125 may also include logic 160. Advantageously, logic 160 and / or logic 170 may include techniques for implementing one or more aspects of any of system 10 (FIG. 1), apparatus 14 (FIG. 2), method 20 (FIG. 3), process flow 40 (FIG. 4), process flow 50 (FIG. 5), storage system 60 (FIG. 6), and / or the functions described herein. For example, logic 170 may include techniques for implementing aspects related to the host device / computer system / agent of the various embodiments described herein, and logic 160 may include techniques for implementing aspects related to the storage device of the various embodiments described herein.

[0061] For example, memory 392 may include a NAND-based storage medium including a first cell region (e.g., SLC) having a first number of levels and a second region (e.g., QLC) having a second number of levels different from the first number of levels. Logic 160 in controller 382 may be configured to determine an LBA position corresponding to a user-configurable capacity placeholder (e.g., a padding file, a padding partition, etc.) and adjust the respective sizes of the first cell region and the second cell region at runtime based on the LBA position. In some embodiments, logic 160 may further be configured to enable a function of user-configuring the size of the first cell region in response to a command (e.g., a vendor-specific command). For example, logic 160 may be configured to reserve a range of LBAs to manage capacity conversion between the first cell region and the second cell region.

[0062] In some embodiments, logic 160 may further be configured to store user data in memory 392 when this function is enabled. For example, logic 160 may be configured to convert blocks of the second cell region into blocks of the first cell region and move data of the second cell region to the converted blocks of the first cell region.

[0063] In other embodiments, SSD130 may be replaced with any suitable storage / memory / technology / media. In some embodiments, logic 160 / 170 may be coupled to one or more substrates (e.g., silicon, sapphire, gallium arsenide, printed circuit board (PCB), etc.) and may include the channel regions of transistors disposed within one or more substrates. In other embodiments, SSD130 may include two or more types of storage media. For example, most of the storage may be NAND, and may further include some NVM that is faster and accessible at a smaller granularity (e.g., byte-addressable). SSD130 may alternatively or additionally include persistent volatile memory (e.g., DRAM or SRAM backed up by a battery or capacitor). For example, SSD130 may include power loss protection (PLI) technology using an energy storage capacitor. The energy storage capacitor can supply enough energy (power) for any ongoing commands to complete and for any data in DRAM / SRAM to be necessarily recorded on the non-volatile NAND media. The capacitor can function as a backup battery for the persistent volatile memory. As shown in FIGS. 7 and 8, the functions or aspects of logic 160 and / or logic 170 may be distributed throughout system 100 and / or may be located in the same place as and / or integrated with various components of system 100.

[0064] [Additional Considerations and Examples]

[0065] Example 1 includes an electronic device, which includes one or more substrates and a controller coupled to the one or more substrates. The controller includes logic, and the logic controls access to a NAND-based storage medium including a first cell region having a first level number and a second region having a second level number different from the first level number, determines a logical block address position corresponding to a user-configurable capacity placeholder, and adjusts the respective sizes of the first cell region and the second cell region at runtime based on the logical block address position.

[0066] Example 2 includes the device described in Example 1, and the logic further enables a function of user-configuring the size of the first cell region in response to a command.

[0067] Example 3 includes the device described in Example 2, and the logic further reserves a range of logical block addresses to manage capacity conversion between the first cell region and the second cell region.

[0068] Example 4 includes the device described in any one of Examples 2 to 3, and the logic further stores user data in the NAND-based storage medium when this function is enabled.

[0069] Example 5 includes the device described in Example 4, and the logic further converts blocks of the second cell region into blocks of the first cell region.

[0070] Example 6 includes the device described in Example 5, and the logic further moves data of the second cell region to the converted blocks of the first cell region.

[0071] Example 7 includes the device described in any one of Examples 1 to 6, and the controller and the NAND-based storage medium are incorporated in a solid state drive.

[0072] Example 8 includes an electronic storage system, which includes a NAND-based storage medium including a first cell region having a first number of levels and a second region having a second number of levels different from the first number of levels, and a controller communicably coupled to the NAND-based storage medium, where the controller includes logic, and the logic determines a logical block address position corresponding to a user-configurable capacity placeholder and adjusts respective sizes of the first cell region and the second cell region at runtime based on the logical block address position.

[0073] Example 9 includes the system described in Example 8, and the logic further enables a function of user-configuring the size of the first cell region in response to a command.

[0074] Example 10 includes the system described in Example 9, and the logic further reserves a range of logical block addresses to manage capacity conversion between the first cell region and the second cell region.

[0075] Example 11 includes the system described in any one of Examples 9 to 10, and the logic further stores user data in the NAND-based storage medium when this function is enabled.

[0076] Example 12 includes the system described in Example 11, and the logic further converts blocks of the second cell region into blocks of the first cell region.

[0077] Example 13 includes the system described in Example 12, and the logic further moves data of the second cell region to the converted blocks of the first cell region.

[0078] Example 14 includes the system described in any one of Examples 8 to 13, and the controller and the NAND-based storage medium are incorporated into a solid state drive.

[0079] Embodiment 15 includes a method for controlling storage. The method includes controlling access to a NAND-based storage medium including a first cell region having a first number of levels and a second region having a second number of levels different from the first number of levels, determining a logical block address position corresponding to a user-configurable capacity placeholder, and adjusting the respective sizes of the first cell region and the second cell region at runtime based on the logical block address position.

[0080] Embodiment 16 includes the method described in Embodiment 15, and further includes enabling a function of user-configuring the size of the first cell region in response to a command.

[0081] Embodiment 17 includes the method described in Embodiment 16, and further includes securing a range of logical block addresses to manage capacity conversion between the first cell region and the second cell region.

[0082] Embodiment 18 includes the method described in any one of Embodiments 16 to 17, and further includes storing user data in the NAND-based storage medium when this function is enabled.

[0083] Embodiment 19 includes the method described in Embodiment 18, and further includes converting blocks of the second cell region into blocks of the first cell region.

[0084] Embodiment 20 includes the method described in Embodiment 19, and further includes moving data of the second cell region to the converted blocks of the first cell region.

[0085] Embodiment 21 includes the method described in any one of Embodiments 15 to 20, and the NAND-based storage medium is incorporated in a solid state drive.

[0086] Example 22 includes at least one non-transitory machine-readable medium, the medium comprising a plurality of instructions that, in response to being executed on a computing device, cause the computing device to control access to a NAND-based storage medium including a first cell region having a first level number and a second region having a second level number different from the first level number, determine a logical block address location corresponding to a user-configurable capacity placeholder, and adjust, at runtime, the respective sizes of the first cell region and the second cell region based on the logical block address location.

[0087] Example 23 includes at least one non-transitory machine-readable medium as described in Example 22, the medium comprising a plurality of additional instructions that, in response to being executed on a computing device, cause the computing device to enable a function of user-configuring the size of the first cell region in response to a command.

[0088] Example 24 includes at least one non-transitory machine-readable medium as described in Example 23, the medium comprising a plurality of additional instructions that, in response to being executed on a computing device, cause the computing device to reserve a range of logical block addresses for managing capacity conversion between the first cell region and the second cell region.

[0089] Example 25 includes at least one non-transitory machine-readable medium as described in any of Examples 23 to 24, the medium comprising a plurality of additional instructions that, in response to being executed on a computing device, cause the computing device to store user data on the NAND-based storage medium when this function is enabled.

[0090] Example 26 includes at least one non-transitory machine-readable medium as described in Example 25, the medium comprising a plurality of additional instructions that, in response to being executed on a computing device, cause the computing device to convert blocks of the second cell region into blocks of the first cell region.

[0091] Example 27 includes at least one non - transitory machine - readable medium described in Example 26, and in response to being executed on a computing device, comprises a plurality of further instructions for causing the computing device to move data of a second cell region to a converted block of a first cell region.

[0092] Example 28 includes at least one non - transitory machine - readable medium described in any of Examples 22 to 27, and the NAND - based storage medium is incorporated in a solid - state drive.

[0093] Example 29 includes a storage controller device, the device comprising means for controlling access to a NAND - based storage medium including a first cell region having a first level number and a second region having a second level number different from the first level number, means for determining a logical block address position corresponding to a user - settable capacity placeholder, and means for adjusting at runtime the respective sizes of the first cell region and the second cell region based on the logical block address position.

[0094] Example 30 includes the device described in Example 29, and further comprises means for enabling a function of user - setting the size of the first cell region in response to a command.

[0095] Example 31 includes the device described in Example 30, and further comprises means for reserving a range of logical block addresses for managing capacity conversion between the first cell region and the second cell region.

[0096] Example 32 includes the device described in any of Examples 30 to 31, and further comprises means for storing user data in the NAND - based storage medium when this function is enabled.

[0097] Example 33 includes the device described in Example 32, and further comprises means for converting blocks of the second cell region into blocks of the first cell region.

[0098] Example 34 includes the apparatus described in Example 33, and further includes means for moving the data in the second cell region to the converted block in the first cell region.

[0099] Example 35 includes the apparatus described in any one of Examples 29 to 34, and the NAND-based storage medium is incorporated in a solid state drive.

[0100] As used herein, the term "connected" may be used to refer to any kind of direct or indirect relationship between the components in question, and can apply to electrical connections, mechanical connections, fluid connections, optical connections, electromagnetic connections, electromechanical connections, or other connections. Further, terms such as "first", "second", etc. may be used herein for ease of explanation only, and unless otherwise indicated, do not have a specific temporal or time-dependent meaning.

[0101] In this application and the claims, a series of items associated with the term "one or more of" may mean any combination of the recited terms. For example, both the phrase "one or more of A, B, and C" and the phrase "one or more of A, B, or C" may mean A; B; C; A and B; A and C; B and C; or A, B, and C. The various components of the systems described herein may be implemented in software, firmware, and / or hardware, and / or any combination thereof. For example, the various components of the systems or devices described herein may be provided, at least in part, by hardware such as a computing SoC that may be found, for example, within a computing system such as a smartphone. One of ordinary skill in the art will recognize that the systems described herein may include additional components not depicted in the corresponding figures. For example, the systems described herein may include additional components such as a bitstream multiplexer or demultiplexer module that are not depicted for clarity.

[0102] The realization of the exemplary processes described herein may include the execution of all the operations shown in the illustrated order, but the disclosure is not limited in this regard, and in various examples, the realization of the exemplary processes herein may include only a subset of the operations shown, operations performed in an order different from that shown, or additional operations.

[0103] Furthermore, any one or more of the operations described herein may be performed in response to instructions provided by one or more computer program products. Such program products may include, for example, a signal-bearing medium that provides instructions which, when executed by a processor, may result in the functions described herein. The computer program products may be provided on any form of one or more machine-readable media. Thus, for example, a processor including one or more image processing devices or processor cores may execute one or more of the blocks of the exemplary processes herein in response to program code and / or instructions or instruction sets sent to the processor by one or more machine-readable media. Generally, the machine-readable media can carry software in the form of program code and / or instructions or instruction sets that can cause at least a portion of the operations described herein and / or any part of the devices, systems, or any module or component described herein to be implemented in any of the devices and / or systems described herein.

[0104] In any of the implementation examples described herein, the term "module" refers to any combination of software logic, firmware logic, hardware logic, and / or circuitry configured to provide the functions described herein. The software may be embodied as a software package, code, and / or instruction set or instructions, and in any of the implementation examples described herein, "hardware" may include, for example, hard-wired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and / or firmware storing instructions executed by programmable circuitry, either alone or in any combination. These modules may be embodied together or separately as circuits forming part of a larger system (e.g., integrated circuits (ICs) and system-on-chips (SoCs), etc.).

[0105] Various embodiments may be implemented using hardware elements, software elements, or a combination of both. Examples of hardware elements may include processors, microprocessors, circuits, circuit elements (such as transistors, resistors, capacitors, and inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), logic gates, registers, semiconductor devices, chips, microchips, and chip sets, etc. Examples of software may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, application program interfaces (APIs), instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The determination of whether an embodiment is implemented using either hardware elements and / or software elements may vary depending on any number of factors such as desired computational rate, power levels, heat tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints.

[0106] One or more aspects of at least one embodiment may be implemented by representative instructions stored on a machine-readable medium that represent various logic within a processor, which, when read by a machine, cause the machine to create logic for performing the techniques described herein. Such representations, known as IP cores, may be stored on a tangible machine-readable medium for loading into a manufacturing machine that actually makes the logic or processor and supplied to various customers or manufacturing facilities.

[0107] The specific features described in this specification have been described with reference to various implementation examples, but this description is not intended to be construed in a limiting sense. Accordingly, various modifications of the implementation examples described herein and other implementation examples will be apparent to those of ordinary skill in the art to which this disclosure pertains and are considered to be within the spirit and scope of this disclosure.

[0108] It will be recognized that these embodiments are not limited to the embodiments so described, but may be practiced with modifications and alterations without departing from the scope of the appended claims. For example, the above embodiments may include a particular combination of features. However, the above embodiments are not limited in this regard, and in various implementation examples, the above embodiments may include the execution of only a subset of such features, the execution of such features in a different order, the execution of such features in different combinations, and / or the execution of additional features with respect to those features explicitly described. Accordingly, the scope of these embodiments should be determined with reference to the appended claims, along with the full scope of equivalents to which such claims are entitled.

Claims

1. An electronic device comprising: one or more substrates; and a controller coupled to the one or more substrates, where the controller includes logic, the logic controlling access to a NAND-based storage medium including a first cell region having a first level number and a second cell region having a second level number different from the first level number, determining a logical block address position corresponding to a user-configurable capacity placeholder, and adjusting respective sizes of the first cell region and the second cell region at runtime based on the logical block address position. An apparatus comprising:

2. The apparatus of claim 1, wherein the logic further enables a function of user-configuring a size of the first cell region in response to a command.

3. The apparatus of claim 2, wherein the logic further reserves a range of logical block addresses to manage capacity conversion between the first cell region and the second cell region.

4. The apparatus of claim 2, wherein the logic further stores user data in the NAND-based storage medium when the function is enabled.

5. The apparatus of claim 4, wherein the logic further converts blocks of the second cell region into blocks of the first cell region.

6. The apparatus of claim 5, wherein the logic further moves data of the second cell region to the converted blocks of the first cell region.

7. The apparatus of claim 1, wherein the controller and the NAND-based storage medium are incorporated in a solid state drive.

8. An electronic storage system comprising: a NAND-based storage medium including a first cell region having a first level number and a second cell region having a second level number different from the first level number; and a controller communicatively coupled to the NAND-based storage medium, where the controller includes logic, the logic determining a logical block address position corresponding to a user-configurable capacity placeholder and adjusting respective sizes of the first cell region and the second cell region at runtime based on the logical block address position. A system comprising:

9. The logic further: ​ ​ ​ ​ ​ ​ ​ ​ The system according to claim 8, which enables a function of user-setting the size of the first cell region in response to a command.

10. The logic further secures a range of logical block addresses to manage capacity conversion between the first cell region and the second cell region, for the system according to claim 9.

11. The logic further stores user data in the NAND-based storage medium when the function is enabled, for the system according to claim 9.

12. The logic further converts blocks of the second cell region into blocks of the first cell region, for the system according to claim 11.

13. The logic further moves data of the second cell region to the converted blocks of the first cell region, for the system according to claim 12.

14. The system according to claim 8, wherein the controller and the NAND-based storage medium are incorporated in a solid state drive.

15. A method for controlling storage, comprising: controlling access to a NAND-based storage medium including a first cell region having a first number of levels and a second cell region having a second number of levels different from the first number of levels; determining a logical block address position corresponding to a user-configurable capacity placeholder, and adjusting respective sizes of the first cell region and the second cell region at runtime based on the logical block address position The method comprising.

16. Further comprising: enabling a function of user-setting the size of the first cell region in response to a command, for the method according to claim 15.

17. Further comprising: securing a range of logical block addresses to manage capacity conversion between the first cell region and the second cell region, for the method according to claim 16.

18. Further comprising: storing user data in the NAND-based storage medium when the function is enabled, for the method according to claim 16.

19. Further comprising: converting blocks of the second cell region into blocks of the first cell region, for the method according to claim 18.

20. Further comprising: moving data of the second cell region to the converted blocks of the first cell region, for the method according to claim 19.

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