Semiconductor device and method of manufacturing the same

Abstract

To provide: a semiconductor device that minimizes an increase in impedance of a PDN due to influence of wiring of a layer PCB substrate and influence of resistance of the PDN, and secures improved impedance characteristics and power noise reduction characteristics; and a method of manufacturing the same.SOLUTION: The method according to the invention includes the steps of: providing a semiconductor chip in a wafer state in which a bonding pad is formed; forming a first passivation layer on the semiconductor chip so that the bonding pad is exposed; forming a first rewiring layer connected to the bonding pad and extending from on the first passivation layer; forming a decoupling capacitor so as to be electrically connected to the first rewiring layer at a wafer level before a conductive bump disposed on an electrical signal path connected to the bonding pad, the first rewiring layer, and a substrate is formed; and forming the conductive bump electrically connected to the bonding pad, the first rewiring layer, and a PCB substrate.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly, to a semiconductor device such as a wafer level package (WLP) or a wafer level chip scale package (WLCSP) and a method for manufacturing the same.

Background Art

[0002] As the operating voltage of a semiconductor integrated circuit (IC) decreases and the operating frequency increases, it is required to reduce power noise in order to ensure the normal operation of the semiconductor IC. A decoupling capacitor having a low equivalent series resistance (ESR) and a low equivalent series inductance (ESL) is used to reduce the impedance of the power delivery network (PDN) from an external substrate (e.g., a multilayer PCB) to the power input pad of the semiconductor IC or from the output pad of the semiconductor IC to the application connection, thereby reducing the power noise. As such a decoupling capacitor, an MLCC (multi-layer ceramic capacitor), an LICC (low inductance ceramic capacitor), or a 3D silicon capacitor is used.

[0003] In order to minimize the impedance in the PDN, the decoupling capacitor is usually disposed close to the input node (input pad), the power node (power pad), or the output node (output pad), that is, the decoupling capacitor is disposed such that the length "A" in the example of FIG. 1 is minimized as much as possible.

[0004] FIG. 2 shows an example of a structure in which a conventional decoupling capacitor is arranged. FIG. 2A shows a structure in which a decoupling capacitor DCAP is arranged on the side of a multilayer PCB substrate (PCB Substrate) to which a packaged semiconductor chip (DIE) is attached (Die Side Capacitor). FIG. 2B shows a structure in which a decoupling capacitor DCAP is arranged inside the multilayer PCB substrate (i.e., on the first floor of the multi-layers of the PCB substrate) (PCB-embedded Capacitor). FIG. 2C shows a structure in which a decoupling capacitor DCAP is arranged on the side of the multilayer PCB substrate (PCB Substrate) to which the packaged semiconductor chip (DIE) is not attached (Land Side Capacitor).

[0005] In the case of the Die Side Capacitor, PCB-embedded Capacitor, and Land Side Capacitor in FIG. 2, since the PDN between the semiconductor chip (DIE) and the multilayer PCB substrate (PCB Substrate) is commonly located within the multilayer PCB substrate (PCB Substrate), there is a problem that the impedance of the PDN increases due to the influence of the wiring of the multilayer PCB substrate (PCB Substrate). Also, it is affected by the impedance of the bumps of the semiconductor chip (DIE) embodied in a conductive material, and there is a limit to reducing the power noise applied to the semiconductor chip (DIE). Consequently, the resistance of the PDN is a factor causing a voltage drop in the voltage applied to the semiconductor chip (DIE). SUMMARY OF THE INVENTION PROBLEMS TO BE SOLVED BY THE INVENTION

[0006] The present invention was devised to solve the above-described problems. An object according to one aspect of the present invention is to provide a semiconductor device having improved impedance characteristics and power noise reduction characteristics compared to the prior art and a method for manufacturing the same.

Means for Solving the Problem

[0007] A semiconductor device according to one aspect of the present invention includes a wafer-shaped semiconductor chip on which bonding pads are formed; a first passivation layer formed on the semiconductor chip so that the bonding pads are exposed; a first re-distribution layer connected to the bonding pads and extending from above the first passivation layer; a conductive bump disposed on an electrical signal path connecting the bonding pads, the first re-distribution layer, and a substrate; and a capacitor formed to be electrically connected to the first re-distribution layer at the wafer level before the conductive bump is formed.

[0008] A method of manufacturing a semiconductor device according to one aspect of the present invention includes forming a first passivation layer on a semiconductor chip so that bonding pads formed on the semiconductor chip are exposed; forming a first re-distribution layer connected to the bonding pads and extending from above the first passivation layer; forming a capacitor to be electrically connected to the first re-distribution layer at the wafer level; and forming a conductive bump on an electrical signal path connecting the bonding pads, the first re-distribution layer, and a substrate after the capacitor is formed.

Advantages of the Invention

[0009] According to the present invention, by forming a capacitor so as to be electrically connected to a redistribution layer at the wafer level, rather than in the manner of forming a capacitor (e.g., a decoupling capacitor) on a PCB substrate, and configuring the wafer-level package to include the capacitor, the distance between the pad and the capacitor (i.e., the length of the PDN, e.g., "A" in FIG. 1) can be significantly reduced. Along with this, the increase in the impedance of the PDN due to the influence of the wiring of the multilayer PCB substrate and the influence of the resistance of the PDN can be minimized. Therefore, improved impedance characteristics and power noise reduction characteristics compared to conventional semiconductor devices can be ensured.

[0010] Also, according to the present invention, since no capacitor is formed on the PCB substrate, the area of the PCB substrate available for use in the SMT (Surface Mount) process can be increased.

[0011] Also, according to the present invention, by directly applying a capacitor to the input / output pads of the wafer-level package, power noise can be reduced and the input / output signals can be stabilized.

[0012] Also, according to the present invention, by using the redistribution layer of the wafer-level package to configure the multi-nodes of the capacitor and reducing the number of capacitors required for impedance reduction, the cost required for implementing the semiconductor device can be reduced.

Brief Description of the Drawings

[0013]

Figure 1

Figure 2A

Figure 2B

Figure 2C

Figure 3

Figure 4A

Figure 4B

Figure 4C

Figure 4D

Figure 4E

Figure 4F

Figure 4G

Figure 4H

Figure 5A

Figure 5B

Figure 5C

Figure 5D

Figure 5E

Figure 5F

Figure 5G

Figure 5H

Figure 5I

Figure 5J

Figure 6A

Figure 6B

Figure 6C

Figure 6D

Figure 6E

Figure 6F

Figure 6G

Figure 6H

Figure 6I

Figure 6J

Figure 7A

Figure 7B

Mode for Carrying Out the Invention

[0014] Hereinafter, a semiconductor device and a method for manufacturing the same according to the present invention will be described with reference to the accompanying drawings. In this process, the thickness of the lines and the size of the components illustrated in the drawings may be exaggerated for clarity and convenience of explanation. Also, the terms described later are terms defined in consideration of the functions in the present invention, and these may vary depending on the intention or convention of the user or operator. Therefore, the definitions of such terms should be given based on the overall content of this specification.

[0015] In this specification, when it is stated that a certain part is "connected (or joined)" to another part, this includes not only the case where it is "directly connected (or joined)", but also the case where it is "indirectly connected (or joined)" with another member interposed therebetween. In this specification, when a certain part is said to "include (or comprise)" a certain component, this means that other components may be further "included (or comprised)" unless otherwise stated to the contrary, and does not exclude other components. Also, in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. Also, when one component is described as being "above" or "on" another component, this includes not only the case where each part is "immediately above" or "immediately on" another part, but also the case where there are further other components between each component and another component.

[0016] FIG. 3 is a flowchart showing a method for manufacturing a semiconductor device according to an embodiment of the present invention.

[0017] Referring to FIG. 3, the method for manufacturing a semiconductor device according to this embodiment mainly includes steps S110 to S160. In step S110, a semiconductor chip 10 in wafer form with bonding pads BP formed thereon is provided. In step S120, a first passivation layer 20 is formed on the semiconductor chip 10 so that the bonding pads BP formed on the semiconductor chip 10 are exposed. In step S130, a first rewiring layer 30 connected to the bonding pads BP and extending from above the first passivation layer 20 is formed. In step S140, a capacitor DCAP is formed so as to be electrically connected to the first rewiring layer 30 at the wafer level. After the capacitor DCAP is formed, in step S150, conductive bumps B are formed on the electrical signal path connecting the bonding pads BP, the first rewiring layer 30, and the PCB substrate. After the conductive bumps B are formed, in step S160, the semiconductor chip 10 in wafer form is diced. The capacitor DCAP can be a decoupling capacitor (e.g., MLCC, LICC, or 3D silicon capacitor) configured to reduce the impedance of the electrical signals connecting the bonding pads BP, the first rewiring layer 30, and the PCB substrate.

[0018] Through steps S110 to S150, a wafer level package (WLP) can be manufactured, and through the dicing process of the wafer level package in step S160, a plurality of chip scale packages can be manufactured. Accordingly, the semiconductor device to be manufactured in this embodiment can refer to a wafer level package or a chip scale package.

[0019] This embodiment presents the manufacturing processes of three embodiments according to the design specifications of the semiconductor device to be manufactured. Hereinafter, the method for manufacturing a semiconductor device will be specifically described for each embodiment.

[0020] First Embodiment

[0021] FIGS. 4A to 4H are exemplary diagrams for explaining each step of the method for manufacturing a semiconductor device according to the first embodiment of the present invention.

[0022] Referring to FIG. 4A, first, a wafer - state semiconductor chip 10 integrated with a pre - designed circuit is provided (S110). In this embodiment, the semiconductor chip 10 means a chip manufactured in a fab (Fabrication Facility). Therefore, it is defined to include a die passivation layer (not shown) for protecting the circuit integrated in the semiconductor chip 10 (the die passivation layer can be implemented with silicon dioxide (SiO2), silicon nitride (SiN), or a stack structure of silicon dioxide and silicon nitride). A plurality of bonding pads BP serving as power supply and electrical input / output paths of the circuit are formed on the semiconductor chip 10 so as to be exposed to the active surface AS (Active Surface or Active Area) side of the semiconductor chip 10 through pad openings. The above - mentioned die passivation layer is formed in a structure where the bonding pads BP are exposed to the active surface AS side. As shown in FIG. 4A, among the plurality of bonding pads BP formed on the semiconductor chip 10, the bonding pads focused on in this embodiment are defined as the first and second bonding pads BP1 and BP2. For example, the first bonding pad BP1 may be a pad for power (e.g., VCC) input, and the second bonding pad BP2 may be a pad for ground GND input.

[0023] Subsequently, as shown in FIG. 4B, a first passivation layer 20 is formed on the semiconductor chip 10 so that the bonding pad BP is exposed (S120). In step S120, the first passivation layer 20 is formed on the active surface AS of the semiconductor chip 10, and after the active surface AS of the semiconductor chip 10 excluding the region where the bonding pad BP is formed (the entire region or a partial region where the bonding pad BP is formed) is coated with photoresist, the bonding pad BP is exposed in the direction of the active surface AS of the semiconductor chip 10 through exposure and development of the photoresist. The first passivation layer 20 may be implemented with a photosensitive polymer or a polyimide material (this also applies identically to the second and third passivation layers 40 and 60 described later).

[0024] Subsequently, as shown in FIG. 4C, a first re-distribution layer 30 is formed so as to be connected to the bonding pad BP and extend from above the first passivation layer 20 (S130). That is, the first re-distribution layer 30 is connected to the bonding pad BP through the region where the bonding pad BP is exposed by the first passivation layer 20 and is formed so as to extend from above the first passivation layer 20. The first re-distribution layer 30 functions as a layer for re-arranging the bonding pads BP and may be implemented with a conductive material such as copper. As is well known, the first re-distribution layer 30 having a target layout can be formed through a seed layer formation process, an electroplating process, and an etching process of the seed layer. As shown in FIG. 4C, the portion of the first re-distribution layer 30 connected to the first bonding pad BP1 is defined as the first re-distribution line 31, and the portion of the first re-distribution layer 30 connected to the second bonding pad BP2 is defined as the second re-distribution line 32. Also, as shown in FIG. 4C, an additional re-distribution line 33 for re-arranging additional bonding pads (not shown) may be formed in step S130.

[0025] Subsequently, as illustrated in FIG. 4D, a second passivation layer 40 is formed on the first passivation layer 20 and the first rewiring layer 30 such that at least a part of the first rewiring layer 30 is exposed (S135A). In step S135A, after the second passivation layer 40 is formed so as to cover the first passivation layer 20 and the first rewiring layer 30 and a photoresist is coated on the remaining region excluding the region where the conductive member 70 described later is to be formed, at least a part of the first rewiring layer 30 is exposed in the direction of the active surface AS of the semiconductor chip 10 through exposure and development of the photoresist.

[0026] Subsequently, as shown in FIG. 4E, a conductive member 70 is formed through a plating process in the region where the first rewiring layer 30 is exposed by the second passivation layer 40 (S135B). The conductive member 70 can be an Under Bump Metal (UBM) provided for easy fusion of the conductive bump B and the capacitor DCAP described later. For clear distinction of terms, the conductive member on which the first conductive bump B1 described later is formed is defined as the first conductive member 71, the conductive member on which the second conductive bump B2 is formed is defined as the second conductive member 72, the conductive member to which the first power input pad of the capacitor DCAP described later is connected is defined as the third conductive member 73, and the conductive member to which the second power input pad of the capacitor DCAP is connected is defined as the fourth conductive member 74. The first conductive member 71 and the third conductive member 73 are electrically connected through the first rewiring line 31, and the second conductive member 72 and the fourth conductive member 74 are electrically connected through the second rewiring line 32. An additional conductive member 75 can also be formed on the additional rewiring line 33 described above. The "first and second conductive members 71, 72" and the "third and fourth conductive members and the additional conductive members 73, 74, 75" are formed through the same process in the S135B stage. However, the physical properties (e.g., thickness) of the first and second conductive members 71, 72 and the physical properties (e.g., thickness) of the third and fourth conductive members and the additional conductive members 73, 74, 75 can be configured to be different from each other. The first and second conductive members 71, 72 have the same physical properties as each other, and the third and fourth conductive members and the additional conductive members 73, 74, 75 have the same physical properties as each other (this is also the same in the third embodiment described later).

[0027] Subsequently, as shown in FIG. 4F, a capacitor DCAP is formed (S140) so as to be electrically connected to the first rewiring layer 30 at the wafer level. The term "at the wafer level" means that the capacitor DCAP is formed not on the PCB substrate to which the packaged semiconductor chip 10 of the present embodiment is attached, but within the wafer level package. The capacitor DCAP can have a plurality of power input pads, for example, a first power input pad (e.g., VCC pad) and a second power input pad (e.g., GND pad). Accordingly, in step S140, the solder cap of the bump (e.g., copper pillar bump) DCAP_B formed on the first power input pad of the capacitor DCAP is brought into contact with the third conductive member 73 electrically connected to the first rewiring line 31, and the solder cap of the bump (e.g., copper pillar bump) DCAP_B formed on the second power input pad of the capacitor DCAP is brought into contact with the fourth conductive member 74 electrically connected to the second rewiring line 32. The capacitor DCAP can be fused to the third and fourth conductive members 73 and 74 in such a manner that a reflow process is performed in a state where the capacitor DCAP is mounted on the semiconductor chip 10. When the capacitor DCAP has additional power input pads, the additional power input pads of the capacitor DCAP can be formed in contact with an additional conductive member 75 electrically connected to the additional rewiring line 33 described above. Through the above-described manner, the first and second rewiring lines 31 and 32, and the additional rewiring line 33 are configured to function as multi-nodes of the capacitor DCAP.

[0028] Subsequently, as illustrated in FIG. 4G, conductive bumps B are formed on an electrical signal path that continues to a PCB substrate (not shown) to which bonding pads BP, a first redistribution layer 30, and a packaged semiconductor chip 10 (i.e., wafer-level package) are attached (S150). When defining the electrical signal path connecting the first bonding pad BP1, the first redistribution line 31, the first conductive member 71, and the PCB substrate as the first electrical signal path, and the electrical signal path connecting the second bonding pad BP2, the second redistribution line 32, the second conductive member 72, and the PCB substrate as the second electrical signal path, the conductive bumps B can be configured to include a first conductive bump B1 disposed on the first electrical signal path and a second conductive bump B2 disposed on the second electrical signal path. Accordingly, at step S150, the first and second conductive bumps B1 and B2 are mounted on the semiconductor chip 10 such that the first conductive bump B1 contacts the first conductive member 71 electrically connected to the first redistribution line 31, and the second conductive bump B2 contacts the second conductive member 72 electrically connected to the second redistribution line 32, and a reflow process is performed so that the first and second conductive bumps B1 and B2 can be fused to the first and second conductive members 71 and 72, respectively.

[0029] On the other hand, in the drawings of the present embodiment, a structure in which the first redistribution line 31 is electrically connected to the first conductive bump B1 and the second redistribution line 32 is electrically connected to the second conductive bump B2 is illustrated. However, in addition to the first and second conductive bumps B1 and B2, additional conductive bumps (a plurality of conductive bumps) may be further provided in the present embodiment. Accordingly, the first redistribution line 31 or the second redistribution line 32 may be configured to be electrically connectable to the additional conductive bumps in addition to the first conductive bump B1 or the second conductive bump B2.

[0030] In FIG. 4G, an example in which the conductive bump B is embodied as a solder bump is illustrated. However, depending on the embodiment, as illustrated in FIG. 4H, the conductive bump B may be embodied as a copper pillar bump. That is, when the power consumption of the semiconductor chip 10 is large, a high operating current is required, and a small number of input / output pads are required, it can be said that it is preferable to apply a solder bump having a relatively large size. When the power consumption of the semiconductor chip 10 is small, a low operating current is required, and a large number of input / output pads are required, it can be said that it is preferable to apply a copper pillar bump having a relatively small size.

[0031] Through the above steps S110 to S150, a wafer-level package (particularly, Fan-In WLP) can be manufactured. In particular, the capacitor DCAP is configured to be electrically connected to a first electrical signal path (e.g., a VCC power input path) and a second electrical signal path (e.g., a ground path) through the first rewiring layer 30, so as to reduce the impedance of the first and second electrical signal paths, thereby ensuring improved impedance characteristics and power noise reduction characteristics.

[0032] On the other hand, after the step S150, a step S160 of dicing the semiconductor chip 10 in a wafer state into a plurality of chip scale packages may be further performed.

[0033] 2. Second Embodiment

[0034] FIGS. 5A to 5J are exemplary diagrams for explaining each step of a method for manufacturing a semiconductor device according to a second embodiment of the present invention.

[0035] In the manufacturing process of the wafer-level package, depending on the number of pads and the overall layout area of the semiconductor chip 10, a plurality of rewiring layers may be required for pad rearrangement. The second embodiment focuses on the structure and process in which the capacitor DCAP is formed inside the passivation layer when the wafer-level package is configured to include a plurality of rewiring layers. Specific descriptions of the same structure and process as in the first embodiment are omitted, and the structures and processes with differences compared to the first embodiment will be described. The same processes and structures as in the first embodiment use the same drawing reference numerals.

[0036] Referring to FIG. 5A, first, a semiconductor chip 10 in wafer form is provided (S110). On the semiconductor chip 10, first and second bonding pads BP1 and BP2, which serve as power supply and electrical input / output paths for the circuit, are formed so as to be exposed on the active surface AS side of the semiconductor chip 10 through pad openings.

[0037] Subsequently, as shown in FIG. 5B, a first passivation layer 20 is formed on the semiconductor chip 10 so that the bonding pad BP is exposed (S120). In step S120, the first passivation layer 20 is formed on the semiconductor chip 10 such that the first and second bonding pads BP1 and BP2 are exposed on the active surface AS side of the semiconductor chip 10.

[0038] Subsequently, as shown in FIG. 5C, a first rewiring layer 30 is formed so as to be connected to the bonding pad BP and extend from above the first passivation layer 20 (S130). A portion of the first rewiring layer 30 connected to the first bonding pad BP1 is defined as a first rewiring line 31, and a portion of the first rewiring layer 30 connected to the second bonding pad BP2 is defined as a second rewiring line 32. Also, as shown in FIG. 5C, an additional rewiring line 33 for rearrangement of additional bonding pads (not shown) may be formed in step S130.

[0039] Subsequently, as illustrated in FIG. 5D, a capacitor DCAP is formed (S140) so as to be electrically connected to the first rewiring layer 30 at the wafer level. In step S140, the capacitor DCAP can be formed by being brought into contact with the first rewiring layer 30 through an SMT (Surface Mount) process. Accordingly, the first and second power input pads of the capacitor DCAP are formed by being brought into contact with the first and second rewiring lines 31 and 32, respectively. When the capacitor DCAP has additional power input pads, the additional power input pads of the capacitor DCAP can be formed by being brought into contact with the aforementioned additional rewiring line 33. Through the above-described manner, the first and second rewiring lines 31 and 32, and the additional rewiring line 33 are configured to function as multi-nodes of the capacitor DCAP.

[0040] Subsequently, as illustrated in FIG. 5E, a second passivation layer 40 is formed on the first passivation layer 20 and the first rewiring layer 30 so that at least a part of the first rewiring layer 30 is exposed (S145A). In step S145A, the second passivation layer 40 is formed to cover the first passivation layer 20, the first rewiring layer 30, and the capacitor DCAP. After a photoresist is coated on the remaining area excluding the area where the second rewiring layer 50 to be described later is formed, at least a part of the first rewiring layer 30 is exposed in the direction of the active surface AS of the semiconductor chip 10 through exposure and development of the photoresist.

[0041] Subsequently, as illustrated in FIG. 5F, a second rewiring layer 50 is formed in the area where the first rewiring layer 30 is exposed by the second passivation layer 40 (S145B). A portion of the second rewiring layer 50 connected to the first rewiring line 31 is defined as a third rewiring line 51, and a portion of the second rewiring layer 50 connected to the second rewiring line 32 is defined as a fourth rewiring line 52. As illustrated in FIG. 5F, the third and fourth rewiring lines 51 and 52 can have portions extending from above the second passivation layer 40.

[0042] Subsequently, as illustrated in FIG. 5G, a third passivation layer 60 is formed on the second passivation layer 40 and the second rewiring layer 50 such that at least a part of the second rewiring layer 50 is exposed (S145C). At the stage of S145C, the third passivation layer 60 is formed to cover the second passivation layer 40 and the second rewiring layer 50, and after a photoresist is coated on the remaining area excluding the area where the conductive member 70 to be described later is formed, at least a part of the second rewiring layer 50 is exposed in the direction of the active surface AS of the semiconductor chip 10 through exposure and development of the photoresist.

[0043] Subsequently, as illustrated in FIG. 5H, a conductive member 70 is formed by a plating process in the area where the second rewiring layer 50 is exposed by the third passivation layer 60 (S145D). The conductive member 70 can be a UBM provided for easy fusion of the conductive bump B to be described later. For clear distinction of terms, the conductive member on which the first conductive bump B1 is formed is defined as the first conductive member 71, and the conductive member on which the second conductive bump B2 is formed is defined as the second conductive member 72.

[0044] Subsequently, as shown in FIG. 5I, conductive bumps B are formed on the bonding pads BP, the first rewiring layer 30, and the electrical signal path following the PCB substrate (not shown) (S150). When defining the electrical signal path connecting the first bonding pad BP1, the first rewiring line 31, the third rewiring line 51, the first conductive member 71, and the PCB substrate as the first electrical signal path, and the electrical signal path connecting the second bonding pad BP2, the second rewiring line 32, the fourth rewiring line 52, the second conductive member 72, and the PCB substrate as the second electrical signal path, the conductive bumps B can be configured to include a first conductive bump B1 disposed on the first electrical signal path and a second conductive bump B2 disposed on the second electrical signal path. Accordingly, at step S150, the first conductive bump B1 is brought into contact with the first conductive member 71 electrically connected to the first and third rewiring lines 31 and 51, and the first and second conductive bumps B1 and B2 are mounted on the semiconductor chip 10 so that the second conductive bump B2 is brought into contact with the second conductive member 72 electrically connected to the second and fourth rewiring lines 32 and 52. The first and second conductive bumps B1 and B2 can be fused to the first and second conductive members 71 and 72, respectively, in such a manner that the reflow process is performed. FIG. 5I illustrates an example in which the conductive bump B is embodied as a solder bump, but depending on the embodiment, as shown in FIG. 5J, the conductive bump B may be embodied as a copper pillar bump.

[0045] Through the above S110 to S150 steps, a wafer-level package (especially, Fan-In WLP) can be manufactured. In particular, the capacitor DCAP is configured to be electrically connected to a first electrical signal path (e.g., VCC power input path) and a second electrical signal path (e.g., ground path) through the first and second redistribution layers 30, 50, so as to reduce the impedance of the first and second electrical signal paths. By being configured in this way, improved impedance characteristics and power noise reduction characteristics can be ensured. Further, the capacitor DCAP is disposed between the first passivation layer 20 and the third passivation layer 60 (i.e., the capacitor DCAP is disposed within the passivation layer), so that the low ESR characteristics and low ESL characteristics of the capacitor DCAP can be maintained without being affected by disturbances.

[0046] On the other hand, after the S150 step, an S160 step of dicing the semiconductor chip 10 in wafer state into a plurality of chip scale packages may be further performed.

[0047] 3. Third Embodiment

[0048] FIGS. 6A to 6J are exemplary diagrams for explaining each step of a method for manufacturing a semiconductor device according to a third embodiment of the present invention.

[0049] As described in the second embodiment, depending on the number of pads and the overall layout area of the semiconductor chip 10 in the manufacturing process of the wafer-level package, a plurality of rewiring layers may be required for the rearrangement of the pads. In this case, although it may be considered to arrange the capacitor DCAP in the passivation layer as in the second embodiment, as the complexity of the rewiring layer increases, there may be a case where a space for arranging the capacitor DCAP in the passivation layer is not formed. The third embodiment focuses on the structure and process in which the capacitor DCAP is formed outside the passivation layer when the wafer-level package is configured to include a plurality of rewiring layers. Specific descriptions of the same structures and processes as those of the first and second embodiments are omitted, and the structures and processes having differences compared with the first and second embodiments will be described. The same processes and structures as those of the first and second embodiments use the same drawing reference numerals.

[0050] Referring to FIG. 6A, first, a semiconductor chip 10 in a wafer state is provided (S110). On the semiconductor chip 10, first and second bonding pads BP1 and BP2, which serve as a power supply and an electrical input / output path of the circuit, are formed so as to be exposed on the active surface AS side of the semiconductor chip 10 through pad openings.

[0051] Subsequently, as shown in FIG. 6B, a first passivation layer 20 is formed on the semiconductor chip 10 so that the bonding pad BP is exposed (S120). In step S120, the first passivation layer 20 is formed on the semiconductor chip 10 such that the first and second bonding pads BP1 and BP2 are exposed on the active surface AS side of the semiconductor chip 10.

[0052] Subsequently, as illustrated in FIG. 6C, a first rewiring layer 30 is formed (S130) so as to be connected to the bonding pad BP and extend from above the first passivation layer 20. A portion of the first rewiring layer 30 connected to the first bonding pad BP1 is defined as a first rewiring line 31, and a portion of the first rewiring layer 30 connected to the second bonding pad BP2 is defined as a second rewiring line 32. Also, as illustrated in FIG. 6C, an additional rewiring line 33 for rearrangement of additional bonding pads (not shown) may be formed at the S130 step.

[0053] Subsequently, as illustrated in FIG. 6D, a second passivation layer 40 is formed on the first passivation layer 20 and the first rewiring layer 30 so that at least a part of the first rewiring layer 30 is exposed (S135C). At the S135C step, after a photoresist is coated on the remaining region excluding the region where the second passivation layer 40 is formed to cover the first passivation layer 20 and the first rewiring layer 30 and the second rewiring layer 50 to be described later, at least a part of the first rewiring layer 30 is exposed in the direction of the active surface AS of the semiconductor chip 10 through exposure and development of the photoresist.

[0054] Subsequently, as illustrated in FIG. 6E, a second rewiring layer 50 is formed in a region where the first rewiring layer 30 is exposed by the second passivation layer 40 (S135D). A portion of the second rewiring layer 50 connected to the first rewiring line 31 is defined as a third rewiring line 51, and a portion of the second rewiring layer 50 connected to the second rewiring line 32 is defined as a fourth rewiring line 52. As illustrated in FIG. 6E, the third and fourth rewiring lines 51, 52 can have portions extending from above the second passivation layer 40. Also, as illustrated in FIG. 6E, at the stage of S135D, an additional rewiring line 53 for rearrangement of additional bonding pads (not shown) can be formed on the additional rewiring line 33 (in order to clearly distinguish the additional rewiring lines corresponding to the reference numerals "33" and "53", the additional rewiring line 33 included in the first rewiring layer 30 can be denoted as a first additional rewiring line 33, and the additional rewiring line 53 included in the second rewiring layer 50 can be denoted as a second additional rewiring line 53).

[0055] Subsequently, as illustrated in FIG. 6F, a third passivation layer 60 is formed on the second passivation layer 40 and the second rewiring layer 50 such that at least a portion of the second rewiring layer 50 is exposed (S135E). At the stage of S135E, after the third passivation layer 60 is formed to cover the second passivation layer 40 and the second rewiring layer 50 and a photoresist is coated on the remaining region except for the region where the conductive member 70 described later is to be formed, at least a portion of the second rewiring layer 50 is exposed in the direction of the active surface AS of the semiconductor chip 10 through exposure and development of the photoresist.

[0056] Subsequently, as illustrated in FIG. 6G, a conductive member 70 is formed through a plating process in a region where the second rewiring layer 50 is exposed by the third passivation layer 60 (S135F). The conductive member 70 may be a UBM provided for easy fusion of the conductive bump B described later. For clear distinction of terms, the conductive member on which the first conductive bump B1 is formed is defined as the first conductive member 71, the conductive member on which the second conductive bump B2 is formed is defined as the second conductive member 72, the conductive member to which the first power input pad of the capacitor DCAP described later is connected is defined as the third conductive member 73, and the conductive member to which the second power input pad of the capacitor DCAP is connected is defined as the fourth conductive member 74. The first conductive member 71 and the third conductive member 73 are electrically connected through the first rewiring line 31, and the second conductive member 72 and the fourth conductive member 74 are electrically connected through the second rewiring line 32. When the capacitor DCAP has additional power input pads, an additional conductive member 75 for fusion of the additional power input pads of the capacitor DCAP may be formed on the second additional rewiring line 53 at the S135F stage.

[0057] Subsequently, as illustrated in FIG. 6H, a capacitor DCAP is formed so as to be electrically connected to the first rewiring layer 30 at the wafer level (S140). In step S140, the solder cap of bump DCAP_B formed on the first power input pad of capacitor DCAP is brought into contact with a third conductive member 73 that is electrically connected to the first and third rewiring lines 31 and 51, and the solder cap of bump DCAP_B formed on the second power input pad of capacitor DCAP is brought into contact with a fourth conductive member 74 that is electrically connected to the second and fourth rewiring lines 32 and 52. The capacitor DCAP can be fused to the third and fourth conductive members 73 and 74 in such a manner that a reflow process is performed with the capacitor DCAP mounted on the semiconductor chip 10. If the capacitor DCAP has additional power input pads, the additional power input pads of the capacitor DCAP can be formed in contact with the aforementioned additional conductive member 75. Through the above-described manner, the first and second rewiring lines 31 and 32 are configured to function as multi-nodes of the capacitor DCAP.

[0058] Continuing, as shown in FIG. 6I, conductive bumps B are formed on the electrical signal path leading to a PCB substrate (not shown) to which bonding pads BP, a first redistribution layer 30, and a packaged semiconductor chip 10 (i.e., wafer-level package) are attached (S150). When defining the electrical signal path connecting the first bonding pad BP1, the first redistribution line 31, the third redistribution line 51, the first conductive member 71, and the PCB substrate as the first electrical signal path, and the electrical signal path connecting the second bonding pad BP2, the second redistribution line 32, the fourth redistribution line 52, the second conductive member 72, and the PCB substrate as the second electrical signal path, the conductive bumps B can be configured to include a first conductive bump B1 disposed on the first electrical signal path and a second conductive bump B2 disposed on the second electrical signal path. Accordingly, at step S150, the first conductive bump B1 contacts the first conductive member 71 that is electrically connected to the first and third redistribution lines 31, 51, and the first and second conductive bumps B1, B2 are mounted on the semiconductor chip 10 so that the second conductive bump B2 contacts the second conductive member 72 that is electrically connected to the second and fourth redistribution lines 32, 52, and the reflow process is performed so that the first and second conductive bumps B1, B2 can be fused to the first and second conductive members 71, 72, respectively. FIG. 6I illustrates an example in which the conductive bumps B are implemented as solder bumps, but depending on the embodiment, as shown in FIG. 6J, the conductive bumps B may be implemented as copper pillar bumps.

[0059] Through the above steps S110 to S150, a wafer-level package (particularly, Fan-In WLP) can be manufactured. After step S150, a step S160 of dicing the semiconductor chip 10 in wafer form into a plurality of chip-scale packages may be further performed.

[0060] FIG. 7A and FIG. 7B are exemplary diagrams showing the structure in which capacitors are arranged in the semiconductor device according to this embodiment. When compared with the conventional capacitor arrangement structure of FIG. 2, it can be confirmed that the capacitors are arranged within the die, and the distance between the pads and the capacitors can be significantly reduced. For the sake of clear understanding of the embodiment, only two conductive bumps are illustrated in FIG. 7, but in the actual manufacturing process of a semiconductor device, the semiconductor chip can be attached to the PCB substrate through two or more conductive bumps.

[0061] Thus, according to the present invention, by forming a capacitor so as to be electrically connected to the redistribution layer at the wafer level, rather than forming the capacitor (e.g., decoupling capacitor) on the PCB substrate, and configuring the wafer-level package to include the capacitor, the distance between the pad and the capacitor (i.e., the length of the PDN, e.g., "A" in FIG. 1) can be significantly reduced. Along with this, the increase in the impedance of the PDN due to the influence of the wiring of the multilayer PCB substrate and the resistance of the PDN can be minimized. Therefore, improved impedance characteristics and power noise reduction characteristics can be ensured as compared with conventional semiconductor devices.

[0062] Also, according to the present invention, since no capacitor is formed on the PCB substrate, the area of the PCB substrate available for use in the SMT (Surface Mount) process can be increased.

[0063] Also, according to the present invention, by directly applying the capacitor to the input / output pads of the wafer-level package, the power noise can be reduced and the input / output signals can be stabilized.

[0064] Also, according to the present invention, by using the redistribution layer of the wafer-level package to configure the multi-nodes of the capacitor and reducing the number of capacitors required for impedance reduction, the cost required for implementing the semiconductor device can be reduced.

[0065] The present invention has been described with reference to the embodiments illustrated in the drawings, which are merely exemplary, and it will be understood by those having ordinary knowledge in the technical field to which the technology pertains that various modifications and equivalent other embodiments will be possible hereafter. Therefore, the true technical protection scope of the present invention should be determined by the following claims.

Explanation of Reference Signs

[0066] BP: Bonding Pad BP1, BP2: First and Second Bonding Pads B: Conductive Bump B1, B2: First and Second Conductive Bumps DCAP: Capacitor AS: Active Surface 10: Semiconductor Chip 20: First Passivation Layer 30: First Redistribution Layer 31, 32: First and Second Redistribution Lines 40: Second Passivation Layer 50: Second Redistribution Layer 51, 52: Third and Fourth Redistribution Lines 60: Third Passivation Layer 70: Conductive Member 71, 72, 73, 74: First to Fourth Conductive Members

Claims

1. A semiconductor chip in a wafer state with bonding pads formed thereon; A first passivation layer formed on the semiconductor chip such that the bonding pads are exposed; A first redistribution layer connected to the bonding pads and extending from above the first passivation layer; Conductive bumps disposed on an electrical signal path connecting the bonding pads, the first redistribution layer, and a substrate; and A capacitor formed to be electrically connected to the first redistribution layer at the wafer level before the conductive bumps are formed; The bonding pads include first and second bonding pads, The first passivation layer is formed on the semiconductor chip such that the first and second bonding pads are exposed, The first redistribution layer includes first and second redistribution lines connected to the first and second bonding pads, respectively, and extending from above the first passivation layer, The conductive bumps include a first conductive bump disposed on a first electrical signal path connecting the first bonding pad, the first redistribution line, and the substrate, and a second conductive bump disposed on a second electrical signal path connecting the second bonding pad, the second redistribution line, and the substrate, The capacitor is electrically connected to the first and second redistribution lines and disposed between the first and second conductive bumps, A second passivation layer formed on the first passivation layer and the first redistribution layer such that at least a part of the first redistribution layer is exposed; A second redistribution layer formed in a region where the first redistribution layer is exposed by the second passivation layer; A third passivation layer formed on the second passivation layer and the second redistribution layer such that at least a part of the second redistribution layer is exposed; and A conductive member formed in a region where the second redistribution layer is exposed by the third passivation layer; The capacitor is formed by being in contact with the first redistribution layer and is formed between the first passivation layer and the third passivation layer, A semiconductor device, wherein the first and second conductive bumps are formed in contact with the conductive member.

2. A wafer-shaped semiconductor chip having bonding pads formed thereon; A first passivation layer formed on the semiconductor chip such that the bonding pads are exposed; A first redistribution layer connected to the bonding pads and extending from above the first passivation layer; A conductive bump disposed on an electrical signal path connecting the bonding pads, the first redistribution layer, and a substrate; and A capacitor formed to be electrically connected to the first redistribution layer at the wafer level before the conductive bump is formed; The bonding pads include first and second bonding pads, The first passivation layer is formed on the semiconductor chip such that the first and second bonding pads are exposed, The first redistribution layer includes first and second redistribution lines connected to the first and second bonding pads, respectively, and extending from above the first passivation layer; The conductive bumps include a first conductive bump disposed on a first electrical signal path connecting the first bonding pad, the first redistribution line, and the substrate, and a second conductive bump disposed on a second electrical signal path connecting the second bonding pad, the second redistribution line, and the substrate; The capacitor is electrically connected to the first and second redistribution lines and is disposed between the first and second conductive bumps, A second passivation layer formed on the first passivation layer and the first redistribution layer such that at least a part of the first redistribution layer is exposed; A second redistribution layer formed in a region where the first redistribution layer is exposed by the second passivation layer; A third passivation layer formed on the second passivation layer and the second redistribution layer such that at least a part of the second redistribution layer is exposed; and A conductive member formed in a region where the second redistribution layer is exposed by the third passivation layer; A semiconductor device, characterized in that the first and second conductive bumps and the capacitor are formed in contact with each other on the conductive member.

3. The first and second redistribution lines function as multi-nodes of the capacitor, The semiconductor device according to claim 1 or 2, wherein the first redistribution line or the second redistribution line is configured to be electrically connectable to an additional conductive bump in addition to the first conductive bump or the second conductive bump.

4. The semiconductor device according to claim 1 or 2, wherein the conductive bump is implemented as a solder bump or a copper pillar bump.

5. The semiconductor device according to claim 1 or 2, wherein the semiconductor device is implemented as a wafer level package (WLP) or a wafer level chip scale package (WL-CSP).

6. Forming a first passivation layer on the semiconductor chip such that bonding pads formed on the semiconductor chip are exposed; Forming a first redistribution layer connected to the bonding pads and extending from above the first passivation layer; Forming a capacitor so as to be electrically connected to the first redistribution layer at the wafer level; and After the capacitor is formed, forming a conductive bump on an electrical signal path connecting the bonding pads, the first redistribution layer, and the substrate; including The bonding pads include first and second bonding pads, The first passivation layer is formed on the semiconductor chip such that the first and second bonding pads are exposed, The first redistribution layer includes first and second redistribution lines connected to the first and second bonding pads, respectively, and extending from above the first passivation layer. The conductive bumps include a first conductive bump disposed on a first electrical signal path connected to the first bonding pad, the first rewiring line, and the substrate, and a second conductive bump disposed on a second electrical signal path connected to the second bonding pad, the second rewiring line, and the substrate. The capacitor is electrically connected to the first and second rewiring lines and is disposed between the first and second conductive bumps. After the step of forming the first rewiring layer, Forming a second passivation layer on the first passivation layer and the first rewiring layer such that at least a part of the first rewiring layer is exposed; and Forming a conductive member in a region where the first rewiring layer is exposed by the second passivation layer; further comprising: In the step of forming the capacitor, the capacitor is formed by being in contact with a conductive member electrically connected to the first rewiring line and a conductive member electrically connected to the second rewiring line, respectively. In the step of forming the conductive bumps, the first conductive bump is formed by being in contact with a conductive member electrically connected to the first rewiring line, and the second conductive bump is formed by being in contact with a conductive member electrically connected to the second rewiring line. A method of manufacturing a semiconductor device, characterized in that. Forming a first passivation layer on the semiconductor chip such that bonding pads formed on the semiconductor chip are exposed; Forming a first rewiring layer connected to the bonding pads and extending from above the first passivation layer; Forming a capacitor so as to be electrically connected to the first rewiring layer at the wafer level; and After the capacitor is formed, forming conductive bumps on an electrical signal path connected to the bonding pads, the first rewiring layer, and the substrate; including The bonding pads include first and second bonding pads. The first passivation layer is formed on the semiconductor chip such that the first and second bonding pads are exposed. The first rewiring layer includes first and second rewiring lines (Re-Distribution Lines) respectively connected to the first and second bonding pads and extending from above the first passivation layer. The conductive bumps include a first conductive bump disposed on a first electrical signal path connected to the first bonding pad, the first rewiring line, and the substrate, and a second conductive bump disposed on a second electrical signal path connected to the second bonding pad, the second rewiring line, and the substrate. The capacitor is electrically connected to the first and second rewiring lines and is disposed between the first and second conductive bumps. In the step of forming the capacitor, the capacitor is formed by being brought into contact with the first rewiring layer. After the step of forming the capacitor. Forming a second passivation layer on the first passivation layer and the first rewiring layer so that at least a part of the first rewiring layer is exposed; Forming a second rewiring layer in a region where the first rewiring layer is exposed by the second passivation layer; Forming a third passivation layer on the second passivation layer and the second rewiring layer so that at least a part of the second rewiring layer is exposed; and Forming a conductive member in a region where the second rewiring layer is exposed by the third passivation layer; further including In the step of forming the conductive bumps, the first conductive bump is formed by being brought into contact with a conductive member electrically connected to the first rewiring line, and the second conductive bump is formed by being brought into contact with a conductive member electrically connected to the second rewiring line. A method of manufacturing a semiconductor device, characterized by that. Forming a first passivation layer on the semiconductor chip so that bonding pads formed on the semiconductor chip are exposed; Forming a first rewiring layer connected to the bonding pads and extending from above the first passivation layer; Forming a capacitor so as to be electrically connected to the first rewiring layer at the wafer level; and After the capacitor is formed, forming conductive bumps on an electrical signal path connected to the bonding pads, the first rewiring layer, and the substrate; including The bonding pads include first and second bonding pads. The first passivation layer is formed on the semiconductor chip so that the first and second bonding pads are exposed. The first redistribution layer is connected to the first and second bonding pads respectively and includes first and second redistribution lines (Re-Distribution Line) extending from above the first passivation layer. The conductive bumps include a first conductive bump disposed on a first electrical signal path connecting the first bonding pad, the first redistribution line, and the substrate, and a second conductive bump disposed on a second electrical signal path connecting the second bonding pad, the second redistribution line, and the substrate. The capacitor is electrically connected to the first and second redistribution lines and is disposed between the first and second conductive bumps. After the step of forming the first redistribution layer. Forming a second passivation layer on the first passivation layer and the first redistribution layer such that at least a part of the first redistribution layer is exposed; and Forming a second redistribution layer in a region where the first redistribution layer is exposed by the second passivation layer; Forming a third passivation layer on the second passivation layer and the second redistribution layer such that at least a part of the second redistribution layer is exposed; and Forming a conductive member in a region where the second redistribution layer is exposed by the third passivation layer; further comprising In the step of forming the capacitor, the capacitor is formed by contacting a conductive member electrically connected to the first redistribution line and a conductive member electrically connected to the second redistribution line respectively. In the step of forming the conductive bumps, the first conductive bump is formed by contacting a conductive member electrically connected to the first redistribution line, and the second conductive bump is formed by contacting a conductive member electrically connected to the second redistribution line. A method of manufacturing a semiconductor device, characterized in that.

9. After the conductive bumps are formed, dicing the semiconductor chip in wafer state into a plurality of chip scale packages (Chip Scale Package); A method of manufacturing a semiconductor device according to any one of claims 6 to 8, further comprising the step of.

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