Method for manufacturing an ultra-thin high-density multilayer interconnected ceramic substrate

Abstract

To provide a ceramic board which has good heat dissipation, and in which an integration density is high.SOLUTION: According to an embodiment, the present invention discloses a manufacturing method of an ultrathin high-density multilayer interconnection ceramic board, containing steps of: preparing a ceramic wafer, performing a laser punching to the ceramic wafer, and forming a via hole; performing a vacuum magnetron sputtering to the ceramic wafer, and forming a seed titan layer and a copper layer onto a front surface of the ceramic wafer and on a wall of the via hole by the sputtering; manufacturing a ceramic double-layer core plate; manufacturing a multilayer substrate; manufacturing a vertical interconnection multilayer substrate; and manufacturing a high-end multilayer HDI ceramic board. The multilayer ceramic plate manufactured in the above mentioned processing can be easily processed as compared with LTCC and HTCC, and an energy consumption amount for the processing is deteriorated. A heat conductivity of a finished product is improved. A wiring is more accurate; a conductive resistance is low; and a signal transmission loss is low.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] The present invention relates to the technical field of printed circuit board manufacturing, and more specifically, to a method for manufacturing an ultra-thin high-density multilayer interconnected ceramic substrate.

Background Art

[0002] With the active development of the microelectronics packaging industry, electronic packaging technology is developing towards miniaturization, high density, multi-output, and high reliability. Currently, the commonly used substrate materials mainly include four types: plastic substrates, metal substrates, ceramic substrates, and composite substrates. Ceramic substrates have become the basic materials for the structural technology and interconnection technology of high-output power electronic circuits due to their good high-temperature performance, corrosion resistance, high thermal conductivity, and thermal expansion coefficient.

[0003] Ceramic substrates can be mainly divided into DPC, TFC, DBC, AMB, LTCC / HTCC, etc. by process. In the manufacturing process of direct plated copper ceramic substrates (DPC: Direct Plated Copper), first, the ceramic wafer is pretreated and cleaned, and a Ti / Cu layer is deposited on the surface of the wafer by vacuum sputtering to form a seed layer. Next, wiring is fabricated through photolithography, development, and etching processes. Finally, electroplating / electroless plating is used to thicken the wiring, and the photoresist is removed to manufacture the substrate. Thick film ceramic substrates (TFC: Thick Film Ceramic) are manufactured by applying a metal slurry to the surface of a ceramic wafer using screen printing technology, followed by drying and high-temperature sintering (700 - 800 °C). The metal slurry generally consists of metal powder (Ag-Pd or Ag-Pt), organic resin, glass powder, etc. Through high-temperature sintering, the resin binder burns away, and most of the remaining is pure metal. Since the glassy binder acts on the surface of the ceramic substrate, the thickness of the metal layer after sintering is 10 - 20 μm, and the minimum line width is 0.3 mm. Direct bonded copper ceramic substrates (DBC: Direct Bonded Copper) are obtained by eutectic sintering a ceramic wafer (Al2O3 or AlN) and copper foil at a high temperature (1065 °C), and finally forming the wiring by etching according to the wiring requirements. Active metal brazing copper substrates (AMB: Active Metal Brazing) add active elements to the brazing material to form a reaction layer on the ceramic surface through chemical reactions, and improve the wettability of the brazing material on the ceramic surface to achieve chemical bonding between the ceramic and the metal. HTCC (High Temperature Co-fired Multilayer Ceramic Substrate) is made by adding an organic binder to ceramic powder (Al2O3 or AlN), mixing it uniformly into a paste-like slurry, then using a doctor blade to scrape the slurry into a sheet shape, making the sheet-shaped slurry green through the drying process, next designing and drilling via holes according to the design of each layer, and performing wiring and filling of via holes by screen printing metal slurry. Finally, each green is laminated and sintered in a high-temperature furnace (1600 °C).The manufacturing process of LTCC (Low Temperature Co-fired Ceramic Substrate) is the same as that of HTCC, except that 30 - 50% of low melting point glass frit is mixed with Al2O3 powder to lower the sintering temperature to 850 - 900°C.

[0004] In the above manufacturing process, except that multilayer wiring is possible for both LTCC and HTCC, the rest are all single-sided wiring or double-sided wiring. Although multilayer wiring is possible for both LTCC and HTCC ceramic circuit boards, LTCC has limitations due to shrinkage rate and heat dissipation problems. LTCC is sintered from slurry and green ceramic tape in an environment of 800 - 900°C, and the thermal conductivity of the ceramic circuit board is only 2 - 6 W / m·K, far lower than the original thermal conductivity of the bare ceramic wafer (alumina: 15 - 25 W / m·K, aluminum nitride > 170 W / m·K, silicon nitride > 80 W / m·K). The manufacturing process of HTCC co-fires at a high temperature of 1600°C. The problem of shrinkage rate during processing affects the circuit layer. Due to the high processing temperature, high melting point metals such as tungsten, molybdenum, molybdenum, and manganese are required for the circuit. Such wiring has a high conductor resistivity and a large signal transmission loss.

Summary of the Invention

Problems to be Solved by the Invention

[0005] Therefore, the object of the present invention is to provide a manufacturing method capable of manufacturing an ultra-thin high-density multilayer interconnected ceramic substrate by a low-temperature process (<350°C). By this manufacturing method, a ceramic substrate with excellent heat dissipation and high integration density can be obtained.

Means for Solving the Problems

[0006] To solve the above problems, the present invention prepares a ceramic wafer, performs laser drilling on the ceramic wafer to form via holes, Performing vacuum magnetron sputtering on the ceramic wafer to form a seed titanium layer and a copper layer on the surface of the ceramic wafer and the walls of the via holes by sputtering; Manufacturing a ceramic two-layer core board; Manufacturing a multilayer substrate, and providing a method for manufacturing an ultra-thin high-density multilayer interconnected ceramic substrate including the above steps.

[0007] Furthermore, the ceramic wafer is a ceramic wafer made of aluminum oxide, aluminum nitride, silicon nitride, or beryllium oxide.

[0008] Furthermore, when forming the seed titanium layer and the copper layer on the surface of the ceramic wafer and the walls of the via holes by sputtering, the thickness of the titanium layer is 0.25 μm or more, and the thickness of the copper layer is 0.8 μm or more.

[0009] Furthermore, after performing vacuum magnetron sputtering on the ceramic wafer to form a seed titanium layer and a copper layer on the surface of the ceramic wafer and the walls of the via holes by sputtering, Performing electroplating on the ceramic substrate to fill the holes to surely fill the via holes of the ceramic wafer, and at the same time, further including the step of increasing the thickness of the surface layer copper of the ceramic wafer to 45 μm or more.

[0010] Furthermore, the step of manufacturing the ceramic two-layer core board includes: Filling the holes by electroplating, polishing the ceramic wafer with an increased surface layer copper thickness to flatten the copper surface; Performing the first pattern transfer to transfer the desired wiring pattern onto the copper surface; Forming the desired wiring on the copper surface by an etching process; Removing titanium from the ceramic wafer using a chemical solution to sufficiently remove the seed titanium layer to obtain a ceramic two-layer core board.

[0011] Furthermore, after manufacturing the ceramic two-layer core board, performing AOI inspection and complete electrical testing on the ceramic core board; forming a brown oxide thin film on the copper surface of the ceramic core board by brown oxidation treatment; and the method includes the steps.

[0012] Furthermore, after manufacturing the ceramic two-layer core board, the method includes the step of manufacturing a multilayer substrate, and this step includes: a combination and lamination step of laminating a semi-cured sheet + copper foil or FPC on the upper and lower surfaces of the ceramic core board after brown oxidation treatment respectively; a step of integrally laminating the semi-cured sheet + copper foil or FPC and the ceramic core board by a lamination method to obtain a laminated multilayer substrate.

[0013] Furthermore, after manufacturing the multilayer substrate, the method includes the step of manufacturing an upper and lower interconnected multilayer board, and this step includes: a mark point exposure step of removing the outer layer of copper and PP dielectric by using a laser to expose the inner layer mark point; a step of forming channels of blind holes in the inner and outer layers through laser treatment of blind holes and through the inner layer mark point; a slag removal step of completely removing the slag in the blind holes by plasma micro-etching; a copper deposition step of depositing seed metal copper on the walls of the blind holes by electroless copper plating; a panel plating step of making the seed layer by electroless copper plating to a thickness of 3 - 5 μm; a blind hole electroplating step of surely filling the blind holes by electroplating method, and at the same time, making the surface layer of the substrate to a thickness of 40 μm or more by copper electroplating; a polishing step of polishing the copper surface of the substrate after electroplating to be flat; a second pattern transfer step of transferring an image onto the copper surface by an image transfer process; An etching step of forming a wiring pattern by an etching process to obtain a vertically interconnected multilayer board is included.

[0014] Furthermore, after manufacturing the vertically interconnected multilayer board, a step of manufacturing a high-end multilayer HDI ceramic substrate is included. This step includes: A step of opening trenches while controlling the thickness of the vertically interconnected multilayer board, removing the dielectric with a picosecond laser, and exposing pads for high-power chip welding on the ceramic core board; A step of forming a solder mask / symbol; A step of performing surface treatment; A step of scribing and slicing using a picosecond laser to obtain a finished high-end HDI ceramic multilayer substrate.

[0015] The present invention also provides an ultra-thin high-density multilayer interconnected ceramic substrate manufactured by the above method.

Advantages of the Invention

[0016] Compared with the prior art, the present invention adopts a thermoelectric separation design, holds devices with a large amount of heat dissipation in the ceramic layer, and vertically interconnects and integrates the remaining conductors. The present invention manufactures multilayer wiring based on the conventional two-layer DPC ceramic substrate. The multilayer ceramic board manufactured in this process is easier to process than LTCC and HTCC, reduces the energy consumption for processing, improves the thermal conductivity of the finished product, has more precise wiring, lower conductor resistivity, and lower signal transmission loss. To more clearly explain the technical solutions of the embodiments of the present application, the attached drawings required for the description of the embodiments are briefly described below. The drawings in the following description are some embodiments of the present application, and it is obvious that those skilled in the art can obtain other drawings from these drawings without creative efforts.

Brief Description of the Drawings

[0017]

Figure 1

Figure 2

Embodiments for Carrying Out the Invention

[0018] Hereinafter, with reference to the drawings in the embodiments of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described. It is obvious that the described embodiments are some of the embodiments of the present application, not all of them. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the protection scope of the present application.

[0019] It should be noted that the terms "comprising" and "containing", when used in this specification and the appended claims, indicate the presence of the described features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their aggregates.

[0020] Also, it should be understood that the terms used in the specification of the present application are only used for the purpose of explaining specific embodiments and are not intended to limit the present application. As used in the specification of the present application and the appended claims, the singular forms "a", "one", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0021] Furthermore, the term "and / or" used in the specification and the appended claims of the present application means any combination and all possible combinations of one or more of the related listed items, and it should be understood that these combinations are included.

[0022] As shown in FIG. 1, FIG. 1 is an example of a flowchart of an embodiment of the manufacturing method of the present invention. Specifically, the present invention provides an embodiment of a manufacturing method of an ultra-thin high-density multilayer interconnected ceramic substrate, which includes the following steps. S1: Use a high-strength ceramic wafer with a thickness of 0.32 mm (bending strength > 700 MPa) to perform laser drilling with a fiber laser to penetrate the front and back surfaces. Here, the ceramic wafers used include, but are not limited to, ceramic wafers made of aluminum oxide, aluminum nitride, silicon nitride, and beryllium oxide. In this embodiment, an extremely thin and high-strength silicon nitride ceramic wafer with a thickness of 0.32 mm is used. S2: Chemically remove the slag using hydrofluoric acid + hydrogen peroxide to completely remove the slag caused by the drilling in S1. Next, clean the hole walls and the ceramic surface by ultrasonic cleaning with pure water multiple times to make them clean. Here, for the ceramic slag caused by laser drilling, after removing the particle slag by physical scraping, the low-density layer on the hole wall is removed by etching using a chemical solution, thereby ensuring the quality of the product. S3: Metallization of the ceramic seed layer: Use vacuum magnetron sputtering to sputter a seed titanium layer and a copper layer on the silicon nitride ceramic wafer, and at the same time, deposit a seed metal thin film layer on the hole walls of the ceramic. Make the thickness of the titanium layer 0.25 μm or more and the thickness of the copper layer 0.8 μm or more. Here, at a vacuum degree of 6.0×10 -4 Pa, utilize the interaction between the magnetic field and the electric field so that electrons collide with argon gas to generate ions, and the ions collide with the target surface under the action of the electric field, and transfer and deposit the titanium target and the copper target on the surface of the ceramic wafer. S4: Perform electroplating on the ceramic wafer with the above-mentioned seed layer to fill the via holes and thicken the copper on the surface layer. After electroplating, the via holes are filled with copper pillars, and the thickness of the surface layer copper is also increased to 45 μm or more by electroplating. Perform electroplating on the ceramic wafer with the above-mentioned seed layer to fill the holes, ensure that the upper via holes and the lower via holes are filled, and increase the thickness of the surface layer copper to 45 μm or more. S5: Mechanically polish the substrate after electroplating to polish the entire surface of the substrate copper flat and control the polished copper surface to be between 30 and 40 μm. In this embodiment, by mechanically polishing the substrate after electroplating, the copper surface is polished uniformly, and the copper thickness after polishing is controlled to be about 35 μm. S6: Perform the first pattern transfer on the polished substrate through the processes of film drying, exposure, and development to transfer the image onto the copper surface. At this time, according to the steps of the panel plating process, the pads to be reserved are protected with a dry film, and the copper for the wiring interval to be removed by etching is exposed. S7: Remove the copper within the trend by reducing the copper through etching to obtain a wiring pattern (for example, after removing the film, use a micro-etching solution to etch and remove the bottom seed copper layer in the pattern plating process); S8: Completely remove the titanium layer, which is the bottom seed layer, using a titanium removal solution to obtain a two-layer ceramic core board. Note that in steps S4 to S8, after performing pattern transfer, electroplating may be performed, and then a pattern plating process of polishing, film removal, and micro-etching of the seed copper may be adopted. S9: Intermediate test: Perform AOI and complete electrical tests on the ceramic core board to ensure that the core board meets the requirements. S10: Perform a brown oxidation treatment on the inspected ceramic core board. S11: Lamination and stacking: In this application, 1080 RC67% is laminated on the upper and lower surfaces of the high-Tg semi-cured sheet respectively, and HOZ is used for the copper foil or an FPC pure adhesive material is used. S12: Laminate (PP + copper foil) or FPC and the ceramic core board together by a lamination method. S13: Since the ceramic core board is a brittle material, expose the mark points with a laser, that is, design the mark area according to the core board, use the laser to remove the outer layer of copper and PP, and expose the inner layer of mark points. S14: Through the alignment of the mark points of the core board, use a laser to form channels for the blind holes of the inner and outer layers. S15: Use plasma to perform slag removal and micro-etching on the substrate after laser processing to completely remove the slag in the blind holes. S16: Copper deposition: Deposit seed metal copper on the blind hole walls by chemical copper deposition. S17: Panel plating: Increase the thickness of the chemically deposited copper layer to 3 - 5 μm by electroplating, thereby avoiding the etching of the copper deposition layer during the pretreatment for filling the holes. S18: Blind hole electroplating: Use electroplating to reliably fill the blind hole channels and at the same time increase the thickness of the surface copper of the substrate to more than 40 μm by electroplating. S19: Polishing: Polish the copper surface of the substrate after electroplating to be flat. S20: Second pattern transfer: Similar to the S6 process, transfer the image onto the copper surface by an image transfer process; S21: Etching: Form the wiring pattern in the same way as the S7 process. S22: AOI / Electrical test 2: Ensure that the product meets the requirements through AOI inspection and a complete electrical test. S23: Repeat S10 - S22 to manufacture multi-layer wiring. S24: Open trenches while controlling the thickness, that is, remove the dielectric with a picosecond laser to expose the pads of the ceramic core board for welding the high-power chip. Here, use a picosecond laser to bake out the dielectric above the pads where the chips are welded to expose the pads of the ceramic core board layer. As shown in Figure 1, also open trenches on the back surface of the heat sink pad by the same process or dissipate heat by densely arranging blind holes in an array. S25: Solder mask / symbol: Follow up on the product design and form the solder mask / symbol. S26: Surface treatment: Follow up on the product design and perform surface treatment. S27: Forming: Use a picosecond laser to perform scribing and slicing to obtain the finished product.

[0023] Since the base plate uses a composite material combining PP / FPC and ceramic, double-sided cutting using a laser is required for its forming. First, the PP / FPC layer is cut, and then, notches are formed in the ceramic by the laser and it is divided into individual pcs.

[0024] As shown in Figure 2, Figure 2 is an example of a laminated schematic diagram of an embodiment of the product of the present invention. The present invention also provides an embodiment of an ultra-thin high-density multilayer interconnected ceramic substrate. The multilayer interconnected ceramic substrate includes a ceramic wafer, and inner copper foils on the upper and lower surfaces of the ceramic wafer become inner copper-clad layers. In this case, outer copper foils are laminated on the inner copper-clad layers on the upper and lower surfaces of the ceramic wafer by PP to form outer copper-clad layers.

[0025] The ceramic wafer is provided with through holes that can penetrate the upper and lower inner copper-clad layers. A copper base for connecting the upper and lower inner copper-clad layers (upper and lower layer wirings) is formed in the through holes. On one surface of the ceramic substrate, a depth control trench is opened at a position corresponding to the through holes, and a ceramic layer pad for welding a high-power chip is formed at the position of this depth control trench. On the other surface of the ceramic substrate, a depth control trench is also opened at a position corresponding to the through holes, or blind holes are densely arranged in an array to achieve heat dissipation.

[0026] In this embodiment, the multilayer interconnected ceramic substrate adopts a design form of thermal and electrical separation, holds devices with a large heat dissipation amount in the ceramic layer, and vertically interconnects and integrates the remaining conductors. That is, the pads of devices with low power and no requirement for heat conduction are designed in other wiring layers, and when designing, wiring is not performed above the heat dissipation pads. Thereby, the advantages of good heat dissipation performance and high integration density of the ceramic substrate are ensured.

[0027] Although the specific embodiments of the invention have been described in detail above, these are exemplary, and the present invention is not limited to the above specific embodiments. For those skilled in the art, all equivalent corrections or substitutions added to the present invention are included within the scope of the present invention. Therefore, equivalent modifications, corrections, improvements, etc. made without departing from the spirit and principles of the present invention are included within the scope of the present invention.

Claims

1. 1. A method for manufacturing an ultra-thin, high density, multi-layer interconnect ceramic substrate, comprising: providing a ceramic wafer and performing laser drilling on the ceramic wafer to form via holes; performing vacuum magnetron sputtering on the ceramic wafer to sputter a seed titanium layer and a copper layer on the surface of the ceramic wafer and on the walls of the via holes; Producing a ceramic two-layer core board; manufacturing a multi-layer substrate; The ceramic wafer is made of aluminum oxide, aluminum nitride, silicon nitride, or beryllium oxide; When a seed titanium layer and a copper layer are formed by sputtering on the surface of a ceramic wafer and the wall of a via hole, the thickness of the seed titanium layer is 0.25 μm or more, and the thickness of the copper layer is 0.8 μm or more; The ceramic wafer is subjected to vacuum magnetron sputtering to form a seed titanium layer and a copper layer on the surface of the ceramic wafer and on the wall of the via hole by sputtering, and then The method further includes the steps of: performing electroplating on the ceramic substrate to fill the holes, thereby completely filling the via holes in the ceramic wafer; and at the same time, increasing the thickness of the surface copper of the ceramic wafer to a thickness of 45 μm or more; The step of manufacturing a ceramic two-layer core board includes: polishing the ceramic wafer with the increased thickness of the surface copper by filling the holes by electroplating to make the copper surface flat; performing a first pattern transfer to transfer a desired wiring pattern onto the copper surface; Etching the desired traces on the copper surface by an etching process; and performing titanium removal on the ceramic wafer using a chemical solution to sufficiently remove the seed titanium layer and obtain a ceramic two-layer core board. After the ceramic two-layer core board is manufactured, performing an AOI inspection and a full electrical test on the ceramic core board; forming a brown oxide thin film on the copper surface of the ceramic core plate by brown oxidation treatment; The step of manufacturing a multi-layer substrate includes: a step of assembling and laminating a semi-hardened sheet + copper foil or FPC on the upper and lower surfaces of the ceramic core plate after brown oxidation treatment; and laminating the semi-cured sheet + copper foil or FPC and the ceramic core board together by a lamination method to obtain a laminated multi-layer board. The steps of manufacturing a top-bottom interconnect multi-layer board include: a mark point exposing step of removing the copper and PP dielectric of the outer layer using a laser to expose the mark points of the inner layer; a blind hole laser processing step of forming a blind hole channel in the inner layer and the outer layer through the mark point in the inner layer; a slag removal step of completely removing the slag in the blind hole by plasma microetching; a copper deposition step of depositing a copper seed metal on the walls of the blind holes by chemical copper deposition; a panel plating step in which a seed layer of chemically deposited copper is electroplated to a thickness of 3-5 μm; a blind hole electroplating step, which uses an electroplating method to completely fill the blind holes and at the same time electroplats the surface of the substrate to a thickness of 40 μm or more with copper; a polishing step of polishing the copper surface of the substrate after electroplating to a flat surface; a second pattern transfer step of transferring the image onto the copper surface by an image transfer process; and an etching step of forming a wiring pattern by an etching process to obtain a top-bottom interconnection multi-layer board.

2. The steps of manufacturing a high-end multi-layer HDI ceramic substrate include: Drilling trenches in a controlled thickness in the upper and lower interconnect multi-layer board and removing the insulating dielectric with a picosecond laser to expose pads for high power chip welding on the ceramic core board; forming a solder mask / symbol; performing a surface treatment; 2. The method of claim 1, further comprising the steps of: using a picosecond laser to scribe and slice to obtain a finished high-end HDI ceramic multi-layer substrate.

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