RF Amplifier Device and Manufacturing Method

Abstract

The transistor amplifier includes a semiconductor layer structure including first and second major surfaces and a plurality of unit cell transistors on the first major surface electrically connected in parallel, each unit cell transistor including a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger, and the semiconductor layer structure does not include vias to the source fingers on the second major surface.

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims priority to U.S. Patent Application No. 17 / 018,762, filed on September 11, 2020, which claims priority as a continuation - in - part of U.S. Patent Application No. 16 / 906,610, filed on June 19, 2020, which claims priority under 35 U.S.C.§119 to U.S. Provisional Patent Application No. 63 / 004,765, filed on April 3, 2020, the entire contents of which are incorporated herein by reference.

[0002] The present disclosure relates to integrated circuit devices, and more particularly, to structures for packaging integrated circuit devices.

Background Art

[0003] RF power amplifiers are used in various applications such as base stations for wireless communication systems, multi - stage and multi - path amplifiers (e.g., Doherty amplifiers). Signals amplified by RF power amplifiers often include signals having a modulated carrier with a frequency in the range from megahertz (MHz) to gigahertz (GHz). For example, there is an increasing prevalence of electrical circuits that operate at high frequencies such as the R band (0.5 - 1 GHz), S band (3 GHz), X band (10 GHz), Ku band (12 - 18 GHz), K band (18 - 27 GHz), Ka band (27 - 40 GHz), and V band (40 - 75 GHz) and require high power handling capabilities. In particular, there is currently a high demand for radio frequency (「RF」) transistor amplifiers used to amplify RF signals at frequencies of, for example, 500 MHz or higher (including microwave frequencies). These RF transistor amplifiers need to exhibit high reliability, good linearity, and be able to handle high output power levels.

[0004] Many RF power amplifier designs utilize semiconductor switching devices as the amplification device. Examples of these switching devices include power transistor devices such as MOSFETs (metal-oxide-semiconductor field-effect transistors), DMOS (double-diffused metal-oxide-semiconductor) transistors, HEMTs (high electron mobility transistors), MESFETs (metal-semiconductor field-effect transistors), and LDMOS (laterally-diffused metal-oxide-semiconductor) transistors.

[0005] RF amplifiers are typically formed as semiconductor integrated circuit chips. Most RF amplifiers are implemented in silicon or using wide-bandgap semiconductor materials such as silicon carbide (“SiC”) and Group III nitride materials (i.e., having a bandgap greater than 1.40 eV). As used herein, the term “Group III nitride” refers to semiconductor compounds formed between nitrogen and Group III elements of the periodic table, typically aluminum (Al), gallium (Ga), and / or indium (In). This term also refers to ternary and quaternary compounds such as AlGaN and AlInGaN. These compounds have an empirical formula in which 1 mole of nitrogen is combined with a total of 1 mole of Group III elements.

[0006] Silicon-based RF amplifiers are typically implemented using LDMOS transistors and can exhibit a high level of linearity in relatively inexpensive manufacturing. Group III nitride-based RF amplifiers are typically implemented using HEMTs in applications that require high output and / or high-frequency operation where LDMOS transistor amplifiers may have inherent performance limitations.

[0007] An RF transistor amplifier can include one or more amplification stages, and each stage is typically implemented as a transistor amplifier. To increase the output power and current handling capacity, an RF transistor amplifier is typically implemented in a "unit cell" configuration where a number of individual "unit cell" transistors are electrically arranged in parallel. The RF transistor amplifier may be implemented as a single integrated circuit chip or "die", or may include multiple dies. When multiple RF transistor amplifier dies are used, they may be connected in series and / or in parallel.

[0008] The RF transistor amplifier often includes a matching circuit such as an impedance matching circuit designed to improve the impedance matching between an active transistor die (including, for example, MOSFET, HEMT, LDMOS, etc.) and a transmission line connected thereto for an RF signal at the fundamental operating frequency, and a harmonic termination circuit designed to at least partially terminate harmonic products that can be generated during device operation, such as second and third harmonic products. The termination of harmonic products also affects the generation of intermodulation distortion products.

[0009] The RF amplifier transistor die, as well as the impedance matching circuit and the harmonic termination circuit, may be encapsulated within a device package. A die or chip can refer to a small block of semiconductor material or other substrate on which electronic circuit elements are fabricated. Integrated circuit packaging can refer to encapsulating one or more dies within a support case or package that protects the die from physical damage and / or corrosion and supports electrical contacts for connection to external circuits. The input and output impedance matching circuits within an integrated circuit device package typically include an LC network that provides at least a portion of an impedance matching circuit configured to match the impedance of the active transistor die to a fixed value. Electrical lead wires may extend from the package to electrically connect the RF amplifier to external circuit elements such as input and output RF transmission lines and a bias voltage source.

[0010] Some conventional methods for assembling RF power devices may involve assembling some of the transistor die and matching network components within a ceramic or overmolded package on a CPC (copper, copper - molybdenum, copper laminate structure) or copper flange. The transistor die, capacitors, and input / output leads may be interconnected with wires such as gold and / or aluminum wires. Such an assembly process can be slow, continuous (e.g., one package is bonded at a time), and can result in high assembly costs (e.g., due to the cost of gold wires and expensive wire bond machines).

Summary of the Invention

[0011] According to some embodiments, a radio frequency ("RF") transistor amplifier includes a semiconductor layer structure including a first and a second major surface and a plurality of unit cell transistors on the first major surface electrically connected in parallel, each unit cell transistor including a gate finger coupled to a gate manifold, a drain finger coupled to a drain manifold, and a source finger. The semiconductor layer structure does not include vias to the source fingers on the second major surface.

[0012] In some embodiments, the RF transistor amplifier further includes coupling elements on the first major surface, the coupling elements including a gate connection pad configured to be connected to the gate manifold, a drain connection pad configured to be connected to the drain manifold, and a source connection pad configured to be connected to each of the source fingers.

[0013] In some embodiments, the RF transistor amplifier further includes a carrier substrate on the second major surface of the semiconductor layer structure.

[0014] In some embodiments, the RF transistor amplifier further includes a thermal conduction layer and / or a conductive layer on the second major surface of the semiconductor layer structure between the semiconductor layer structure and the carrier substrate.

[0015] In some embodiments, the RF transistor amplifier further includes a circuit module on a semiconductor layer structure, the circuit module including a gate lead wire connection pad electrically coupled to a gate manifold and a drain lead wire connection pad electrically coupled to a drain manifold.

[0016] In some embodiments, the RF transistor amplifier further includes an input lead wire electrically coupled to the gate lead wire connection pad and configured to extend externally from a package including the RF transistor amplifier, and an output lead wire electrically coupled to the drain lead wire connection pad and configured to extend externally from a package including the RF transistor amplifier.

[0017] In some embodiments, the RF transistor amplifier further includes one or more circuit elements attached to a first side and / or a second side of the circuit module.

[0018] In some embodiments, the RF transistor amplifier further includes a thermally conductive and / or electrically conductive auxiliary spacer layer on the one or more circuit elements.

[0019] In some embodiments, the semiconductor layer structure further comprises a high electron mobility transistor (HEMT) or a laterally diffused metal oxide semiconductor (LDMOS) transistor.

[0020] According to some embodiments, a transistor amplifier includes a Group-III nitride-based amplifier die including a gate terminal, a drain terminal, and a source terminal on a first surface of the amplifier die, and a circuit module on the first surface of the amplifier die and on the gate terminal, the drain terminal, and the source terminal of the amplifier die and electrically coupled to the gate terminal, the drain terminal, and the source terminal of the amplifier die. The circuit module includes one or more circuit elements coupled between the gate terminal of the transistor amplifier and a first lead wire and / or between the drain terminal of the transistor amplifier and a second lead wire. The circuit module has a first surface and a second surface opposite the first surface of the circuit module, and the first surface of the circuit module is adjacent to the first surface of the amplifier die.

[0021] In some embodiments, the one or more circuit elements are attached to the first surface and / or the second surface of the circuit module.

[0022] In some embodiments, the transistor amplifier further includes a thermally conductive and / or electrically conductive auxiliary spacer layer on the one or more circuit elements.

[0023] In some embodiments, the one or more circuit elements are formed within the circuit module.

[0024] In some embodiments, the first and / or second lead wires are coupled to the second surface of the circuit module.

[0025] In some embodiments, the first and / or second lead wires are coupled to the first surface of the circuit module.

[0026] In some embodiments, the circuit module includes a first interconnect pad and a second interconnect pad on the first surface of the circuit module. The first interconnect pad is configured to be coupled to the gate terminal of the amplifier die, and the second interconnect pad is configured to be coupled to the drain terminal of the amplifier die.

[0027] In some embodiments, the circuit module further comprises a third interconnect pad configured to be coupled to the source terminal of the amplifier die on the first surface of the circuit module.

[0028] In some embodiments, the transistor amplifier further includes a coupling element between the amplifier die and the circuit module.

[0029] According to some embodiments, a radio frequency (RF) transistor amplifier includes an RF transistor amplifier die having a first major surface and a second major surface, the RF transistor amplifier die including a gate terminal, a drain terminal, and a source terminal on the first major surface, a circuit module on the first major surface of the RF transistor amplifier die, the circuit module including a gate lead wire connection pad electrically coupled to the gate terminal and a drain lead wire connection pad electrically coupled to the drain terminal, a carrier substrate on the second major surface of the RF transistor amplifier die, and a thermally conductive and / or electrically conductive spacer layer between the RF transistor amplifier die and the carrier substrate.

[0030] In some embodiments, the circuit module includes a first side adjacent to the first major surface of the RF transistor amplifier die and a second side opposite the first side, and the circuit module includes one or more circuit elements coupled to the gate terminal and / or the drain terminal.

[0031] In some embodiments, the one or more circuit elements are attached to the first side and / or the second side of the circuit module.

[0032] In some embodiments, the RF transistor amplifier further includes a thermally conductive and / or electrically conductive auxiliary spacer layer on the one or more circuit elements.

[0033] In some embodiments, the spacer layer and the auxiliary spacer layer form an integral spacer layer.

[0034] In some embodiments, the RF transistor amplifier further includes an input lead wire and / or an output lead wire coupled to a second side surface of the circuit module.

[0035] In some embodiments, the RF transistor amplifier further includes a coupling element between the RF transistor amplifier die and the circuit module, the coupling element having a bottom surface adjacent to a first major surface of the RF transistor amplifier die and an upper surface opposite the bottom surface. The upper surface of the coupling element includes a gate connection pad configured to be connected to a first interconnect pad of the circuit module, a drain connection pad configured to be connected to a second interconnect pad of the circuit module, and a source connection pad configured to be connected to a third interconnect pad of the circuit module.

[0036] In some embodiments, the RF transistor amplifier further includes a sidewall and a lid. The carrier substrate, the sidewall, and the lid define an internal cavity, and the RF transistor amplifier die is within the internal cavity.

[0037] In some embodiments, the RF transistor amplifier further includes overmolded material on the circuit module and the RF transistor amplifier die.

[0038] In some embodiments, the RF transistor amplifier die is a group III nitride-based RF transistor amplifier die.

[0039] In some embodiments, the operating frequency of the RF transistor amplifier is in the R band, S band, X band, Ku band, K band, Ka band, and / or V band.

[0040] Other devices, apparatuses, and / or methods according to some embodiments will become apparent to those skilled in the art by considering the following drawings and detailed description. In addition to every possible combination of the above embodiments, all such additional embodiments are included within this description, are within the scope of the present invention, and are intended to be protected by the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0041]

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DETAILED DESCRIPTION OF THE INVENTION

[0042] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of embodiments of the present disclosure. However, it will be understood by those of ordinary skill in the art that the present disclosure may be practiced without these specific details. In some instances, well-known methods, procedures, components, and circuits have not been described in detail so as not to obscure the present disclosure. All embodiments disclosed herein are intended to be practiced separately or in any method and / or combination. Aspects described with respect to one embodiment may be incorporated into different embodiments even if not specifically described with respect thereto. That is, all embodiments and / or features of any embodiment may be combined in any method and / or combination.

[0043] According to an embodiment of the present invention, there is provided a group-III nitride-based RF transistor amplifier including an RF transistor amplifier die in which a gate terminal, a drain terminal, and a source terminal are all located on an upper surface of the RF transistor amplifier die. In some embodiments, the RF transistor amplifier may not include bond wires for gate and drain connections, thereby reducing the amount of inductance present in the circuit. The upper surface contacts can enable a coupling element to be directly coupled to the gate terminal, drain terminal, and source terminal of the RF transistor amplifier die. The coupling element may be further connected in a convenient manner to additional circuits such as a harmonic termination circuit, an input impedance matching circuit, and / or an output impedance matching circuit. In certain embodiments where the substrate of the transistor die has a high thermal conductivity, such as a SiC growth substrate for a group-III nitride-based HEMT, the die can be mounted with the substrate on a thermally conductive carrier substrate or submount such as a metal slug, a lead frame, or a flange to improve heat dissipation of heat generated by the die from the amplifier package.

[0044] Figure 1A is a schematic cross-sectional view of a conventional high electron mobility transistor 10. As shown in Figure 1A, the high electron mobility transistor 10 may be formed on a substrate 22 such as silicon carbide, silicon, sapphire, etc. A channel layer 24 is formed on the substrate 22. A barrier layer 26 is formed on the channel layer 24 on the opposite side of the substrate 22. The channel layer 24 may include, for example, gallium nitride (GaN), and the barrier layer 26 may include, for example, aluminum gallium nitride (AlGaN).

[0045] Both the channel layer 24 and the barrier layer 26 can form a semiconductor structure 90 on the substrate 22. Source contact 56 and drain contact 54 are formed on the upper surface of the barrier layer 26 and are laterally spaced apart from each other. The source contact 56 and the drain contact 54 may form ohmic contacts to the barrier layer 26.

[0046] A gate contact 52 is formed on the upper surface of the barrier layer 26 between the source contact 56 and the drain contact 54. When the HEMT device 10 is biased to be in its conducting state or "on" state, a two-dimensional electron gas (2DEG) layer is formed at the junction between the channel layer 24 and the barrier layer 26. The 2DEG layer acts as a highly conductive layer that allows current to flow between the source region and the drain region of the device, which are respectively under the source contact 56 and the drain contact 54.

[0047] The source contact 56 can be coupled to a reference signal such as a ground voltage. The coupling to the reference signal may be provided by a via 66 that extends from the lower surface 22A of the substrate 22 through the substrate 22 to the upper surface 26A of the barrier layer. The via 66 can expose the lower surface 56A of the source contact 56. A back metal layer 35 may be formed on the lower surface 22A of the substrate 22 and on the sidewalls of the via 66. The back metal layer 35 may be in direct contact with the source contact 56. Thus, the back metal layer 35, and the signal coupled thereto, can be electrically connected to the source contact 56.

[0048] In some embodiments, one or more insulating layers 50 may directly contact the top surface of the semiconductor structure 90 (e.g., contact the top surface 26A of the barrier layer 26). The one or more insulating layers 50 can function as a passivation layer for the HEMT device 10. In some embodiments, additional metal contacts (not shown) may be provided to contact the gate contact 52 and / or the drain contact 54.

[0049] As described above, group III nitride-based RF amplifiers including the HEMT device shown in FIG. 1A are often used in high-power and / or high-frequency applications. Typically, a high level of heat is generated within the group III nitride-based RF amplifier die during operation. If the RF die becomes too hot, the performance of the RF amplifier (e.g., output power, efficiency, linearity, gain, etc.) may degrade and / or the RF amplifier die may be damaged. Thus, group III nitride-based RF amplifiers are typically mounted in packages that can be optimized for heat removal. FIGS. 1B and 1C show conventional packaged group III nitride-based RF amplifiers. In particular, FIG. 1B is a schematic side view of a conventional packaged group III nitride-based RF amplifier 100, and FIG. 1C is a schematic cross-sectional view of an RF transistor amplifier die included in the packaged group III nitride-based RF transistor amplifier 100, the cross-section being along line 1C-1C of FIG. 1B. FIGS. 1B-1C (and various other figures) are highly simplified figures, and it will be understood that an actual RF amplifier may include many unit cells as well as various circuits and elements not shown in the simplified figures herein.

[0050] As shown in FIG. 1B, the group-III nitride-based RF amplifier 100 includes an RF amplifier die 110 mounted within a package 170. The package 170 includes a gate lead wire 172, a drain lead wire 174, a carrier substrate 176, and a housing 178. The RF transistor amplifier die 110 is mounted on the upper surface of a carrier substrate 176 that can be provided with, for example, a metal flange. The RF amplifier die 110 has an upper surface 112 and a bottom surface 114. The RF amplifier die 110 includes a bottom surface (also referred to as the "back" surface) metallization structure 120, a semiconductor layer structure 130, and an upper surface metallization structure 140 that are sequentially stacked. The bottom surface metallization structure 120 includes a source terminal 126. The RF amplifier 100 may be a HEMT-based RF amplifier as shown in FIG. 1A, in which case the semiconductor layer structure 130 may include at least a channel layer and a barrier layer that are typically formed on a semiconductor or insulating growth substrate (such as a SiC, silicon, or sapphire substrate). The growth substrate may be formed of a non-semiconductor material or may be considered part of the semiconductor layer structure 130. The upper surface metallization structure 140 includes, among other things, a gate terminal 142 and a drain terminal 144.

[0051] The input matching circuit 190 and / or the output matching circuit 192 may also be mounted within the housing 178. The matching circuits 190, 192 may be impedance matching circuits that match the impedance of the fundamental wave component of the RF signal input to or output from the RF transistor amplifier 100 to the impedance at the input or output of the RF transistor amplifier die 110, respectively, and / or harmonic termination circuits configured to short-circuit harmonics of the fundamental RF signal that may be present at the input or output of the RF transistor amplifier die 110, such as second or third harmonics. As schematically shown in FIG. 1B, the input and output matching circuits 190, 192 may be attached to the metal flange 176. The gate lead 172 may be connected to the input matching circuit 190 by one or more first bond wires 182, and the input matching circuit 190 may be connected to the gate terminal 142 of the RF amplifier die 110 by one or more second bond wires 183. Similarly, the drain lead 174 may be connected to the output matching circuit 192 by one or more fourth bond wires 185, and the output matching circuit 192 may be connected to the drain terminal 144 of the RF amplifier die 110 by one or more third bond wires 184. The source terminal 126 of the RF transistor amplifier die 110 may be directly attached to the metal flange 176. The metal flange 176 can provide an electrical connection to the source terminal 126 and can also function as a heat dissipation structure. The first to fourth bond wires 182 to 185 can form part of the input and / or output matching circuits. The housing 178 can include a ceramic housing, and the gate lead 172 and the drain lead 174 can extend through the housing 178. The housing 178 can include a plurality of components such as a lower portion of a side wall, a frame that supports the gate and drain leads 172, 174, and a lid disposed on the upper portion of the frame. The interior of the device can have a cavity filled with air.

[0052] FIG. 1C is a schematic cross-sectional view of the RF amplifier die 110 through a portion of the upper surface metallization structure 140. Dielectric layers insulating the various conductive elements of the upper surface metallization structure 140 from each other are not shown in FIG. 1C for simplicity of the figure.

[0053] As shown in FIG. 1C, the RF transistor amplifier die 110 includes a group-III nitride-based HEMT RF transistor amplifier having a plurality of unit cell transistors 116 each including a gate finger 152, a drain finger 154, and a source finger 156. The gate fingers 152 are electrically connected to a common gate manifold 146, and the drain fingers 154 are electrically connected to a common drain manifold 148. The gate manifold 146 is electrically connected to a gate terminal 142 (e.g., via a conductive via extending upward from the gate manifold 146) that can be implemented as a gate bond pad (see FIG. 1B), and the drain manifold 148 is electrically connected to a drain terminal 144 (e.g., via a conductive via extending upward from the drain manifold 148) that can be implemented as a drain bond pad (see FIG. 1B). The source fingers 156 are electrically connected to a source terminal 126 via a plurality of conductive source vias 166 extending through the semiconductor layer structure 130. The conductive source vias 166 can include metal plating vias extending completely through the semiconductor layer structure 130.

[0054] Referring back to FIG. 1B, the carrier substrate 176 (here a metal flange) can act as a heat sink to dissipate heat generated within the RF amplifier die 110. The heat is mainly generated at the upper portion of the RF amplifier die 110 where a relatively high current density is generated, for example, within the channel regions of the unit cell transistors 116. This heat may be transferred to the carrier substrate 176 through both the source vias 166 and the semiconductor layer structure 130.

[0055] FIG. 1D is a schematic side view of a conventional packaged group III nitride-based RF transistor amplifier 100' similar to the RF transistor amplifier described above with reference to FIG. 1B. The RF transistor amplifier 100' is different from the RF transistor amplifier 100 in that it includes a different package 170'. The package 170' includes a metal submount 176 (which acts as a metal heat sink and can be mounted as a metal slug), as well as gate lead wires and drain lead wires 172', 174'. In some embodiments, a metal lead frame can be formed, which is then processed to provide the metal submount 176 and / or the gate lead wires and drain lead wires 172', 174'. The RF transistor amplifier 100' also includes a plastic overmold 178' that at least partially surrounds the RF transistor amplifier die 110, the lead wires 172', 174', and the metal submount 176. The plastic overmold 178' replaces the ceramic sidewalls and lid 178 included in the RF transistor amplifier 100.

[0056] Depending on the embodiment, the packaged transistor amplifier 100' can include, for example, a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die 110, in which case the RF transistor amplifier die 110 incorporates a plurality of individual devices. In some embodiments, the packaged RF transistor amplifier 100 can include a plurality of RF transistor amplifier dies connected in series to form a multi-stage RF transistor amplifier, and / or a plurality of transistor dies arranged in a plurality of paths (e.g., in parallel) to form an RF transistor amplifier having a plurality of RF transistor amplifier dies and a plurality of paths, such as in a Doherty amplifier configuration.

[0057] In other cases, the group-III nitride-based RF amplifier may be implemented as a MMIC device in which one or more RF amplifier dies are implemented in a single integrated circuit die together with their associated impedance matching circuits and harmonic termination circuits. An example of such a group-III nitride-based RF amplifier is disclosed, for example, in U.S. Patent No. 9,947,616, the entire content of which is incorporated herein by reference. When the RF transistor amplifier die 110 is a MMIC implementation, the input matching circuit 190 and / or the output matching circuit 192 may be omitted (since they may alternatively be implemented within the RF transistor amplifier die 110), and the bond wires 182 and / or 185 may extend directly from the gate lead wire and drain lead wires 172', 174' to the gate terminal and drain terminal 142, 144.

[0058] Conventional group-III nitride-based RF transistor amplifiers, such as the RF transistor amplifier 100 of FIGS. 1A-1D, can connect the RF transistor amplifier die 110 to other parts of the package using bond wires 182, 184. These bond wires 182, 184 have an inherent inductance that can be used to implement some of the inductors in the impedance matching circuit and / or harmonic termination circuit of the RF transistor amplifier. The amount of inductance provided can be varied by changing the length and / or cross-sectional area (e.g., diameter) of the bond wires 182, 184 such that the bond wires 182, 184 provide the desired amount of inductance. Unfortunately, as the application migrates to higher frequencies, the inductance of the bond wires 182, 184 can exceed the desired amount of inductance for the impedance matching circuit and / or harmonic termination circuit. If this occurs, bond wires 182, 184 having a very short and / or large cross-sectional area can be used as an attempt to reduce the inductance to an appropriate level. However, very short bond wires 182, 184 can be difficult to solder in place, can increase manufacturing costs, and / or can result in a higher device failure rate. Bond wires 182, 184 having a large cross-sectional area may require larger gate bond pads and drain bond pads on the RF transistor amplifier die, which can increase the overall size of the RF transistor amplifier die, which is also undesirable. Further, in some high-frequency applications, even very short bond wires 182, 184 having a large cross-sectional area can have excessive inductance, such that the matching network cannot properly terminate, for example, second or third harmonics. To avoid the problem of the inductance in the bond wires 182, 184 being too large, the RF transistor amplifier can be implemented as an MMIC device, but MMIC RF amplifiers are more costly to manufacture, can only be used within the frequency range of the matching circuit, and have reduced flexibility.

[0059] Furthermore, wire bonding apparatuses commonly used in mass production can have a tolerance of + / - 1 mil, which means that the length of any particular wire bond can vary by 2 mils (i.e., + / - 1 mil at each end of the bond wire). In high-frequency applications, the inductance variation associated with a 2-mil wire bond can be significant, and thus, if the bond wire is 1 - 2 mils too short or too long from the desired nominal length, the performance of the matching circuit can degrade. By forming gate and drain terminals on the upper surface of the device and using coupling elements to connect these terminals to additional circuitry, the variations in this process can be significantly eliminated, resulting in improved performance.

[0060] Embodiments of the present invention will be described in further detail with reference to the accompanying drawings.

[0061] Figures 2A - 2G show a group III nitride-based RF transistor amplifier 200 according to a particular embodiment of the present invention. In particular, Figure 2A is a schematic side view of the group III nitride-based RF transistor amplifier 200. Figure 2B is a schematic plan view of an RF transistor amplifier die 210, which is part of the group III nitride-based RF transistor amplifier 200 of Figure 2A, taken along line 2B - 2B of Figure 2A. Figures 2C - 2F are schematic cross-sectional views of the RF transistor amplifier die 210 taken along lines 2C - 2C to 2F - 2F of Figure 2B, respectively. Figure 2G is an alternative embodiment of the source terminal shown in Figure 2D. Figures 2H - 2L are cross-sectional views of additional embodiments of group III nitride-based RF transistor amplifiers 200', 200'' according to particular embodiments of the present invention.

[0062] As shown in FIG. 2A, in some embodiments, the group III nitride-based RF transistor amplifier 200 can include an RF transistor amplifier die 210 attached to the bottom surface of the coupling element 270. The RF transistor amplifier die 210 has an upper surface 212 and a back surface 214. The RF transistor amplifier die 210 includes an upper surface metallization structure 220, a semiconductor layer structure 230, and a bottom surface thermal layer 240 that are sequentially stacked. The upper surface metallization structure 220 includes a gate terminal 222, a drain terminal 224, and one or more source terminals 226. The RF transistor amplifier 200 may be a HEMT-based RF transistor amplifier, in which case the semiconductor layer structure 230 may include at least a channel layer and a barrier layer, as will be described in more detail with reference to FIGS. 2C and 2D. In some configurations, as further described herein, the coupling element 270 may be omitted from the RF transistor amplifier 200.

[0063] The coupling element 270 may be configured to couple to the gate terminal 222, the drain terminal 224, and one or more source terminals 226. In some cases, the coupling element 270 can include a redistribution layer (RDL) stack and / or an interposer. The RDL stack refers to a substrate having conductive layer patterns and / or conductive vias. The RDL stack can be manufactured using semiconductor processing techniques by depositing conductive and insulating layers and / or patterns on a substrate and by forming vias and routing patterns (e.g., from copper) in the structure for transmitting signals through the RDL stack. For example, as shown in FIG. 2A, the coupling element 270 can include a conductive pattern 273 formed within an encapsulation structure 277.

[0064] On the upper surface of the coupling element 270, a gate connection pad 272, a drain connection pad 274, and a source connection pad 276 are provided. Each of these connection pads 272, 274, 276 can include, for example, an exposed copper pad, but the present invention is not limited thereto. The gate connection pad 272 may be electrically coupled to the gate terminal 222 by one or more conductive patterns 273 within the coupling element 270. Similarly, the drain connection pad 274 may be electrically coupled to the drain terminal 224 by one or more conductive patterns 273 within the coupling element 270, and the source connection pad 276 may be electrically coupled to the source terminal 226 by one or more conductive patterns 273 within the coupling element 270.

[0065] In some embodiments, the conductive pattern 273 of the coupling element 270 may be configured in a fan-out (FO) configuration. The FO configuration can enable an increase in the spacing between the connection portions to each of the source terminal, the gate terminal, and the drain terminal, and can enable an increase in the separation of the connection portions. However, the present invention is not limited to FO connections. In some embodiments, fan-in connections, fan-in and fan-out configurations, or other configurations can be used.

[0066] In some embodiments, the bonding element 270 and / or the RDL stack structure may be formed as part of a wafer level packaging (WLP) operation, but the invention is not limited thereto. For example, the bonding element 270 can be formed by disposing conductive pillars on the gate terminal 222, the drain terminal 224, and one or more source terminals 226. In some embodiments, the conductive pillars may include copper. For example, the conductive pillars may be formed by electroplating a copper seed using one or more masks to form a pattern. The conductive pillars may form a conductive pattern 273. Also, the gate connection pad 272, the drain connection pad 274, and the source connection pad 276 may be formed on the conductive pattern 273. The conductive pattern 273, the gate connection pad 272, the drain connection pad 274, and the source connection pad 276 can be at least partially disposed within an encapsulation structure 277 that can include an overmold material. Examples of the overmold material include silicon oxide, silicon nitride, oxides of the conductive pattern 273, polymers, molding compounds, and / or combinations thereof. The overmold material can be processed (e.g., planarized) to expose the gate connection pad 272, the drain connection pad 274, and / or the source connection pad 276. In some embodiments, the formation of the bonding element 270 may be performed at the wafer level, and the individual RF transistor amplifier dies 210 and / or the RF transistor amplifiers 200 may be isolated from the wafer.

[0067] In some embodiments, the bonding element 270 may be formed in a chip - first or chip - last process. In a chip - first process, the RDL structure may be formed on the die 210 (or the wafer including the die 210). For example, a seed layer can be deposited (e.g., on one or more of the gate terminal 222, drain terminal 224, and one or more source terminals 226). The seed can then be patterned and electroplated to form a layer of conductive material. This process may be repeated multiple times from the conductive pattern 273 of the bonding element 270. These conductive patterns 273 can then be encapsulated within the encapsulation structure 277 to form the bonding element 270.

[0068] In a chip - last process, the RDL layer of the bonding element 270 can be formed on a temporary carrier layer. The conductive pattern 273 may be formed on the temporary carrier layer in the same manner as the chip - first process. When completed, the bonding element 270 can be separated from the temporary carrier layer and then re - bonded to the die 210. For example, the bonding element 270 may be bonded (e.g., via solder) to one or more of the gate terminal 222, drain terminal 224, and one or more source terminals 226.

[0069] For example, other bonding elements 270 such as a printed circuit board (e.g., a multi - layer printed circuit board), a ceramic substrate including conductive vias and / or pads, or any bonding structure for the RF transistor amplifier die 210 that makes an electrical connection to the upper surface 212 of the RF transistor amplifier die 210 may be alternatively used.

[0070] The arrangement of the conductive pattern 273 shown in FIG. 2A is merely an example, and other arrangements are possible without departing from the present invention. For example, in some embodiments, the conductive pattern 273 of the bonding element 270 may extend adjacent to the side surface of the RF transistor amplifier die 210. In some embodiments, the bonding element 270 may have terminals other than those shown in FIG. 2A.

[0071] The thermal layer 240 may be on the back surface 214 of the RF transistor amplifier die 210. The thermal layer 240 may be a thermal conduction layer configured to facilitate heat transfer between the RF transistor amplifier die 210 and the carrier substrate to which the RF transistor amplifier die 210 is attached. In some embodiments, the thermal layer 240 may be omitted. In some embodiments, the thermal layer 240 may be a die attach layer such as a eutectic layer. The thermal layer 240 may be on the transistor amplifier die 210 and / or may extend onto the encapsulation structure 277. The thermal layer 240 can be a metal layer for forming a eutectic bond or other metal bond. In some embodiments, the thermal layer 240 may be a thermal adhesive.

[0072] The RF transistor amplifier die 210 can include a Group-III nitride-based HEMT RF transistor amplifier including a plurality of unit cell transistors 216 electrically connected in parallel to each other. This can be best seen in FIG. 2B which schematically shows a plan view of the RF transistor amplifier die 210 under the upper surface metallization structure 220. The upper surface metallization structure 220 including the gate terminal 222, the drain terminal 224, and one or more source terminals 226 is shown by dashed lines in FIG. 2B.

[0073] As shown in FIG. 2B, the RF transistor amplifier die 210 includes a gate manifold 242 and a drain manifold 244, a plurality of gate fingers 252, a plurality of drain fingers 254, and a plurality of source fingers 246, all of which may be formed on the upper surface of the semiconductor layer structure 230. The gate manifold 242 and the gate fingers 252 are part of the gate electrode of the RF transistor amplifier die 210. The gate manifold 242 and the gate fingers 252 may be implemented as a first monolithic metal pattern, but the present invention is not limited thereto. The drain manifold 244 and the drain fingers 254 are part of the drain electrode of the RF transistor amplifier die 210 and may be implemented as a second monolithic metal pattern, but the present invention is not limited thereto.

[0074] The gate finger 252 can be formed of a material capable of forming a Schottky contact with a group III nitride-based semiconductor material such as Ni, Pt, Cu, Pd, Cr, W, and / or WSiN. The drain finger 254 and the source finger 246 can include a metal (e.g., TiAlN, TiSiNi, etc.) capable of forming an ohmic contact with a group III nitride-based material. A dielectric layer (or a series of dielectric layers) that helps to separate the gate manifold / finger 242, 252, the drain manifold / finger 244, 254, and the source finger 246 from each other is not shown in FIG. 2B for better illustration of the elements of the RF transistor amplifier die 210.

[0075] The gate terminal 222, the drain terminal 224, and the source terminal 226 may be provided on the upper surface of the RF transistor amplifier die 210. The gate terminal 222 may be physically and electrically connected to the gate manifold 242 (e.g., by a conductive via), the source terminal 226 may be physically and electrically connected to the source finger 246 (e.g., by a conductive via), and the drain terminal 224 may be physically and electrically connected to the drain manifold 244 (e.g., by a conductive via). Although the various terminals are shown as being directly connected to the gate / drain manifold and / or the source finger, it will be understood that in some embodiments, intermediate elements may be present. For example, in some embodiments, a capacitor, an inductor, a resistor, etc. may be coupled between the terminal and the respective manifold and / or finger. As an example, a capacitor may be formed on the surface of the RF transistor amplifier die 210 coupled to the drain manifold 244, and the drain terminal 224 may be coupled to the capacitor.

[0076] FIG. 2B also shows one of the unit cell transistors 216. As shown, the unit cell transistor 216 includes gate fingers 252, drain fingers 254, and source fingers 246 together with the portion under the semiconductor layer structure 230. Since all the gate fingers 252 are electrically connected to a common gate manifold 242, all the drain fingers 254 are electrically connected to a common drain manifold 244, and all the source fingers 246 are electrically connected to each other via a source terminal 226 (described later), it can be seen that all the unit cell transistors 216 are electrically connected in parallel.

[0077] The unit cell transistor 216 may be a HEMT device. Suitable structures for III-nitride based HEMT devices that can utilize embodiments of the present invention are described, for example, in U.S. Patent Application Publication No. 2002 / 0066908A1, "Aluminum Gallium Nitride / Gallium Nitride High Electron Mobility Transistors Having A Gate Contact On A Gallium Nitride Based Cap Segment And Methods Of Fabricating Same", published Jun. 6, 2002, by the same applicant; U.S. Patent Application Publication No. 2002 / 0167023A1, "Group-III Nitride Based High Electron Mobility Transistor (HEMT) With Barrier / Spacer Layer", published Nov. 14, 2002; U.S. Patent Application Publication No. 2004 / 0061129, "Nitride-Based Transistors And Methods Of Fabrication Thereof Using Non-Etched Contact Recesses", published Apr. 1, 2004; U.S. Patent No. 7,906,799, "Nitride-Based Transistors With A Protective Layer And A Low-Damage Recess", issued Mar. 15, 2011; and U.S. Patent No. 6,316,793, "Nitride Based Transistors On Semi-Insulating Silicon Carbide Substrates", issued Nov. 13, 2001, the disclosures of which are hereby incorporated by reference in their entirety.

[0078] Referring to FIGS. 2C and 2D, the semiconductor layer structure 230 includes a plurality of semiconductor layers. In the illustrated embodiment, a total of two semiconductor layers are shown, namely a channel layer 234 and a barrier layer 236 on the upper surface of the channel layer 234. The semiconductor layer structure 230 can include additional semiconductor layers and / or non-semiconductor layers. For example, the semiconductor layer structure 230 can include a growth substrate 232 on which other semiconductor layers are grown. The growth substrate 232 can be, for example, a semi-insulating silicon carbide (SiC) substrate which may be a 4H polytype silicon carbide. Other silicon carbide candidate polytypes include 3C, 6H, and 15R polytypes. The growth substrate 232 can be a high-purity semi-insulating (HPSI) substrate available from Cree, Inc. The term "semi-insulating" is used descriptively herein and not in an absolute sense.

[0079] In some embodiments of the present invention, the silicon carbide bulk crystal of the growth substrate 232 can have a resistivity of about 1×10 5 ohm-cm or more at room temperature. Exemplary SiC substrates that can be used in some embodiments of the present invention are manufactured, for example, by Cree, Inc. of Durham, N.C., the assignee of the present invention, and methods of manufacturing such substrates are described, for example, in U.S. Reissue Patent No. 34,861, U.S. Patent No. 4,946,547, U.S. Patent No. 5,200,022, and U.S. Patent No. 6,218,680, the disclosures of which are incorporated herein by reference in their entirety. Although silicon carbide can be used as the substrate material, embodiments of the present application can utilize any suitable substrate such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LGO, zinc oxide (ZnO), LAO, indium phosphide (InP), etc. The growth substrate 232 can be a silicon carbide wafer, and the RF transistor amplifier 200 can be formed at least in part by wafer-level processing, and then the wafer can be diced to provide a plurality of individual RF transistor amplifiers 200.

[0080] SiC has a much closer crystal lattice match to group III nitrides than sapphire (Al2O3) or silicon, which are very common substrate materials for group III nitride devices. The closer lattice match of SiC can result in higher quality group III nitride films than those generally available on sapphire or silicon. SiC also has a very high thermal conductivity, so the total output power of group III nitride devices on silicon carbide is not usually limited by heat dissipation from the substrate as in the case of the same devices formed on sapphire. Also, the availability of semi-insulating SiC substrates can provide device isolation and reduction of parasitic capacitance.

[0081] An optional buffer layer, nucleation layer, and / or transfer layer (not shown) can be provided on the growth substrate 232 under the channel layer 234. For example, an AlN buffer layer can be included to provide an appropriate crystal structure transition between the SiC growth substrate 232 and the rest of the semiconductor layer structure 230. Further, a strain balancing transfer layer can also be provided, for example, as described in U.S. Patent Application Publication No. 2003 / 0102482A1, filed on June 5, 2003, and titled "Strain Balanced Nitride Heterojunction Transistors And Methods Of Fabricating Strain Balanced Nitride Heterojunction Transistors" by the same applicant, which is incorporated herein by reference as if the disclosure were fully set forth herein.

[0082] In some embodiments, the channel layer 234 and the barrier layer 236 may each be formed by epitaxial growth. Techniques for epitaxial growth of group III nitrides are described, for example, in U.S. Patent No. 5,210,051, U.S. Patent No. 5,393,993, and U.S. Patent No. 5,523,589, the disclosures of which are also incorporated herein by reference in their entirety. The channel layer 234 may have a bandgap smaller than the bandgap of the barrier layer 236, and the channel layer 234 may also have an electron affinity greater than that of the barrier layer 236. The channel layer 234 and the barrier layer 236 may include group III nitride-based materials.

[0083] In some embodiments, the channel layer 234 is Al x Ga 1-x N-based group III nitride material such as N, where 0 ≦ x < 1. In a particular embodiment of the present invention, x = 0, indicating that the channel layer 234 is gallium nitride ("GaN"). The channel layer 234 may also be other group III nitrides such as InGaN, AlInGaN, etc. The channel layer 234 may not be doped, or may be unintentionally doped, and may be grown, for example, to a thickness exceeding about 2 nm. The channel layer 234 may also be a multilayer structure such as a superlattice or a combination of GaN, AlGaN, etc.

[0084] The channel layer 234 may have a bandgap smaller than at least a portion of the bandgap of the barrier layer 236, and the channel layer 234 may also have an electron affinity greater than that of the barrier layer 236. In certain embodiments, the barrier layer 236 is AlN, AlInN, AlGaN or AlInGaN having a thickness of about 0.1 nm to about 10 nm or more. In certain embodiments, the barrier layer 236 is thick enough and has an Al composition and doping high enough to induce a significant carrier concentration at the interface between the channel layer 234 and the barrier layer 236.

[0085] The barrier layer 236 may be a group III nitride and may have a bandgap larger than that of the channel layer 234 and an electron affinity smaller than that of the channel layer 234. Thus, in certain embodiments of the present invention, the barrier layer 236 may include AlGaN, AlInGaN, and / or AlN, or a combination of those layers. The barrier layer 236 may be, for example, about 0.1 nm to about 30 nm thick. In certain embodiments, the barrier layer 236 is either undoped or doped with an n-type dopant to a concentration of less than about 10 19 cm -3 -. In some embodiments of the present invention, the barrier layer 236 is Al x Ga 1-x N, where 0 < x < 1. In certain embodiments, the aluminum concentration is about 25%. However, in other embodiments of the present invention, the barrier layer 236 includes AlGaN having an aluminum concentration of about 5% to about 100%. In certain embodiments of the present invention, the aluminum concentration exceeds about 10%.

[0086] Due to the difference in bandgap between the barrier layer 236 and the channel layer 234 and the piezoelectric effect at the interface between the barrier layer 236 and the channel layer 234, a two-dimensional electron gas (2DEG) is induced in the channel layer 234 at the junction between the channel layer 234 and the barrier layer 236. The 2DEG acts as a highly conductive layer that enables conduction between the source region and its associated drain region of each unit cell transistor 216, where the source region is the portion of the semiconductor layer structure 230 directly under the source finger 246 and the drain region is the portion of the semiconductor layer structure 230 directly under the corresponding drain finger 254.

[0087] The semiconductor structure 230 is shown with a channel layer 234 and a barrier layer 236 for illustrative purposes, but the semiconductor structure 230 can include additional layers / structures / elements such as a buffer and / or nucleation layer between the channel layer 234 and the substrate 232, and / or a cap layer on the barrier layer 236. HEMT structures including a substrate, a channel layer, a barrier layer, and other layers are described, for example, in U.S. Patent Nos. 5,192,987, 5,296,395, 6,316,793, 6,548,333, 7,544,963, 7,548,112, 7,592,211, 7,615,774, 7,548,112, and 7,709,269, the disclosures of which are hereby incorporated by reference in their entirety. For example, an AlN buffer layer can be formed on the upper surface of the substrate 232 to provide an appropriate crystal structure transition between the silicon carbide substrate 232 and the rest of the RF transistor amplifier 200. Further, for example, a strain balanced transition layer can be provided as well and / or alternatively, as described in U.S. Patent No. 7,030,428 by the same applicant, the disclosure of which is hereby incorporated by reference as if fully set forth herein. Optional buffer / nucleation / transition layers may be deposited by MOCVD, MBE, and / or HVPE.

[0088] An interlayer insulating layer 238 is formed above the gate fingers 252, the drain fingers 254, and the source fingers 246. The interlayer insulating layer 238 can include a dielectric material such as SiN, SiO2.

[0089] The coupling element 270 may be on the semiconductor layer structure 230 and / or may be coupled to the semiconductor layer structure 230. For example, the conductive pattern 273 may be coupled between the gate connection pad 272 and the gate terminal 222, between the drain connection pad 274 and the drain terminal 224, and between the source connection pad 276 and the source terminal 226, respectively. In FIG. 2C, for ease of explanation, the encapsulation structure 277 of the coupling element 270 is omitted. The gate connection pad 272, the drain connection pad 274, and the source connection pad 276 of the coupling element 270 may extend perpendicular to the gate fingers 252 and the drain fingers 254.

[0090] By disposing all the terminals on the upper surface of the RF transistor amplifier die 210, the RF transistor amplifier 200 according to a particular embodiment of the present invention can omit vias to the back surface of the RF transistor amplifier die 210. If there are no vias on the back surface of the RF transistor amplifier die 210 connecting the source to a grounded conductive submount, the conductive submount need not be electrically active. Further, the back surface of the substrate 232 of the RF transistor amplifier die 210 may be thermally coupled to a thermally conductive submount such as a heat sink or a flange (not shown) to improve heat dissipation. In some embodiments, the thermal layer 240 can facilitate this thermal coupling. When SiC is used as the substrate material, the thermal characteristics of the package can be further improved due to the improved thermal conductivity of SiC.

[0091] Furthermore, by disposing all the terminals on the upper surface of the RF transistor amplifier die 210, it becomes possible to use the coupling element 270 that can bring all the transistor connections to their respective connection pads. Thereby, the RF transistor amplifier die 210 can be further coupled to other elements of the circuit (e.g., other routing elements, ground elements, harmonic and / or input / output impedance matching elements) using a connection method that avoids bonding wires such as solder.

[0092] FIG. 2D shows an example of the connection between various source fingers 246 and source terminals 226. As shown in FIG. 2D, each of the source fingers 246 may be coupled to a respective source terminal 226, but the present invention is not limited thereto. In some embodiments, one or more source terminals 226 may be coupled to two or more source fingers 246. For example, as shown in FIG. 2G, in some embodiments, a single source terminal 226 may be provided, and the source terminal 226 may be connected to each of the individual source fingers 246. In some embodiments, a plurality of source terminals 226 may be provided, each of which is connected to a plurality of source fingers 246. One or more source terminals 226 may be coupled to a source connection pad 276 by a conductive pattern 273 of a coupling element 270.

[0093] FIG. 2E shows an example of the connection between a gate manifold 242 and a gate terminal 222. As shown in FIG. 2E, the gate manifold 242 may be coupled to the gate terminal 222, for example, by a plurality of vias. FIG. 2F shows an example of the connection between a drain manifold 244 and a drain terminal 224. As shown in FIG. 2E, the drain manifold 244 may be coupled to the drain terminal 224, for example, by a plurality of vias. In both FIG. 2E and FIG. 2F, the gate terminal 222 and / or the drain terminal 224 may each be coupled to a gate connection pad 272 and / or a drain connection pad 274 of the coupling element 270 by one or more conductive patterns 273.

[0094] Figures 2C, 2E, and 2F illustrate embodiments where the gate manifold 242 and the gate terminal 222 are separate elements, and the drain-gate manifold 244 and the drain terminal 224 are separate elements (e.g., connected by vias), but the present invention is not limited thereto. For example, FIGS. 2H - 2J illustrate examples where the gate / drain manifold and terminals are single elements. For example, referring to FIGS. 2H and 2I, the device 200' may be configured such that the gate manifold 242 extends to the surface of the RF transistor amplifier die 210 and functions as the gate terminal 222. Similarly, FIGS. 2H and 2J show that the device 200' can be configured such that the drain manifold 244 extends to the surface of the RF transistor amplifier die 210 and functions as the drain terminal 224.

[0095] In some embodiments, additional conductive elements and / or discrete circuit components may be formed as part of the RF transistor amplifier die. FIG. 2K shows an additional embodiment of the RF transistor amplifier die 210' according to some embodiments of the present invention. FIG. 2K is an embodiment shown from the perspective of line 2C - 2C of FIG. 2A as modified as described herein. For example, as shown in FIG. 2K, the RF transistor amplifier die 210' can utilize some conductive patterns 223 between the gate manifold 242 and the gate terminal 222, between the drain-gate manifold 244 and the drain terminal 222, and / or between one or more of the source fingers 246 and the source terminal 246. The conductive patterns 223 may be formed within the interlayer insulating layer 238 of the RF transistor amplifier die 210'.

[0096] The conductive pattern 223 may be utilized to form individual circuit elements integrated with the RF transistor amplifier die 210'. For example, the conductive pattern 223 can form RDLs within the RF transistor amplifier die 210'. FIG. 2K shows a fan-in configuration that couples the gate / drain manifolds 242, 244 and the source fingers 246 to the gate terminal, drain terminal, and source terminals 222, 224, 226, respectively. However, the present invention is not limited thereto. In some embodiments, the conductive pattern 223 may also be coupled to individual circuit elements within the interlayer insulating layer 238, such as in an MMIC configuration. The use of on-die RDLs can enable more flexible packaging options, as well as the integration of specific circuit functions such as impedance matching and / or harmonic termination.

[0097] FIG. 2L shows that the RF transistor amplifier die 210' may be used with a coupling element 270 within the RF transistor amplifier 200''. The embodiment of FIG. 2L can include a first RDL as part of the RF transistor amplifier die 210' and a second RDL as part of the coupling element 270. In some embodiments, the conductive pattern 223 of the RF transistor amplifier die 210' can provide one or more additional integrated circuits such as impedance matching or harmonic termination, and the conductive pattern 273 of the coupling element 270 can provide a fan-in, fan-out, or other configuration. In some embodiments, the combination of the coupling element 270 and the RF transistor amplifier die 210' may be encapsulated within an encapsulation structure (not shown).

[0098] Figures 2A - 2L show a semiconductor layer structure 230 that includes a HEMT, but it will be understood that other types of semiconductor devices can be formed within the semiconductor layer structure 230 without departing from the present invention. For example, the semiconductor layer structure 230 can include a MOSFET, a DMOS transistor, a MESFET, and / or an LDMOS transistor. One of ordinary skill in the art will recognize that by placing all source / drain / gate contacts on one side of the semiconductor layer structure 230, including the use of the coupling element 270, the connection possibilities can be improved and the thermal performance can be improved.

[0099] By placing the gate contact, drain contact, and source contact on the same side of the RF transistor amplifier 200, connection options that were previously not possible can be utilized. These connection options can also enable embodiments that can more strongly utilize the improved thermal conductivity of the SiC material.

[0100] FIG. 3A is a schematic cross - sectional view of an RF transistor amplifier 200 coupled to a circuit module 310 according to some embodiments of the present invention. FIG. 3A includes the elements of the aforementioned RF transistor amplifier 200. Thus, the description of FIG. 3A focuses on portions of the embodiment that are different from those described with respect to the previous figures.

[0101] Referring to FIG. 3A, circuit module 310 may be configured to couple to gate connection pad 272, drain connection pad 274, and source connection pad 276 of coupling element 270. For example, circuit module 310 may expose interconnect pads 322, 324, 326 that may be configured to couple to gate connection pad 272, drain connection pad 274, and source connection pad 276. For example, the first interconnect pad 322 may be configured to couple to gate connection pad 272, the second interconnect pad 324 may be configured to couple to drain connection pad 274, and the third interconnect pad 326 may be configured to couple to source connection pad 276. In some embodiments, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the first, second, and third interconnect pads 322, 324, 326 to gate connection pad 272, drain connection pad 274, and source connection pad 276, respectively. Although shown as a single pad, in some embodiments, one or more of the first, second, and / or third interconnect pads 322, 324, 326 may include multiple pads.

[0102] Each of the first, second, and third interconnect pads 322, 324, 326 may be coupled to one or more conductive patterns 373 within the circuit module 310. The conductive patterns 373 can provide various routings and / or circuits within the circuit module 310. For example, the conductive pattern 373 may connect the first interconnect pad 322 to one or more first surface connection pads 372 and one or more gate lead connection pads 382. Accordingly, the gate connection pad 272 may be electrically coupled to one or more first surface connection pads 372 and one or more gate lead connection pads 382. The conductive pattern 373 may also connect the second interconnect pad 324 to one or more second surface connection pads 374 and one or more drain lead connection pads 384. Accordingly, the drain connection pad 274 may be electrically coupled to one or more second surface connection pads 374 and one or more drain lead connection pads 384. The conductive pattern 373 may also connect the third interconnect pad 326 to one or more third surface connection pads 376 and one or more source lead connection pads 386. Accordingly, the source connection pad 276 may be electrically coupled to one or more third surface connection pads 376 and one or more source lead connection pads 386. Accordingly, the circuit module 310 may have a surface (e.g., the top surface) having a plurality of first surface connection pads 372 each coupled to the gate connection pad 272 of the coupling element 270, a plurality of second surface connection pads 374 each coupled to the drain connection pad 274 of the coupling element 270, and a plurality of third surface connection pads 376 each coupled to the source connection pad 276 of the coupling element 270.

[0103] The conductive pattern 373 may be housed within the separation material 315. In some embodiments, the separation material 315 can include, for example, silicon oxide, silicon nitride, an oxide of the conductive pattern 273, a polymer, a molding compound, or a combination thereof. In some embodiments, the circuit module 310 may be formed as a printed circuit board (PCB). In a PCB embodiment, the separation material 315 may be the substrate of the PCB, and the conductive pattern 373 may be a trace formed within the substrate.

[0104] The presence of the conductive pattern 373 and the first, second, and third surface connection pads 372, 374, 376 may enable several different circuits to be coupled to the RF transistor amplifier 200. For example, the circuit element 350 may be coupled (e.g., via solder or other bonding) between two or more of the first, second, and third surface connection pads 372, 374, 376. The circuit element 350 can provide various electronic functions to the RF transistor amplifier 200. For example, the circuit element 350 can comprise an impedance (e.g., including resistive elements, inductive elements, and capacitive elements) that can be used for impedance matching and / or harmonic termination. In some embodiments, the circuit element 350 can provide strip line components and / or baseband termination to the RF transistor amplifier 200.

[0105] Although shown as being on the surface of circuit module 310, it will be understood that additional circuit elements 350 may be provided internally within circuit module 310. For example, as circuit elements 350 within circuit module 310, one or more ground planes may be formed. Similarly, a stripline may be formed within circuit module 310 (e.g., in conjunction with one or more ground planes). The configurations of conductive pattern 373 and circuit elements 350 shown in FIG. 3A are merely examples and are not intended to limit embodiments of the present invention. In some embodiments, circuit elements 350 and / or conductive pattern 373 may be configured to provide at least a portion of a harmonic termination circuit, a matching circuit, a dividing circuit, a combining circuit, and / or a bias circuit. Other configurations of conductive pattern 373 and / or other types of circuit elements 350 may be used without departing from the scope of the present invention.

[0106] In some embodiments, circuit module 310 and circuit elements 350 may optionally be housed within encapsulation material 316. In some embodiments, encapsulation material 316 may include, for example, silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof.

[0107] The gate lead wire connection pads 382, drain lead wire connection pads 384, and source lead wire connection pads 386 can provide terminals for connecting signals to the respective gates, drains, and sources of the RF transistor amplifier 200. For example, a connection for providing an input signal to the RF transistor amplifier 200 may be coupled to one or more of the gate lead wire connection pads 382. In some embodiments, a connection for receiving an output signal from the RF transistor amplifier 200 may be coupled to the drain lead wire connection pads 384. In some embodiments, a ground signal may be coupled to the source lead wire connection pads 386, but the present invention is not limited thereto. The gate lead wire connection pads 382, drain lead wire connection pads 384, and source lead wire connection pads 386 are shown as being on the bottom surface of the circuit module 310, but this is merely an example and is not intended to limit the present invention. In some embodiments, various lead wire connections may be on the top surface or other surfaces of the circuit module 310.

[0108] By using the circuit module 310 in conjunction with the upper surface contacts of the RF transistor amplifier 200, additional functions such as impedance matching and / or harmonic termination can be conveniently added to the RF transistor amplifier 200 without using extensive wire bonding. Thus, by simply using different circuit modules 310, different functions and / or capabilities can be coupled to the RF transistor amplifier 200. Since the connection points (e.g., terminals) of the RF transistor amplifier 200 are consistent, variations in the configuration of the RF transistor amplifier 200 can be achieved more efficiently than previously available. The reduction or elimination of the need for wire bonds can also enable a reduction in die size in some applications (where the size of the wire bond pads determines the die size), and thus, the RF transistor amplifier die according to embodiments of the present invention can also exhibit an increase in integration density. Thus, the RF amplifier die according to embodiments of the present invention can exhibit improved product assembly consistency, higher yield, increased product integration, cost reduction, and improved RF performance, particularly for products operating at high frequencies such as millimeter wave frequencies.

[0109] The techniques disclosed herein may be particularly beneficial in high-frequency applications because the inductance required for an integrated circuit can be much lower in such applications, and thus the use of conventional bond wires can inject excessive inductance. Further, the tolerance of bond wire length can have a greater impact at higher frequencies, and in high-frequency applications (especially at lower power), the size of the bond pads can determine the size of the die. In some embodiments, any of the RF transistor amplifier dies disclosed herein may be configured to operate at frequencies greater than 1 GHz. In other embodiments, these RF transistor amplifier dies may be configured to operate at frequencies greater than 2.5 GHz. In still other embodiments, these RF transistor amplifier dies may be configured to operate at frequencies greater than 3.1 GHz. In yet additional embodiments, these RF transistor amplifier dies may be configured to operate at frequencies greater than 5 GHz. In some embodiments, these RF transistor amplifier dies may be configured to operate in at least one of the frequency bands of 2.5 - 2.7 GHz, 3.4 - 4.2 GHz, or 5.1 - 5.8 GHz or sub-portions thereof.

[0110] FIG. 3B is a schematic cross-sectional view of an RF transistor amplifier die 210 coupled to a circuit module 310, according to some embodiments of the present invention. FIG. 3B includes elements of the aforementioned circuit module 310, circuit element 350, and RF transistor amplifier die 210. Thus, the description of FIG. 3B focuses on portions of different embodiments than those described with respect to the previous figures.

[0111] Figure 3B shows an embodiment in which circuit module 310 is directly connected to RF transistor amplifier die 210 without intervening coupling element 270. Thus, circuit module 310 may be configured to couple to one or more of gate terminal 222, drain terminal 224, and source terminal 226 of RF transistor amplifier die 210. For example, first interconnect pad 322 of circuit module 310 may be configured to couple to gate terminal 222, second interconnect pad 324 of circuit module 310 may be configured to couple to drain terminal 224, and third interconnect pad 326 of circuit module 310 may be configured to couple to one or more of source terminals 226. In some embodiments, bonding elements (e.g., solder balls and / or bumps) 320 may be used to couple first, second, and third interconnect pads 322, 324, 326 to one or more of gate terminal 222, drain terminal 224, and source terminal 226, respectively. Although shown as a single pad, in some embodiments, one or more of first, second, and / or third interconnect pads 322, 324, 326 may include multiple pads. The configuration shown in Figure 3B may be useful when a fan-in or fan-out configuration of coupling element 270 is not required to provide a connection between RF transistor amplifier die 210 and circuit module 310.

[0112] FIG. 3C shows an embodiment in which circuit module 310 is directly connected to an RF transistor amplifier die 210' incorporating an on-die RDL that utilizes conductive pattern 223 without intervening coupling element 270. Thus, circuit module 310 may be configured to couple to one or more of the gate terminal 222, drain terminal 224, and source terminal 226 of RF transistor amplifier die 210'. RF transistor amplifier die 210' of FIG. 3C is shown in cross-section to illustrate an example of an internal conductive pattern (e.g., of the RDL) coupled to one or more of the gate terminal 222, drain terminal 224, and source terminal 226. In some embodiments, RF transistor amplifier die 210' may be a MMIC. Although shown without coupling element 270, it will be understood that in some embodiments, coupling element 270 may also be present between RF transistor amplifier die 210' and circuit module 310.

[0113] The use of coupling element 270 that utilizes conductive pattern 273 (if present), on-die RDL that utilizes conductive pattern 223 (if present), and circuit module 310 that utilizes conductive pattern 373 can provide an interconnection structure between the gate, drain, and source of RF transistor amplifier die 210 and the gate lead connection pad 382, drain lead connection pad 384, and source lead connection pad 386. By utilizing various combinations of these elements and electrical bonding techniques, a semiconductor package can be provided that eliminates and / or reduces wire bonding.

[0114] FIG. 3D is a schematic cross-sectional view of a circuit module 310' coupled to a plurality of RF transistor amplifiers 200, according to some embodiments of the present invention. FIG. 3E is a schematic cross-sectional view of a circuit module 310' coupled to a plurality of RF transistor amplifier dies 210, according to some embodiments of the present invention. FIGS. 3E and 3E include elements of the aforementioned circuit module 310', circuit element 350, RF transistor amplifier die 210, and RF transistor amplifier 200. Thus, the description of FIGS. 3D and 3E focuses on portions of different embodiments than those described with respect to the previous figures.

[0115] Referring to FIG. 3D, the circuit module 310' may be configured to couple to two or more RF transistor amplifiers 200. FIG. 3D also shows that the conductive pattern 373, interconnect pads, and surface connection pads may be modified without departing from the scope of the present invention. For example, the circuit module 310' may include a plurality of interconnect pads 327. The interconnect pads 327 may be configured to couple to terminals of the plurality of RF transistor amplifiers 200. For example, the interconnect pads 327 of the circuit module 310' may be configured to couple to one or more gate connection pads 272, drain connection pads 274, and / or source connection pads 276 of the plurality of RF transistor amplifiers 200.

[0116] Similarly, the circuit module 310' may have surface connection pads 377 coupled to one or more of the interconnect pads 327 via the conductive pattern 373. The circuit element 350 may be coupled to one or more of the surface connection pads 377. By using the conductive pattern 373, interconnect pads 327, surface connection pads 377, and / or circuit element 350, various circuit connections between the plurality of RF transistor amplifiers 200 can be realized. The configuration shown in FIG. 3D is merely a schematic example, and it will be understood that the routing and connection of the various elements of the circuit module 310' can be varied in various ways to produce a complex circuit including the RF transistor amplifiers 200.

[0117] In some embodiments, the circuit module 310' can include one or more gate lead wire connection pads 382, one or more drain lead wire connection pads 384, and one or more source lead wire connection pads 386. Signals provided to the one or more gate lead wire connection pads 382, the one or more drain lead wire connection pads 384, and the one or more source lead wire connection pads 386 may be distributed through the circuit module 310' via the conductive pattern 373 to various ones of the RF transistor amplifiers 200.

[0118] FIG. 3D shows an embodiment in which each of the plurality of RF transistor amplifiers 200 has its own coupling element 270, but it will be understood that other configurations are possible. For example, in some embodiments, a single coupling element 270 may be coupled to a plurality of RF transistor amplifier dies 210. The use of a single coupling element 270 can enable the use of a circuit module 310' with fewer interconnections to the transistor elements of the circuit.

[0119] FIG. 3D shows an embodiment in which the circuit module 310' is coupled to a plurality of RF transistor amplifiers 200 including a coupling element 270. However, the present invention is not limited thereto. In some embodiments, the circuit module 310' may be directly coupled to a plurality of RF transistor amplifier dies 210, 210' that do not include a coupling element 270. FIG. 3E shows an embodiment in which the circuit module 310' is coupled to a plurality of RF transistor amplifier dies 210. It will be understood that the circuit module 310' may also be coupled to a plurality of RF transistor amplifier dies 210' (e.g., as shown in FIG. 2K) without departing from the present invention. The circuit module 310' may be coupled to the RF transistor amplifier dies 210, 210' by, for example, bonding elements (e.g., solder balls and / or bumps) 320. It will be understood that the circuit module 310 may be coupled to a combination of RF transistor amplifiers 200 including a coupling element 270 and RF transistor amplifier dies 210, 210'.

[0120] The circuit module 310' can be used to provide an interconnection to an RF transistor amplifier 200 that can be used to implement a multi-stage and / or multi-path amplifier circuit, such as a Doherty amplifier. The conductive pattern 373 can provide electrical connections for the multi-stage and / or multi-path amplifier circuit and can be coupled to one of the circuit elements 350 to provide a capacitor, inductor, resistor, and / or other circuit elements used in the multi-stage and / or multi-path amplifier circuit. Thus, the circuit module 310' may be configured to provide a modular interconnection that can be easily coupled to a plurality of RF transistor amplifiers without using bond wires.

[0121] Figures 3A - 3E show various combinations of circuit modules 310, 310', coupling elements 270, and RF transistor amplifier dies 210, 210', but it will be understood that the present invention is not limited to the specific combinations shown in those figures. As will be understood by those skilled in the art, the circuit modules 310, 310', coupling elements 270, and RF transistor amplifier dies 210, 210' may be combined in a plurality of variations including those not specifically shown without departing from the present invention. For example, embodiments of the present invention include transistor amplifier dies 210, 210' directly coupled to the circuit modules 310, 310'. Some embodiments of the present invention include transistor amplifier dies 210, 210' coupled to the circuit modules 310, 310' via the coupling element 270. The coupling element 270 and / or the circuit modules 310, 310' can include a PCB or a metal-core PCB and traces on a patterned dielectric material. In some embodiments, the transistor amplifier die 210' can have a conductive pattern such as RDL at the die level, which can include a fan-in and / or fan-out configuration that can be connected to other structures such as the coupling element 270 or the circuit modules 310, 310'.

[0122] FIG. 4A is a schematic cross-sectional view of an RF transistor amplifier 200 and a circuit module 310 coupled to a carrier substrate 410, according to some embodiments of the present invention. FIG. 4B is a schematic cross-sectional view of an RF transistor amplifier 200 coupled to a carrier substrate 410 without a coupling element 270, according to some embodiments of the present invention. FIGS. 4A and 4B include the elements of the aforementioned RF transistor amplifier 200, coupling element 270, and circuit module 310. Thus, the description of FIGS. 4A and 4B focuses on portions of different embodiments than those described with respect to the previous figures.

[0123] Referring to FIG. 4A, the RF transistor amplifier 200 may be disposed on a carrier substrate 410. The carrier substrate 410 can include any structure that provides a mounting surface suitable for the RF transistor amplifier 200. In some embodiments, the carrier substrate 410 may include a thermally conductive element such as a metal flange. In some embodiments, the carrier substrate 410 may include, for example, an RDL stack structure or a PCB. In some embodiments, the carrier substrate 410 may include copper, molybdenum, and / or combinations thereof. In some embodiments, the carrier substrate 410 may be composed of multiple layers and / or may include vias / interconnections. The carrier substrate 410 may be configured to facilitate packaging of the RF transistor amplifier 200. As shown in FIG. 4A, the circuit module 310 may be coupled to the RF transistor amplifier 200 as described herein.

[0124] In some embodiments, the thermal layer 240 may be disposed between the bottom surface of the RF transistor amplifier 200 and the carrier substrate 410. The thermal layer 240 can assist in the transfer of thermal energy from the RF transistor amplifier 200 to the carrier substrate 410. In embodiments where SiC is utilized as part of the RF transistor amplifier 200, the excellent thermal conductivity of SiC may enable the carrier substrate 410 to more efficiently dissipate the heat of the device. In some embodiments, the thermal layer 240 may include or be replaced by a eutectic layer.

[0125] One or more lead wires 415 may be coupled to one or more gate lead wire connection pads 382, one or more drain lead wire connection pads 384, and one or more source lead wire connection pads 386 of the circuit module 310. For example, the first input lead wire 415A may be coupled to one or more gate lead wire connection pads 382 (e.g., via a bonding layer 420A such as solder) to provide an input signal to the RF transistor amplifier 200, and the second output lead wire 415B may be coupled to one or more drain lead wire connection pads 384 (e.g., via a bonding layer 420B such as solder) to receive an output signal from the RF transistor amplifier 200, but the present invention is not limited thereto.

[0126] The lead wire connections of FIG. 4A are merely examples, and other connections and / or connection pads are possible. For example, in FIG. 4A, one or more source lead wire connection pads 386 are shown as being connected to both lead wires 415A and 415B. However, in some embodiments, one or more source lead wire connection pads 386 may not be coupled to the source of the RF transistor amplifier 200 (e.g., via one or more source terminals 226). For example, in some embodiments, one or more of the circuit elements 350 and / or the conductive pattern 373 may be configured to control whether one or more source lead wire connection pads 386 are coupled to the input lead wire 415A, the output lead wire 415B, or neither. For example, a circuit element 350 may be provided on the circuit module 310 to connect the source terminal 226 of the RF transistor amplifier 200 to the lead wire 415. Similarly, the circuit module 310 may be configured to remove a circuit element 350 (e.g., a resistor) to enable the disconnection of the connection between the lead wire 415A or 415B and the source terminal 226 of the RF transistor amplifier 200.

[0127] Furthermore, FIG. 4A shows an embodiment with two lead wires 415A and 415B, which is merely an example and is not intended to limit the present invention. In some embodiments, a plurality of lead wires may be provided, each of which is coupled to a gate lead wire connection pad 382, a drain lead wire connection pad 384, a source lead wire connection pad 386, and / or combinations thereof. For example, in some embodiments, an additional lead wire configured to provide a ground connection to the source lead wire connection pad 386 can be provided. In some embodiments, the source lead wire connection pad 386 can be configured to couple to a lead wire of an RF semiconductor package that can be coupled to ground, for example. As used herein, the combination of the RF transistor amplifier 200, the circuit module 310, the lead wires 415A, 415B, and the carrier substrate 410 may be referred to as a packaged RF transistor amplifier, an RF transistor amplifier package, or simply an RF transistor amplifier.

[0128] The lead wires 415A, 415B may be between the circuit module 310 and the carrier substrate 410, but the present invention is not limited thereto. In some embodiments, the carrier substrate 410 is under the lead wires 415A and 415B, and in some embodiments, a pedestal 410p for supporting the lead wires 415A and 415B can be provided, but the present invention is not limited thereto. In some embodiments, the pedestal 410p may include an insulating material and / or may be separated from the lead wires 415A, 415B by an insulating layer 460. In some embodiments, as further described herein, the lead wires 415A, 415B may be supported by a part of the package of the RF transistor amplifier 200.

[0129] FIG. 4A shows the use of the coupling element 270, but the present invention is not limited thereto. FIG. 4B shows an embodiment in which the coupling element is omitted. In the embodiment of FIG. 4B, the circuit module 310 can have first, second, and third interconnect pads 322, 324, 326 that are spaced apart from each other at a similar distance as the gate terminal 222, drain terminal 224, and one or more source terminals 226. For example, the first interconnect pad 322 can be connected to the gate terminal 222 (e.g., via a bonding element such as a solder ball and / or bump 320), the second interconnect pad 324 can be connected to the drain terminal 224, and the third interconnect pad 326 can be connected to the source terminal 226. A direct connection to the circuit module 310 can be useful when adjustment of the spacing of the terminals of the RF transistor amplifier 200 (e.g., via a fan-in or fan-out structure) is not required. Thus, in some embodiments, the coupling element 270 is optional in the RF transistor amplifier 200.

[0130] FIG. 4C shows an embodiment in which a plurality of RF transistor amplifiers 200 are coupled to a circuit module 310' and disposed on a carrier substrate 410. For example, as described herein with respect to FIGS. 3D and 3E, a plurality of RF transistor amplifier dies 210, 210' can be coupled to the circuit module 310'. The plurality of RF transistor amplifier dies 210, 210' can be coupled to the circuit module 310' via the coupling element 270, or (as shown in FIG. 3E) directly coupled to the circuit module 310'. The RF transistor amplifier dies 210, 210' and / or the circuit module 310' can be further disposed on the carrier substrate 410 to which the lead wires 415A and 415B are coupled. In some embodiments, the thermal layer 240 can be disposed between the RF transistor amplifier dies 210, 210' and the carrier substrate 410.

[0131] Figures 4A-4C show various combinations of circuit modules 310, 310', coupling element 270, and RF transistor amplifier dies 210, 210', but it should be understood that the present invention is not limited to the specific combinations shown in those figures. As will be understood by those skilled in the art, circuit modules 310, 310', coupling element 270, and RF transistor amplifier dies 210, 210' may be combined in a plurality of variations including those not specifically shown without departing from the present invention. Each of these combinations may be disposed on a carrier substrate 410 to which appropriate lead wires (e.g., lead wires 415A, 415B) are connected, as generally shown in Figures 4A-4C.

[0132] Figures 5A-5C are schematic cross-sectional views of various packaging options 500a, 500b, 500c of an RF transistor amplifier 200 according to some embodiments of the present invention. Figures 5A-5C include the elements of the aforementioned RF transistor amplifier 200, coupling element 270, and circuit module 310. Thus, the description of Figures 5A-5C focuses on portions of embodiments that are different from those described with respect to the previous figures.

[0133] Referring to Figure 5A, a semiconductor package 500a can incorporate an RF transistor amplifier 200 according to some embodiments of the present invention. The semiconductor package 500a may be, for example, an open air or open cavity package. The semiconductor package 500a can include a carrier substrate 410, sidewalls 520, and a lid 525. The carrier substrate 410, sidewalls 520, and lid 525 can define an internal cavity 530. The RF transistor amplifier 200 and the circuit module 310 may be disposed inside the internal cavity 530. The term "semiconductor package" is not intended to be limiting. As described above, the combination of the RF transistor amplifier 200, circuit module 310, lead wires 415A, 415B, and carrier substrate 410 may be referred to as a packaged RF transistor amplifier, a semiconductor package, or simply an RF transistor amplifier.

[0134] The carrier substrate 410 can include materials configured to assist in the thermal management of the semiconductor package 500a. For example, the carrier substrate 410 can include copper and / or molybdenum. In some embodiments, the carrier substrate 410 may be composed of multiple layers and / or may include vias / interconnections. In an exemplary embodiment, the carrier substrate 410 may be a multi-layer copper / molybdenum / copper metal flange including a core molybdenum layer having copper clad layers on both main surfaces. The provided examples of the materials of the carrier substrate 410 are not intended to limit the present invention. In some embodiments, the thermal layer 240 may be between the RF transistor amplifier 200 and the carrier substrate 410.

[0135] In some embodiments, the sidewall 520 and / or the lid 525 may be formed of or include an insulating material. For example, the sidewall 520 and / or the lid 525 may be formed of or include ceramic and / or PCB. In some embodiments, the sidewall 520 and / or the lid 525 may be formed of, for example, Al2O3. The lid 525 may be adhered to the sidewall 520 using an epoxy adhesive. The sidewall 520 may be attached to the carrier substrate 410, for example, by soldering. The lead wires 415A, 415B may be configured to extend through the sidewall 520, but the present invention is not limited thereto.

[0136] In some embodiments, the RF transistor amplifier 200 may be disposed on the carrier substrate 410 and the lead wires 415A, 415B, and the circuit module 310 may be disposed on the RF transistor amplifier 200. The lead wires 415A, 415B may be coupled to the circuit module 310 using, for example, a conductive die attach material. In some embodiments, the lead wires 415A, 415B may extend from the sidewall 520 so as to contact the circuit module 310. Thus, in some embodiments, the use of wire bonds to connect the RF transistor amplifier 200 to the lead wires 415A, 415B can be avoided and / or reduced.

[0137] Additional circuit elements 350 are attached to the circuit module 310. These additional components can include, for example, input matching components and output matching components used for impedance matching at the fundamental frequency and / or for terminating the intermodulation products to ground. These circuit elements 350 can be passive RF components including, for example, resistors, capacitors and / or inductors (at least partially) implemented on an integrated passive device or a printed circuit board. The lead wires 415A, 415B enable the RF transistor amplifier 200 to be connected to an external device / circuit / power supply. In the illustrated embodiment, the circuit module 310 is used to connect the conductive lead wires 415A, 415B to the circuit elements 350 on the circuit module 310. The RF signal input to the RF transistor amplifier 200 on the first lead wire 415A may pass through the circuit module 310 to the circuit elements 350 and from there to the gate terminal 222 of the RF transistor amplifier die 210, and the amplified output RF signal may pass from the drain terminal 224 of the RF transistor amplifier die 210 to the circuit elements 350 and from there through the circuit module 310, and the RF signal is output through the lead wire 415B.

[0138] Referring to FIG. 5B, the semiconductor package 500b can incorporate the RF transistor amplifier 200 according to an embodiment of the present invention. The semiconductor package 500b may be, for example, an overmold plastic (OMP) package. The semiconductor package 500b can include a carrier substrate 410 on which the RF transistor amplifier 200 is disposed. The circuit module 310 may be disposed on the RF transistor amplifier 200.

[0139] The RF transistor amplifier 200 and the circuit module 310 may be housed within an overmold material 540. The overmold material 540 may be formed from a plastic or plastic polymer compound and is injection molded around the RF transistor amplifier 200 and / or the circuit module 310, thereby providing protection from the external environment.

[0140] A method of manufacturing an OMP semiconductor package 500b that can be modified to incorporate the RF transistor amplifier 200 and / or the circuit module 310 is described in U.S. Patent No. 9,515,011, entitled "Over-mold plastic packaged wide band-gap power transistors and MMICS" by Wood et al., issued on December 6, 2016, the disclosure of which is incorporated herein by reference as if fully set forth herein. In the semiconductor package 500b according to the present invention, the lead wires 415A, 415B may extend from the outside of the semiconductor package 500b into the overmold material 540 so as to connect to the circuit module 310. Thus, in some embodiments, the use of wire bonds to connect the RF transistor amplifier 200 to the lead wires 415A, 415B can be avoided and / or reduced.

[0141] Similar to semiconductor package 500a, the carrier substrate 410 of semiconductor package 500b can include materials configured to assist with thermal management. For example, the carrier substrate 410 can include copper and / or molybdenum. In some embodiments, the carrier substrate 410 may be composed of multiple layers and / or may include vias / interconnections. In some embodiments, the carrier substrate 410 can include a metal heat sink that is part of a lead frame or metal slug that is at least partially surrounded by a plastic overmold 540. The provided examples of the material of the carrier substrate 410 are not intended to limit the present invention. In some embodiments, the thermal layer 240 may be between the RF transistor amplifier 200 and the carrier substrate 410.

[0142] FIG. 5C is a schematic cross-sectional view of a packaged RF transistor amplifier 500c that includes an RF transistor amplifier die within a printed circuit board-based package. The packaged RF transistor amplifier 500c is very similar to the packaged RF transistor amplifier 500a described above with reference to FIG. 5A, except that the lead wires 415A, 415B of the packaged RF transistor amplifier 500c are replaced with traces 415A, 415B that act as input and output lead wires on a printed circuit board 522. The printed circuit board 522 may be attached to the carrier substrate 410, for example, via a conductive adhesive. The carrier substrate 410 may include, for example, a pedestal 410P. The pedestal 410P may be composed of an insulating material and / or metal. The printed circuit board 652 can include a central opening, and the circuit module 310 is attached within this opening on the carrier substrate (e.g., a metal flange) 410. The RF transistor amplifier 200 and the circuit element 350 are attached to the circuit module 310.

[0143] Figures 5A - 5C illustrate the use of the RF transistor amplifier 200 having the coupling element 270, but the present invention is not limited thereto. In some embodiments, the semiconductor packages 500a, 500b, 500c may be configured to include a circuit module 310 directly coupled to the RF transistor amplifier die 210, as shown in FIGS. 3B, 3C, and 4B. In some embodiments, the semiconductor packages 500a, 550b, and 500c may be configured to include a circuit module 310 coupled to a plurality of RF transistor amplifiers 200, 200' and / or a plurality of RF transistor amplifier dies 210, 210, as shown in FIGS. 3D, 3E, and 4C.

[0144] It will be appreciated that any of the RF transistor amplifiers according to embodiments of the invention described herein may be mounted within a package such as the packages shown in FIGS. 5A-5C. Accordingly, the RF transistor amplifier die 210, coupling element 270, and / or circuit module 310 shown in FIGS. 5A-5C may be replaced with an RF transistor amplifier die 210, 210', coupling element 270, and / or circuit module 310, 310' according to any of the embodiments of the invention described herein to provide many further embodiments of the packaged RF transistor amplifier. Depending on the embodiment, the packaged RF transistor amplifier may include a monolithic microwave integrated circuit (MMIC) as the RF transistor amplifier die, and the RF transistor amplifier die incorporates a plurality of individual circuits within a single integrated die. Additionally and / or alternatively, the package may include a plurality of RF transistor amplifier dies in series in a path forming a multi-stage RF transistor amplifier, and / or a plurality of RF transistor amplifier dies arranged in a plurality of paths (e.g., in parallel) to form an RF transistor amplifier having a plurality of transistor amplifier dies and a plurality of paths, such as in a Doherty amplifier configuration. In some embodiments, the packaged RF transistor amplifier may include an RF transistor amplifier die according to an embodiment of the invention having a conductive gate and / or conductive drain via providing an electrical connection to a backside interconnect structure, as well as a conventional RF transistor amplifier die having a gate terminal and a drain terminal connected to other structures via wire bonds.

[0145] In some embodiments described herein, circuit element 350 may be disposed on the upper surface of circuit module 310, but the embodiments described herein are not limited thereto. FIGS. 6A - 6C are schematic cross-sectional views of additional embodiments of RF transistor amplifier 200 coupled to circuit module 610, according to some embodiments of the present invention. FIGS. 6A - 6C correspond to the cross-section of FIG. 3A. FIGS. 6A - 6C include the elements of the aforementioned RF transistor amplifier 200. Thus, the description of FIGS. 6A - 6C focuses on portions of embodiments that are different from those described with respect to the previous figures.

[0146] Referring to FIG. 6A, circuit module 610 may be configured to couple to gate connection pad 272, drain connection pad 274, and source connection pad 276 of coupling element 270. Coupling element 270 can be coupled to RF transistor amplifier die 210, as described herein with respect to FIGS. 2A - 2L, for example.

[0147] For example, circuit module 610 can have exposed interconnect pads 622, 624, 626 configured to be coupled to gate connection pad 272, drain connection pad 274, and source connection pad 276, respectively. In some embodiments, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the first, second, and third interconnect pads 622, 624, 626 to gate connection pad 272, drain connection pad 274, and source connection pad 276, respectively. Although shown as a single pad, in some embodiments, one or more of the first, second, and / or third interconnect pads 622, 624, 626 may include multiple pads.

[0148] The circuit module 610 may be coupled to the coupling element 270 at the first side surface 601 of the circuit module 610. At the second side surface 602 of the circuit module 610 opposite to the first side surface 601, a plurality of pads may be exposed. For example, the gate lead wire 682, the drain lead wire 684, and the source lead wire 686 may be exposed at the second side surface 602 of the circuit module 610. In FIG. 6A, only a single gate lead wire 682, drain lead wire 684, and source lead wire 686 are shown, but it will be understood that a plurality of each type of lead wire may be provided. As will be further described herein, the gate lead wire 682, the drain lead wire 684, and the source lead wire 686 may be configured to be coupled to the gate terminal 222, the drain terminal 224, and the source terminal 226 of the RF transistor amplifier die 210, respectively. The encapsulating material 625 may be on the surface of the RF transistor amplifier die 210, the coupling element 270, and / or the circuit module 610. The encapsulating material 625 may be formed from a plastic or a plastic polymer compound, but the present invention is not limited thereto. In some embodiments, the encapsulating material 625 may be or may include a polymer having a filler.

[0149] Each of the first, second, and third interconnect pads 622, 624, 626 may be coupled to one or more conductive patterns 673 within the circuit module 610. The conductive patterns 673 can provide various routings and / or circuits within the circuit module 610. For example, the conductive pattern 673 may connect the first interconnect pad 622 to one or more first surface connection pads 672 and a gate lead 682. In some embodiments, the first surface connection pad 672 may be exposed on the first side 601 of the circuit module 610. In some embodiments, the first circuit element 650a may be coupled to one or more of the first surface connection pads 672 so as to be electrically coupled between the gate lead 682 and the first interconnect pad 622. In some embodiments, the first circuit element 650a may be coupled (e.g., via a coupling element 270) between the gate lead 682 and the gate terminal 222 of the RF transistor amplifier die 210. Accordingly, the first circuit element 650a may be electrically coupled between the gate of the RF transistor amplifier die 210 and the gate lead 682. In some embodiments, the first circuit element 650a may be coupled to the first side 601 of the circuit module 610. Accordingly, the first circuit element 650a may be coupled to the same side (e.g., the first side 601) of the circuit module 610 as the coupling element 270.

[0150] Similarly, the conductive pattern 673 may connect the second interconnect pad 624 to one or more second surface connection pads 674 and drain lead wires 684. In some embodiments, the second circuit element 650b may be coupled to one or more of the second surface connection pads 674 such that it is electrically coupled between the drain lead wire 684 and the second interconnect pad 624. In some embodiments, the second surface connection pads 674 may be exposed on the first side 601 of the circuit module 610. In some embodiments, the second circuit element 650b may be coupled (e.g., via the coupling element 270) between the drain lead wire 684 and the drain terminal 224 of the RF transistor amplifier die 210. Thus, the second circuit element 650b may be electrically coupled between the drain of the RF transistor amplifier die 210 and the drain lead wire 684.

[0151] The first circuit element 650a and / or the second circuit element 650b can provide various electronic functions to the RF transistor amplifier 200. For example, the first circuit element 650a and / or the second circuit element 650b can comprise impedances (e.g., including resistive, inductive, and capacitive elements) that can be used for impedance matching and / or harmonic termination. In some embodiments, the first circuit element 650a and / or the second circuit element 650b may be surface mount devices or may include surface mount devices. In some embodiments, the first circuit element 650a and / or the second circuit element 650b may be integrated passive devices (IPDs) or may include integrated passive devices. In some embodiments, the first circuit element 650a and / or the second circuit element 650b may be harmonic and / or input / output impedance matching elements or may include them.

[0152] For example, the first circuit element 650a may be configured to provide input matching capabilities. Due to its position between the gate lead wire 682 and the RF transistor amplifier die 210, the first circuit element 650a can affect and / or condition the signal provided to the gate of the RF transistor amplifier die 210. Similarly, the second circuit element 650b may be configured to provide output matching capabilities. Due to its position between the drain lead wire 684 and the RF transistor amplifier die 210, the second circuit element 650b can affect and / or condition the signal provided from the drain of the RF transistor amplifier die 210.

[0153] By using a circuit module 610 having exposed connection pads such as the first and second surface connection pads 672, 674, a surface-mounted device can be used to provide circuit elements that can be coupled to the RF transistor amplifier die 210. The surface-mounted device can be replaced and / or configured as needed to provide a more flexible solution. For example, when different types of input / output matching and / or harmonic terminations are required, the same circuit module 610 may be used, but the first and / or second circuit elements 650a, 650b may be replaced to provide different capabilities.

[0154] Although the first circuit element 650a and the second circuit element 650b are each shown as a single element, it will be understood that in some embodiments, the first circuit element 650a and / or the second circuit element 650b may include a plurality of individual devices. Similarly, the interconnections between the first and second circuit elements 650a, 650b and the RF transistor amplifier die 210 are merely examples, and different configurations of the conductive pattern 673 may be provided without departing from the present invention.

[0155] The conductive pattern 673 may also connect the third interconnect pad 626 to one or more source lead wires 686. Accordingly, the source connection pad 276 may be electrically coupled to one or more source lead wires 686.

[0156] The conductive pattern 673 may be housed within the isolation material 615. In some embodiments, the isolation material 615 may include, for example, silicon oxide, silicon nitride, an oxide of the conductive pattern 673, a polymer, a molding compound, or a combination thereof. In some embodiments, the circuit module 610 may be formed as a printed circuit board (PCB). In a PCB embodiment, the isolation material 615 may be the substrate of the PCB, and the conductive pattern 673 may be a trace formed within the substrate.

[0157] FIG. 6A shows the use of the circuit module 610 for coupling to the RF transistor amplifier die 210 using the coupling element 270, but the present invention is not limited thereto. As shown in FIG. 6B, in some embodiments, the RF transistor amplifier die 210 may be directly coupled to the circuit module 610. For example, the gate terminal 222, drain terminal 224, and source terminal 226 of the RF transistor amplifier die 210 may be coupled to the interconnect pads 622, 624, 626 of the circuit module 610, respectively, using, for example, bonding elements 320.

[0158] Similarly, it will be understood that other configurations of the circuit module 610 and the RF transistor amplifier die 210, such as those shown in FIGS. 3C-3E, are also possible. In some embodiments, the circuit module 610 may be configured to couple to an RF transistor amplifier die 210' incorporating internal conductive patterns as shown in FIG. 3C. In some embodiments, the circuit module 610 may be configured to couple to a plurality of RF transistor amplifier dies 210 as shown in FIGS. 3D and 3E.

[0159] It will also be understood that the RF transistor amplifier die 210 can have a variety of different configurations. For example, the RF transistor amplifier die 210 has upper surface gate, drain, and source terminals 222, 224, 226, but in some embodiments may also have one or more of back surface gate, drain, and source terminals 222’, 224’, 226’. Such a configuration is schematically shown in FIG. 6C, which is a schematic cross-sectional view of the RF transistor amplifier die 210’’. As shown in FIG. 6C, the gate via 211, drain via 213, and / or source via 215 may be formed through the semiconductor layer structure 230 that connects to the respective gate, drain, and source terminals 222’, 224’, 226’. For example, as described in U.S. Provisional Patent Application No. 63 / 004,985, filed on April 3, 2020 (the “’985 application”), including gate and drain terminals on the back surface of the RF transistor amplifier die can have various advantages, such as enabling a more flexible impedance matching circuit implementation. The entire content of the ’985 application is incorporated herein by reference. It will be understood that the back surface gate, drain, and source terminals 222’, 224’, 226’ and / or the corresponding gate, drain, and source vias 211, 213, 215 can be included in any of the RF transistor amplifier dies disclosed herein.

[0160] FIGS. 3A - 3E show embodiments where the circuit element 350 is on the upper surface of the circuit module 310 (e.g., on the opposite side of the circuit module 310 from the RF transistor amplifier die 210), and FIGS. 6A - 6C show embodiments where the circuit element 650 is on the bottom surface of the circuit module 610 (e.g., between the circuit module 610 and the RF transistor amplifier die 210), but it will be understood that other combinations are also possible. In some embodiments, the circuit element 350 / 650 may be on both sides of the circuit module 310 / 610. In some embodiments, the circuit element 350 / 650 may be on the side surface of the circuit module 310 / 610.

[0161] As shown in FIGS. 6A-6C, a plurality of components of the RF transistor amplifier die 210 and / or the RF transistor amplifier 200 may be coupled to the circuit module 610. In subsequent figures, an embodiment will be described in which the RF transistor amplifier die 210 is directly coupled to the circuit module 610. However, this convention is for ease of explanation only, and the subsequent description related to the circuit module 610 may equally apply to other types of interconnections between the RF transistor amplifiers 210 (e.g., using the coupling element 270) and / or between the RF transistor amplifiers 200 without departing from the present invention.

[0162] FIGS. 7A-7E are schematic diagrams showing a method of coupling a circuit module and an RF transistor amplifier die according to a particular embodiment of the present invention. As shown in FIG. 7A, a circuit module 610 may be provided. The circuit module 610 may have a first side surface 601 and a second side surface 602. In some embodiments, the first side surface 601 may expose first, second, and third interconnect pads 622, 624, 626, and first and second surface connection pads 672, 674. In some embodiments, the second side surface 602 may have an exposed gate lead 682, drain lead 684, and source lead 686.

[0163] Referring to FIG. 7B, a first circuit element 650a and a second circuit element 650b may be provided on the first side surface 601 of the circuit module 610. For example, a bonding element (e.g., a solder ball and / or bump 320) may be used to couple the first circuit element 650a to the first surface connection pad 672. Similarly, a bonding element (e.g., a solder ball and / or bump 320) may be used to couple the second circuit element 650b to the second surface connection pad 674.

[0164] Referring to FIG. 7C, the RF transistor amplifier die 210 may be provided on the first side 601 of the circuit module 610. For example, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the gate terminal 222, drain terminal 224, and source terminal 226 of the RF transistor amplifier die 210 to the first, second, and third interconnect pads 622, 624, 626, respectively. It will be appreciated that the order of FIGS. 7B and 7C can be reversed such that the RF transistor amplifier die 210 is coupled to the circuit module 610 before the first and second circuit elements 650a, 650b.

[0165] As shown in FIG. 7D, an encapsulation material 625 can be injected between the conductive structures of the RF transistor amplifier die 210, the first and second circuit elements 650a, 650b, and / or the circuit module 610 using a capillary underfill process. The encapsulation material 625 can help prevent short circuits, enhance the structural integrity of the resulting device, and provide proper impedance matching. In some embodiments, the encapsulation material 625 may also encapsulate the RF transistor amplifier die 210 within a protective material.

[0166] FIG. 7E shows an additional optional step in which the thermal layer 240 is disposed on the back side of the RF transistor amplifier die 210. In some embodiments, an additional thermal management structure 642, such as a metal flange, metal fins, a heat sink, or other structure, can be provided on the thermal layer 240. In some embodiments, the thermal management structure 642 can be part of a larger semiconductor package (e.g., a carrier substrate), as further described herein. The thermal layer 240 can be a thermal conductive layer configured to facilitate heat transfer between the RF transistor amplifier die 210 and the thermal management structure 642 to which the RF transistor amplifier die 210 is attached. In some embodiments, the thermal layer 240 and / or the thermal management structure 642 can be omitted. In some embodiments, the thermal layer 240 can be a die attach layer, such as a eutectic layer. The thermal layer 240 can be on the transistor amplifier die 210 and / or can extend over the encapsulation material 625 and / or the first and second circuit elements 650a, 650b. The thermal layer 240 can be a metal layer for forming a eutectic bond or other metal bond. In some embodiments, the thermal layer 240 can be a thermal adhesive.

[0167] The embodiments of FIGS. 6A-6C provide a common gate lead wire 682, a drain lead wire 684, and a source lead wire 686 on a common side (e.g., the second side surface 602) of the circuit module 610. This enables the circuit module 610 to be mounted with the second side surface 602 facing up in various different configurations. For example, FIGS. 8A and 8B are schematic cross-sectional views of various packaging options 800a, 800b of the circuit module 610 according to some embodiments of the present invention. FIGS. 8A and 8B include the aforementioned RF transistor amplifier die 210 and elements of the circuit module 610. Accordingly, the description of FIGS. 8A and 8B focuses on portions of different embodiments than those described with respect to the previous figures.

[0168] Referring to FIG. 8A, semiconductor package 800a may be similar to semiconductor package 500a described herein with respect to FIG. 5A, and duplicate descriptions already described with respect to that figure are omitted. Semiconductor package 800a may be, for example, an open air or open cavity package. Semiconductor package 800a may include a carrier substrate 410, sidewalls 520, and a lid 525. The carrier substrate 410, sidewalls 520, and lid 525 may define an internal cavity 530. The RF transistor amplifier die 210 and the circuit module 610 may be disposed inside the internal cavity 530. In some embodiments, a thermal layer 240 may be between the RF transistor amplifier die 210 and the carrier substrate 410.

[0169] Leads 415A, 415B may be configured to extend through the sidewalls 520, but the present invention is not limited thereto. In some embodiments, the RF transistor amplifier 210 may be disposed on the carrier substrate 410 and leads 415A, 415B, and the circuit module 610 may be disposed on the RF transistor amplifier die 210. Leads 415A, 415B may be coupled to the circuit module 610 using, for example, a conductive die attach material. In some embodiments, leads 415A, 415B may extend from the sidewalls 520 and contact and / or connect to the circuit module 610. For example, lead 415a may be coupled to gate lead 682, and lead 415b may be coupled to drain lead 684. In some embodiments, additional leads and / or connections (not shown) can be coupled to source lead 686. Thus, in some embodiments, the use of wire bonds to connect the RF transistor amplifier die 210 to leads 415A, 415B can be avoided and / or reduced.

[0170] Referring to FIG. 8B, the semiconductor package 800b can incorporate the RF transistor amplifier 210 and the circuit module 610 according to an embodiment of the present invention. The semiconductor package 800b may be similar to the semiconductor package 500b described herein with respect to FIG. 5B, and duplicate descriptions already provided with respect to that figure are omitted. The semiconductor package 800b may be, for example, an overmolded plastic (OMP) package.

[0171] In the semiconductor package 800b according to the present invention, the lead wires 415A, 415B may extend from the outside of the semiconductor package 800b into the overmolded material 540 so as to be connected to the circuit module 610. For example, the lead wire 415a may be coupled to the gate lead wire 682, and the lead wire 415b may be coupled to the drain lead wire 684. In some embodiments, additional lead wires and / or connections (not shown) can be coupled to the source lead wire 686. In some embodiments, the thermal layer 240 may be between the RF transistor amplifier die 210 and the carrier substrate 410 within the semiconductor package 800b.

[0172] In addition to the semiconductor packages 800a, 800b shown with respect to FIGS. 8A and 8B, it will be understood that other packaging configurations are possible without departing from the present invention. For example, the circuit module 610 can be utilized in semiconductor packages similar to those of FIG. 5C, as well as in other configurations.

[0173] In FIGS. 6A - 6C, circuit elements 650a, 650b, and RF transistor amplifier die 210 are on the same side of circuit module 610, and gate, drain, and source lead lines 682, 684, 686 are on the opposite side, but the present embodiment is not limited thereto. FIG. 9A is a plan view of an embodiment of circuit module 610B according to some embodiments of the present invention, and lead lines 682, 684, 686, circuit elements 650a, 650b, and RF transistor amplifier die 210 are all on the same side of circuit module 610B. FIG. 9B is a cross - sectional view taken along line 9B - 9B of FIG. 9A. FIG. 9C is a cross - sectional view taken along line 9C - 9C of FIG. 9A. FIGS. 9A - 9C include the aforementioned RF transistor amplifier die 210 and elements of circuit module 610. Thus, the description of FIGS. 9A - 9C focuses on portions of embodiments different from those described with respect to the previous figures.

[0174] Referring to FIGS. 9A - 9C, circuit module 610B may be attached to RF transistor amplifier die 210. RF transistor amplifier die 210 is attached under circuit module 610B in the schematic plan view of FIG. 9A and is thus shown using a dashed line. Circuit module 610B may be configured to couple to the gate terminal 222, drain terminal 224, and / or source terminal 226 of RF transistor amplifier die 210. FIGS. 9A - 9C show circuit module 610B directly coupled to RF transistor amplifier die 210, but it will be understood that other connection types are possible, such as other configurations of RF transistor amplifier 200, including those shown with respect to FIGS. 2A - 2L. For example, a coupling element 270 may be coupled between circuit module 610B and RF transistor amplifier die 210.

[0175] For example, circuit module 610B can have exposed interconnect pads 622, 624, 626 configured to be coupled to the gate terminal 222, drain terminal 224, and source terminal 226 of RF transistor amplifier die 210, respectively. For example, the first interconnect pad 622 may be configured to couple to the gate terminal 222, the second interconnect pad 624 may be configured to couple to the drain terminal 224, and the third interconnect pad 626 may be configured to couple to the source terminal 226. In some embodiments, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the first, second, and third interconnect pads 622, 624, 626 to the gate terminal 222, drain terminal 224, and source terminal 226, respectively. Although shown as a single pad, in some embodiments, one or more of the first, second, and / or third interconnect pads 622, 624, 626 may include multiple pads.

[0176] Circuit module 610B may be coupled to RF transistor amplifier die 210 at a first side 601 of circuit module 610B. Further, gate lead 682B, drain lead 684B, and source lead 686B may be exposed at the first side 601 of circuit module 610B. As further described herein, gate lead 682B, drain lead 684B, and source lead 686B may be configured to be coupled to the gate terminal 222, drain terminal 224, and source terminal 226 of RF transistor amplifier die 210, respectively. Encapsulant material 625 may be on the surface of RF transistor amplifier die 201 and / or circuit module 610B.

[0177] Each of the first, second, and third interconnect pads 622, 624, 626 may be coupled to one or more conductive patterns 673B within the circuit module 610B. The conductive patterns 673B can provide various routings and / or circuits within the circuit module 610B. For example, the conductive pattern 673B may connect the first interconnect pad 622 to one or more first surface connection pads 672 and the gate lead wire 682B. In some embodiments, the first surface connection pad 672 may be exposed at the first side surface 601 of the circuit module 610B. In some embodiments, the first circuit element 650a may be coupled to one or more of the first surface connection pads 672 so as to be electrically coupled between the gate lead wire 682B and the first interconnect pad 622. In some embodiments, the first circuit element 650a may be coupled between the gate lead wire 682B and the gate terminal 222 of the RF transistor amplifier die 210. Thus, the first circuit element 650a may be electrically coupled between the gate of the RF transistor amplifier die 210 and the gate lead wire 682B. In some embodiments, the first circuit element 650a may be coupled to the first side surface 601 of the circuit module 610B. Thus, the first circuit element 650a may be coupled to the same side surface (e.g., the first side surface 601) of the circuit module 610B as the RF transistor amplifier die 210 and the gate lead wire 682B.

[0178] Similarly, the conductive pattern 673B may connect the second interconnect pad 624 to the drain terminal 224 and the drain lead 684B. In some embodiments, the second circuit element 650b may be coupled to one or more of the second surface connection pads 674 so as to be electrically coupled between the drain lead 684B and the second interconnect pad 624. In some embodiments, the second surface connection pads 674 may be exposed on the first side 601 of the circuit module 610B. In some embodiments, the second circuit element 650b may be coupled between the drain lead 684B and the drain terminal 224 of the RF transistor amplifier die 210. Thus, the second circuit element 650b may be electrically coupled between the drain of the RF transistor amplifier die 210 and the drain lead 684B.

[0179] The conductive pattern 673B may also connect the third interconnect pad 626 to one or more source leads 686B. The source leads 686B may be on the same first side 601 as the third interconnect pad 626 and the RF transistor amplifier die 210. In some embodiments, as shown in FIG. 9A, the gate lead 682B and the drain lead 684B may be on two opposing sides of the RF transistor amplifier die 210, and the source lead 686B may be on a side different from the two opposing sides of the RF transistor amplifier die 210. In other words, in some embodiments, the gate lead 682B may be adjacent to the first side of the RF transistor amplifier die 210, the drain lead 684B may be adjacent to the second side of the RF transistor amplifier die 210, and one or more of the source leads 686B may be adjacent to a third side of the RF transistor amplifier die 210 that is different from the first and second sides of the RF transistor amplifier die 210.

[0180] The circuit module 610B of FIGS. 9A - 9C may differ from the circuit module 610 of FIGS. 6A - 6C in that the circuit module 610B provides gate, drain, and source lead lines 682B, 684B, 686B on the same side as the RF transistor amplifier die 210 of the circuit module 610B. That is, the conductive pattern 673 of the circuit module 610B may be configured to allow the gate, drain, and source lead lines 682B, 684B, 686B to be exposed at different portions of the circuit module 610B. By shifting the side on which the gate, drain, and source lead lines 682B, 684B, 686B are located, additional packaging options are possible.

[0181] FIG. 9D is a cross - sectional view of the circuit module 610B of FIG. 9A mounted on a carrier substrate 410 according to some embodiments of the present invention. As shown in FIG. 9D, the circuit module 610B may be coupled on the RF transistor amplifier die 210, and the RF transistor amplifier die 210 may then be on the carrier substrate 410.

[0182] In some embodiments, the thermal layer 240 may be between the RF transistor amplifier die 210 and the carrier substrate 410. In some embodiments, additional thermal management structures 642, such as metal flanges, metal fins, heat sinks, or other structures, may be provided on the thermal layer 240 and / or between the thermal layer 240 and the carrier substrate 410. The thermal layer 240 may be a thermal conduction layer configured to facilitate heat transfer between the RF transistor amplifier die 210 and the carrier substrate 410 to which the RF transistor amplifier die 210 is attached. In some embodiments, the thermal layer 240 and / or the thermal management structure 642 may be omitted. In some embodiments, the thermal layer 240 may be a die attach layer, such as a eutectic layer. The thermal layer 240 may be on the RF transistor amplifier die 210 and / or may extend over the encapsulation material 625 and / or the first and second circuit elements 650a, 650b. The thermal layer 240 can be a metal layer for forming a eutectic bond or other metal bond. In some embodiments, the thermal layer 240 may be a thermal adhesive.

[0183] In some embodiments, additional contacts may be provided within the carrier substrate 410, but the present invention is not limited thereto. For example, a gate connector 982, a drain connector 984, and / or a source connector (not shown) may be provided on and / or within the carrier substrate 410. For example, the gate lead 682B of the circuit module 610B may be configured to be coupled to the gate connector 982 (e.g., via bonding elements such as solder balls and / or bumps 320), the drain lead 684B may be configured to be coupled to the drain connector 984, and the source lead 686B may be configured to be coupled to a source connector (not shown).

[0184] It should be understood that the packaging example of FIG. 9B is merely an example, and the present invention is not limited thereto. In some embodiments, the circuit module 610B of FIGS. 9A-9C can be coupled within other semiconductor packages described herein, such as those described with respect to FIGS. 5A-5C and FIGS. 8A and 8B. For example, FIGS. 10A and 10B are schematic cross-sectional views of various packaging options 1000a, 1000b of the circuit module 610B according to some embodiments of the present invention. FIGS. 10A and 10B include the aforementioned RF transistor amplifier die 210 and elements of the circuit module 610B. Accordingly, the description of FIGS. 10A and 10B focuses on portions of embodiments different from those described with respect to the previous figures.

[0185] Referring to FIG. 10A, the semiconductor package 1000a may be similar to the semiconductor packages 500a and 800a described herein with respect to FIGS. 5A and 8A, respectively, and duplicate descriptions already provided with respect to those figures are omitted. The semiconductor package 1000a may be, for example, an open air or open cavity package. The semiconductor package 1000a can include a carrier substrate 410, sidewalls 520, and a lid 525. The carrier substrate 410, sidewalls 520, and lid 525 can define an internal cavity 530. The RF transistor amplifier die 210 and the circuit module 610B may be disposed inside the internal cavity 530. In some embodiments, a thermal layer 240 may be between the RF transistor amplifier die 210 and the carrier substrate 410.

[0186] The lead wires 415A and 415B may be configured to extend through the sidewall 520, but the present invention is not limited thereto. In some embodiments, the RF transistor amplifier 210 may be disposed on the carrier substrate 410 and the lead wires 415A and 415B, and the circuit module 610B may be disposed on the RF transistor amplifier die 210. The lead wires 415A and 415B may be coupled to the circuit module 610B using, for example, a conductive die attach material. For example, the lead wire 415a may be coupled to the gate lead wire 682B, and the lead wire 415b may be coupled to the drain lead wire 684B. In some embodiments, additional lead wires and / or connections (not shown) can be coupled to the source lead wire 686B. Thus, in some embodiments, the use of wire bonds to connect the RF transistor amplifier die 210 to the lead wires 415A and 415B can be avoided and / or reduced.

[0187] Referring to FIG. 10B, the semiconductor package 1000b can incorporate the RF transistor amplifier 210 and the circuit module 610B according to an embodiment of the present invention. The semiconductor package 1000b may be similar to the semiconductor packages 500b and 800b described herein with respect to FIGS. 5B and 8B, and duplicate descriptions already described with respect to those figures are omitted. The semiconductor package 1000b may be, for example, an overmolded plastic (OMP) package.

[0188] In the semiconductor package 1000b according to the present invention, the lead wires 415A and 415B may extend into the overmold material 540 from the outside of the semiconductor package 800b so as to be connected to the circuit module 610B. For example, the lead wire 415a may be coupled to the gate lead wire 682B, and the lead wire 415b may be coupled to the drain lead wire 684B. In some embodiments, additional lead wires and / or connections (not shown) can be coupled to the source lead wire 686B.

[0189] In addition to the semiconductor packages 1000a, 1000b shown with respect to FIGS. 10A and 10B, it will be understood that other packaging configurations are possible without departing from the present invention. For example, the circuit module 610B can be used in a semiconductor package similar to that of FIG. 5C, as well as in other configurations.

[0190] As described herein, a circuit module can include circuit elements on the surface of the circuit module, but can also include circuit elements within the circuit module itself. FIGS. 11A-11D are schematic cross-sectional views of additional embodiments of the RF transistor amplifier die 210 coupled to the circuit module 610C according to some embodiments of the present invention. FIGS. 11A-11D include the elements of the aforementioned RF transistor amplifier die 210 and circuit module 610C. Accordingly, the description of FIGS. 11A-11D focuses on portions of embodiments different from those described with respect to the previous figures.

[0191] Referring to FIG. 11A, the circuit module 610C may be attached to the RF transistor amplifier die 210. The circuit module 610C may be configured to couple to the gate terminal 222, drain terminal 224, and source terminal 226 of the RF transistor amplifier die 210. Although FIG. 11A shows the circuit module 610C directly coupled to the RF transistor amplifier die 210, it will be understood that other connection types are possible, such as other configurations of the RF transistor amplifier 200, including those shown with respect to FIGS. 2A-2L. For example, a coupling element 270 may be coupled between the circuit module 610C and the RF transistor amplifier die 210.

[0192] The circuit module 610C can have exposed interconnect pads 622, 624, 626 configured to be coupled to the gate terminal 222, the drain terminal 224, and the source terminal 226, respectively. In some embodiments, bonding elements (e.g., solder balls and / or bumps 320) may be used to couple the first, second, and third interconnect pads 622, 624, 626 to the gate terminal 222, the drain terminal 224, and the source terminal 226, respectively. Although shown as a single pad, in some embodiments, one or more of the first, second, and / or third interconnect pads 622, 624, 626 may include multiple pads.

[0193] The circuit module 610C may be coupled to the RF transistor amplifier die at the first side 601 of the circuit module 610C. Further, the gate lead 682C, the drain lead 684C, and a source lead (not shown) may be exposed at the first side 601 of the circuit module 610C. The gate lead 682C, the drain lead 684C, and the source lead may be configured to be coupled to the gate terminal 222, the drain terminal 224, and the source terminal 226 of the RF transistor amplifier die 210, respectively.

[0194] The circuit module 610C can include one or more conductive patterns 1173, a first circuit element 1150a, and a second circuit element 1150b. The first and second circuit elements 1150a, 1150b are schematically shown in FIG. 11A. The circuit module 610C may differ from the circuit modules 610, 610B described herein in that the first and second circuit elements 1150a and 1150b can be incorporated into the structure of the circuit module 610C. For example, the conductive pattern 1173 within the circuit module 610C can be used to implement a plate capacitor, an interdigitated finger capacitor, and / or a capacitor. Similarly, a spiral inductor or other inductive element may also be implemented within the circuit module 610C. A resistive element can be formed on or within the circuit module 610C, for example, by using a higher-resistance conductive material to form a trace segment or a conductive via.

[0195] In some embodiments, the first and second circuit elements 1150a, 1150b and / or the conductive pattern 1173 may be configured to provide at least a portion of a harmonic termination circuit, a matching circuit, a dividing circuit, a combining circuit, and / or a bias circuit. Other configurations of the conductive pattern 1173 and / or other types of circuit elements 1150a, 1150b can be used without departing from the scope of the present invention. It will also be understood that the configurations of the conductive pattern 1173 and the circuit elements 1150a, 1150b shown in FIG. 11A are merely examples and are not intended to limit the embodiments of the present invention.

[0196] In some embodiments, the circuit module 610C may be formed as a PCB module, and the first and second circuit elements 1150a, 1150b may be formed from traces within the PCB. In some embodiments, the circuit module 610C may be formed from an insulating material 615, and the conductive pattern 1173 may be a conductive material within the insulating material 615 such as a conductive pillar and / or a via (e.g., a copper pillar).

[0197] Each of the first, second, and third interconnect pads 622, 624, 626 may be coupled to one or more of the conductive patterns 1173 within the circuit module 610C. The conductive patterns 1173 can provide various routings and / or circuits within the circuit module 610C. For example, the conductive pattern 1173 may connect the first interconnect pad 622 to the gate lead wire 682C via the first circuit element 1150a. The first circuit element 1150a can provide an input matching function and / or a harmonic termination function between the gate lead wire 682C and the first interconnect pad 622.

[0198] Similarly, the conductive pattern 1173 may connect the second interconnect pad 624 to the drain lead wire 684C via the second circuit element 1150b. The second circuit element 1150b can provide an output matching function and / or a harmonic termination function between the drain lead wire 684C and the second interconnect pad 624.

[0199] As shown in FIG. 11A, in some embodiments, the encapsulation material 1125 may be formed over the RF transistor amplifier die 210, the circuit module 610C, the gate lead wire 682C, and / or the drain lead wire 684C. The encapsulation material 1125 can help prevent short circuits, enhance the structural integrity of the resulting device, and provide proper impedance matching. In some embodiments, the encapsulation material 1125 may also encapsulate the RF transistor amplifier die 210 within a protective material.

[0200] In some embodiments, the vias 1115 may be formed within the encapsulation material 1125. The vias 1115 may include a conductive material and can provide a conductive path to the gate lead 682C and / or the drain lead 684C. For example, the vias 1115 can expose the gate connection 1182 and / or the drain connection 1184 on the bottom surface of the encapsulation material 1125. The gate connection 1182 and / or the drain connection 1184 can each provide a connection point for the gate lead 682C and the drain lead 684C, respectively.

[0201] In some embodiments, the gate connection 1182 and the drain connection 1184 may be substantially on the same plane. In some embodiments, the encapsulation material 1125 may be configured to expose the bottom surface of the RF transistor amplifier die 210, and the gate connection 1182 and the drain connection 1184 may also be substantially on the same plane as the bottom surface of the RF transistor amplifier die 210, but the present invention is not limited thereto. Although only the gate connection 1182 and the drain connection 1184 are shown in FIG. 11A, it will be understood that a source connection may be provided in the same manner.

[0202] The use of the gate connection 1182 and the drain connection 1184 can enable the use of direct bonding between the combination of the RF transistor amplifier die 210 and the circuit module 610C and other pads and / or dies. For example, as shown in FIG. 11B, the gate connection 1182 may be coupled (e.g., via a bonding element such as solder) to the gate pad 1192, and the drain connection 1184 may be coupled to the drain pad 1194. In some embodiments, a thermal layer 240 may be provided under the RF transistor amplifier die 210, but the present invention is not limited thereto. In some embodiments, the thermal layer 240 may be omitted. In some embodiments, additional contacts may be provided for connecting to the third interconnect pad 626 and / or the source terminal 226 of the RF transistor amplifier die 210.

[0203] It should be understood that the packaging example of FIG. 11B is merely an example, and the present invention is not limited thereto. FIGS. 11C and 11D show the use of packaging similar to that described herein with respect to FIGS. 5A-5C, 8A, 8B, 10A, and 10B. For example, the encapsulant 1125 including the circuit module 610C, the RF transistor amplifier die 210, and the gate and drain connections 1182, 1184 may be disposed within the open cavity semiconductor package 1100a (FIG. 11C) or the OMP package 1100b (FIG. 11D). The elements of FIGS. 11C and 11D of the semiconductor packages 1100a and 1100b similar to those described above with respect to FIGS. 5A-5C, 8A, 8B, 10A, and 10B are omitted for simplicity.

[0204] In some embodiments, the gate connection 1182 may be coupled to the gate lead 415A by a bonding element (e.g., a solder ball and / or a bump), and the drain connection 1184 may also be coupled to the drain lead 415B. The gate lead 415A and the drain lead 415B may be electrically insulated from the carrier substrate 410 (e.g., by an insulating layer and / or an overmold material 540). In some embodiments, a thermal layer 240 may be between the RF transistor amplifier die 210 and the carrier substrate 410. In some embodiments, the thermal layer 240 may be omitted. In some embodiments, the thermal layer 240 may be a die attach layer such as a eutectic layer. The thermal layer 240 may be on the transistor amplifier die 210 and / or may extend over the encapsulant 1125. The thermal layer 240 can be a metal layer for forming a eutectic bond or other metal bond. In some embodiments, the thermal layer 240 may be a thermal adhesive. Although not shown in FIGS. 11C and 11D, in some embodiments, additional thermal management structures such as those shown in FIGS. 7E and 9D may be used.

[0205] The packaging embodiments shown in FIGS. 11C and 11D are merely examples intended to illustrate how circuit module 610C and RF transistor amplifier die 210 may be coupled within a semiconductor package. It will be understood that without departing from the present invention, a plurality of other possible configurations and / or orientations of the semiconductor package are possible.

[0206] In some embodiments, via 1115 and / or encapsulant 1125 may be omitted. For example, FIGS. 12A - 12D are schematic cross - sectional views of additional embodiments of RF transistor amplifier die 210 coupled to circuit module 610C according to some embodiments of the present invention. As shown in FIG. 12A, circuit module 610C may be substantially similar to FIGS. 11A - 11D, and thus overlapping descriptions are omitted. The embodiment of FIG. 12A, for example, omits encapsulant 1125, via 1115, and / or gate / drain connections 1182, 1184, and gate lead 682C and drain lead 684C can be directly exposed. FIG. 12A shows all of encapsulant 1125 removed, but it will be understood that in some embodiments, some encapsulant 1125 may be present. For example, in some embodiments, encapsulant 1125 may be over part of RF transistor amplifier die 210 and circuit module 610C, but gate lead 682C and drain lead 684C may be exposed.

[0207] The embodiment shown in FIG. 12A can be utilized in a plurality of packaging configurations. FIGS. 12B and 12C show the use of packaging similar to that described herein with respect to FIGS. 5A-5C, 8A, 8B, 10A, and 10B. For example, circuit module 610C and RF transistor amplifier die 210 may be disposed within open cavity semiconductor package 1200a (FIG. 12B) or OMP package 1200b (FIG. 12C). The elements of FIGS. 12B and 12C of semiconductor package 1200a and semiconductor package 1200b similar to those described above with respect to FIGS. 5A-5C, 8A, 8B, 10A, and 10B are omitted for simplicity. In some embodiments, gate lead 682C may be coupled to gate lead 415A by bonding elements (e.g., solder balls and / or bumps 320), and drain lead 684C may also be coupled to drain lead 415B. It will be appreciated that a plurality of other possible configurations and / or orientations of the semiconductor package are possible without departing from the present invention.

[0208] While many of the embodiments described herein reduce and / or eliminate wire bonding, it will be appreciated that the present invention can further improve configurations that utilize wire bonding. For example, FIG. 12D shows semiconductor package 1200c that utilizes circuit module 610C that utilizes wire bonding. Referring to FIG. 12D, semiconductor package 1200c may be, for example, an open air or open cavity package. Semiconductor package 1200c can include carrier substrate 410, sidewalls 520, and lid 525. Carrier substrate 410, sidewalls 520, and lid 525 can define an internal cavity 530. RF transistor amplifier die 210 and circuit module 610C may be disposed within internal cavity 530.

[0209] The lead wires 415A and 415B may be configured to extend through the side wall 520, but the present invention is not limited thereto. In some embodiments, the circuit module 610C may be disposed on the carrier substrate 410 and the lead wires 415A and 415B, and the RF transistor amplifier die 210 may be disposed on the circuit module 610C. The lead wires 415A and 415B may be coupled to the circuit module 610C using, for example, wire bonds 1280. For example, the lead wire 415a may be coupled to the gate lead wire 682C, and the lead wire 415b may be coupled to the drain lead wire 684C. Although the semiconductor package 1200c utilizes wire bonds 1280, there are still advantages to a direct connection between the RF transistor amplifier die 210 and the circuit module 610C. Further, the circuit module 610C incorporates first and second circuit elements 1150a and 1150b that can enable additional internalized functions such as harmonic termination and / or input / output impedance matching. Further, the use of the circuit module 610C allows for greater flexibility in that different performance characteristics (e.g., to handle harmonics at different frequencies, different impedances, etc.) can be achieved by simply replacing the circuit module 610C.

[0210] FIG. 12D utilizes the circuit module 610C, but it will be understood that the wire bonds 1280 may be incorporated into other semiconductor packaging configurations that utilize any of the circuit modules and / or RF transistor amplifiers described herein.

[0211] Referring back to FIGS. 6A-6C, various embodiments are shown that provide an RF transistor amplifier die 210 coupled to a circuit module 610. In some embodiments, the RF transistor amplifier die 210 is directly coupled to the circuit module 610 (e.g., FIG. 6B), and in some embodiments, the RF transistor amplifier die 210 is coupled to the circuit module 610 via a coupling element 270 (e.g., FIG. 6A). In embodiments such as FIGS. 6A-6C, the encapsulation material 625 may be on one or more sides of the RF transistor amplifier die 210 and can protect / enclose the RF transistor amplifier die 210. In some embodiments, as shown in FIGS. 6A-6C, the bottom surface of the RF transistor amplifier die 210 may be exposed by the encapsulation material 625, but the present invention is not limited thereto.

[0212] FIGS. 13A-13D are schematic cross-sectional views of additional embodiments of an RF transistor amplifier die 210 coupled to a circuit module 610 and incorporating a spacer, according to some embodiments of the present invention. The foregoing portions of FIGS. 13A-13D are not repeated here for the sake of brevity. Referring to FIG. 13A, in some embodiments, a spacer 245 may be disposed on the bottom surface 210a of the RF transistor amplifier die 210. The encapsulation material 625 may expose the bottom surface 245a of the spacer 245.

[0213] In some embodiments, the spacer 245 may be formed of a conductive material such as metal and / or a thermally conductive material. In some embodiments, the spacer 245 may be or may include gold (Au), copper (Cu), Cu alloy, gold tin (AuSn), and / or epoxy, but the present invention is not limited thereto. In some embodiments, the spacer 245 may be electrically insulating and / or may be or may include a dielectric material such as silicon oxide, silicon nitride, polymer, molded compound, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the spacer 245 may be thermally conductive. Thus, the spacer 245 may be configured to dissipate heat transferred from the RF transistor amplifier die 210. In some embodiments, the spacer 245 may be composed of multiple layers, but the present invention is not limited thereto. In some embodiments, the spacer 245 may perform a function similar to that of the thermal layer 240 described herein and / or may be composed of similar materials. Incorporating the spacer 245 onto the RF transistor amplifier die 210 within the encapsulation material 625 can provide a packaging option that is easier to disperse and attach. FIG. 13A shows an embodiment in which the RF transistor amplifier die 210 is directly coupled to the circuit module 610, but the present invention is not limited thereto. In some embodiments, the transistor amplifier die 210 may be coupled to the circuit module 610 via a coupling element 270 as shown in FIG. 6B. Similarly, in some embodiments, the RF transistor amplifier die 210 may incorporate an on-die RDL such as the RF transistor amplifier die 210' of FIG. 3C.

[0214] As shown in FIG. 13A, the encapsulating material 625 may be on the RF transistor amplifier die 210 and also on the first and second circuit elements 650a, 650b. However, the present invention is not limited to such a configuration. Depending on the electrical and thermal requirements of the first and second circuit elements 650a, 650b, alternative and / or additional terminal / junction / spacer structures may be utilized with at least one of the first and second circuit elements 650a, 650b to provide electrical conductivity, thermal conductivity, and / or a mechanical interface to one of the first and second circuit elements 650a, 650b.

[0215] In some embodiments, the surfaces of the first and second circuit elements 650a, 650b may be exposed and / or coupled to auxiliary spacers as part of the RF transistor amplifier. For example, FIG. 13B is a schematic cross-sectional view of an RF transistor amplifier die 210 coupled to a circuit module 610 according to some embodiments of the present invention. As shown in FIG. 13B, the circuit module 610 and / or the RF transistor amplifier die 210 may be substantially the same as the foregoing embodiments, and thus overlapping descriptions are omitted. The embodiment shown in FIG. 13B may include, for example, a first auxiliary spacer 246a and a second auxiliary spacer 246b.

[0216] In some embodiments, the first auxiliary spacer 246a may be formed on the first circuit element 650a. In some embodiments, the second auxiliary spacer 246b may be formed on the second circuit element 650B. For example, the first auxiliary spacer 246a may be formed to be on and / or in contact with the first circuit element 650a, and the second auxiliary spacer 246b may be formed to be on and / or in contact with the second circuit element 650b. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be formed of a conductive and / or thermally conductive material such as metal. In some embodiments, the surfaces of the first and / or second auxiliary spacers 246a, 246b may be exposed from the encapsulating material 625. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be or may include gold (Au), copper (Cu), Cu alloys, gold tin (AuSn), and / or epoxy, but the present invention is not limited thereto. The first and / or second auxiliary spacers 246a, 246b may be configured to be electrically coupled to the first and / or second circuit elements 650a, 650b, and for example, may provide a mechanism by which a ground signal is provided to the first and / or second circuit elements 650a, 650b. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be thermally conductive. Thus, the first and / or second auxiliary spacers 246a, 246b may be configured to dissipate heat transferred from the first and / or second circuit elements 650a, 650b. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be electrically insulating and / or may be or may include a dielectric material such as silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be composed of multiple layers, but the present invention is not limited thereto.

[0217] In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be composed of the same material as spacer 245, but the present invention is not limited thereto. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be composed of a material different from that of spacer 245. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be electrically disconnected from spacer 245. By forming the first and / or second auxiliary spacers 246a, 246b from a material different from that of spacer 245 and / or electrically disconnecting them from spacer 245, it is possible to assist in restricting current sharing and / or current vortices between the RF transistor amplifier die 210 and the first and / or second circuit elements 650a, 650b. The first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 are shown as separate individual elements, but the present invention is not limited thereto. In some embodiments, the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be connected to each other as an integral layer (see, for example, FIG. 13C).

[0218] The materials / thicknesses of the first and second auxiliary spacers 246a, 246b can be the same as or different from those of spacer 245. In some embodiments, the spacer 245 and the first and second auxiliary spacers 246a, 246b may have different thicknesses so that the bottoms of the first and second auxiliary spacers 246a, 246b are flat with the bottom of the spacer 245 to facilitate packaging / manufacturing / bonding to the package substrate or circuit board of the RF transistor amplifier die 210 and the circuit module 610. In some embodiments, the spacer 245 and the first and second auxiliary spacers 246a, 246b have the same thickness. In still other embodiments, the spacer 245 spans at least one or all of the RF transistor amplifier die 210 and the first and second circuit elements 650, 650b, for example, to provide the advantage of a flat interface surface.

[0219] Additional and / or intervening spacers, bonds and other layers can be provided to provide the desired electrical, thermal, and mechanical interfaces. Depending on the desired electrical, thermal, and / or mechanical properties, the layers can be made of conductive and / or thermally conductive and / or insulating materials. For example, in some embodiments, the spacer 245 may be thermally conductive and electrically insulating, and both the first and second auxiliary spacers 246a, 246b may be both conductive and thermally conductive. In some embodiments, only the spacer 245 may be present on the RF transistor amplifier die 210. In some embodiments, only the first auxiliary spacer 246a may be present on the first circuit element 650a. In some embodiments, only the second auxiliary spacer 246b may be present on the second circuit element 650b. In other embodiments, any combination of the spacer 245, the first auxiliary spacer 246a, and the second auxiliary spacer 246b may be present.

[0220] In some embodiments, the exposed surfaces of the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be substantially in the same plane. That is, the exposed surfaces of the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 24 may be configured to be attached to another substrate (e.g., via an attachment method such as soldering).

[0221] It will be appreciated that the manufacturing methods of the embodiments of FIGS. 13A - 13C can be similar to those shown with respect to FIGS. 7A - 7D. For example, the manufacture of an RF transistor amplifier device can include the placement of a spacer 245 on the RF transistor amplifier die 210, the placement of a first auxiliary spacer 246a on the first circuit element 650a, and the placement of a second auxiliary spacer 246b on the second circuit element 650b. For example, the spacer 245 may be electrically and / or thermally connected to the RF transistor amplifier die 210 (e.g., via a die attach material). For example, the first auxiliary spacer 246a and the second auxiliary spacer 246b may each be electrically and / or thermally connected to the first and second circuit elements 650a, 650b (e.g., via a die attach material). This step may be performed, for example, after the first and second circuit elements 650a, 650b and the RF transistor amplifier die 210 are placed on the circuit module 610 (shown in connection with FIGS. 7B and 7C). In some embodiments, the placement of the spacer 245, the first auxiliary spacer 246a, and the second auxiliary spacer 246b may be performed before or after the formation of the encapsulation material 625 on the RF transistor amplifier die 210 (shown in connection with FIG. 7D). In some embodiments, the deposition of the spacer 245 may be performed by a process different from that of the first auxiliary spacer 246a and / or the second auxiliary spacer 246b.

[0222] As described above, in some embodiments, the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be interconnected and / or integrally formed. FIG. 13C shows an embodiment having an integrated spacer layer 245'. The integrated spacer layer 245' may extend to connect and / or contact the first circuit element 350a, the second circuit element 350b, and the RF transistor amplifier die 10 (e.g., the source terminal 26 of the RF transistor amplifier die 10). In some embodiments, the surface 245a' of the integrated spacer layer 245' may be exposed from the encapsulating material 325. In some embodiments, the integrated spacer layer 245' may be formed of the same or similar materials as the first auxiliary spacer 246a, the second auxiliary spacer 246b, and / or the spacer 245 described with respect to the previous embodiments. For example, the integrated spacer layer 245' may be formed of a conductive material such as metal and / or a thermally conductive material. In some embodiments, the integrated spacer layer 245' may be gold (Au), copper (Cu), a Cu alloy, gold tin (AuSn), and / or epoxy, or may include them, but the present invention is not limited thereto. In some embodiments, the integrated spacer layer 245' may be electrically insulating and / or may be a dielectric material such as, for example, silicon oxide, silicon nitride, a polymer, a molding compound, or a combination thereof, or may include them, but the present invention is not limited thereto. In some embodiments, the integrated spacer layer 245' may be composed of a plurality of layers, but the present invention is not limited thereto. As used herein, the "integrated" spacer layer 245' refers to a substantially continuous spacer layer 245' that is not necessarily of uniform composition. In some embodiments, different portions of the integrated spacer layer 245' may be composed of different materials. As an example, a portion of the integrated spacer layer 245' on the first auxiliary spacer 246a and / or the second auxiliary spacer 246b may be different from a portion of the integrated spacer layer 245' on the RF transistor amplifier die 210.

[0223] The monolithic spacer layer 245’ is shown as a uniform layer having a relatively flat upper surface 245b’, but the present invention is not limited thereto. In some embodiments, the upper surface 245b’ of the monolithic spacer layer 245’ may be non-flat. For example, in some embodiments, the first circuit element 650a, the second circuit element 650b, and the RF transistor amplifier die 210 may have different heights, and the monolithic spacer layer 245’ may be formed to have an upper surface 245b’ having portions at the different heights of each of the first circuit element 650a, the second circuit element 650b, and the RF transistor amplifier die 210.

[0224] FIG. 13D shows an exemplary embodiment of an RF transistor amplifier device in which the first auxiliary spacer 246a and the second auxiliary spacer 246b are omitted. Referring to FIG. 13D, the surface 650a_s of the first circuit element 650a and / or the surface 650b_s of the second circuit element 650b may be exposed by the encapsulation material 625. The exposure of the surfaces 650a_s, 650b_s of the first and / or second circuit elements 650a, 650b may enable applying additional external connections to the first and / or second circuit elements 650a, 650b. For example, a separate electrical connection such as a ground signal may be connected to the first and / or second circuit elements 650a, 650b via their respective exposed surfaces 650a_s, 650b_s.

[0225] The RF transistor amplifier device of FIG. 13D may be formed, for example, by constructing an embodiment similar to the embodiment of FIG. 13A and then performing a planarization operation on a portion of the encapsulation material 625 to expose the surfaces 650a_s, 650b_s of the first and / or second circuit elements 650a, 650b.

[0226] The RF transistor amplifier die 210 coupled to the circuit module 610 shown in FIGS. 13A - 13D may be utilized in a plurality of packaging configurations. FIGS. 14A - 14D show the use of packaging similar to that described herein with respect to FIGS. 8A and 8B. For example, the circuit module 610 and the RF transistor amplifier die 210 may be disposed within open cavity semiconductor packages 1400a_1, 1400a_2 (FIGS. 14A and 14B) or OMP packages 1400b_1, 1400b_2 (FIGS. 14C and 14D). The elements of FIGS. 14A and 14B of semiconductor packages 1400a_1 and 1400a_2, which are similar to those described above with respect to FIG. 8A etc., will not be described further for the sake of brevity. The elements of FIGS. 14C and 14D of semiconductor packages 1400b_1 and 1400b_2, which are similar to those described above with respect to FIG. 8B etc., will not be described further for the sake of brevity.

[0227] In FIGS. 14A and 14C, semiconductor packages 1400a_1 and 1400b_1 illustrate the use of circuit module 610 coupled to RF transistor amplifier die 210 within an open cavity package and an OMP package. FIG. 14A shows open cavity semiconductor package 1400a_1 and FIG. 14C shows OMP semiconductor package 1400b_1. Semiconductor packages 1400a_1 and 1400b_1 further include spacer 425, first auxiliary spacer 246a, and second auxiliary spacer 246b as illustrated and described with respect to FIG. 13B. Circuit module 610 can expose gate lead 682 and drain lead 684 that can be connected to lead wires 415A, 415B, respectively. In some embodiments, semiconductor packages 1400a_1 and 1400b_1 can include first auxiliary spacer 246a, second auxiliary spacer 246b, and spacer 245 that are substantially in the same plane. Depending on the electrical and thermal requirements of first and second circuit elements 650a, 650b, additional terminal / junction / spacer structures can be utilized with at least one of first and second circuit elements 650a, 650b to provide an electrical, thermal, and / or mechanical interface between at least one of first and second circuit elements 650a, 650b and carrier substrate 410.

[0228] In some embodiments, the first auxiliary spacer 246a and the second auxiliary spacer 246b may be composed of a material different from that of the spacer 425. For example, in some embodiments, the first auxiliary spacer 246a and the second auxiliary spacer 246b may be conductive so as to be electrically coupled to the carrier substrate 410. For example, the first auxiliary spacer 246a and the second auxiliary spacer 246b may provide an electrical connection (e.g., a ground signal) to the first and second circuit elements 650a, 650b. In some embodiments, the spacer 245 may be thermally conductive but an electrical insulator. Thereby, it can be made possible for the spacer 245 to dissipate heat from the RF transistor amplifier die 210. In some embodiments, the first and second auxiliary spacers 246a, 246b may be electrically insulating or conductive, but may thermally connect the first and second circuit elements 650a, 650b to the carrier substrate 410 in order to dissipate thermal energy (e.g., heat) from the first and second circuit elements 650a, 650b.

[0229] Figures 14B and 14D illustrate exemplary semiconductor packages 1400a_2 and 1400b_2 incorporating an integrated spacer layer 245 within an open cavity package and an OMP package. Figure 14B shows the open cavity semiconductor package 1400a_2, and Figure 14D shows the OMP semiconductor package 1400b_2. The semiconductor packages 1400a_2 and 1400b_2 can utilize an integrated spacer layer 245' as described herein with respect to Figure 13C. The integrated spacer layer 245' can be connected to and / or in direct contact with the carrier substrate 410. The integrated spacer 245' may be coupled to the first circuit element 650a, the second circuit element 650b, and / or the RF transistor amplifier die 210. In some embodiments, the integrated spacer layer 245' may be configured to have a non-flat surface (e.g., the top surface) for coupling to the first circuit element 650a, the second circuit element 650b, and the RF transistor amplifier die 210. The present invention is not limited thereto, and in some embodiments, the top surface of the integrated spacer layer 245' may be flat. In some embodiments, different portions of the integrated spacer layer 245' may be composed of different materials. In some embodiments, additional layers may be disposed between the first and second circuit elements 650a, 650b and the integrated spacer layer 245', or between the integrated spacer layer 245' and the carrier substrate 410, respectively. (e.g., an additional spacer layer).

[0230] In Figures 14A - 14D, the RF transistor amplifier die 210 is shown as being directly coupled to the circuit module 610 within the semiconductor packages 1400a_1, 1400a_2, 1400b_1, and 1400b_2, but it will be understood that the RF transistor amplifier die 210 can be coupled to the circuit module via a coupling element 270 or by utilizing on-die RDL, with the necessary modifications.

[0231] Figures 15A - 15D are schematic cross - sectional views of embodiments of an additional RF transistor amplifier incorporating a circuit module 610B and a mechanism for coupling to first and second circuit elements 650a, 650b, according to some embodiments of the present invention. Since the portions of the RF transistor amplifier die 210 and the circuit module 610B can be substantially similar to those in Figures 9A - 9D, and other previously described figures, duplicate explanations are omitted. The embodiments of Figures 15A - 15D can incorporate, for example, a circuit module 610B that exposes a gate lead wire 682B and / or a drain lead wire pad 684B on the same side surface 601 (e.g., the bottom surface) of the circuit module 610B to which the RF transistor amplifier die 210 is coupled. The embodiments of the RF transistor amplifier in Figures 15A - 15D can include, for example, embodiments similar to those of Figure 9B with the addition of a spacer 245, a first auxiliary spacer 246a, and / or a second auxiliary spacer 246b.

[0232] For example, Figure 15A shows an RF transistor amplifier die 210 coupled to a circuit module 610B, and the spacer 245 is disposed on the bottom surface 210a of the RF transistor amplifier die 210. The encapsulating material 625 may expose the bottom surface 245a of the spacer 245.

[0233] In some embodiments, the spacer 245 may be formed of a conductive material such as metal and / or a thermally conductive material. In some embodiments, the spacer 245 may be or may include gold (Au), copper (Cu), Cu alloy, gold tin (AuSn), and / or epoxy, but the present invention is not limited thereto. In some embodiments, the spacer 245 may be electrically insulating and / or may be or may include a dielectric material such as silicon oxide, silicon nitride, polymer, molded compound, or a combination thereof, but the present invention is not limited thereto. In some embodiments, the spacer 245 may be thermally conductive. Thus, the spacer 245 may be configured to dissipate heat transferred from the RF transistor amplifier die 210. In some embodiments, the spacer 245 may perform a function similar to that of the thermal layer 240 described herein and / or may be composed of a similar material. In some embodiments, the spacer 245 may be composed of multiple layers, but the present invention is not limited thereto. FIG. 15A shows an embodiment in which the RF transistor amplifier die 210 is directly coupled to the circuit module 610, but the present invention is not limited thereto. In some embodiments, the transistor amplifier die 210 may be coupled to the circuit module 610 via a coupling element 270 as shown in FIG. 6B. Similarly, in some embodiments, the RF transistor amplifier die 210 may incorporate an on-die RDL such as the RF transistor amplifier die 210' of FIG. 3C.

[0234] FIG. 15B shows an embodiment similar to FIG. 15A with the addition of a first auxiliary spacer 246a and a second auxiliary spacer 246b. In some embodiments, the first auxiliary spacer 246a may be formed to be on and / or in contact with the first circuit element 650a, and the second auxiliary spacer 246b may be formed to be on and / or in contact with the second circuit element 650b. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be formed of a conductive and / or thermally conductive material such as metal. In some embodiments, the surfaces of the first and / or second auxiliary spacers 246a, 246b may be exposed from the encapsulating material 625. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be or include gold (Au), copper (Cu), Cu alloy, gold tin (AuSn), and / or epoxy, but the present invention is not limited thereto. As described herein with respect to other embodiments, the first and / or second auxiliary spacers 246a, 246b may provide a mechanism by which a ground signal is provided to the first and / or second circuit elements 650a, 650b, or by which thermal energy is dissipated from the first and / or second circuit elements 650a, 650b.

[0235] In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be composed of the same material as the spacer 245, but the present invention is not limited thereto. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be composed of a material different from that of the spacer 245. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be electrically disconnected (e.g., separated) from the spacer 245. In some embodiments, the first and / or second auxiliary spacers 246a, 246b may be composed of multiple layers, but the present invention is not limited thereto.

[0236] The first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 are shown as separate individual elements, but the present invention is not limited thereto. In some embodiments, the first auxiliary spacer 246a, the second auxiliary spacer 246b, and the spacer 245 may be formed as an integral (e.g., interconnected) spacer layer 245'. Such an embodiment is shown in FIG. 15C, which depicts an RF transistor amplifier die 210 coupled to a circuit module 610B that includes an integral spacer layer 245'. The integral spacer layer 245' may be similar to that described herein with respect to FIG. 13C. The integral spacer layer 245' may extend to contact the first circuit element 650a, the second circuit element 650b, and / or the RF transistor amplifier die 210. In some embodiments, the surface 245a of the integral spacer layer 245' may be exposed from the encapsulating material 625. In some embodiments, the integral spacer layer 245' may be formed of the same or similar material as the first auxiliary spacer 246a, the second auxiliary spacer 246b, and / or the spacer 245. In some embodiments, the upper surface 245b' of the integral spacer layer 245' may be non-planar or planar. For example, in some embodiments, the first circuit element 650a, the second circuit element 650b, and / or the RF transistor amplifier die 210 may have different heights, and the integral spacer layer 245' may be formed to have an upper surface 245b' with portions at each of the different heights of the first circuit element 650a, the second circuit element 650b, and the RF transistor amplifier die 210.

[0237] FIG. 15D shows an embodiment of an RF transistor amplifier device in which the first auxiliary spacer 246a and the second auxiliary spacer 246b are omitted. The RF transistor amplifier die 210 may be coupled to the circuit module 610B as in FIG. 15A, and thus, duplicate descriptions are omitted. Referring to FIGS. 15A and 15D, the upper surface 650a_s of the first circuit element 650a and / or the upper surface 650b_s of the second circuit element 650b may be exposed from the encapsulation material 625. The exposure of the surfaces 650a_s, 650b_s of the first and / or second circuit elements 650a, 650b may enable applying additional external connections to the first and / or second circuit elements 650a, 650b. For example, a separate electrical connection such as a ground signal may be connected to the first and / or second circuit elements 650a, 650b via their respective exposed surfaces 650a_s, 650b_s.

[0238] The RF transistor amplifier device of FIG. 15D may be formed, for example, by constructing the RF transistor amplifier device of FIG. 15A and then performing a planarization operation on portions of the encapsulation material 625 to expose the surfaces 650a_s, 650b_s of the first and / or second circuit elements 650a, 650b.

[0239] The RF transistor amplifier devices shown in FIGS. 15A - 15D can be utilized in a plurality of packaging configurations. FIGS. 16A - 16D show the use of packaging similar to that described herein with respect to FIGS. 10A, 10B, and FIGS. 14A - 14D. For example, circuit module 610B and RF transistor amplifier die 210 may be disposed within open cavity semiconductor packages 1600a_1, 1600a_2 (FIGS. 16A, 16B) or OMP packages 1600b_1, 1600b_2 (FIGS. 16C, 16D). In some embodiments, spacer layer 245 can be utilized with first and second auxiliary spacers 246a, 246b within open cavity semiconductor package 1600a_1 (FIG. 16A) or OMP package 1600b_1 (FIG. 16C). In some embodiments, an integrated spacer layer 245’ can be utilized with open cavity semiconductor package 1600a_2 (FIG. 16B) or OMP package 1600b_2 (FIG. 16D). Elements of FIGS. 16A - 16D of semiconductor packages 1600a_1, 1600a_2, 1600b_1, and 1600b_2, which are similar to those described above with respect to other figures such as FIGS. 10A and 10B, will not be described further for the sake of brevity. In some embodiments, semiconductor packages 1600a_1, 1600a_2, 1600b_1, and 1600b_2 can accommodate an RF transistor amplifier device in which gate lead wire pads 682B and drain lead wire pads 684B are exposed on the bottom surface of circuit module 610B. In FIGS. 16A - 16D, RF transistor amplifier die 210 is shown as being directly coupled to circuit module 610B within semiconductor packages 1600a_1, 1600a_2, 1600b_1, and 1600b_2, but it will be understood that RF transistor amplifier die 210 can be coupled to the circuit module via coupling element 270 or using on - die RDL with necessary modifications.

[0240] Referring to FIGS. 16A and 16C, the first and second auxiliary spacers 246a, 246b can be connected to and / or in direct contact with the carrier substrate 410. In this way, the first and second auxiliary spacers 246a, 246b may be configured to dissipate heat from the first and second circuit elements 650a, 650b and / or provide an electrical signal (e.g., a ground signal). Depending on the electrical and thermal requirements of the first and second circuit elements 650a, 650b, additional terminal / junction / spacer structures may be utilized with at least one of the first and second circuit elements 650a, 650b to provide an electrical, thermal, and / or mechanical interface between at least one of the first and second circuit elements 650a, 650b and the substrate 410.

[0241] Referring to FIGS. 16B and 16D, the first and second auxiliary spacers 246a, 246b can be replaced with an integrated spacer layer 245' coupled to the first circuit element 650a, the second circuit element 650b, and / or the RF transistor amplifier die 210. The integrated spacer layer 245' can be connected to and / or in direct contact with the carrier substrate 410. The integrated spacer layer 245' can have a flat or non-flat upper surface. In some embodiments, additional layers may be disposed between the first and second circuit elements 650a, 650b and the integrated spacer layer 245', or between the integrated spacer layer 245' and the carrier substrate 410, respectively. (e.g., additional spacer layers).

[0242] The embodiments described herein provide an improved RF transistor amplifier and an improved packaging incorporating such an RF transistor amplifier. By avoiding and / or reducing the use of backside vias, some embodiments of the present invention provide improved thermal management of the power amplifier. Further, by placing the contacts of the power amplifier on the same side of the device, interconnections and circuit modules can be utilized and the need for wire bonding can be reduced. As a result, the RF transistor amplifier and associated packages can exhibit improved performance and thermal characteristics compared to conventional devices. The advantages of direct bonding provided by embodiments of the present invention are reduced form factor, low electrical resistance, and improved communication speed.

[0243] Various embodiments are described herein with reference to the accompanying drawings that illustrate exemplary embodiments. However, these embodiments may be embodied in different forms and should not be construed as limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the invention to those skilled in the art. Various modifications to the exemplary embodiments described herein as well as general principles and features will be readily apparent. In the drawings, the size and relative sizes of layers and regions are not shown to scale and may in some cases be exaggerated for clarity.

[0244] In this specification, terms such as "first", "second", etc. may be used to describe various elements, but it should be understood that these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the present invention, the first element can be referred to as the second element and, similarly, the second element can be referred to as the first element. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0245] The terms used in this specification are for the purpose of describing particular embodiments only and are not intended to limit the invention. As used in this specification, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprise", "comprising", "include", and / or "including", as used in this specification, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0246] Unless otherwise defined, all terms (including technical and scientific terms) used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terms used in this specification should be interpreted as having a meaning that is consistent with their meaning in the context of this specification and the related art, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0247] When an element such as a layer, region, or substrate is referred to as being "on", "attached to", or "extending over" another element, it will be understood that the element can be directly on the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly on", "directly attached to", or "directly extending over" another element, no intervening elements are present. When an element is referred to as being "connected" or "coupled" to another element, it will be understood that the element can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly coupled" or "directly connected" to another element, no intervening elements are present.

[0248] Relative terms such as "downward", "upward", "upper", "lower", "horizontal", "lateral", or "vertical" may be used herein to describe the relationship of one element, layer, or region to another element, layer, or region, as shown in the figures. It will be understood that these terms are intended to encompass different orientations of the device in addition to the orientation shown in the figures.

[0249] Embodiments of the present invention are described herein with reference to cross-sectional views that are schematic illustrations of idealized embodiments (and intermediate structures) of the present invention. The thicknesses of layers and regions in the drawings may be exaggerated for clarity. Further, variations from the shapes of the figures are to be expected as a result of, for example, manufacturing techniques and / or tolerances. Accordingly, embodiments of the present invention should not be construed as limited to the particular shapes of regions shown herein but should include deviations in shapes resulting, for example, from manufacturing. Elements shown by dashed lines may be optional in the embodiments shown.

[0250] The same numbers refer to the same elements throughout. Thus, even if not referred to or described in the corresponding drawings, the same or similar numbers can be described with reference to other drawings. Also, elements without reference numerals may be described with reference to other drawings.

[0251] In the drawings and the specification, typical embodiments of the present invention are disclosed and specific terms are used, but they are used only in a general and descriptive sense and not for purposes of limitation, and the scope of the present invention is set forth in the following claims.

Claims

1. A transistor amplifier, comprising: a III-nitride-based amplifier die including a semiconductor layer structure, a metallization structure, and an interlayer insulating layer thereabove, wherein the metallization structure includes a gate terminal, a drain terminal, and a source terminal on a first surface of the amplifier die; an amplifier die; an interconnection structure electrically bonded to the gate terminal, the drain terminal, and the source terminal of the metallization structure on the first surface of the amplifier die and electrically bonded to an input path and an output path of the transistor amplifier; Comprising, The interconnection structure is external to the amplifier die, the interconnection structure includes a coupling element provided on the interlayer insulating layer of the amplifier die, and the coupling element includes a rewiring layer and conductive patterns connecting a gate connection pad to the gate terminal, a drain connection pad to the drain terminal, and a source connection pad to the source terminal, respectively; The transistor amplifier, wherein the gate connection pad, the drain connection pad, and the source connection pad are exposed on an upper surface of the coupling element on a side opposite to the first surface.

2. The interconnection structure further includes a circuit module electrically bonded to gate, drain, and source connection portions on the rewiring layer; The transistor amplifier according to claim 1, wherein the circuit module includes a circuit including at least a part of a harmonic termination circuit, a matching circuit, a dividing circuit, a combining circuit, and / or a bias circuit.

3. The gate connection pad, the drain connection pad, and the source connection pad are respectively provided with an input connection portion; an output connection portion; a ground connection portion, and a circuit module including a gate connection portion electrically bonded to the input connection portion, a drain connection portion coupled to the output connection portion, and a source connection portion coupled to the ground connection portion. The transistor amplifier according to claim 1, further comprising:

4. The amplifier die further includes a second surface opposite to the first surface; The transistor amplifier further includes a carrier substrate; The amplifier die is thermally coupled to the carrier substrate on the second surface of the amplifier die; The transistor amplifier according to any one of claims 1 to 3, wherein the carrier substrate includes a metal.

5. The interconnection structure includes a circuit module including a first side surface adjacent to the first surface of the amplifier die and a second side surface opposite to the first side surface. The input path includes an input metal lead wire, and the output path includes an output metal lead wire. The input metal lead wire and the output metal lead wire are electrically joined at the first side surface or the second side surface of the circuit module. The transistor amplifier according to claim 1.

6. The transistor amplifier according to claim 5, wherein the circuit element is on the second side surface and / or the first side surface of the circuit module, or the circuit element is within the circuit module.

7. The transistor amplifier is a radio frequency (RF) transistor amplifier. The amplifier die includes a plurality of unit cell transistors electrically connected in parallel, and each unit cell transistor includes a respective gate finger coupled to a gate manifold, a respective drain finger coupled to a drain manifold, and a respective source finger. The gate connection pad is connected to the gate manifold, the drain connection pad is connected to the drain manifold, and the source connection pad is connected to each of the source fingers. The transistor amplifier according to claim 1.

8. The unit cell transistor extends in a first direction within the semiconductor layer structure. The gate connection pad, the drain connection pad, and the source connection pad of the coupling element extend in a second direction intersecting the first direction. The transistor amplifier according to claim 7.

9. The coupling element is further configured to be coupled to an input matching circuit and / or an output matching circuit. The transistor amplifier according to claim 7 or 8, wherein each conductive pattern of the coupling element has a fan-out connection configuration.

10. The RF transistor amplifier further includes a carrier substrate on a second surface of the amplifier die opposite to the first surface. The transistor amplifier according to any one of claims 7 to 9, further including a thermal and / or electrical conduction layer on the second surface between the semiconductor layer structure and the carrier substrate.

11. Further provided with a circuit module on the upper surface of the coupling element, such that the coupling element is between the circuit module and the semiconductor layer structure. The circuit module is an input matching circuit and / or an output matching circuit, a ground plane, and / or a first side surface adjacent to the first surface of the amplifier die and a second side surface opposite to the first side surface, the transistor amplifier according to claim 7.

12. The amplifier die further comprises a second surface, the semiconductor layer structure has no vias on the second surface, the transistor amplifier according to claim 7.

13. The transistor amplifier according to any one of claims 7 to 12, wherein the semiconductor layer structure further comprises a silicon and / or silicon carbide substrate.

14. The transistor amplifier according to any one of claims 7 to 13, wherein the semiconductor layer structure further comprises a high electron mobility transistor (HEMT) or a laterally diffused metal oxide semiconductor (LDMOS) transistor.

15. The transistor amplifier is a radio frequency (RF) transistor amplifier, the interconnect structure is a circuit module on the upper surface of the coupling element, including a gate lead wire connection pad electrically coupled to the gate connection pad and a drain lead wire connection pad electrically coupled to the drain connection pad, an input lead wire extending from the outside of the RF transistor amplifier and electrically coupled to the gate lead wire connection pad, an output lead wire extending from the outside of the RF transistor amplifier and electrically coupled to the drain lead wire connection pad, and the first electrical path from the input lead wire to the gate terminal does not include a bond wire, and the second electrical path from the output lead wire to the drain terminal does not include a bond wire, the transistor amplifier according to claim 1.

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