Method for configuring and manufacturing a package

Abstract

To provide an improved semiconductor package structure and a method of forming the same for advanced packaging applications.SOLUTION: A glass or silicon substrate 302 is structured by microblasting or laser ablation, and forms a structure to form interconnects 1444 therethrough. A substrate is then utilized as a frame to form a semiconductor package with a die 1026 embedded therein.SELECTED DRAWING: Figure 14-2

Description

Technical Field

[0001]

[0001] Embodiments of the present disclosure generally relate to semiconductor package structures and methods of forming the same. More specifically, the embodiments described herein relate to the structure and method of forming a thin-form-factor semiconductor package.

Background Art

[0002]

[0002] Due to the ever-increasing demand for miniaturized electronic devices and components, integrated circuits have evolved into complex 2.5D and 3D devices that can include millions of transistors, capacitors, and resistors on a single chip. The evolution of chip design has led to greater circuit density in order to improve the process capabilities and speed of integrated circuits. The requirement for greater circuit density and higher processing speed has also imposed corresponding requirements on the materials, structures, and processes used in the manufacture of integrated circuit packages. However, in addition to these trends towards greater integration and performance, there is always a need to reduce manufacturing costs.

[0003]

[0003] Conventionally, integrated circuit packages have been manufactured on organic package substrates because not only are the package manufacturing costs associated with organic composite materials relatively low, but it is also easy to form features and connections inside. However, as circuit density increases and electronic devices become further miniaturized, the use of organic package substrates has become impractical because there are limitations to the resolution of material structuring to maintain device scaling and related performance requirements. More recently, to compensate for some of the limitations associated with organic package substrates, 2.5D and / or 3D integrated circuit packages have been manufactured using passive silicon interposers placed on organic package substrates as redistribution layers. The use of silicon interposers is driven by the high bandwidth density, low power inter-chip communication, and the possibility of heterogeneous integration requirements in advanced packaging applications. However, the formation of features in silicon interposers such as Si through-silicon vias (TSVs) remains difficult and costly. In particular, high aspect ratio silicon via etching, chemical mechanical planarization, and semiconductor back-end-of-line (BEOL) interconnects impose high costs.

[0004]

[0004] Accordingly, what is needed in the art is an improved semiconductor package structure and method of forming the same for advanced packaging applications.

Summary of the Invention

[0005]

[0005] In one embodiment, a package assembly is provided. The package assembly includes a silicon frame having a first surface opposite a second surface and at least one cavity with a semiconductor die disposed therein. The frame further includes vias having via surfaces that define openings extending through the frame from the first surface to the second surface. An insulating layer is formed over the first surface and the second surface and contacts at least a portion of each side of the semiconductor die. Electrical connections are disposed within the vias, and the insulating layer is disposed between the electrical interconnects and the via surfaces.

[0006]

[0006] In one embodiment, a package assembly is provided. The package assembly includes a frame containing silicon, an oxide layer disposed above the surface of the frame, and one or more semiconductor dies disposed within the frame, the one or more semiconductor dies having an integrated circuit formed thereon. An insulating layer is formed on the oxide layer and includes an epoxy resin material with ceramic particles disposed therein. The package assembly further includes one or more metal interconnects disposed within a portion of an embedded die assembly. In some configurations, the oxide layer is disposed above all exposed surfaces of the frame and thus surrounds the frame.

[0007]

[0007] In one embodiment, a package assembly is provided. The package assembly includes an embedded die assembly having a frame containing silicon, one or more semiconductor dies disposed within the frame, a first insulating layer formed on the frame, and one or more electrical interconnects disposed through the frame or the first insulating layer. The first insulating layer is formed of an epoxy resin material having ceramic particles. A redistribution layer is further formed on the embedded die assembly and includes a second insulating layer formed on the first insulating layer and one or more electrical redistribution connections disposed therethrough.

[0008]

[0008] To enable a more detailed understanding of the above features of the present disclosure, a more specific description of the present disclosure, briefly summarized above, is obtained by reference to the embodiments, some of which are shown in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only exemplary embodiments and should not be regarded as limiting the scope of the present disclosure, which may admit of other equally effective embodiments.

Brief Description of the Drawings

[0009]

Figure 1

[0009] A flowchart of a process for forming a semiconductor package according to an embodiment described herein is shown.

Figure 2

[0010] A flowchart of a process for substrate structuring for forming a semiconductor package according to an embodiment described herein is shown.

Figure 3

[0011] A - D schematically show cross - sectional views of a substrate at various stages of the substrate structuring process shown in FIG. 2.

Figure 4

[0012] A - F schematically show cross - sectional views of a substrate at various stages of feature formation and subsequent damage removal according to an embodiment described herein.

Figure 5

[0013] A - F schematically show cross - sectional views of a substrate at various stages of feature formation and subsequent damage removal according to an embodiment described herein.

Figure 6

[0014] A - E schematically show cross - sectional views of a substrate at various stages of feature formation and subsequent damage removal according to an embodiment described herein.

Figure 7

[0015] A - D schematically show cross - sectional views of a substrate at various stages of feature formation and subsequent damage removal according to an embodiment described herein.

Figure 8

[0016] A schematic top view of a substrate structured by the process shown in FIGS. 2, 3A - 3D, 4A - 4F, 5A - 5F, 6A - 6E, and 7A - 7D according to an embodiment described herein is shown.

Figure 9

[0017] A flowchart of a process for forming an embedded die assembly having assembly through - vias and contact holes according to an embodiment described herein is shown.

Figure 10

[0018] A - K schematically show cross - sectional views of an embedded die assembly at various stages of the process shown in FIG. 9.

Figure 11

[0019] A flowchart of a process for forming an embedded die assembly having assembly through - vias and contact holes according to an embodiment described herein is shown.

Figure 12

[0020] A-G schematically show cross-sectional views of an embedded die assembly at various stages of the process shown in FIG. 11.

Figure 13

[0021] A flow diagram of a process for forming interconnects within an embedded die assembly according to embodiments described herein is shown.

Figure 14

[0022] A-H schematically show cross-sectional views of an embedded die assembly at various stages of the interconnect formation process shown in FIG. 13.

Figure 15

[0023] A flow diagram of a process for forming a redistribution layer on an embedded die assembly and then performing package singulation according to embodiments described herein is shown.

Figure 16

[0024] A-L schematically show cross-sectional views of an embedded die assembly at various stages of forming a redistribution layer and then performing package singulation as shown in FIG. 15.

Figure 17A

[0025] A cross-sectional view of a dynamic random access memory (DRAM) stack including a plurality of semiconductor packages formed using the processes shown in FIGS. 1-16L according to embodiments described herein is schematically shown.

Figure 17B

DETAILED DESCRIPTION OF THE INVENTION

[0010]

[0026] For ease of understanding, the same reference numbers are used where possible to refer to the same elements common to the figures. Elements and features of one embodiment are assumed to be beneficially incorporated into other embodiments without further description.

[0011]

[0027] The present disclosure relates to a method and apparatus for forming a thin form factor semiconductor package. In one embodiment, a substrate is structured or shaped by micro - blasting to enable the formation of interconnects therethrough. In another embodiment, the substrate is structured by direct laser patterning. Thereafter, the substrate is utilized as a package frame for forming one or more semiconductor packages with dies disposed therein. In still other embodiments, the substrate is utilized as a frame for a stack of semiconductor devices such as a dynamic random access memory (DRAM) stack.

[0012]

[0028] The methods and apparatus disclosed herein further include a novel thin form factor semiconductor package structure intended to replace more conventional package structures that utilize glass fiber - filled epoxy frames and silicon interposers as redistribution layers. Generally, the scalability of current packages is limited by the rigidity and planarity of the materials utilized to form the various package structures (e.g., epoxy molding compounds having an epoxy resin binder, FR - 4 and FR - 5 grade glass fiber woven cloth, etc.). Due to the inherent properties of these materials, it becomes difficult to pattern fine (e.g., less than 50μm) features internally. Further, as a result of the thermal properties of current package materials, a coefficient of thermal expansion (CTE) mismatch can occur between the package substrate, molding compound, and any semiconductor die integrated therein. Thus, current package structures require larger solder bumps with larger spacing in order to mitigate any warping caused by CTE mismatches. Accordingly, conventional package structures are characterized by a low die - to - package area ratio and a low package through - bandwidth, resulting in a reduction in overall power efficiency. The methods and apparatus disclosed herein provide a semiconductor package structure that overcomes many of the drawbacks associated with the conventional package structures described above.

[0013]

[0029] FIG. 1 shows a flow diagram of a representative method 100 for forming a thin form factor semiconductor package. Method 100 has a plurality of steps 110, 120, 130, and 140. Each step will be described in more detail with reference to FIGS. 2-16L. This method may include one or more additional steps that are performed before any of the defined steps, between two of the defined steps, or after all of the defined steps (except when the context excludes the possibility).

[0014]

[0030] Generally, method 100 includes structuring a substrate that is used as a package frame in step 110, which is described in more detail with reference to FIGS. 2, 3A-3D, 4A-4F, 5A-5F, 6A-6E, 7A-7D, and FIG. 8. In step 120, an embedded die assembly having one or more embedded dies and an insulating layer is formed, which is described in more detail with reference to FIGS. 9 and 10A-10K, and FIGS. 11 and 12A-12G. In step 130, one or more interconnects are formed within and / or through the embedded die assembly for interconnecting the embedded die frame set, which is described in more detail with reference to FIGS. 13 and 14A-14H. In step 140, a first redistribution layer is formed on the embedded die assembly and the interconnect contacts are repositioned to desired lateral positions on the surface of the embedded die assembly. In some embodiments, one or more additional redistribution layers may be formed in addition to the first redistribution layer before the individual packages are separated from the embedded die assembly. This is described in more detail with reference to FIGS. 15 and 16A-16L.

[0015]

[0031] FIG. 2 shows a flow diagram of a representative method 200 for structuring a substrate that is utilized as a frame during the formation of a semiconductor package. FIGS. 3A-3D schematically show cross-sectional views of a substrate 302 at different stages of the substrate structuring process 200 represented in FIG. 2. Thus, FIGS. 2 and 3A-3D are described together herein for clarity.

[0016]

[0032] Method 200 begins with step 210 and corresponding FIG. 3A. Substrate 302 is formed from any suitable frame material including, but not limited to, III-V compound semiconductor materials, silicon, crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, silicon germanium, doped or undoped silicon, doped or undoped polysilicon, silicon nitride, quartz, borosilicate glass, glass, sapphire, alumina, and ceramics. In one embodiment, substrate 302 is a single crystal p-type or n-type silicon substrate. In one embodiment, substrate 302 is a polycrystalline p-type or n-type silicon substrate. In another embodiment, substrate 302 is a p-type or n-type silicon solar substrate. Substrate 302 may further have a polygonal or circular shape. For example, substrate 302 includes a substantially square silicon substrate having a lateral dimension between about 120 mm and about 180 mm and may or may not have a chamfered edge. In another example, substrate 302 may include a circular silicon-containing wafer having a diameter between about 20 mm and about 700 mm (such as between about 100 mm and about 500 mm (e.g., about 300 mm)).

[0017]

[0033] Unless otherwise specified, the embodiments and examples described herein are performed on substrates having a thickness between about 50 μm and about 1000 μm (such as between about 90 μm and about 780 μm). For example, substrate 302 has a thickness between about 100 μm and about 300 μm (such as between about 110 μm and about 200 μm). In another example, substrate 302 has a thickness between about 60 μm and about 160 μm (such as between about 80 μm and about 120 μm).

[0018]

[0034] Before operation 210, the substrate 302 can be sliced and separated from a bulk material by wire sawing, scribing and breaking, mechanical grinding sawing, or laser cutting. Slicing typically introduces mechanical defects or deformations, such as scratches, microcracks, chipping, and other mechanical defects, to the surface of the formed substrate. Thus, the substrate 302 is exposed to a first damage removal process in operation 210 to smooth and planarize its surface and remove any mechanical defects in preparation for subsequent structuring and packaging operations. In some embodiments, the substrate 302 can be made thinner by adjusting the process parameters of the first damage removal process. For example, the thickness of the substrate 302 can decrease as the exposure to the first damage removal process increases.

[0019]

[0035] The damage removal process in operation 210 includes exposing the substrate 302 to a substrate polishing process and / or an etching process, followed by a rinsing and drying process. In some embodiments, operation 210 includes a chemical mechanical polishing (CMP) process. In one embodiment, the etching process is a wet etching process that includes a buffered etching process that is selective for the removal of desired materials (e.g., contaminants and other undesirable compounds). In other embodiments, the etching process is a wet etching process that utilizes an isotropic aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used in the wet etching process. In one embodiment, the substrate 302 is immersed in an HF aqueous etching solution for etching. In another embodiment, the substrate 302 is immersed in a KOH aqueous etching solution for etching.

[0020]

[0036] In some embodiments, the etchant is heated to a temperature between about 30°C and about 100°C (such as between about 40°C and about 90°C) during the etching process. For example, the etching solution is heated to a temperature of about 70°C. In still other embodiments, the etching process in step 210 is a dry etching process. An example of a dry etching process includes a plasma-based dry etching process. The thickness of the substrate 302 is adjusted by controlling the exposure time of the substrate 302 to the etchant (for example, the etching solution) used during the etching process. For example, the final thickness of the substrate 302 decreases as the exposure to the etchant increases. Alternatively, the substrate 302 may have a greater final thickness as the exposure to the etchant decreases.

[0021]

[0037] In steps 220 and 230, the now planarized and substantially defect-free substrate 302 has one or more features, such as vias 303 and cavities 305, that are internally patterned and smoothed (one cavity 305 and four vias 303 are depicted in the cross-section of the underside of the substrate 302 in FIG. 3B). The vias 303 are utilized to form direct contact electrical interconnections through the substrate 302, and the cavities 305 are utilized to receive and encapsulate (i.e., embed) one or more semiconductor dies therein. FIGS. 4A-4C, FIGS. 5A-5C, FIGS. 6A-6C, and FIGS. 7A-7B show cross-sectional views of the substrate 302 at different stages of the feature formation and damage or defect removal (e.g., smoothing) processes according to the embodiments described herein. Accordingly, steps 220 and 230 will be described in more detail with reference to FIGS. 4A-4C, FIGS. 5A-5C, FIGS. 6A-6C, and FIGS. 7A-7B.

[0022]

[0038] In embodiments where the substrate 302 has a thickness of less than about 200 μm (such as a thickness of about 100 μm or a thickness of about 50 μm), the substrate 302 can first be coupled to an optional carrier plate 406 as shown in FIGS. 4A and 5A. The carrier plate 406 provides mechanical support to the substrate 302 during the substrate structuring process 200 and prevents the substrate 302 from breaking. The carrier plate 406 is formed from any suitable chemically and thermally stable rigid material, including but not limited to glass, ceramic, metal, etc. The carrier plate 406 has a thickness between about 1 mm and about 10 mm (such as between about 2 mm and about 5 mm). In one embodiment, the carrier plate 406 has a textured surface. In other embodiments, the carrier plate 406 has a polished or smoothed surface.

[0023]

[0039] The substrate 302 can be coupled to the carrier plate 406 via an adhesive layer 408. The adhesive layer 408 is formed from any suitable temporary bonding material, including but not limited to wax, adhesive, or similar bonding materials. The adhesive layer 408 is applied onto the carrier plate 406 by mechanical rolling, pressing, lamination, spin coating, or doctor blading. In one embodiment, the adhesive layer 408 is a water-soluble or solvent-soluble adhesive layer. In other embodiments, the adhesive layer 408 is a UV-release adhesive layer. In still other embodiments, the adhesive layer 408 is a heat-release adhesive layer. In such embodiments, the bonding properties of the adhesive layer 408 deteriorate when exposed to heat treatment, for example, by exposing the adhesive layer 408 to a temperature above 110 °C (such as above 150 °C). The adhesive layer 408 can further include one or more additional films (not shown) such as a liner, a base film, a pressure-sensitive film, and other suitable layers.

[0024]

[0040] In some embodiments, after coupling the substrate 302 to the carrier plate 406, a resist film is applied to the substrate 302 to form the resist layer 404 shown in FIGS. 4A and 5A. In embodiments where the substrate 302 has a thickness greater than about 200 μm (such as a thickness of about 250 μm), the resist layer 404 is first formed on the substrate 302 without first coupling the substrate 302 to the carrier plate 406. The resist layer 404 is used to transfer a desired pattern to the substrate 302 on which the resist layer 404 is formed during subsequent processing steps. After patterning, the resist layer 404 protects selected regions of the underlying substrate 302 during later structuring steps.

[0025]

[0041] The substrate 302 generally has a substantially planar surface on which the resist layer 404 is formed. In some embodiments, such as those shown in FIG. 5A, the resist layer 404 is coupled to the substrate 302 via a resist adhesion layer 409. The resist adhesion layer 409 is formed from any suitable temporary bonding material including, but not limited to, polyvinyl alcohol, a triester with 2-ethyl-2-(hydroxymethyl)-1,3-propanediol, and other water-soluble or solvent-soluble materials. In one embodiment, the resist adhesion layer 409 is formed of a material different from the adhesion layer 408. In one embodiment, the resist adhesion layer 409 has a substantially similar composition to the adhesion layer 408. The resist adhesion layer 409 is applied onto the substrate 302 by mechanical rolling, pressing, lamination, spin coating, or doctor blading. In other embodiments, the resist layer 404 is formed of a temporary bonding material such as polyvinyl alcohol, and thus the resist layer 404 can be applied directly to and bonded to the surface of the substrate 302. The resist layer 404 can include one or more layers, such as a first resist layer and a second resist layer (not shown).

[0026]

[0042] In one embodiment, such as the embodiment shown in FIG. 4A, the resist layer 404 is a photosensitive layer (e.g., a photoresist). The resist layer 404 can include a solvent, a photoresist resin, and a photoacid generator. The photoresist resin can be any positive photoresist resin or any negative photoresist resin. Representative photoresist resins include acrylates, novolak resins, poly(methyl methacrylate), and poly(olefin sulfone). Other photoresist resins can also be used. When exposed to electromagnetic radiation, the photoacid generator generates charged species such as acid cations and anions. The photoacid generator can also generate polarized species. The photoacid generator renders the resin sensitive to electromagnetic radiation. Representative photoacid generators include, for example, sulfonic acid compounds such as sulfonates, sulfonic acid esters, and sulfonyloxy ketones. Other suitable photoacid generators include onium salts or selenium salts such as aryldiazonium salts, halonium salts, aromatic sulfonium salts, and sulfoxonium salts. Other representative photoacid generators include nitrobenzyl esters, s-triazine derivatives, ionic iodonium sulfonic acids, perfluoroalkane sulfonic acids, aryl triflates and their derivatives and analogs, pyrogallol derivatives, and alkyl disulfones. Other photoacid generators can also be used. In one embodiment, such as the embodiment shown in FIG. 5A, the resist layer 404 is a laser-sensitive resist.

[0027]

[0043] After the formation of the resist layer 404, the substrate 302 with the resist layer 404 formed thereon is exposed to electromagnetic radiation to pattern the resist layer 404, as shown in FIGS. 4B and 5B. In the embodiment shown in FIG. 4B, the substrate 302 with the resist layer 404 formed thereon is exposed to electromagnetic radiation in the ultraviolet (UV) range. A portion of the resist layer 404 is selectively exposed, and a portion of the resist layer 404 is selectively not exposed to the UV radiation. When exposed to the UV radiation, the selectively exposed portions of the resist layer 404 are structurally weakened (indicated by hatching), while the non-selectively exposed portions maintain their structural integrity. In one embodiment, a mask 412 having a desired pattern is formed on or adjacent to the photosensitive resist layer 404 prior to the UV radiation exposure. In other embodiments, the mask 412 is a reticle positioned between the resist layer 404 and the UV radiation source. The mask 412 is configured to transfer the UV radiation of the desired pattern to the resist layer 404. The mask 412 is formed from any suitable polymeric material including, but not limited to, PTFE, PVDF, FEP, polyimide, and the like.

[0028]

[0044] In the embodiment shown by FIG. 5B, the substrate 302 with the laser-sensitive resist layer 404 formed thereon is exposed to the electromagnetic radiation generated by the laser source 307 instead of the UV radiation source. In this way, patterning is achieved by targeted laser ablation without using a mask. The laser source 307 can be any suitable type of laser for patterning the resist layer 404. In some examples, the laser source 307 is a femtosecond green laser. In other examples, the laser source 307 is a femtosecond UV laser. The laser source 307 generates a continuous or pulsed laser beam 310 for patterning the resist layer 404. For example, the laser source 307 can generate a pulsed laser beam 310 having a frequency between 100 kHz and 1200 kHz (such as between about 200 kHz and about 1000 kHz). The laser source 307 is generally configured to form any desired pattern in the resist layer 404. It is further contemplated that the electromagnetic radiation during operation can alternatively include an electron beam or an ion beam instead of a laser beam.

[0029]

[0045] The resist layer 404 can be formed of any material having an appropriate hardness, for example, after the resist layer 404 is patterned, such as after exposing a negative photoresist to electromagnetic radiation to crosslink the materials in the resist. Generally, the resist layer 404 needs to have one or more desirable mechanical properties after the resist layer 404 is patterned (e.g., deposited, exposed, and developed). In one embodiment, the resist layer 404 is formed of a material having a Shore A scale hardness value between 40 and 90 (such as between 60 and 70) after patterning. For example, the resist layer 404 is formed of a material having a Shore A scale hardness value of about 65 after patterning. In one embodiment, the resist layer 404 is formed of a material having a tensile strength between about 0.5 MPa and about 10 MPa (such as between about 1 MPa and about 8 MPa) after patterning. For example, the resist layer 404 can be formed of a material having a tensile strength of about 7 MPa after patterning. In one embodiment, the resist layer 404 is formed of a polydimethylsiloxane material. In other embodiments, the resist layer 404 is formed of polyvinyl alcohol, a triester having 2-ethyl-2-(hydroxymethyl)-1, 3-propanediol, and the like.

[0030]

[0046] Following the patterning of the resist layer 404, the substrate 302 with the resist layer 404 formed thereon is micro-blasted to form a desired pattern on the substrate 302 as shown in FIGS. 4C and 5C. During the micro-blasting process, the flow of powder particles 309 is propelled towards the substrate 302 by using a high-pressure carrier gas to move the exposed portions of the substrate 302 and / or the layers formed thereon. The micro-blasting process is performed using any suitable substrate polishing system.

[0031]

[0047] The micro-blast process is determined by the material properties of the powder particles 309, the momentum of the powder particles impinging on the exposed surface of the substrate 302, and the material properties of the substrate 302, and, where applicable, the selectively exposed portions of the resist layer 404. To achieve the desired substrate patterning characteristics, adjustments are made to the type and size of the powder particles 309, the size and distance of the applicator nozzle of the polishing system to the substrate 302, the pressure correlated to the velocity and flow rate of the carrier gas utilized to propel the powder particles 309, and the density of the powder particles 309 in the fluid flow. For example, the desired fluid pressure of the carrier gas used to propel the powder particles 309 towards the substrate 302 for a desired fixed micro-blast device nozzle orifice size is determined based on the materials of the substrate 302 and the powder particles 309. In one embodiment, the fluid pressure utilized to micro-blast the substrate 302 ranges between about 50 psi and about 150 psi (such as between about 75 psi and about 125 psi), and the carrier gas and particle velocity between about 300 meters per second (m / s) and about 1000 m / s, and / or a flow rate between about 0.001 cubic meters per second (m 3 / s) and about 0.002 m 3 / s is achieved. For example, the fluid pressure of the inert gas (e.g., nitrogen (N2), CDA, argon) utilized to propel the powder particles 309 during micro-blasting is about 95 psi, achieving a carrier gas and particle velocity of about 2350 m / s. In one embodiment, the applicator nozzle utilized to micro-blast the substrate 302 has an inner diameter between about 0.1 mm and about 2.5 mm and is positioned at a distance between about 1 millimeter (mm) and about 5 mm (such as between about 2 mm and about 4 mm) from the substrate 302. For example, the applicator nozzle is positioned at a distance of about 3 mm from the substrate 302 during micro-blasting.

[0032]

[0048] Generally, the micro-blast process is performed using powder particles 309 that have sufficient hardness and a high melting point to prevent particle adhesion when contacting the substrate 302 and / or any layer formed thereon. For example, the micro-blast process is performed using powder particles 309 formed from a ceramic material. In one embodiment, the powder particles 309 utilized in the micro-blast process are formed from aluminum oxide (Al2O3). In another embodiment, the powder particles 309 are formed from silicon carbide (SiC). Other materials suitable for the powder particles 309 are also contemplated. The powder particles 309 generally range in size from about 15 μm to about 60 μm (from about 20 μm to about 40 μm in diameter). For example, the powder particles 309 have an average particle size of about 27.5 μm in diameter. In another example, the powder particles 309 have an average particle size of about 23 μm in diameter.

[0033]

[0049] The effectiveness of the micro-blast process shown in FIGS. 4C and 5C in step 220 further depends on the material properties of the resist layer 404. Using a material with too high a Shore A scale hardness causes undesirable ricocheting of the powder particles 309 between the sidewalls of the resist layer 404, thus reducing the speed at which the powder particles 309 collide with the substrate 302 and ultimately potentially reducing the effectiveness of the powder particles 309 in eroding or moving the exposed area of the substrate 302. Conversely, using a material with too low a Shore A scale hardness may cause the powder particles 309 to undesirably adhere to the resist layer 404. A Shore A scale hardness value between about 40 and about 90 is contemplated to be utilized for the resist layer 404 material as described above.

[0034]

[0050] In an embodiment where the resist layer 404 is a photoresist as in the embodiment shown in FIG. 4C, the substrate 302 remains unexposed at the start of the micro-blasting process. Thus, the powder particles 309 first collide with the surface of the photoresist, moving and removing material from portions of the photoresist that have been UV-exposed and structurally weakened. The powder particles 309 ultimately penetrate and remove the brittle UV-exposed portions, forming voids within the resist layer 404, thereby exposing the desired regions of the substrate 302 while other regions remain shielded by the unexposed portions of the photoresist to UV. The micro-blasting then continues until the powder particles 309 have moved and removed the desired amount or depth of material from the exposed regions of the substrate 302, thereby forming the desired pattern on the substrate 302. In an embodiment where the resist layer 404 is patterned by laser ablation as in the embodiment shown in FIG. 5C, the desired regions of the substrate 302 are already exposed through voids within the resist layer 404 prior to the micro-blasting process. Thus, it is contemplated that the removal of the resist layer 404 during micro-blasting is minimized or eliminated altogether.

[0035]

[0051] The process described above for forming features within the substrate 302 in step 220 can cause undesirable mechanical defects such as chipping and cracking on the surface of the substrate 302. Thus, after performing step 220 to form the desired features within the substrate 302, the substrate 302 is subjected to a second damage removal and cleaning process in step 230 to smooth the surface of the substrate 302, remove unwanted debris, and subsequently, strip the resist layer 404 and, optionally, decouple the substrate 302 from the carrier plate 406. FIGS. 4D-4F and FIGS. 5D-5F show cross-sectional views of the substrate 302 at different stages of the process of second damage removal, cleaning, resist stripping, and substrate decoupling according to the embodiments described herein. Thus, step 230 will now be described in more detail with reference to FIGS. 4D-4F and FIGS. 5D-5F.

[0036]

[0052] The second damage removal process in operation 230 is substantially similar to the first damage removal process in operation 210 and includes exposing the substrate 302 to an etching process, followed by rinsing and drying. The etching process proceeds for a predetermined duration to smooth the surface of the substrate 302, particularly the surface exposed to the micro-blasting process. In another aspect, the etching process is utilized to remove unwanted debris remaining from the micro-blasting process. Residual powder particles adhering to the substrate 302 can be removed during the etching process. FIGS. 4D and 5D show the substrate 302 after debris removal and surface smoothing.

[0037]

[0053] In one embodiment, the etching process is a wet etching process that utilizes a buffered etching process that preferentially etches the substrate surface relative to the resist layer 404 material. For example, the buffered etching process is selective with respect to polyvinyl alcohol. In other embodiments, the etching process is a wet etching process that utilizes an aqueous etching process. Any suitable wet etchant or combination of wet etchants may be used in the wet etching process. In one embodiment, the substrate 302 is immersed in an HF etching aqueous solution for etching. In another embodiment, the substrate 302 is immersed in a KOH etching aqueous solution for etching. The etching solution can be further heated to a temperature between about 40° C. and about 80° C. (between about 50° C. and about 70° C.) during the etching process. For example, the etching solution is heated to a temperature of about 60° C. The etching process may be isotropic or anisotropic. In still other embodiments, the etching process in operation 230 is a dry etching process. An example of a dry etching process includes a plasma-based dry etching process.

[0038]

[0054] After the debris is removed and the substrate surface is smoothed, the substrate 302 is exposed to a resist stripping process. The stripping process is utilized to decouple the resist layer 404 from the substrate 302, as shown in FIGS. 4E and 5E. In one embodiment, a wet process is used to decouple the resist layer 404 from the substrate 302 by dissolving / solubilizing the resist adhesion layer 409. Other types of etching processes are also contemplated for liberating the resist adhesion layer 409. In one embodiment, a mechanical rolling process is used to physically strip the resist layer 404 or the resist adhesion layer 409 from the substrate 302. In one embodiment, an ashing process is used to remove the resist layer 404 from the substrate 302, for example, by using an oxygen plasma-assisted process.

[0039]

[0055] After the resist stripping process, the substrate 302 is exposed to an optional carrier decoupling process, as shown in FIGS. 4F and 5F. The utilization of the carrier decoupling process depends on whether the substrate 302 is coupled to the carrier plate 406 and the type of bonding material utilized to couple the substrate 302 and the carrier plate 406. As described above and shown in FIGS. 4A-4F and 5A-5F, in embodiments where the substrate 302 has a thickness of less than about 200 μm, the substrate 302 is coupled to the carrier plate 406 for mechanical support during feature formation in step 220. The substrate 302 is coupled to the carrier plate 406 via the adhesion layer 408. Thus, after microblasting and subsequent substrate etching and resist stripping, the substrate 302 coupled to the carrier plate 406 is exposed to a carrier decoupling process to decouple the substrate 302 from the carrier plate 406 by liberating the adhesion layer 408.

[0040]

[0056] In one embodiment, the adhesive layer 408 is released by exposing the substrate 302 to a baking process. The substrate 302 is exposed to a temperature between about 50°C and about 300°C (such as a temperature between about 100°C and about 250°C). For example, the substrate 302 is exposed to a temperature between about 150°C and about 200°C (such as about 160°C) for a desired time to release the adhesive layer 408. In other embodiments, the adhesive layer 408 is released by exposing the substrate 302 to UV radiation.

[0041]

[0057] FIGS. 4F and 5F show the substrate 302 after completion of steps 210-230. The cross-section of the substrate 302 in FIGS. 4F and 5F shows a single cavity 305 formed therethrough and surrounded on both sides by two vias 303. A schematic top view of the substrate 302 at the completion of the operations described with reference to FIGS. 4A-4F and 5A-5F is depicted in FIG. 8 and described in further detail below.

[0042]

[0058] Figures 6A-6E show schematic cross-sectional views of substrate 302 during an alternative sequence of processes 220 and 230 similar to those described above. The alternative sequences shown for processes 220 and 230 include patterning substrate 302 on major surfaces on two opposite sides as compared to only one surface, thus allowing for improved efficiency during the structuring of substrate 302. The embodiments shown in FIGS. 6A-6E include substantially all of the processes described with reference to FIGS. 4A-4F and FIGS. 5A-5F. For example, FIG. 6A corresponds to FIGS. 4A and 5A, FIG. 6B corresponds to FIGS. 4B and 5B, FIG. 6C corresponds to FIGS. 4C and 5C, FIG. 6D corresponds to FIGS. 4D and 5D, and FIG. 6E corresponds to FIGS. 4F and 5F. However, unlike the previous embodiments, the embodiment of process 220 shown in FIGS. 6A-6E includes substrate 302 having two resist layers 404 formed on major surfaces 606, 608 on opposite sides thereof, as opposed to one resist layer 404 formed on a single surface. Thus, the processes performed during processes 210-230 will need to be performed at the same time (i.e., simultaneously) or one after the other (i.e., sequentially) on both sides of the substrate during each operation. FIGS. 6A-6E show only the formation of vias 303, but the processes described herein can also be used to form cavities 305, or cavities 305 and vias 303.

[0043]

[0059] Thus, after exposing the resist layer 404 on one side of the substrate 302, such as the side surface including the surface 608, to electromagnetic radiation for patterning, the resist layer 404 on the opposite surface 606 may also be optionally inverted as shown in FIG. 6B. Similarly, after performing a microblasting process on the surface 608 of the substrate 302, the substrate 302 may be optionally inverted so that a microblasting process can be performed on the opposite surface 606 as shown in FIG. 6C. Thereafter, the substrate 302 is exposed to a second damage removal and cleaning process and a resist stripping process as shown in FIGS. 6D-6E. By using the two resist layers 404 on the major surfaces 606, 608 on the opposite sides of the substrate 302 and performing a microblasting process on both surfaces 606 and 608, the potential tapering of the features formed inside by the microblasting process can be reduced or eliminated, and the effectiveness of the process used to structure the substrate 302 can be enhanced.

[0044]

[0060] FIGS. 7A-7D show schematic cross-sectional views of the substrate 302 during another alternative sequence of steps 220 and 230, where a desired pattern is formed on the substrate 302 by direct laser ablation. As shown in FIG. 7A, a substrate 302, such as a solar substrate or a semiconductor wafer, is placed on a stage 706 of a laser ablation system (not shown). The stage 706 can be any suitable rigid, planar or textured (e.g., structured) surface for mechanically supporting the substrate 302 during laser ablation. In some embodiments, the stage 706 includes an electrostatic chuck for electrostatically chucking the substrate 302 to the stage 706. In some embodiments, the stage 706 includes a vacuum chuck for vacuum chucking the substrate 302 to the stage 706. After placing the substrate 302 on the stage 706, as shown in FIG. 7B, a desired pattern is formed on the substrate 302 by laser ablation.

[0045]

[0061] The laser ablation system can include any suitable type of laser source 307 for patterning the substrate 302. In some examples, the laser source 307 is an infrared (IR) laser. In some examples, the laser source 307 is a picosecond UV laser. In other examples, the laser source 307 is a femtosecond UV laser. In still other examples, the laser source 307 is a femtosecond green laser. The laser source 307 generates a continuous laser beam or a pulsed laser beam 310 for patterning the substrate 302. For example, the laser source 307 can generate a pulsed laser beam 310 having a frequency between 5 kHz and 500 kHz (such as between 10 kHz and about 200 kHz). In one example, the laser source 307 is configured to deliver a pulsed laser beam at an output power between about 10 watts and about 100 watts, at a wavelength between about 200 nm and about 1200 nm, and with a pulse duration between about 10 ns and about 5000 ns. The laser source 307 is configured to form any desired pattern and features, including cavities 305 and vias 303, within the substrate 302.

[0046]

[0062] Similar to the microblast process, the process of directly laser patterning the substrate 302 can cause unwanted mechanical defects on the surface of the substrate 302, including chipping and cracking. Thus, after forming the desired features in the substrate 302 by direct laser patterning, the substrate 302 is exposed to a second damage removal and cleaning process that is substantially similar to the embodiments described above. FIGS. 7C - 7D show the structured substrate 302 before and after performing the second damage removal and cleaning process, resulting in a smoothed substrate 302 with cavities 305 and four vias 303 formed therein.

[0047]

[0063] Referring again to FIGS. 2 and 3D here, after removing mechanical defects in the substrate 302 in step 230, the substrate 302 is exposed to an oxidation process in step 240 to grow or deposit an insulating oxide film (i.e., layer) 314 on its desired surface. For example, the oxide film 314 can be formed on all surfaces of the substrate 302 so as to surround the substrate 302. The insulating oxide film 314 acts as a passivation layer on the substrate 302 and provides a protective outer barrier against corrosion and other forms of damage. In one embodiment, the oxidation process is a thermal oxidation process. The thermal oxidation process is performed at a temperature between about 800°C and about 1200°C (such as between about 850°C and about 1150°C). For example, the thermal oxidation process is performed at a temperature between about 900°C and about 1100°C (such as between about 950°C and about 1050°C). In one embodiment, the thermal oxidation process is a wet oxidation process that utilizes water vapor as an oxidizing agent. In one embodiment, the thermal oxidation process is a dry process that utilizes molecular oxygen as an oxidizing agent. It is contemplated that the substrate 302 can be exposed to any suitable oxidation process in step 240 to form the oxide film 314 thereon. The oxide film 314 generally has a thickness between about 100 nm and about 3 μm (such as between about 200 nm and about 2.5 μm). For example, the oxide film 314 has a thickness between about 300 nm and about 2 μm (such as about 1.5 μm).

[0048]

[0064] FIG. 8 shows a schematic top view of an exemplary structured substrate 302 according to one embodiment. Substrate 302 can be structured during processes 210-240 as described above with reference to FIGS. 2, 3A-3D, 4A-4F, 5A-5F, 6A-6E, and 7A-7D. Substrate 302 is shown as having two quadrilateral cavities 305, each cavity 305 being surrounded by a plurality of vias 303. In one embodiment, each cavity 305 is surrounded by two rows 801, 802 of vias 303 disposed along each edge 306a-d of the quadrilateral cavity 305. Ten vias 303 are shown in each row 801, 802, although any desired number of vias 303 can be formed in one row. Further, any desired number and arrangement of cavities 305 and vias 303 can be formed in substrate 302 during process 220. For example, substrate 302 can have more than two or fewer cavities 305 formed therein. In another example, substrate 302 can have more than two or fewer vias 303 formed along each edge 306a-d of cavity 305. In another example, substrate 302 can have more than two rows of vias 303. The vias 303 in each row are staggered and not aligned with the vias 303 in another row.

[0049]

[0065] In one embodiment, cavities 305 and vias 303 have a depth equal to the thickness of substrate 302 and thus form holes on a surface on the opposite side of substrate 302 (e.g., through the thickness of substrate 302). For example, cavities 305 and vias 303 formed within substrate 302 can have a depth between about 50 μm and about 1 mm (e.g., between about 100 μm and about 200 μm (e.g., between about 110 μm and about 190 μm)) depending on the thickness of substrate 302. In other embodiments, cavities 305 and / or vias 303 can have a depth less than the thickness of substrate 302. Thus, holes are formed only on one surface (e.g., side surface) of substrate 302.

[0050]

[0066] In one embodiment, each cavity 305 has a lateral dimension in the range of between about 3 mm and about 50 mm (between about 8 mm and about 12 mm, between about 9 mm and about 11 mm, etc.), depending on the size of one or more semiconductor dies 1026 (shown in FIG. 10B) embedded therein during package manufacturing. A semiconductor die generally includes a plurality of integrated electronic circuits formed on and / or within a substrate material such as a piece of semiconductor material. In one embodiment, the cavity 305 is sized to have a lateral dimension substantially similar to the lateral dimension of the die 1026 embedded therein. For example, each cavity 305 is formed to have a lateral dimension that exceeds the lateral dimension of the die 1026 by less than about 150 μm (less than about 120 μm (e.g., less than 100 μm), etc.). When the variation in the size of the cavity 305 and the die 1026 embedded therein is reduced, the amount of gap filling material utilized thereafter is reduced.

[0051]

[0067] In one embodiment, each via 303 has a diameter in the range of between about 50 μm and about 200 μm (between about 60 μm and about 130 μm (e.g., between about 80 μm and 110 μm), etc.). The minimum pitch 807 between the center of a via 303 in column 801 and the center of an adjacent via 303 in column 802 is between about 70 μm and about 200 μm (between about 85 μm and about 160 μm (e.g., between about 100 μm and 140 μm), etc.). Although embodiments are described with reference to FIG. 8, the substrate structuring processes described above with reference to steps 210 - 240 and FIGS. 2, 3A - 3B, 4A - 4C, 5A - 5C, 6A - 6C, and 7A - 7B can be utilized to form patterned features having any desired depth, lateral dimension, and morphology on the substrate 302.

[0052]

[0068] After structuring the substrate 302, by using the substrate 302 as a frame, one or more packages are formed around the substrate 302. FIGS. 9 and 11 respectively show flowcharts of representative methods 900 and 1100 for manufacturing an intermediate embedded die assembly 1002 around the substrate 302 before final package formation. FIGS. 10A - 10K schematically show cross-sectional views of the substrate 302 at different stages of the method 900 shown in FIG. 9, and FIGS. 12A - 12G schematically show cross-sectional views of the substrate 302 at different stages of the method 1100 shown in FIG. 11. For clarity, FIGS. 9 and 10A - 10K are described together in this specification, and FIGS. 11 and 12A - 12G are described together in this specification.

[0053]

[0069] Generally, method 900 begins with step 902 and FIG. 10A, where the first side 1075 (e.g., surface 606) of the substrate 302 in which the desired features are formed is disposed on the first insulating film 1016a. In one embodiment, the first insulating film 1016a includes one or more layers formed of a polymer-based dielectric material. For example, the first insulating film 1016a includes one or more layers formed of a flowable build-up material. In the embodiment shown in FIG. 10A, the first insulating film 1016a includes a flowable epoxy resin layer 1018a. The epoxy resin layer 1018a can be formed from a ceramic-filled epoxy resin such as an epoxy resin filled with silica (SiO2) particles (e.g., containing silica (SiO2) particles). Other examples of ceramic fillers that can be used to form the epoxy resin layer 1018a and other layers of the insulating film 1016a are aluminum nitride (AlN), aluminum oxide (Al2O3), silicon carbide (SiC), silicon nitride (Si3N4), Sr2Ce2Ti5O 16 , zirconium silicate (ZrSiO4), wollastonite (CaSiO3), beryllium oxide (BeO), cerium dioxide (CeO2), boron nitride (BN), calcium copper titanium oxide (CaCu3Ti4O 12) It includes magnesium oxide (MgO), titanium dioxide (TiO2), zinc oxide (ZnO), etc. In some examples, the ceramic filler used to form the epoxy resin layer 1018a has particles ranging in size from about 40 nm to about 1.5 μm (from about 80 nm to about 1 μm). For example, the ceramic filler used to form the epoxy resin layer 1018a has particles in the size range of from about 200 nm to about 800 nm (such as from about 300 nm to about 600 nm). In some embodiments, the ceramic filler used to form the epoxy resin layer 1018a includes particles having a size of less than about 25% of the width or diameter of a desired feature (such as less than about 15% of the width or diameter of the desired feature), such as vias, cavities, or assembly through vias.

[0054]

[0070] The epoxy resin layer 1018a typically has a thickness of less than about 60 μm, for example, between about 5 μm and about 50 μm. For example, the epoxy resin layer 1018a has a thickness between about 10 μm and about 25 μm. In one embodiment, the insulating film 1016a further includes one or more protective layers. For example, the insulating film 1016a includes a polyethylene terephthalate (PET) protective layer 1022a. However, any suitable combination of layers and insulating materials is contemplated for the insulating film 1016a. In some embodiments, the entire insulating film 1016a has a thickness of less than about 120 μm (such as less than about 90 μm).

[0055]

[0071] The substrate 302 is connected to the insulating film 1016a on its first side surface 1075, particularly to the epoxy resin layer 1018a of the insulating film 1016a, and can optionally be further placed on a carrier 1024 for mechanical support during subsequent processing operations. The carrier is formed from any suitable mechanically and thermally stable material. The carrier 1024 is formed, for example, of polytetrafluoroethylene (PTFE). In another example, the carrier 1024 is formed of PET.

[0056]

[0072] In operation 904 and as depicted in FIG. 10B, one or more semiconductor dies 1026 are placed within cavity 305 formed within substrate 302, such that semiconductor die 1026 is hereby coupled by insulating film 1016a on one side thereof (a single semiconductor die 1026 is depicted in FIG. 10B). In one embodiment, die 1026 is a multi-purpose die on which an integrated circuit is formed on its active surface 1028. Die 1026 is placed within cavity 305 and disposed on the surface of insulating film 1016a that is exposed through cavity 305. In one embodiment, die 1026 is placed on an adhesive layer (not shown) disposed or formed on insulating film 1016a.

[0057]

[0073] After placing die 1026 within cavity 305, in operation 906 and FIG. 10C, a first protective film 1060 is placed above a second side surface 1077 (e.g., surface 608) of substrate 302. Protective film 1060 is coupled to second side surface 1077 of substrate 302 and to the opposite side of first insulating film 1016a so as to contact and cover active surface 1028 of die 1026 disposed within cavity 305. In one embodiment, protective film 1060 is formed of a material similar to protective layer 1022a. Protective film 1060 is formed of, for example, PET such as biaxial PET. However, protective film 1060 may be formed from any suitable protective material. In some embodiments, protective film 1060 has a thickness between about 50 μm and about 150 μm.

[0058]

[0074] Here, substrate 302 is secured to insulating film 1016a on first side surface 1075 and to protective film 1060 on second side surface 1077, and further has die 1026 disposed therein, and in operation 908, is exposed to a lamination process. During the lamination process, substrate 302 is subjected to high temperature to soften epoxy resin layer 1018a of insulating film 1016a. Cause it to flow into an open void or space (e.g., into via 303 and gap 1051 between the inner wall of cavity 305 and die 1026) between insulating film 1016a and protective film 1060. Thus, semiconductor die 1026 becomes at least partially embedded within the materials of insulating film 1016a and substrate 302, as depicted in FIG. 10D.

[0059]

[0075] In one embodiment, the lamination process is a vacuum lamination process that can be performed in an autoclave or other suitable device. In one embodiment, the lamination process is performed using a hot press process. In one embodiment, the lamination process is performed at a temperature between about 80° C. and about 140° C. and for a period between about 5 seconds and about 1.5 minutes (between about 30 seconds and about 1 minute). In some embodiments, the lamination process includes applying a pressure between about 1 psig and about 50 psig, while a temperature between about 80° C. and about 140° C. is applied to substrate 302 and insulating film 1016a for a period between about 5 seconds and about 1.5 minutes. For example, the lamination process is performed at a pressure between about 5 psig and about 40 psig, at a temperature between about 100° C. and about 120° C., and for a period between about 10 seconds and about 1 minute. The lamination process is performed, for example, at a temperature of about 110° C. for about 20 seconds.

[0060]

[0076] In operation 910, the protective film 1060 is removed, and a substrate 302 having a laminated insulating material of an epoxy resin layer 1018a that at least partially surrounds the substrate 302 and one or more dies 1026 is placed on a second protective film 1062. As depicted in FIG. 10E, the second protective film 1062 is coupled to a first side surface 1075 of the substrate 302 such that the second protective film 1062 is disposed (e.g., adjacent) to the protective layer 1022a of the insulating film 1016a. In some embodiments, the substrate 302 coupled to the protective film 1062 may optionally be placed on a carrier 1024 for additional mechanical support on the first side surface 1075. In some embodiments, the protective film 1062 is placed on the carrier 1024 and laminated with the insulating film 1016a here before coupling the protective film 1062 to the substrate 302. Generally, the protective film 1062 is substantially similar in composition to the protective film 1060. For example, the protective film 1062 may be formed from PET such as biaxial PET. However, the protective film 1062 may be formed from any suitable protective material. In some embodiments, the protective film 1062 has a thickness between about 50 μm and about 150 μm.

[0061]

[0077] When the substrate 302 is coupled to the second protective film 1062, a second insulating film 1016b that is substantially similar to the first insulating film 1016a is placed on the second side 1077 of the substrate 302 in step 912 and FIG. 10F, and thus replaces the protective film 1060. In one embodiment, the epoxy resin layer 1018b of the second insulating film 1016b contacts and covers the active surface 1028 of the die 1026 within the cavity 305, and thus the second insulating film 1016b is disposed on the second side 1077 of the substrate 302. In one embodiment, placement of the second insulating film 1016b on the substrate 302 may form one or more voids between the insulating film 1016b and the already laminated insulating material of the epoxy resin layer 1018a that partially surrounds one or more dies 1026. The second insulating film 1016b may include one or more layers formed from a polymeric dielectric material. As shown in FIG. 10F, the second insulating film 1016b includes an epoxy resin layer 1018b similar to the epoxy resin layer 1018a described above. The second insulating film 1016b may further include a protective layer 1022b formed of a material similar to the protective layer 1022a such as PET.

[0062]

[0078] In step 914, as shown in FIG. 10G, a third protective film 1064 is placed over the second insulating film 1016b. Generally, the protective film 1064 has a composition that is substantially similar to the protective films 1060, 1062. The protective film 1064 is formed of, for example, PET such as biaxially oriented PET. However, the protective film 1064 may be formed from any suitable protective material. In some embodiments, the protective film 1064 has a thickness between about 50 μm and about 150 μm.

[0063]

[0079] Here, the substrate 302 fixed to the insulating film 1016b and the protective layer 1064 on the second side 1077, as well as the protective film 1062 and the optional carrier 1024 on the first side 1075, is exposed to a second lamination process in step 916 and FIG. 10H. Similar to the lamination process in step 908, the substrate 302 is subjected to high temperature to soften the epoxy resin layer 1018b of the insulating film 1016b and allow it to flow into any open void or space (volume) between the insulating film 1016b and the already laminated insulating material of the epoxy resin layer 1018a, thus integrating itself with the insulating material of the epoxy resin layer 1018a. Accordingly, the cavity 305 and the via 303 are filled (e.g., packed, sealed) with insulating material, and the semiconductor die 1026 previously placed in the cavity 305 becomes completely embedded in the insulating material of the epoxy resin layers 1018a, 1018b.

[0064]

[0080] In one embodiment, the lamination process can be a vacuum lamination process that can be performed in an autoclave or other suitable device. In one embodiment, the lamination process is performed using a hot press process. In one embodiment, the lamination process is carried out at a temperature between about 80°C and about 140°C and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 10 psig and about 150 psig, while a temperature between about 80°C and about 140°C is applied to the substrate 302 and the insulating film 1016b for a period between about 1 minute and about 30 minutes. For example, the lamination process is carried out at a pressure between about 20 psig and about 100 psig and at a temperature between about 100°C and about 120°C for a period between about 2 minutes and 10 minutes. For example, the lamination process is carried out at a temperature of about 110°C for about 5 minutes.

[0065]

[0081] After lamination, the substrate 302 is disengaged from the carrier 1024, and the protective films 1062 and 1064 are removed in step 918, obtaining a stacked embedded die assembly 1002. As shown in FIG. 10I, the embedded die assembly 1002 includes a substrate 302 in which one or more cavities 305 and / or vias 303 are formed and filled with an insulating dielectric material of epoxy resin layers 1018a and 1018b, and an embedded die 1026 in the cavity 305. The insulating dielectric materials of the epoxy resin layers 1018a and 1018b accommodate the substrate 302 such that the insulating material covers at least two surfaces or sides of the substrate 302, such as two major surfaces 606 and 608, and covers all sides of the embedded semiconductor die 1026. In some examples, the protective layers 1022a and 1022b are also removed from the embedded die assembly 1002 in step 918. Generally, the protective layers 1022a and 1022b, the carrier 1024, and the protective films 1062 and 1064 are removed from the embedded die assembly 1002 by any suitable mechanical process (e.g., peeling therefrom).

[0066]

[0082] When the protective layers 1022a and 1022b and the protective films 1062 and 1064 are removed, the embedded die assembly 1002 is exposed to a curing process to fully cure (i.e., strengthen through chemical reaction and cross-linking) the insulating dielectric materials of the epoxy resin layers 1018a and 1018b, thus forming a cured insulating layer 1018. The insulating layer 1018 substantially surrounds the substrate 302 and the semiconductor die 1026 embedded therein. For example, the insulating layer 1018 contacts or encapsulates at least the sides 1075 and 1077 (including the surfaces 606 and 608) of the substrate 302 and at least six sides or surfaces of each semiconductor die 1026 having a right prism shape as shown in FIG. 10I (i.e., only the four surfaces 1028 and 1029 shown in the 2D view).

[0067]

[0083] In one embodiment, the curing process is performed at a high temperature to fully cure the embedded die assembly 1002. For example, the curing process is carried out at a temperature between about 140°C and about 220°C for a period between about 15 minutes and about 45 minutes (e.g., at a temperature between about 160°C and about 200°C for a period between about 25 minutes and about 35 minutes). It is carried out. The curing process is performed, for example, at a temperature of about 180°C for about 30 minutes. In a further embodiment, the curing process in step 918 is carried out at or near ambient (e.g., atmospheric) pressure conditions.

[0068]

[0084] After curing, one or more assembly through vias 1003 are drilled through the embedded die assembly 1002 in step 920 to form channels through the entire thickness of the embedded die assembly 1002 for subsequent interconnect formation. In some embodiments, the embedded die assembly 1002 can be placed on a carrier, such as carrier 1024, for mechanical support during the formation of the assembly through vias 1003 and subsequent contact holes 1032. The assembly through vias 1003 are formed within the substrate 302 and are drilled through a via 303 subsequently filled with an insulating layer 1018. Thus, the assembly through vias 1003 can be circumferentially surrounded by the insulating layer 1018 filled within the via 303. By lining the wall of the via 303 with the ceramic filler-containing epoxy resin material of the insulating layer 1018, the capacitive coupling between the conductive silicon-based substrate 302 and the interconnect 1444 (described with reference to FIGS. 13 and 14E-14H), and thus the capacitive coupling between adjacent vias 303 and / or redistribution connections 1644 (described with reference to FIGS. 15 and 16H-16L), is significantly reduced in the completed package 1602 (described with reference to FIGS. 15 and 16K and FIGS. 16L) compared to other conventional interconnect structures that utilize a conventional via insulation liner or film. Further, the fluidity of the epoxy resin material enables more consistent and reliable encapsulation and insulation, thus improving the electrical performance by minimizing the leakage current of the completed package 1602.

[0069]

[0085] In one embodiment, the assembly through-via 1003 has a diameter of less than about 100 μm (such as less than about 75 μm). For example, the assembly through-via 1003 has a diameter of less than about 60 μm (such as less than about 50 μm). In one embodiment, the assembly through-via 1003 has a diameter between about 25 μm and about 50 μm (such as between about 35 μm and about 40 μm). In one embodiment, the assembly through-via 1003 is formed using any suitable mechanical process. For example, the assembly through-via 1003 is formed using a mechanical drilling process. In one embodiment, the assembly through-via 1003 is formed through the embedded die assembly 1002 by laser ablation. For example, the assembly through-via 1003 is formed using an ultraviolet laser. In one embodiment, the laser source utilized for laser ablation has a frequency between about 5 kHz and about 500 kHz. In one embodiment, the laser source is configured to deliver a pulsed laser beam with a pulse energy between about 50 microjoules (μJ) and about 500 μJ and a pulse duration between about 10 ns and about 100 ns. Utilizing an epoxy resin material with small ceramic filler particles further facilitates more precise and accurate laser patterning of small-diameter vias such as via 1003, as the small ceramic filler particles therein exhibit reduced laser light reflection, scattering, diffraction, and transmission of the laser light away from the region where the via is formed during the laser ablation process.

[0070]

[0086] In Project 922 and FIG. 10K, one or more contact holes 1032 are drilled through the insulating layer 1018 to expose one or more contacts 1030 formed on the active surface 1028 of each embedded die 1026. The contact holes 1032 are drilled through the insulating layer 1018 by laser ablation, and all external surfaces of the semiconductor die 1026 remain exposed, covered and surrounded by the insulating layer 1018 and the contacts 1030. Thus, by forming the contact holes 1032, the contacts 1030 are exposed. In one embodiment, the laser source can generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one embodiment, the laser source is configured to deliver a pulsed laser beam with a wavelength between about 100 nm and about 2000 nm, a pulse duration between about 10E-4 ns and about 10E-2 ns, and a pulse energy between about 10 μJ and about 300 μJ. In one embodiment, the contact holes 1032 are drilled using a CO2, green, or UV laser. In one embodiment, the contact holes 1032 have a diameter between about 5 μm and about 60 μm (such as a diameter between about 20 μm and about 50 μm).

[0071]

[0087] After the formation of the contact holes 1032, the embedded die assembly 1002 is exposed to a desmear process in step 922 to remove any unwanted residues and / or debris caused by laser ablation during the formation of the assembly through-vias 1003 and the contact holes 1032. Thus, the desmear process cleans the assembly through-vias 1003 and the contact holes 1032, and fully exposes the contacts 1030 on the active surface 1028 of the embedded die 1026 for subsequent metallization. In one embodiment, the desmear process is a wet desmear process. Any suitable aqueous etchant, solvent, and / or combinations thereof can be utilized for the wet desmear process. In one example, a potassium permanganate (KMnO4) solution can be utilized as the etchant. Depending on the thickness of the residues, the exposure of the embedded die assembly 1002 to the wet desmear process in step 922 can be varied. In another embodiment, the desmear process is a dry desmear process. For example, the desmear process can be a plasma desmear process using an O2:CF4 mixed gas. The plasma desmear process can include generating a plasma by applying a power of about 700 W and flowing O2:CF4 at a ratio of about 10:1 (e.g., 100:10 sccm) for a period between about 60 seconds and about 120 seconds. In a further embodiment, the desmear process is a combination of a wet process and a dry process.

[0072]

[0088] Following the desmear process in step 922, the embedded die assembly 1002 is ready to form internal interconnect paths as described below with reference to FIGS. 13 and 14A-14H.

[0073]

[0089] As described above, FIGS. 9 and 10A - 10K illustrate a representative method 900 for forming an intermediate - embedded die assembly 1002. FIGS. 11 and 12A - 12G illustrate an alternative method 1100 that is substantially similar to method 900 but has fewer steps. Method 1100 generally includes seven steps 1110 - 1170. However, steps 1110, 1120, 1160, and 1170 of method 1100 are substantially similar to steps 902, 904, 920, and 922 of method 900, respectively. Therefore, only steps 1130, 1140, and 1150, shown in FIGS. 12C, 12D, and 12E, respectively, are described herein for clarity.

[0074]

[0090] After placing one or more semiconductor dies 1026 on the surface of the insulating film 1016a exposed through the cavity 305, the second insulating film 1016b is disposed above the second side surface 1077 (e.g., surface 608) of the substrate 302 in step 1130 and FIG. 12C prior to lamination. In some embodiments, the second insulating film 1016b is disposed on the second side surface 1077 of the substrate 302 such that the epoxy resin layer 1018b of the second insulating film 1016b contacts and covers the active surface 1028 of the die 1026 within the cavity 305. In some embodiments, the second carrier 1025 is adhered to the protective layer 1022b of the second insulating film 1016b for additional mechanical support during subsequent processing operations. As depicted in FIG. 12C, one or more voids 1050 are formed between the insulating films 1016a and 1016b and the semiconductor die 1026 and the gap 1051 between the interior walls of the cavity 305 through the vias 303.

[0075]

[0091] In operation 1140 and FIG. 12D, substrate 302 is here adhered to insulating films 1016a and 1016b, die 1026 is disposed therein, and is exposed to a single lamination process. During the single lamination process, substrate 302 is exposed to high temperature, softening the epoxy resin layers 1018a and 1018b of both insulating films 1016a, 1016b, and causing it to flow into the open void or space between insulating films 1016a and 1016b (such as via 303 and gap 1051 between the inner wall of cavity 305 and die 1026). Thus, semiconductor die 1026 becomes embedded within the materials of insulating films 1016a, 1016b, and via 303 filled therewith.

[0076]

[0092] Similar to the lamination process described with reference to FIGS. 9 and 10A - 10K, the lamination process in operation 1140 can be a vacuum lamination process that can be performed in an autoclave or other suitable device. In another embodiment, the lamination process is performed using a hot press process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between about 1 psig and about 150 psig, while a temperature between about 80°C and about 140°C is applied to substrate 302 and insulating films 1016a, 1016b layers for a period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 10 psig and about 100 psig, at a temperature between about 100°C and about 120°C, for a period between about 2 minutes and 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for about 5 minutes.

[0077]

[0093] In operation 1150, one or more protective layers of the insulating films 1016a and 1016b are removed from the substrate 302, resulting in a stacked embedded die assembly 1002. As shown in FIG. 12E, the embedded die assembly 1002 includes a substrate 302 with one or more cavities 305 and / or vias 303 formed therein and filled with an insulating dielectric material of epoxy resin layers 1018a, 1018b, and an embedded die 1026 within the cavity 305. The insulating material encloses the substrate 302 such that the insulating material covers at least two surfaces or sides of the substrate 302, e.g., surfaces 606, 608. In one example, the protective layers 1022a, 1022b are removed from the embedded die assembly 1002, and thus, the embedded die assembly 1002 is disengaged from the carriers 1024, 1025. Generally, the protective layers 1022a, 1022b and the carriers 1024, 1025 are removed by any suitable mechanical process (e.g., peeling them off, etc.).

[0078]

[0094] Removing the protective layers 1022a, 1022b exposes the embedded die assembly 1002 to a curing process to fully cure the insulating dielectric material of the epoxy resin layers 1018a, 1018b. Curing of the insulating material results in the formation of a cured insulating layer 1018. As depicted in FIG. 12E and similar to operation 918 corresponding to FIG. 10I, the insulating layer 1018 substantially surrounds the substrate 302 and the semiconductor die 1026 embedded therein.

[0079]

[0095] In one embodiment, the curing process is performed at an elevated temperature to fully cure the embedded die assembly 1002. For example, the curing process is performed at a temperature between about 140°C and about 220°C for a period between about 15 minutes and about 45 minutes (e.g., at a temperature between about 160°C and about 200°C for a period between about 25 minutes and about 35 minutes). The curing process is, for example, performed at a temperature of about 180°C for about 30 minutes. In a further embodiment, the curing process in operation 1150 is performed at or near ambient (e.g., atmospheric) pressure conditions.

[0080]

[0096] After curing in Project 1150, Method 1100 is substantially similar to Steps 920 and 922 of Method 900. For example, the embedded die assembly 1002 has one or more assembly through vias 1003 and one or more contact holes 1032 that are drilled through the insulating layer 1018. Thereafter, the embedded die assembly 1002 is exposed to the desmear process, and then the embedded die assembly 1002 is ready to form internal interconnect paths as described below.

[0081]

[0097] FIG. 13 shows a flow diagram of a representative method 1300 for forming electrical interconnects through the embedded die assembly 1002. FIGS. 14A-14H schematically show cross-sectional views of the embedded die assembly 1002 at different stages of the process of the method 1300 shown in FIG. 13. Accordingly, FIGS. 13 and 14A-14H are described together herein for clarity.

[0082]

[0098] In one embodiment, the electrical interconnections formed through the embedded die assembly 1002 are formed of copper. Thus, method 1300 can optionally start with step 1310 and FIG. 14A. Here, an adhesive layer 1440 and / or a seed layer 1442 are formed on top of the embedded die assembly 1002 having assembly through vias 1003 and contact holes 1032 formed therein. An enlarged view of the adhesive layer 1440 and the seed layer 1442 formed on the embedded die assembly 1002 is shown in FIG. 14H for reference. The adhesive layer 1440 is formed on the desired surfaces of the insulating layer 1018 such as the major surfaces 1005, 1007 of the embedded die assembly 1002, as well as on the active surface 1028 of the contact holes 1032 on each die 1026 and the inner walls of the assembly through vias 1003, and can assist in promoting the adhesion and preventing the diffusion of the subsequently formed seed layer 1442 and copper interconnect 1444. Thus, in one embodiment, the adhesive layer 1440 acts as an adhesive layer, and in another embodiment, the adhesive layer 1440 acts as a barrier layer. However, in both embodiments, the adhesive layer 1440 will be described hereinafter as the "adhesive layer".

[0083]

[0099] In one embodiment, the optional adhesive layer 1440 is formed from titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combinations thereof. In one embodiment, the adhesive layer 1440 has a thickness between about 10 nm and about 300 nm (such as between about 50 nm and about 150 nm). For example, the adhesive layer 1440 has a thickness between about 75 nm and about 125 nm (such as about 100 nm). The adhesive layer 1440 is formed by any suitable deposition process including, but not limited to, chemical vapor deposition (CVD), physical vapor deposition (PVD), plasma CVD (PECVD), atomic layer deposition (ALD), etc.

[0084]

[0100] The optional seed layer 1442 can be formed on the adhesive layer 1440 or directly on the insulating layer 1018 (e.g., without forming the adhesive layer 1440). The seed layer 1442 is formed from a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combinations thereof. In one embodiment, the seed layer 1442 has a thickness between about 50 nm and about 500 nm (such as between about 100 nm and about 300 nm). For example, the seed layer 1442 has a thickness between about 150 nm and about 250 nm (such as about 200 nm). In one embodiment, the seed layer 1442 has a thickness between about 0.1 μm and about 1.5 μm. Similar to the adhesive layer 1440, the seed layer 1442 is formed by any suitable deposition process such as CVD, PVD, PECVD, ALD dry process, electroless plating wet process, etc. In one embodiment, the molybdenum adhesive layer 1440 is formed on the embedded die assembly in combination with the copper seed layer 1442. The combination of the Mo-Cu adhesive and seed layers enables improved adhesion to the surface of the insulating layer 1018 and reduces the undercut of the conductive interconnect lines during the subsequent seed layer etching process in step 1370.

[0085]

[0101] In processes 1320 and 1330, corresponding to FIGS. 14B and 14C respectively, a spin-on / spray-on or dry resist film 1450, such as a photoresist, is applied to both major surfaces 1005, 1007 of the embedded die assembly 1002 and then patterned. In one embodiment, the resist film 1450 is patterned via selective exposure to UV radiation. In one embodiment, an adhesion promoter (not shown) is applied to the embedded die assembly 1002 prior to the formation of the resist film 1450. The adhesion promoter improves the adhesion of the resist film 1450 to the embedded die assembly 1002 by creating an interfacial bonding layer for the resist film 1450 and by removing any moisture from the surface of the embedded die assembly 1002. In some embodiments, the adhesion promoter is formed from bis(trimethylsilyl)amine or hexamethyldisilazane (HMDS) and propylene glycol monomethyl ether acetate (PGMEA).

[0086]

[0102] In processes 1340 and FIG. 14D, the embedded die assembly 1002 is exposed to a resist film development process. As shown in FIG. 14D, when the resist film 1450 is developed, the assembly through vias 1003 and contact holes 1032 are exposed, where the adhesion layer 1440 and the seed layer 1442 are formed thereon. In one embodiment, the film development process is a wet process, such as a wet process that includes exposing the resist to a solvent. In one embodiment, the film development process is a wet etching process that utilizes an aqueous etching process. In other embodiments, the film development process is a wet etching process that utilizes a buffered etching process selective to the desired material. Any suitable combination of wet solvents or wet etchants can be used for the resist film development process.

[0087]

[0103] In processes 1350 and 1360, corresponding to FIGS. 14E and 14F respectively, an interconnect 1444 is formed through the exposed assembly through-via 1003, and then the contact hole 1032 and the resist film 1450 are removed. The interconnect 1444 is formed by any suitable method including electroplating and electroless plating. In one embodiment, the resist film 1450 is removed by a wet process. As depicted in FIGS. 14E and 14F, the formed interconnect 1444 fills the assembly through-via 1003 and the contact hole 1032 and / or covers its inner peripheral wall, and protrudes from the surfaces 1005, 1007, and 1028 of the embedded die assembly 1002 when the resist film 1450 is removed. In one embodiment, the interconnect 1444 is formed of copper. In other embodiments, the interconnect 1444 can be formed of any suitable conductive material including, but not limited to, aluminum, gold, nickel, silver, palladium, tin, etc.

[0088]

[0104] In process 1370 and FIG. 14G, the embedded die assembly 1002 with the interconnect 1444 formed therein is exposed to an adhesion and / or seed layer etching process to remove the adhesion layer 1440 and the seed layer 1442. In one embodiment, the seed layer etching is a wet etching process including rinsing and drying of the embedded die assembly 1002. In one embodiment, the seed layer etching process is a selective buffer etching process for a desired material such as copper, tungsten, aluminum, silver, or gold. In other embodiments, the etching process is an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the seed layer etching process.

[0089]

[0105] Following the seed layer etching process in Project 1370, one or more electrically functional packages can be separated from the embedded die assembly 1002. Alternatively, the embedded die assembly 1002 can, if desired, have one or more redistribution layers 1658 and / or 1660 (shown in FIGS. 16K - 16L) formed thereon, which can enable rerouting of the contacts of the interconnect 1444 to desired locations on the surface of the embedded die assembly 1002. FIG. 15 shows a flow diagram of a representative method 1500 for forming a redistribution layer 1658 on the embedded die assembly 1002. FIGS. 16A - 16L schematically show cross-sectional views of the embedded die assembly 1002 at different stages of the method 1500 shown in FIG. 15. Thus, FIGS. 15 and 16A - 16L are described together herein for clarity.

[0090]

[0106] Method 1500 is substantially similar to methods 900, 1100, and 1300 described above. Generally, method 1500 begins with step 1502 and FIG. 16A, where insulating film 1616 is formed on the embedded die assembly 1002 and then laminated. Insulating film 1616 may be substantially similar to insulating film 1016 and includes one or more layers formed from a polymer-based flowable dielectric material. In one embodiment, as shown in FIG. 16A, insulating film 1616 includes a flowable epoxy resin layer 1618 and one or more protective layers 1622. In one embodiment, insulating film 1616 may include a ceramic filler-containing epoxy resin layer 1618 and one or more protective layers 1622. In another example, insulating film 1616 may include a photosensitive polyimide layer 1618 and one or more protective layers 1622. The material properties of the photosensitive polyimide enable the formation of smaller (e.g., narrower) vias through the resulting interconnect layer formed from insulating film 1616. However, any suitable combination of layers and insulating materials is contemplated for insulating film 1616. For example, insulating film 1616 may be formed of non-photosensitive polyimide, polybenzoxazole (PBO), silicon dioxide, and / or silicon nitride. In some examples, insulating film 1616 is formed from a polymer-based flowable dielectric material different from insulating film 1016. For example, insulating film 1016 includes a ceramic filler-containing epoxy resin layer and insulating film 1616 may include a photosensitive polyimide layer. In another example, insulating film 1616 is formed from an inorganic dielectric material different from insulating film 1016. For example, insulating film 1016 includes a ceramic filler-containing epoxy resin layer and insulating film 1616 may include a silicon dioxide layer.

[0091]

[0107] The thermal insulation film 1616 has a thickness of less than about 120 mm (such as between about 40 mm and about 100 mm). For example, the insulating film 1616 including the epoxy resin layer 1618 and the PET protective layer 1622 has a total thickness between about 50 μm and about 90 μm. In one embodiment, the epoxy resin layer 1618 has a thickness of less than about 60 μm, such as a thickness between about 5 μm and about 50 μm (such as a thickness of about 20 μm). The insulating film 1616 is placed on the surface (such as the main surface 1005) of the embedded die assembly 1002 having an exposed interconnect 1444 that is connected to the contact 1030 on the active surface 1028 of the die 1026 and / or connected to the metallization assembly through via 1003.

[0092]

[0108] After placement of the insulating film 1616, the embedded die assembly 1002 is exposed to a lamination process substantially similar to the lamination processes described with reference to steps 908, 916, and 1140. The embedded die assembly 1002 is exposed to a high temperature to soften the epoxy resin layer 1618, which then binds to the insulating layer 1018 already formed on the embedded die assembly 1002. Thus, in one embodiment, the epoxy resin layer 1618 is integrated with the insulating layer 1018 to form an extension thereof. The integration of the epoxy resin layer 1618 and the insulating layer 1018 results in an extended and integrated insulating layer 1018 that covers the previously exposed interconnect 1444. Thus, here, the combined epoxy resin layer 1618 and insulating layer 1018 will be described as the insulating layer 1018. However, in other embodiments, the lamination and subsequent curing of the epoxy resin layer 1618 forms a second insulating layer (not shown) on the insulating layer 1018. In some examples, the second insulating layer is formed of a material layer different from the insulating layer 1018.

[0093]

[0109] In one embodiment, the lamination process is a vacuum lamination process that can be performed within an autoclave or other suitable device. In one embodiment, the lamination process is performed using a hot press process. In one embodiment, the lamination process is performed at a temperature between about 80°C and about 140°C and for a period between about 1 minute and about 30 minutes. In some embodiments, the lamination process includes applying a pressure between 10 psig and about 100 psig, while a temperature between about 80°C and about 140°C is applied to the substrate 302 and the insulating film 1616 for a period between about 1 minute and about 30 minutes. For example, the lamination process is performed at a pressure between about 30 psig and about 80 psig and at a temperature between about 100°C and about 120°C for a period between about 2 minutes and about 10 minutes. For example, the lamination process is performed at a temperature of about 110°C for about 5 minutes. In a further example, the lamination process is performed at a pressure between about 30 psig and about 70 psig (such as about 50 psig).

[0094]

[0110] In step 1504 and FIG. 16B, the protective layer 1622 and the carrier 1624 are removed from the embedded die assembly 1002 by a mechanical process. After removing the protective layer 1622 and the carrier 1624, the embedded die assembly 1002 is exposed to a curing process to fully cure the newly expanded insulating layer 1018. In one embodiment, the curing process is substantially similar to the curing process described with reference to steps 918 and 1150. For example, the curing process is performed at a temperature between about 140°C and about 220°C for a period between about 15 minutes and about 45 minutes (e.g., at a temperature between about 160°C and about 200°C for a period between about 25 minutes and about 35 minutes) is performed. The curing process is, for example, performed at a temperature of about 180°C for about 30 minutes. In a further embodiment, the curing process in step 1504 is performed at or near ambient pressure conditions.

[0095]

[0111] Next, the embedded die assembly 1002 is selectively patterned by laser ablation in step 1506 and FIG. 16C. The laser ablation in step 1506 forms redistribution vias 1603 through the newly enlarged insulating layer 1018, exposing the desired interconnects 1444 for redistribution of their contacts. In one embodiment, the redistribution vias 1603 have a diameter between about 5 μm and about 60 μm (such as a diameter between about 10 μm and about 50 μm (e.g., between about 20 μm and about 45 μm)). In one embodiment, the laser ablation process in step 1506 is performed using a CO2 laser. In one embodiment, the laser ablation process in step 1506 is performed using a UV laser. In one embodiment, the laser ablation process in step 1506 is performed using a green laser. For example, the laser source can generate a pulsed laser beam having a frequency between about 100 kHz and about 1000 kHz. In one example, the laser source is configured to deliver a pulsed laser beam with a wavelength between about 100 nm and about 2000 nm, a pulse duration between about 10E-4 ns and about 10E-2 ns, and a pulse energy between about 10 μJ and about 300 μJ.

[0096]

[0112] When the embedded die assembly 1002 is patterned, the embedded die assembly 1002 is exposed to a desmear process that is substantially similar to the desmear processes in steps 922 and 1170. During the desmear process in step 1506, unwanted residues and debris formed by laser ablation during the formation of redistribution via 1603 are removed from redistribution via 1603, and its surface is cleared (e.g., cleaned) for subsequent metallization. In one embodiment, the desmear process is a wet process. Any suitable aqueous etchant, solvent, and / or combinations thereof can be utilized for the wet desmear process. In one example, a KMnO4 solution can be utilized as the etchant. In another embodiment, the desmear process is a dry desmear process. For example, the desmear process can be a plasma desmear process using an O2 / CF4 mixed gas. In a further embodiment, the desmear process is a combination of a wet process and a dry process.

[0097]

[0113] In steps 1508 and FIG. 16D, an optional adhesive layer 1640 and / or seed layer 1642 is formed on the insulating layer 1018. In one embodiment, the adhesive layer 1640 is formed from titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, cobalt nitride, or any other suitable material or combinations thereof. In one embodiment, the adhesive layer 1640 has a thickness between about 10 nm and about 300 nm (such as between about 50 nm and about 150 nm). For example, the adhesive layer 1640 has a thickness between about 75 nm and about 125 nm (such as about 100 nm). The adhesive layer 1640 can be formed by any suitable deposition process including, but not limited to, CVD, PVD, PECVD, ALD, etc.

[0098]

[0114] The optional seed layer 1642 is formed of a conductive material such as copper, tungsten, aluminum, silver, gold, or any other suitable material or combination thereof. In one embodiment, the seed layer 1642 has a thickness between about 50 nm and about 500 nm (such as between about 100 nm and about 300 nm). For example, the seed layer 1642 has a thickness between about 150 nm and about 250 nm (such as about 200 nm). In one embodiment, the seed layer 1642 has a thickness between about 0.1 μm and about 1.5 μm. Similar to the adhesive layer 1640, the seed layer 1642 can be formed by any suitable deposition process such as CVD, PVD, PECVD, ALD dry process, wet electroless plating process, etc. In one embodiment, a molybdenum adhesive layer 1640 and a copper seed layer 1642 are formed on the embedded die assembly 1002 to reduce the undercut of the conductive interconnect lines during the subsequent seed layer etching process in step 1520.

[0099]

[0115] In steps 1510, 1512, and 1514 corresponding to FIGS. 16E, 16F, and 16G respectively, a spin-on / spray-on or dry resist film 1650 such as photoresist is applied over the adhesive surface and / or the seed surface of the embedded die assembly 1002 and then patterned and developed. In one embodiment, an adhesion promoter (not shown) is applied to the embedded die assembly 1002 before placing the resist film 1650. Exposure and development of the resist film 1650 opens the redistribution vias 1603. Thus, patterning of the resist film 1650 can be performed by selectively exposing a portion of the resist film 1650 to UV radiation and then developing the resist film 1650 by a wet process such as a wet etching process. In one embodiment, the resist film development process is a wet etching process that utilizes a buffer etching process selective to the desired material. In other embodiments, the resist film development process is a wet etching process that utilizes an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the resist film development process.

[0100]

[0116] In steps 1516 and 1518 corresponding to FIGS. 16H and 16I respectively, redistribution connection 1644 is formed through exposed redistribution via 1603, and then resist film 1650 is removed. Redistribution connection 1644 is formed by any suitable method including electroplating and electroless deposition. In one embodiment, resist film 1650 is removed by a wet process. As shown in FIGS. 16H and 16I, redistribution connection 1644 fills redistribution via 1603 and protrudes from the surface of embedded die assembly 1002 when resist film 1650 is removed. In one embodiment, redistribution connection 1644 is formed of copper. In other embodiments, redistribution connection 1644 can be formed of any suitable conductive material including, but not limited to, aluminum, gold, nickel, silver, palladium, tin, etc.

[0101]

[0117] In step 1520 and FIG. 16J, embedded die assembly 1002 on which redistribution connection 1644 is formed is exposed to a seed layer etching process substantially similar to that of step 1370. In one embodiment, seed layer etching is a wet etching process including rinsing and drying of embedded die assembly 1002. In one embodiment, the seed layer etching process is a wet etching process utilizing a buffered etching process selective to the desired material of seed layer 1642. In other embodiments, the etching process is a wet etching process utilizing an aqueous etching process. Any suitable wet etchant or combination of wet etchants can be used for the seed layer etching process.

[0102]

[0118] In operation 1522, one or more completed packages 1602, shown in FIGS. 16K and 16L, are separated from the embedded die assembly 1002. However, prior to operation 1522, as shown in FIG. 16L, additional redistribution layers may be formed on the embedded die assembly 1002 using the sequences and processes described above (FIG. 16K shows a completed package 1602 having one additional redistribution layer 1658). For example, one or more additional redistribution layers 1660 may be formed on a side or surface of the embedded die assembly 1002 opposite the first additional redistribution layer 1658, such as the major surface 1007. Alternatively, one or more additional redistribution layers 1660 may be formed on the same side or surface as the first additional redistribution layer 1658 (not shown), such as the major surface 1005. The completed package 1602 may then be separated from the embedded die assembly 1002 after all desired redistribution layers have been formed.

[0103]

[0119] The package 1602 formed in operation 1522 may be utilized in any suitable packaging application and in any suitable configuration. In one exemplary embodiment shown in FIG. 17A, four packages 1602 are utilized to form a stacked DRAM structure 1700. Thus, each package 1602 includes a memory die 1726 (i.e., a memory chip) that is embedded within a substrate 302 and encapsulated by an insulating layer 1018 (e.g., a portion of each side contacts the insulating layer 1018). One or more interconnects 1444 are formed through the entire thickness of each package 1602 and contact directly one or more solder bumps 1746 disposed between the major surfaces 1005 and 1007 of adjacent (i.e., stacked on top of or below) packages 1602. For example, as depicted in the stacked DRAM structure 1700, more than four solder bumps 1746 are disposed between adjacent packages 1602 to bridge (e.g., couple, connect) the interconnects 1444 of each package 1602 with the interconnects 1444 of adjacent packages 1602.

[0104]

[0120] In one embodiment, voids between adjacent packages 1602 connected by solder bumps 1746 are filled with encapsulating material 1748 to enhance the reliability of the solder bumps 1746. The encapsulating material 1748 can be any suitable type of encapsulant or underfill. In one example, the encapsulating material 1748 includes pre-assembly underfill materials such as no-flow underfill (NUF) materials, non-conductive paste (NCP) materials, and non-conductive film (NCF) materials. In one example, the encapsulating material 1748 includes post-assembly underfill materials such as capillary underfill (CUF) materials and molded underfill (MUF) materials. In one embodiment, the encapsulating material 1748 includes a low-expansion filler-containing resin such as an epoxy resin filled with (e.g., containing) SiO2, AlN, Al2O3, SiC, Si3N4, Sr2Ce2Ti5O 16 , ZrSiO4, CaSiO3, BeO, CeO2, BN, CaCu3Ti4O 12 , MgO, TiO2, ZnO, etc.

[0105]

[0121] In one embodiment, the solder bumps 1746 are formed of a compound between one or more metals such as tin (Sn) and lead (Pb), silver (Ag), copper (Cu), or any other suitable combination of these metals. For example, the solder bumps 1746 are formed of a solder alloy such as Sn-Pb, Sn-Ag, Sn-Cu, or any other suitable material or combination thereof. In one embodiment, the solder bumps 1746 include C4 (controlled collapse chip connection) bumps. In one embodiment, the solder bumps 1746 include C2 (chip connection such as Cu pillars with solder caps) bumps. The use of C2 solder bumps allows for a smaller pitch between contact pads and enables improved thermal and / or electrical characteristics for the stacked DRAM structure 1700. In some embodiments, the solder bumps 1746 have a diameter between about 10 μm and about 150 μm (such as between about 50 μm and about 100 μm). The solder bumps 1746 can be formed by any suitable wafer bumping process including, but not limited to, electrochemical deposition (ECD) and electroplating.

[0106]

[0122] In another exemplary embodiment shown in FIG. 17B, the stacked DRAM structure 1701 is formed by stacking four packages 1602 and directly coupling one or more interconnects 1444 of each package 1602 to the interconnects 1444 of one or more adjacent packages 1602. As shown, the packages 1602 may be coupled by hybrid bonding, where the major surfaces 1005 and 1007 of adjacent packages are planarized and in complete contact with each other. Thus, one or more interconnects 1444 of each package 1602 are formed through the entire thickness of each package 1602 and are in direct contact with one or more interconnects 1444 of at least another adjacent package 1602.

[0107]

[0123] The stacked DRAM structures 1700 and 1701 offer several advantages over conventional DRAM structures. Such advantages include a thin form factor and a high die-to-package volume ratio, which enable greater I / O scaling to meet the increasing bandwidth and power efficiency requirements of artificial intelligence (AI) and high-performance computing (HPC). The use of a structured silicon frame provides optimal material stiffness and thermal conductivity for improved electrical performance, thermal management, and reliability of three-dimensional integrated circuit (3D IC) architectures. Further, the manufacturing methods for the assembly through vias and via-in-via structures described herein provide high performance and flexibility for 3D integration at relatively low manufacturing costs compared to conventional TSV technologies.

[0108]

[0124] Embodiments described herein advantageously provide an improved method of substrate structuring and die assembly for manufacturing high - density integrated circuit packages. By utilizing the methods described above, high aspect ratio features are formed on glass and / or silicon substrates, thus enabling the economical formation of thinner and narrower semiconductor packages. The thin and small form factor packages manufactured using the methods described above offer not only high I / O density and improved bandwidth and power advantages, but also greater reliability due to lower stress resulting from a package architecture that allows for reduced weight / inertia and flexible solder ball distribution. Further advantages of the methods described above include economical manufacturing with double - sided metallization capabilities and high production yields by eliminating flip - chip attachment steps and over - molding steps that are prone to damage characteristic of mass production of conventional and advanced packages.

[0109]

[0125] While the above is directed to embodiments of the present disclosure, other and further embodiments of the present disclosure may be devised without departing from its basic scope, which is determined by the following claims.

Claims

1. A frame, wherein the frame comprises a silicon substrate having a first side opposite to a second side, a quadrilateral cavity formed in the substrate and extending through the substrate from the first side to the second side, and a plurality of cylindrical vias formed in the substrate and extending through the substrate from the first side to the second side, the plurality of cylindrical vias being arranged in one or more columns on each side of the cavity, a frame including the above, an active die disposed within the cavity, a first plurality of electrical interconnections, each of the first plurality of electrical interconnections being disposed within one of the plurality of cylindrical vias, and a dielectric layer formed on the first side and the second side, the dielectric layer being disposed on each side of the active die and between each of the first plurality of electrical interconnections and the sidewalls of the corresponding vias in which each of the first plurality of electrical interconnections is disposed, a package structure including the above.

2. The package structure according to claim 1, further comprising an intermediate layer disposed between the dielectric layer and each of the first plurality of electrical interconnections.

3. The package structure according to claim 2, wherein the intermediate layer comprises at least one of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, and cobalt nitride.

4. The package structure according to claim 2, wherein the intermediate layer comprises at least one of copper, tungsten, aluminum, silver, and gold.

5. The package structure according to claim 2, wherein the intermediate layer comprises a first layer including molybdenum and a second layer including copper.

6. The package structure according to claim 1, wherein the substrate comprises crystalline silicon.

7. The package structure according to claim 6, wherein the substrate comprises single crystal p-type or n-type silicon.

8. The package structure according to claim 1, wherein the substrate has a thickness between about 110 μm and about 200 μm.

9. The package structure according to claim 1, wherein the dielectric layer has a thickness of less than about 150 μm between the active die and the sidewalls of the cavity.

10. The package structure according to claim 1, wherein the dielectric layer has a thickness of less than about 150 μm between each of the first plurality of electrical interconnections and the sidewalls of the corresponding vias in which each of the first plurality of electrical interconnections is disposed.

11. The package structure according to claim 1, further comprising an oxide layer formed on the first side surface and the second side surface of the substrate.

12. The package structure according to claim 11, wherein the oxide layer has a thickness between about 300 nm and about 2 μm.

13. The package structure according to claim 1, wherein the dielectric layer comprises a laminated epoxy resin having a ceramic filler.

14. The package structure according to claim 13, wherein the ceramic filler comprises at least one of silica, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, zirconium silicate, wollastonite, beryllium oxide, cerium dioxide, boron nitride, calcium copper titanium oxide, magnesium oxide, titanium dioxide, and zinc oxide.

15. The package structure according to claim 1, further comprising a second plurality of electrical interconnections formed through the dielectric layer and electrically connected to the active die.

16. The package structure according to claim 1, wherein a minimum pitch between each of the plurality of cylindrical vias is between about 70 μm and about 200 μm.

17. The package structure according to claim 1, further comprising a molybdenum layer and a copper layer formed inside each of the plurality of cylindrical vias and disposed between the electrical interconnection in the via and the dielectric layer.

18. A frame, wherein the frame comprises A patterned substrate including a semiconductor material and having a first side surface opposite to a second side surface, A first opening formed in the patterned substrate and extending from the first side surface to the second side surface, and A plurality of second openings formed along an edge of the first opening in the patterned substrate and extending from the first side surface to the second side surface, wherein each of the plurality of second openings has a first lateral dimension adjacent to the first side surface and a second lateral dimension adjacent to the second side surface, and a form of the plurality of second openings is different from a form of the first opening, the plurality of second openings, A frame including A semiconductor device disposed in the first opening, Disposed inside at least one of the plurality of second openings, a metal interconnect extending at least between the first side surface and the second side surface, A dielectric material disposed on the first side surface and the second side surface and inside each of the first opening and the plurality of second openings, the dielectric material being disposed on each side surface of the semiconductor device and between the metal interconnect and at least one side wall of the plurality of second openings, An intermediate layer disposed between the dielectric material and the metal interconnect inside at least one of the plurality of second openings, A semiconductor device package including the above.

19. The semiconductor device package according to claim 18, wherein the dielectric material includes an epoxy resin.

20. The semiconductor device package according to claim 19, wherein the epoxy resin includes ceramic filler particles.

21. The semiconductor device package according to claim 20, wherein the ceramic filler particles include at least one of silica, aluminum nitride, aluminum oxide, silicon carbide, silicon nitride, zirconium silicate, wollastonite, beryllium oxide, cerium dioxide, boron nitride, calcium copper titanium oxide, magnesium oxide, titanium dioxide, and zinc oxide.

22. The semiconductor device package according to claim 18, wherein the intermediate layer includes at least one of titanium, titanium nitride, tantalum, tantalum nitride, manganese, manganese oxide, molybdenum, cobalt oxide, and cobalt nitride.

23. The semiconductor device package according to claim 18, wherein the intermediate layer includes a first layer containing molybdenum and a second layer containing copper.

24. A method of forming a semiconductor device package, Placing a semiconductor die in at least one cavity formed in a substrate and extending through the substrate, Placing an epoxy resin material on a first side surface and a second side surface of the substrate and on a surface of at least one via formed in the substrate, the epoxy resin material filling a void formed between a surface of the semiconductor die and a surface of the cavity, the epoxy resin material including ceramic particles having a size in a range between about 200 nm and about 800 nm, and the first side surface, the second side surface, and the surface of the at least one via constituting an oxide layer, placing the epoxy resin material. Forming an opening through the epoxy resin material disposed in the at least one via, wherein the epoxy resin material is disposed between a surface defining the formed opening and a surface of the at least one via, and forming an opening through the epoxy resin material disposed in the at least one via, Depositing a conductive layer on a surface of the formed opening, A method comprising.

25. The method according to claim 24, wherein the substrate is a silicon-containing substrate having a thickness between about 60 μm and about 160 μm.

26. The method according to claim 24, wherein the at least one cavity has a lateral dimension between about 3 mm and about 50 mm.

27. The method according to claim 26, wherein a lateral dimension of the at least one cavity is greater than a lateral dimension of the semiconductor die by less than about 150 μm.

28. The method according to claim 24, wherein the at least one via has a diameter between about 50 μm and about 200 μm.

29. The method according to claim 24, wherein the epoxy resin material has a thickness between about 5 μm and about 50 μm.

30. The method according to claim 24, wherein the ceramic particles include silica particles.

31. Depositing a conductive layer on the formed opening, The method according to claim 24, further comprising depositing an adhesive layer and a seed layer on a surface of the formed opening, wherein the adhesive layer and the seed layer are disposed between the conductive layer and the epoxy resin material.

32. The method according to claim 31, wherein the adhesive layer contains molybdenum and the seed layer contains copper.

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