DC / DC Converter and High-Side Regulator

Abstract

To provide: a DC / DC converter capable of reducing current consumption without reducing drivability of a high-side MOS transistor; and high side regulator.SOLUTION: A DC / DC converter 1 comprises a high side regulator 9 for turning on and turning off a high-side power MOS transistor MPW1. The high side regulator 9 includes an output capacitor C1 and a Zener diode DZ1 which are connected in parallel with each other. When a voltage across the output capacitor C1 exceeds a Zener voltage, a current flows to a Zener diode DZ2, and a current detection unit 172 detects this and outputs a detection signal to a delay circuit 181. The delay circuit 181 turns on a transistor Mn3 just for a fixed delay time from input of the detection signal and cuts off a current to be supplied to the output capacitor C1 and the Zener diode DZ2.SELECTED DRAWING: Figure 2

Description

Technical Field

[0001] The present invention relates to a DC / DC converter and a high-side regulator.

Background Art

[0002] Conventionally, a circuit shown in FIG. 10 has been proposed as a high-side regulator used in a DC / DC converter. The high-side regulator 100 shown in FIG. 10 is a power supply circuit for on / off driving a high-side MOS transistor provided between an input voltage source and a coil of a DC / DC converter. The high-side regulator 100 includes a Zener diode D Z1 an output capacitor C1, and a current mirror circuit 16 composed of transistors Mn1 and Mn2.

[0003] When a bias current I BIAS is supplied to the output capacitor C1 by the current mirror circuit 16, the voltage across the output capacitor C1, that is, the voltage V HREG rises. When the voltage V HREG exceeds the Zener voltage V Z1 of the Zener diode D DZ , the Zener diode D Z1 conducts, and the voltage V HREG is clamped to the Zener voltage V DZ to generate a constant voltage.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, the above-described high-side regulator 100 always has the Zener diode D Z1Since the output capacitor C1 is supplied with current from the current mirror circuit 16, there is a problem of high current consumption.

[0006] The present invention has been made in view of the above-described circumstances, and an object thereof is to provide a DC / DC converter and a high-side regulator that can reduce current consumption without reducing the drive ability of the high-side MOS transistor.

Means for Solving the Problems

[0007] In order to achieve the above-described object, the DC / DC converter and the high-side regulator according to the present invention are characterized by the following [1] to [6]. [1] An inductor, A high-side MOS transistor provided between the input voltage source and the inductor for supplying the input voltage of the input voltage source to the inductor, A control circuit for controlling the on / off of the high-side MOS transistor to convert the input voltage, In a DC / DC converter having a high-side regulator that is a power supply circuit for on / off driving the high-side MOS transistor by the control circuit, The high-side regulator includes An output capacitor, A first Zener diode connected in parallel with the output capacitor, A current supply circuit provided on the low-side of the output capacitor and the first Zener diode for supplying current to the output capacitor and the first Zener diode, A current detection circuit for detecting that current flows through the first Zener diode, A blocking circuit for blocking the current supplied from the current supply circuit to the output capacitor and the first Zener diode when the current detection circuit detects that current flows through the first Zener diode, A DC / DC converter. [2] In the DC / DC converter described in [1], the cutoff circuit cuts off the current for a certain period from the timing when the current detection circuit detects that current is flowing through the first Zener diode. It is a DC / DC converter. [3] In the DC / DC converter described in [1], the control circuit includes an oscillator that outputs a clock, and a PWM control unit that outputs a PWM signal of duty based on a comparison between a slope signal synchronized with the clock and an error signal indicating a difference between the output voltage or output current of the DC / DC converter and a reference value. The on / off of the MOS transistor on the high side is controlled according to the PWM signal. The cutoff circuit cuts off the current only from the time when the current detection circuit detects that current is flowing through the first Zener diode until the clock rises or falls. It is a DC / DC converter. [4] In the DC / DC converter described in [1], the cutoff circuit cuts off the current only from the time when the current detection circuit detects that current is flowing through the first Zener diode until the MOS transistor on the high side switches from off to on. It is a DC / DC converter. [5] In the DC / DC converter according to any one of [1] to [4], the current detection circuit includes a second Zener diode whose cathode is connected to the cathode of the first Zener diode, and a current mirror circuit that copies the current flowing through the output capacitor and the first Zener diode and sends it through the second Zener diode. A current detection unit that detects that current has flowed through the second Zener diode due to conduction of the second Zener diode by the current mirror circuit. It is a DC / DC converter. [6] A high-side regulator that is a power supply circuit for on / off driving a high-side MOS transistor provided between an input voltage source and a coil of a DC / DC converter, An output capacitor, A first Zener diode connected in parallel with the output capacitor, A current supply circuit provided on the low side of the output capacitor and the first Zener diode for supplying current to the output capacitor and the first Zener diode, A current detection circuit that detects that current has flowed through the first Zener diode, A cutoff circuit that cuts off the current supplied from the current supply circuit to the output capacitor and the first Zener diode when the current detection circuit detects that current has flowed through the first Zener diode. It is a high-side regulator.

Advantages of the Invention

[0008] According to the present invention, it is possible to provide a DC / DC converter and a high-side regulator that can reduce power consumption while suppressing a decrease in the drive ability of a high-side MOS transistor.

[0009] The present invention has been briefly described above. Further, the details of the present invention will be further clarified by reading through the embodiments for carrying out the invention described below (hereinafter referred to as "embodiments") with reference to the accompanying drawings.

Brief Description of the Drawings

[0010]

Figure 1

Figure 2

Figure 3

Figure 4

Figure 5

Figure 6

Figure 7

Figure 8

Figure 9

Figure 10

DETAILED DESCRIPTION OF THE INVENTION

[0011] (First Embodiment) A specific first embodiment of the present invention will be described below with reference to the respective figures.

[0012] The DC / DC converter 1 shown in FIG. 1 steps down the DC input voltage V PWH , M PWL supplied from the input voltage source by turning on and off, and outputs the output voltage V IN from the output terminal OUT. OUTOutput as such. The DC / DC converter 1 includes a power MOS transistor M PWH , M PWL , a coil L OUT1 , a capacitor C OUT1 , a voltage detection resistor R B1 , R B2 , and a control IC2 (control circuit) that controls the on / off of the power MOS transistors M PWH , M PWL .

[0013] The power MOS transistor M PWH as the high-side MOS transistor is composed of a P-channel field-effect transistor. The power MOS transistor M PWH has its source connected to the positive electrode of the input voltage source, its drain connected to one end of the coil L OUT1 described later and the drain of the power MOS transistor M PWL , and its gate connected to the control IC2 described later via the resistor R H .

[0014] The power MOS transistor M PWL is composed of an N-channel field-effect transistor. The power MOS transistor M PWL has its drain connected to the drain of the power MOS transistor M PWH and one end of the coil L OUT1 , its source connected to the ground, and its gate connected to the control IC2 described later via the resistor R L .

[0015] One end of the coil L OUT1 is connected to the drains of the power MOS transistors M PWH , M PWL , and the other end is connected to the positive electrode side of the output terminal OUT. The capacitor C OUT1 and the voltage detection resistors R B1 , R B2 are connected in parallel to each other between the pair of output terminals OUT. Specifically, one end of the capacitor C OUT1 is connected to the coil L OUT1is connected to the other end and the positive electrode side of the output terminal OUT, and the other end is connected to the ground.

[0016] Voltage detection resistors R B1 and R B2 are connected in series with each other. The voltage detection resistor R B1 has one end connected to the other end of the coil L OUT1 and the positive electrode side of the output terminal OUT, and the other end is connected to the voltage detection resistor R B2 . The voltage detection resistor R B2 has one end connected to the voltage detection resistor R B1 and the other end is connected to the ground. The output voltage V OUT is divided by the voltage detection resistors R B1 and R B2 to obtain the detected voltage V OUTS which is supplied to the control IC2.

[0017] When the above-mentioned power MOS transistor M PWH is turned on and the power MOS transistor M PWL is turned off, the energy from the input voltage V OUT1 is accumulated in the coil L IN . On the other hand, when the power MOS transistor M PWH is turned off and the power MOS transistor M PWL is turned on, the current corresponding to the energy accumulated in the coil L OUT1 is sent from the ground to the coil L OUT1 , and the output voltage V OUT1 smoothed by the capacitor C OUT is output.

[0018] The control IC2 turns on and off the power MOS transistors M OUTS so that the detected voltage V PWH and M PWL becomes the reference value. The control IC2 includes a PWM control unit 3, an oscillator 4, a dead time control unit 5, a high side drive unit 6, a low side drive unit 7, and a regulator 8.

[0019] The PWM control unit 3 compares the detected voltage V OUTSOutputs a PWM signal with a duty cycle corresponding to the comparison between the error signal, which is the difference from the reference value, and the slope signal synchronized with the clock output from the oscillator 4, to the dead time control unit 5. The dead time control unit 5 outputs PWM signals with dead time provided so that the power MOS transistors M PWH , M PWL do not turn on simultaneously, to the high-side drive unit 6 and the low-side drive unit 7 respectively.

[0020] The high-side drive unit 6 outputs a drive voltage to the gate of the high-side power MOS transistor M PWH according to the PWM signal output from the dead time control unit 5.

[0021] The high-side drive unit 6 includes transistors M 1H , M 2H , a high-side regulator 9, a level shifter 10, and a pre-driver 11. Transistor M 1H is composed of a P-channel field effect transistor. Transistor M 1H has its source connected to the positive electrode of the input voltage source, its drain connected to the gate of the power MOS transistor M H via a resistor R PWH , and its gate connected to the pre-driver 11 described later. Transistor M 2H is composed of an N-channel field effect transistor. Transistor M 2H has its source connected to the output terminal of the high-side regulator 9, its drain connected to the gate of the power MOS transistor M H via a resistor R PWH , and its gate connected to the pre-driver 11 described later.

[0022] The high-side regulator 9 generates an output voltage (V IN - V HREG ). The high-side regulator 9 will be described later. The level shifter 10 sets the H level to V IN and the L level to V IN - VHREG Perform level shifting so as to obtain the following, and supply it to the pre-driver 11. The pre-driver 11 outputs the level-shifted PWM signal to the gates of transistors M 1H , M 2H .

[0023] As a result, H when a PWM signal of a certain level is output, transistor M 1H turns on, transistor M 2H turns off, and the input voltage V PWH is supplied to the gate of the power MOS transistor M IN , causing the power MOS transistor M PWH to turn off. On the other hand, L when a PWM signal of another level is output, transistor M 1H turns off, transistor M 2H turns on, and the output voltage (V PWH -V IN -V HREG ) is supplied to the gate of the power MOS transistor M PWH , causing the power MOS transistor M

[0024] The low-side driver 7 outputs a driving voltage to the gate of the low-side power MOS transistor M PWL according to the PWM signal output from the dead-time control unit 5.

[0025] The low-side driver 7 includes transistors M 1L , M 2L , a low-side regulator 12, a level shifter 13, and a pre-driver 14. Transistor M 1L is composed of a P-channel field-effect transistor. The source of transistor M 1L is connected to the output terminal of the low-side regulator 12, the drain is connected to the gate of the power MOS transistor M PWL via a resistor R L , and the gate is connected to the pre-driver 14 described later. Transistor M 2L is composed of an N-channel field-effect transistor. Transistor M2L has its source connected to ground and its drain connected to the gate of power MOS transistor M PWL through resistor R L and its gate is connected to the pre-driver 14 described later.

[0026] The low-side regulator 12 generates an output voltage V LREG The level shifter 13 level-shifts the PWM signal output from the dead-time control unit 5 so that the H level is V LREG and the L level is ground (0 V), and supplies it to the pre-driver 14. The pre-driver 14 outputs the level-shifted PWM signal to the gates of transistors M 1L and M 2L .

[0027] As a result, when an L-level PWM signal is output, transistor M 1L turns on, transistor M 2L turns off, and voltage V PWL is supplied to the gate of power MOS transistor M LREG , causing power MOS transistor M PWL to turn on. On the other hand, when an H-level PWM signal is output, transistor M 1L turns off, transistor M 2L turns on, and 0 V is supplied to the gate of power MOS transistor M PWL , causing power MOS transistor M PWL to turn off.

[0028] The regulator 8 generates the output voltage V REG to be supplied to the above-described PWM control unit 3, oscillator 4, dead-time control unit 5, high-side regulator 9, and level shifter 13.

[0029] Next, the details of the above-described high-side regulator 9 will be described with reference to FIG. 2. The high-side regulator 9 includes a Zener diode D as a first Zener diode Z1and an output capacitor C1, a bias current source 15, a current mirror circuit 16 as a current supply circuit, a current detection circuit 17, and a cutoff circuit 18 are provided.

[0030] Zener diode D Z1 And the output capacitor C1 is connected in parallel to each other between the output terminals VH and VL. The bias current source 15 outputs a bias current I BIAS The bias current source 15 is connected between the output voltage V of the regulator 8 and the current mirror circuit 16 described later. REG

[0031] The current mirror circuit 16 is provided on the low side (between the output terminal VL and the ground) of the output capacitor C1 and the Zener diode D, and copies the bias current I Z1 to supply the output capacitor C1 and the Zener diode D. The current mirror circuit 16 has transistors Mn1 and Mn2. The transistors Mn1 and Mn2 are composed of N-channel field effect transistors. The drain of the transistor Mn1 is connected to the bias current source 15, the source is connected to the ground, and the gate is connected to the drain. BIAS Z1 The drain of the transistor Mn2 is connected to the anode of the Zener diode D and one end of the output capacitor C1 via the transistor Mp1 described later. The source of the transistor Mn2 is connected to the source of the transistor Mn1, and the gate is connected to the gate of the transistor Mn1.

[0032] Z1

[0033] When the bias current I BIAS is supplied to the output capacitor C1 by the current mirror circuit 16, the voltage across the output capacitor C1, that is, the voltage V HREG rises. When the voltage V HREG exceeds the Zener voltage V Z1 of the Zener diode D DZ the Zener diode D Z1 ​​​​conducts, and the voltage V HREG is clamped to the Zener voltage V DZ to generate a constant voltage. The high-side regulator 9 supplies the input voltage V IN to the output terminal VH, and outputs the output voltage (V IN - V HREG ) from the output terminal VL.

[0034] The current detection circuit 17 is a circuit that detects that current flows through the Zener diode D Z1 . The current detection circuit 17 includes a Zener diode D Z2 as a second Zener diode, a current mirror circuit 171, and a current detection unit 172. The Zener diode D Z2 is of the same type as the Zener diode D Z1 and has the same characteristics (the Zener voltage V DZ is the same). The cathode of the Zener diode D Z2 is connected to the cathode of the Zener diode D Z1 , and the anode is connected to the source of a transistor Mp2 described later.

[0035] When the Zener diode D Z1 conducts, the current mirror circuit 171 copies the bias current I Z1 flowing through the output capacitor C1 and the Zener diode D BIAS and flows it through the Zener diode D Z2 . When current flows through the Zener diode D Z1 due to this current mirror circuit 171, current also flows through the Zener diode D Z2 . The current mirror circuit 171 is composed of transistors Mp1 and Mp2. The transistors Mp1 and Mp2 are composed of P-channel field effect transistors. The drain of the transistor Mp1 is connected to the drain of the transistor Mn2, the source is connected to one end of the output capacitor C1 and the anode of the Zener diode D Z1 , and the gate is connected to the drain.

[0036] The drain of transistor Mp2 is connected to the ground via a current detection unit 172 described later, the source is connected to the anode of a Zener diode D Z2 and the gate is connected to the gate of transistor Mp1. The current detection unit 172 is provided between the drain of transistor Mp2 and the ground. When the current detection unit 172 detects that a current has flowed through the Zener diode D Z2 and the drain of transistor Mp2, it outputs a detection signal indicating that fact to a delay circuit 181.

[0037] When the current detection circuit 17 detects that a current has flowed through the Zener diode D Z2 and transistor Mp2, a cutoff circuit 18 cuts off the bias current I Z1 supplied from a current mirror circuit 16 to an output capacitor C1 and the Zener diode D BIAS . The cutoff circuit 18 includes a delay circuit 181 and a transistor Mn3. The delay circuit 181 is provided between the output terminal of the current detection unit 172 and the gate of the transistor Mn3. When a detection signal is input from the current detection unit 172, the delay circuit 181 outputs a signal of H level to the gate of the transistor Mn3 until a predetermined delay time (a certain period) elapses from the timing when the detection signal is input, turning on the transistor Mn3.

[0038] The transistor Mn3 is composed of an N-channel field effect transistor. The drain of the transistor Mn3 is connected to the drain of the transistor Mn1, the source is connected to the source of the transistor Mn1, and the gate is connected to the output terminal of the delay circuit 181.

[0039] Next, the operation of the above-described high-side regulator 9 will be described with reference to the time chart of FIG. 3. When the bias current I BIAS is supplied to the output capacitor C1 by the current mirror circuit 16, the voltage across the output capacitor C1, that is, the voltage V HREG increases (FIG. 3(A)). When the bias current I BIASWhile it is being supplied, a drain current flows through transistor Mp1 (Fig. 3(B)). Voltage V HREG is the Zener voltage V Z1 of Zener diode D DZ . When it exceeds the Zener voltage V Z1 of Zener diode D HREG , Zener diode D DZ conducts, and voltage V Z2 is clamped to the Zener voltage V DZ . At this time, since the voltage V HREG clamped to the Zener voltage V Z2 is applied across both ends of Zener diode D

[0040] When current detection unit 172 detects that current is flowing through Zener diode D Z2 and transistor Mp2, it outputs a detection signal to delay circuit 181. When a detection signal is input from current detection unit 172, delay circuit 181 outputs a gate signal of H level to the gate of transistor Mn3 until a predetermined delay time elapses from the timing when the detection signal is input (Fig. 3(D)). When transistor Mn3 is supplied with a gate signal of H level from delay circuit 181, it turns on and shorts the gate-source of transistor Mn1. As a result, the bias current I BIAS supplied to output capacitor C1 is cut off, and the drain currents of transistors Mp1 and Mp2 become 0 A (Fig. 3(B), (C)).

[0041] Even when the bias current I BIAS supplied to output capacitor C1 is cut off, voltage V HREG is maintained constant (= Zener voltage V DZ ) by the charge stored in output capacitor C1. When the delay time elapses and the H-level gate signal output from delay circuit 181 is cut off and an L-level signal is output to transistor Mn3, transistor Mn3 turns off, and current mirror circuit 16 supplies bias current I BIASis supplied, and a drain current flows through the transistor Mp1. At this time, if the voltage V HREG is maintained at the Zener voltage V DZ , when the transistor Mn3 is turned off, current flows through the Zener diodes D Z1 , D Z2 , a detection signal is output from the current detection unit 172, a gate signal of H level is supplied from the delay circuit 181, and the bias current I BIAS supplied to the output capacitor C1 is cut off.

[0042] According to the first embodiment described above, when the voltage across the output capacitor C1 reaches the Zener voltage V DZ and current flows through the Zener diode D Z1 , the bias current I Z1 supplied from the current mirror circuit 16 to the output capacitor C1 and the Zener diode D BIAS is cut off. Therefore, since the bias current I Z1 is not constantly supplied to the output capacitor C1 and the Zener diode D BIAS , power consumption can be reduced. Also, when the voltage across the output capacitor C1 has not reached the Zener voltage V DZ , since the bias current I BIAS is not cut off, a decrease in the drive ability of the high-side power MOS transistor M PW1 can be suppressed.

[0043] According to the first embodiment described above, the delay circuit 181 outputs a gate signal for cutting off the bias current I Z1 supplied to the output capacitor C1 and the Zener diode D Z1 to the transistor Mn3 only until a delay time elapses after current starts flowing through the Zener diode D BIAS . As a result, the cutting off and supply of the bias current I Z1 to the output capacitor C1 and the Zener diode D BIAS are not repeatedly performed at high speed, and further reduction in power consumption can be achieved.

[0044] (Second Embodiment) Next, the second embodiment will be described with reference to FIGS. 4 and 5. In FIGS. 4 and 5, parts equivalent to the DC / DC converter 1 and the high-side regulator 9 shown in FIGS. 1 and 2 already described in the first embodiment are denoted by the same reference numerals, and detailed descriptions thereof are omitted.

[0045] A significant difference between the DC / DC converter 1 of the first embodiment and the DC / DC converter 1B of the second embodiment is that, as shown in FIG. 4, the clock output from the oscillator 4 is input to the high-side regulator 9B.

[0046] A significant difference between the high-side regulator 9 of the first embodiment and the high-side regulator 9B of the second embodiment is the configuration of the cutoff circuit 18B. As shown in FIG. 5, the cutoff circuit 18B of the second embodiment is provided with a flip-flop circuit 182 instead of the delay circuit 181.

[0047] The flip-flop circuit 182 is provided between the output terminal of the current detection unit 172 and the gate of the transistor Mn3. Also, the clock output from the oscillator 4 is input to the flip-flop circuit 182. The flip-flop circuit 182 outputs an H-level signal to the gate of the transistor Mn3 until the clock rises after the detection signal is input from the current detection unit 172.

[0048] Next, the operation of the high-side regulator 9B described above will be described below with reference to the time chart of FIG. 6. Similar to the first embodiment, when the bias current I BIAS is supplied to the output capacitor C1 by the current mirror circuit 16, the voltage across the output capacitor C1, that is, the voltage V HREG increases (FIG. 6(A)). While the bias current I BIAS is being supplied to the output capacitor C1, a drain current flows through the transistor Mp1 (FIG. 6(B)). The voltage V HREG is the Zener voltage V Z1 of the Zener diode D DZWhen it exceeds, Zener diode D Z1 conducts, and voltage V HREG is clamped to Zener voltage V DZ . At this time, the voltage V Z2 clamped to Zener voltage V DZ is applied across both ends of Zener diode D HREG , so Zener diode D Z2 conducts and a drain current flows through transistor Mp2 (Fig. 6(C)).

[0049] When current detection unit 172 detects that current has flowed through Zener diode D Z2 and transistor Mp2, it outputs a detection signal to flip-flop circuit 182. When a detection signal is input from current detection unit 172, flip-flop circuit 182 outputs a gate signal of H level to transistor Mn3 (Fig. 6(C), (E)) to turn on transistor Mn3. As a result, bias current I BIAS supplied to output capacitor C1 is cut off, and the drain currents of transistors Mp1 and Mp2 become 0 A (Fig. 6(B), (C)).

[0050] After flip-flop circuit 182 outputs a gate signal of H level, it cuts off the gate signal of H level at the timing when the clock rises to H level, and outputs a signal of L level to transistor Mn3 (Fig. 6(D), (E)). As a result, transistor Mn3 turns off, and bias current I BIAS is supplied to output capacitor C1 again by current mirror circuit 16.

[0051] At this time, if voltage V HREG is maintained at Zener voltage V DZ , when transistor Mn3 is turned off, current flows through Zener diodes D Z1 , D Z2 again, a detection signal is output from current detection unit 172, a gate signal of H level is supplied from flip-flop circuit 182, and bias current I BIAS supplied to output capacitor C1 is cut off by transistor Mn3.

[0052] According to the second embodiment described above, the flip-flop circuit 182 cuts off the bias current I supplied to the output capacitor C1 and the Zener diode D only during the period from when current flows through the Zener diode D until the clock rises. Since the period of the clock is the on / off period of the power MOS transistor M, the bias current I supplied to the output capacitor C1 and the Zener diode D can be cut off in accordance with the on / off period of the power MOS transistor M. As a result, it is possible to further reduce the power consumption while suppressing a decrease in the driving ability of the high-side power MOS transistor M. Z1 According to the second embodiment described above, the flip-flop circuit 182 cuts off the bias current I supplied to the output capacitor C1 and the Zener diode D only during the period from when current flows through the Zener diode D until the clock rises. Since the period of the clock is the on / off period of the power MOS transistor M, the bias current I supplied to the output capacitor C1 and the Zener diode D can be cut off in accordance with the on / off period of the power MOS transistor M. As a result, it is possible to further reduce the power consumption while suppressing a decrease in the driving ability of the high-side power MOS transistor M. Z1 supplied to the output capacitor C1 and the Zener diode D BIAS is cut off. Since the period of the clock is the on / off period of the power MOS transistor M, the bias current I supplied to the output capacitor C1 and the Zener diode D can be cut off in accordance with the on / off period of the power MOS transistor M. PWH of the power MOS transistor M, the bias current I supplied to the output capacitor C1 and the Zener diode D PW1 can be cut off in accordance with the on / off period of the power MOS transistor M. Z1 to the output capacitor C1 and the Zener diode D BIAS can be cut off. As a result, it is possible to further reduce the power consumption while suppressing a decrease in the driving ability of the high-side power MOS transistor M. PWH of the high-side power MOS transistor M.

[0053] Note that, according to the second embodiment described above, the flip-flop circuit 182 turns on the transistor Mn3 and cuts off the bias current I supplied to the output capacitor C1 and the Zener diode D from when the detection signal is input until the clock rises. However, the present invention is not limited to this. The flip-flop circuit 182 may be configured to turn on the transistor Mn3 from when the detection signal is input until the clock falls, and the same effect can be obtained by matching the on / off period of the power MOS transistor M. Z1 supplied to the output capacitor C1 and the Zener diode D BIAS is cut off. However, the present invention is not limited to this. The flip-flop circuit 182 may be configured to turn on the transistor Mn3 from when the detection signal is input until the clock falls, and the same effect can be obtained by matching the on / off period of the power MOS transistor M. PW1 of the power MOS transistor M.

[0054] (Third Embodiment) Next, the third embodiment will be described with reference to FIGS. 7 and 8. In FIGS. 7 and 8, the same reference numerals are given to the parts equivalent to the DC / DC converter 1 and the high-side regulator 9 shown in FIGS. 1 and 2 already described in the first embodiment, and the detailed description thereof is omitted.

[0055] A major difference between the DC / DC converter 1 of the first embodiment and the DC / DC converter 1C of the third embodiment is that, as shown in FIG. 7, a PWM signal output from the PWM control unit 3 is input to the high-side regulator 9C.

[0056] A major difference between the high-side regulator 9 of the first embodiment and the high-side regulator 9C of the third embodiment is the configuration of the cutoff circuit 18C, as shown in FIG. 8. The cutoff circuit 18C is different in that a flip-flop circuit 183 is provided instead of the delay circuit 181.

[0057] The flip-flop circuit 183 is provided between the output terminal of the current detection unit 172 and the gate of the transistor Mn3. Also, a PWM signal output from the PWM control unit 3 is input to the flip-flop circuit 183. The flip-flop circuit 183 outputs a signal of H level to the gate of the transistor M3 until the PWM signal rises after a detection signal is input from the current detection unit 172.

[0058] Next, the operation of the high-side regulator 9C described above will be described below with reference to the time chart of FIG. 9. Similar to the first embodiment, when the bias current I BIAS is supplied to the output capacitor C1 by the current mirror circuit 16, the voltage across the output capacitor C1, that is, the voltage V HREG increases (FIG. 9(A)). While the bias current I BIAS is being supplied to the output capacitor C1, a drain current flows through the transistor Mp1 (FIG. 9(B)). When the voltage V HREG exceeds the Zener voltage V Z1 of the Zener diode D DZ , the Zener diode D Z1 conducts, and the voltage V HREG is clamped to the Zener voltage V DZ . At this time, since the voltage V Z2 clamped to the Zener voltage V DZ is also applied across the Zener diode D HREG , the voltage V Z2Conducts, and a drain current flows through transistor Mp2 (Fig. 9(C)).

[0059] When current detection unit 172 detects that a current has flowed through Zener diode D Z2 and transistor Mp2, it outputs a detection signal to flip-flop circuit 183. When a detection signal is input to flip-flop circuit 183, it outputs a gate signal of H level to transistor Mn3 at the timing when the detection signal is input (Fig. 9(C), (E)), turning on transistor Mn3. As a result, bias current I BIAS supplied to output capacitor C1 is cut off, and the drain currents of transistors Mp1 and Mp2 become 0 A (Fig. 9(B), (C)).

[0060] Flip-flop circuit 183 cuts off the gate signal of H level at the timing when the PWM signal falls to L level after outputting the gate signal of H level, and outputs a signal of L level to transistor Mn3 (Fig. 9(D), (E)). As a result, transistor Mn3 turns off, and bias current I BIAS is supplied to output capacitor C1 again by current mirror circuit 16, and a drain current flows through transistor Mp1.

[0061] While the PWM signal is at L level, power MOS transistor M PWH is on, supplying current to coil L OUT1 , so voltage V HREG decreases. At this time, when voltage V HREG becomes less than Zener voltage V DZ , no current flows through Zener diodes D Z1 , D Z2 during the period when the PWM signal is at L level, and bias current I BIAS supplied to output capacitor C1 is not cut off. On the other hand, while the PWM signal is at H level, power MOS transistor M PWH is off and power MOS transistor M PWL is on, so voltage V HREG increases. Thereafter, voltage VHREG when it reaches the Zener voltage V DZ the Zener diode D Z1 D Z2 conducts current, and again, the transistor Mn3 turns on, and the bias current I BIAS supplied to the output capacitor C1 is cut off, and this is repeated.

[0062] According to the above-described third embodiment, the flip-flop circuit 183 outputs a gate signal to the transistor Mn3 that cuts off the bias current I Z1 supplied to the output capacitor C1 and the Zener diode D only during the period from when current starts flowing through the Zener diode D PWH until the power MOS transistor M Z1 switches from off to on. Therefore, when the power MOS transistor M BIAS turns on and supplies current to the coil L PWH the bias current I OUT1 is not cut off, and when the power MOS transistor M BIAS turns off, the bias current I PWH can be cut off. As a result, it is possible to further suppress a decrease in the drive ability of the high-side power MOS transistor M BIAS . PWH Also, in the DC / DC converter, when the load connected to the output terminal OUT is a light load, the PWM signal output by the PWM control unit 3 causes the power MOS transistor M PWH to have a shorter on time with respect to the period of the PWM signal and a longer off time. Therefore, in the DC / DC converter 1C of the third embodiment, when the load connected to the output terminal OUT is a light load, the time during which the bias current I BIAS is cut off becomes longer, and it is possible to significantly suppress the current consumption of the high-side regulator 9C per PWM signal cycle. That is, with respect to the driving ability of the power MOS transistor M PWH the high-side regulator 9C can operate with an appropriate current consumption.

[0063] Note that the present invention is not limited to the above-described embodiments, and can be appropriately modified, improved, etc. In addition, the material, shape, dimensions, number, arrangement location, etc. of each component in the above-described embodiments are arbitrary as long as the present invention can be achieved, and are not limited.

[0064] According to the above-described embodiment, a delay circuit 181, flip-flop circuits 182 and 183 are provided between the current detection unit and the transistor Mn3, but it is not limited to this. The current detection unit 172 and the transistor Mn3 may be directly connected so that the transistor Mn3 is turned on when a current flows through the Zener diode D Z1 to cut off the bias current I Z1 supplied to the output capacitor C1 and the Zener diode D BIAS .

[0065] According to the above-described embodiment, the error signal used in the PWM control unit 3 is the difference between the detection voltage V OUT corresponding to the output voltage V OUTS and the reference value, but it is not limited to this. The error signal may be the difference between the output current flowing from the output terminal OUT to the load and the reference value.

Explanation of Reference Numerals

[0066] 1, 1B, 1C DC / DC converters 2 Control IC (control circuit) 3 PWM control unit 4 Oscillator 9, 9B, 9C High-side regulators 16 Current mirror circuit (current supply circuit) 17 Current detection circuit 18 Cut-off circuit 171 Current mirror circuit 172 Current detection unit C1 Output capacitor D Z1 Zener diode (first Zener diode) D Z2 Zener diode (second Zener diode) L OUT1 Coil M PWH High-side power MOS transistor V IN Input voltage

Claims

1. A coil, a high-side MOS transistor provided between an input voltage source and the coil for supplying the input voltage of the input voltage source to the coil, and a control circuit for controlling on / off of the high-side MOS transistor to convert the input voltage, in a DC / DC converter having a high-side regulator which is a power supply circuit for on / off driving the high-side MOS transistor by the control circuit, wherein the high-side regulator includes an output capacitor, a first Zener diode connected in parallel with the output capacitor, a current supply circuit provided on the low side of the output capacitor and the first Zener diode for supplying current to the output capacitor and the first Zener diode, a current detection circuit for detecting that current has flowed through the first Zener diode, and a cutoff circuit for cutting off the current supplied from the current supply circuit to the output capacitor and the first Zener diode when the current detection circuit detects that current has flowed through the first Zener diode. DC / DC converter.

2. In the DC / DC converter according to Claim 1, the cutoff circuit cuts off the current only for a certain period from the timing when the current detection circuit detects that current has flowed through the first Zener diode. DC / DC converter.

3. In the DC / DC converter according to Claim 1, the control circuit includes an oscillator for outputting a clock, and a PWM control unit for outputting a PWM signal of duty based on comparison between a slope signal synchronized with the clock and an error signal indicating a difference between the output voltage or output current of the DC / DC converter and a reference value, wherein on / off of the high-side MOS transistor is controlled according to the PWM signal, and the cutoff circuit cuts off the current only from when the current detection circuit detects that current has flowed through the first Zener diode until the clock rises or falls. DC / DC converter.

4. In the DC / DC converter according to Claim 1, the cutoff circuit cuts off the current only from when the current detection circuit detects that current has flowed through the first Zener diode until the high-side MOS transistor switches from off to on. DC / DC converter.

5. In the DC / DC converter according to any one of Claims 1 to 4, the current detection circuit includes a second Zener diode having a cathode connected to the cathode of the first Zener diode, a current mirror circuit that copies the current flowing through the output capacitor and the first Zener diode and flows it through the second Zener diode, and a current detection unit that detects that the second Zener diode has conducted and current has flowed through the second Zener diode by the current mirror circuit. A DC / DC converter.

6. A high-side regulator which is a power supply circuit for on / off driving a high-side MOS transistor provided between an input voltage source of a DC / DC converter and a coil, an output capacitor, a first Zener diode connected in parallel with the output capacitor, a current supply circuit provided on the low-side of the output capacitor and the first Zener diode for supplying current to the output capacitor and the first Zener diode, a current detection circuit for detecting that current has flowed through the first Zener diode, and a cutoff circuit for cutting off the current supplied from the current supply circuit to the output capacitor and the first Zener diode when the current detection circuit detects that current has flowed through the first Zener diode. A high-side regulator.

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