Optimization Method for Flash Memory Chip and Related Device

Abstract

An embodiment of the present application provides a method and related device for optimizing a flash memory chip. According to the method, some channels in a non-volatile flash interface NFI bus of a flash memory chip may be suspended in a service execution process of the flash memory chip: the optimization target channel that needs to be optimized is determined from the suspended channels; the optimization parameters of each optimization target channel are determined based on the training data of each optimization target channel; each optimization target channel is optimized based on the optimization parameters of each optimization target channel. In the above technical solution, some channels in the NFI bus can be optimized in a normal execution process of the flash memory chip. In other words, other channels can maintain a normal working state. In this way, the NFI bus channel can be optimized without disk disconnection.

Description

Technical Field

[0001] This application claims priority to Chinese Patent Application No. 202110220794.2, filed with the China National Intellectual Property Administration on February 26, 2021, entitled "METHOD FOR OPTIMIZING FLASH MEMORY CHIP AND RELATED APPARATUS", which is incorporated herein by reference in its entirety.

[0002] This application relates to the field of memory technologies, and in particular, to a method for optimizing a flash memory chip and related apparatus.

Background Art

[0003] A flash memory chip with high read / write (I / O) Rate usually provides a better user experience for users. Increasing the bus rate of the non-volatile flash interface (N FI) is an effective way to improve the I / O rate. However, when the bus rate of the NFI increases, the ideal data width decreases accordingly. As a result, the reliability of the bus link is reduced, and data loss such as faults are caused.

[0004] A solution to a single-bit error in a single channel on the NFI bus is to retransmit the data of the channel where the bit error occurred. However, when the number of NFI bus channels increases, the probability of a single-bit error increases accordingly. In addition, data retransmission major affects the read and write performance of the flash memory chip and degrades the user experience.

Summary of the Invention

Means for Solving the Problems

[0005] Embodiments of the present application provide a method for optimizing a flash memory chip and related devices so that some channels in the NFI bus can be optimized without disk disconnection.

[0006] According to a first aspect, an embodiment of the present application provides a method for optimizing a flash memory chip. The method includes, in a service execution process of the flash memory chip, pausing N channels in a non-volatile flash interface NFI bus of the flash memory chip, where N is an integer greater than or equal to 1 and less than or equal to the total number of channels in the NFI bus; determining at least one channel to be optimized from the N channels; determining optimization parameters for each channel to be optimized based on training data of each channel to be optimized in at least one channel to be optimized; and optimizing each channel to be optimized based on the optimization parameters of each channel to be optimized.

[0007] In the above technical solution, some channels in the NFI bus can be optimized in the normal execution process of the flash memory chip. In other words, other channels can maintain the normal operating state. In this way, the NFI bus channels can be optimized without disk disconnection.

[0008] Referring to the first aspect, in a possible implementation form of the first aspect, the step of determining at least one channel to be optimized from the N channels is to perform a margin test on the nth channel to obtain the margin of the nth channel among the N channels, where n is an integer from 1 to N in sequence. (including 1 and N)a step of determining whether the margin of the n-th channel satisfies a margin condition, the margin condition including at least one of a timing margin condition and a voltage margin condition; and a step of determining that the n-th channel belongs to an optimization target channel if the margin of the n-th channel does not satisfy the margin condition.

[0009] In the above technical solution, in order to prepare for subsequent optimization, the channel that needs to be optimized may be determined.

[0010] Referring to the first aspect, in a possible implementation form of the first aspect, the optimization parameters include a read optimization voltage and a write optimization voltage, the training data of each optimization target channel includes K read margins and K write margins of each optimization target channel, K is a positive integer greater than 1; and based on the training data of each optimization target channel within at least one optimization target channel, the step of determining the optimization parameters of each optimization target channel includes determining the average value of the K read margins as the read optimization voltage; and determining the average value of the K write margins as the write optimization voltage.

[0011] The read reference voltage of the channel may be optimized using the determined read optimization parameter. Correspondingly, the write reference voltage of the channel may be optimized using the determined write optimization parameter. By optimizing the read reference voltage and the write reference voltage, the probability of error in the transmission between the flash memory controller and the NAND flash chip can be reduced, and the storage performance can be improved.

[0012] Referring to the first aspect, in a possible implementation form of the first aspect, the K read margins are K read timing margins, the K write margins are K write timing margins, the K read timing margins correspond one-to-one with K voltage levels, and the K write timing margins correspond one-to-one with K voltage levels; the read optimization voltage is determined by the following formula in accordance with determined: [Number] (wherein, Vrx_best represents the read optimization voltage, Vk represents the k-th voltage level among the K voltage levels, Trx1 represents the k-th read timing margin among the K read timing margins, and k = 1,..., K); and the write optimization voltage is determined by the following formula in accordance with determined: [Number] (wherein, Vtx_best represents the write optimization voltage, Vk represents the k-th voltage level among the K voltage levels, and Ttx1 represents the k-th write timing margin among the K write timing margins).

[0013] Referring to the first aspect, in a possible implementation form of the first aspect, the K read margins are K read voltage margins, the K write margins are K write voltage margins, the K read voltage margins correspond one-to-one with K data strobe signal DQS delay levels, the K write voltage margins correspond one-to-one with K DQS delay levels; the read optimization voltage is the arithmetic mean value of the K read voltage margins; and the write optimization voltage is the arithmetic mean value of the K write voltage margins.

[0014] Referring to the first aspect, in a possible implementation of the first aspect, the optimization parameters include read optimization DQS timing optimization parameters and write optimization DQS timing optimization parameters. The training data for each channel to be optimized includes read direction training data and write direction training data. And the step of determining the optimization parameters for each channel to be optimized based on the training data of each channel to be optimized in at least one channel to be optimized includes: a step of determining read optimization DQS timing optimization parameters based on read direction training data, where the read direction training data includes a left boundary and a right boundary obtained by read direction timing training, and the read optimization DQS timing optimization parameters are used to adjust the delay line of DQS to a first center position, and the first center position is the average value of the left boundary and the right boundary obtained by read direction timing training; and a step of determining write optimization DQS timing optimization parameters based on write direction training data, where the write direction training data includes a left boundary and a right boundary obtained by write direction timing training, and the write optimization DQS timing optimization parameters are used to adjust the delay line of DQS to a second center position, and the second center position is the average value of the left boundary and the right boundary obtained by write direction timing training.

[0015] In the above solution, in order to enable the effective width of the timing margin of the signal at the receiving end to be maximized and the setup time margin and hold time margin to be maximized, the timing margin can be optimized by adjusting the position of the delay line of the DQS signal, thereby meeting the specification requirements and avoiding data loss caused by bit errors during data read / write.

[0016] According to a second aspect, an embodiment of the present application provides an electronic device. The electronic device includes a unit configured to implement any one of the first aspect or a possible implementation of the first aspect.

[0017] According to a third aspect, an embodiment of the present application provides a solid state disk including an SSD controller. The SSD controller is coupled to a flash memory via a non-volatile flash interface bus, and the SSD controller is further configured to be coupled to a memory and read and execute instructions and / or program codes in the memory in order to implement any one of the first aspect or possible implementation forms of the first aspect.

[0018] According to a fourth aspect, an embodiment of the present application provides a chip system. The chip system includes a logic circuit, and the logic circuit is coupled to an input / output interface and configured to transmit data via the input / output interface in order to implement any one of the first aspect or possible implementation forms of the first aspect.

[0019] According to a fifth aspect, an embodiment of the present application provides a computer-readable storage medium. The computer-readable storage medium stores program codes, and when the computer storage medium is executed on a computer, the computer is enabled to implement any one of the first aspect or possible implementation forms of the first aspect.

[0020] According to a sixth aspect, an embodiment of the present application provides a computer program product. The computer program product includes computer program codes, and when the computer program codes are executed on a computer, the computer is enabled to implement any one of the first aspect or possible implementation forms of the first aspect.

Brief Description of the Drawings

[0021]

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Embodiments for Carrying Out the Invention

[0022] Hereinafter, the technical solution of the present application will be described with reference to the accompanying drawings.

[0023] In this application, "at least one" means one or more, and "a plurality of" means two or more. The term "and / or" describes the relationship for explaining related objects and indicates that three relationships can exist. For example, A and / or B represents the following three cases: namely, the case where only A exists, the case where both A and B exist, and the case where only B exists. Each of A and B may be singular or plural. The character " / " generally indicates the "or" relationship between the associated objects. At least one of the following (elements) or a similar expression refers to any combination of these, including any combination of singular (elements) or plural (elements). For example, at least one of a, b, or c may indicate a, b, c, a - b, a - c, b - c, or a - b - c, and a, b, and c may be singular or plural.

[0024] To help those skilled in the art better understand the technical solution of this application, the application scenarios and some related concepts included in the technical solution of this application will be described first.

[0025] FIG. 1 is a schematic diagram of a possible application scenario according to an embodiment of this application. As shown in FIG. 1, a solid state disk (S SD) 100 includes an SSD controller 110 and a NAND flash memory Li 1 30.

[0026] The SSD controller 110 includes a host interface controller 111, a processor 112, and a flash memory controller 113. The host interface controller 111, the processor 112, and the flash memory controller 113 are connected via a bus 114. In addition to the host interface controller 111, the processor 112, and the flash memory controller 113 shown in FIG. 1, the SSD controller may include other modules, such as a cache controller and an error correction code (EIt should be understood that it may further include a CC) module.

[0027] Host interface control RA is , which may be called the front end. The front end is the communication for interface between the host and the SSD. Commands and data are transmitted between the host and the SSD via the front-end bus. The host may be a computer, a mobile phone, a base station, a trip computer (which may also be called an electronic control unit (E CU)), etc. The front-end interface may be a high-speed serial Peripheral Component Interconnect (P CIe) interface, a mini-serial advanced technology attachment (m SATA) interface, an M.2 (or what is called the next-generation form factor (N GFF)), or another user-defined interface.

[0028] Processor 112 may include one or more central processing units (C PU) cores. Processor 112 is responsible for functions such as computing and system scheduling. In addition to the CPU core, processor 112 may further have some peripheral modules, such as a general-purpose asynchronous receiver / transmitter Machine (U ART), general-purpose input / output Force( GPIO) module, a temperature sensor, and a timer.

[0029] Flash memory controller 113 is responsible for managing the writing of data to NAND flash 130 or the reading of data from NAND flash 130. Flash memory controller 113 is connected to NAND flash 130 via NFI bus 120.

[0030] Hereinafter, with reference to FIG. 2, flash memory controller 113 will be described.

[0031] FIG. 2 is a schematic diagram of a flash memory controller and a NAND flash chip. The NAND flash 130 shown in FIG. 1 includes a plurality of NAND flash chips. The NAND flash chip 131 shown in FIG. 2 may be any one of the plurality of NAND flash chips included in the NAND flash 130.

[0032] As shown in FIG. 2, the flash memory controller 113 is connected to the NAND flash chip 131 via the NFI bus 120. The NFI bus 120 includes a plurality of data signal lines (e.g., data signal lines L0 to L7 in FIG. 2) and a plurality of timings Signal line (e.g., timing signal lines LS-P and LS-N in FIG. 1).

[0033] The data signal lines L0 to L7 may transmit eight data signals (D Q) in parallel. For example, the data signal line L0 may transmit DQ0, the data signal line L1 may transmit DQ1, …, and the data signal line L7 may transmit DQ7. It should be understood that DQ is a periodic digital signal and can therefore carry data. For example, DQ may transmit TO's one bit of data in one cycle. In a low electrical level cycle, one bit of data "0" may be transmitted, and in a high electrical level cycle, one bit of data "1" may be transmitted. The data signal lines L0 to L7 may transmit eight DQs in parallel. Therefore, in one cycle, a total of eight bits of data are transmitted via the data signal lines L0 to L7.

[0034] Since DQ is a digital signal, it should be understood that the receiving end of DQ needs to correctly distinguish the cycle of DQ through a clock signal having the same cycle as DQ in order to correctly identify the electrical level state of DQ and correctly obtain the data carried by DQ. Considering this, the NFI bus 120 may further include a timing signal line LS-N and a timing signal line LS-P. The timing signal line LS-N and the timing signal line LS-P may transmit a data strobe signal (D QS).

[0035] Specifically, the timing signal line LS-N may transmit DQS-N, and the timing signal line LS-P may transmit DQS-P. DQS-N and DQS-P are phase-inverted signals. For example, DQS-N and DQS-P may be shown in FIG. 3. DQS includes DQS-N and DQS-P. DQS may be used as a clock signal corresponding to DQ, have the same transmission end and receiving end as DQ, and trigger the receiving end of DQ to identify the electrical level state of DQ. For ease of explanation, in this embodiment of the present application, DQS is used to represent DQS-N and DQS-P.

[0036] It should be noted that the bidirectional data transmission between the flash memory controller 113 and the NAND flash chip 131 may be implemented via the NFI bus 120. For example, in the process of the flash memory controller 113 writing data to the NAND flash chip 131, the flash memory controller 113 may be used as the transmission end of DQS and DQ, and the NAND flash chip 131 may be used as the receiving end of DQS and DQ. In the process of the flash memory controller 113 reading data from the NAND flash chip 131, the NAND flash chip 131 may be used as the transmission end of DQS and DQ, and the flash memory controller 113 may be used as the receiving end of DQS and DQ.

[0037] For ease of explanation, in the following embodiments of the present application, write DQ and write DQS are respectively used to represent DQ and DQS transmitted by the flash memory controller 113 to the NAND flash chip 131 in the process of the flash memory controller 113 writing data to the NAND flash chip 131; read DQ and read DQS are respectively used to represent DQ and DQS transmitted by the NAND flash chip 131 to the flash memory controller 113 in the process of the flash memory controller 113 reading data from the NAND flash chip 131. Write DQ includes write DQ0 to write DQ7, and read DQ includes read DQ0 to read DQ7.

[0038] In the following, the specific implementation forms of data writing and data reading will be described separately.

[0039] Scenario 1: The flash memory controller 113 writes data to the NAND flash chip 131.

[0040] The processor 110 may call the flash memory controller 113 to write data to the NAND flash chip 131. For the specific implementation form of calling the flash memory controller 113 by the processor 110, please refer to the prior art. This is not limited in this embodiment of the present application.

[0041] When called by the processor 112, the flash memory controller 113 may write data to the NAND flash chip 131. Specifically, the flash memory controller 113 may transmit write DQ0 to write DQ7 to the NAND flash chip 131 via the data signal lines L0 to L7. The write DQ0 to write DQ7 transmitted by the flash memory controller 113 may carry the target write data that needs to be written to the NAND flash chip 131.

[0042] In the process of the flash memory controller 113 writing data to the NAND flash chip 131, the flash memory controller 113 further transmits write DQS to the NAND flash chip 131. The write DQS may trigger the NAND flash chip 131 to identify the electrical level states of write DQ0 to write DQ7. The NAND flash chip 131 may store the data carried by write DQ0 to write DQ7 based on the identified electrical level states, thereby implementing the writing of data to the NAND flash chip 131.

[0043] Generally, in the write DQS transmitted by the flash memory controller 113 to the NAND flash chip 131, the crossover point (shown in Figure 3) between write DQS-N and write DQS-P may be used as a trigger point for triggering the NAND flash chip 131 to identify the electrical level states of the write DQs. That is, when the NAND flash chip 131 determines that the received write DQS is at the crossover point, the NAND flash chip 131 may identify the current electrical level states of write DQ0 to write DQ7, whereby the target write data carried by write DQ0 to write DQ7 may be written to the NAND flash chip 131.

[0044] For example, when the target write data is 11010011 and corresponds to the same cross point in the write DQS, in this case, the data carried by write DQ0 to write DQ7 is as follows: write DQ0 may carry "1", write DQ1 may carry "1", write DQ2 may carry "0", write DQ3 may carry "1", write DQ4 may carry "0", write DQ5 may carry "0", write DQ6 may carry "1", and write DQ7 may carry "1".

[0045] When it is determined that the received write DQS is at the cross point, the NAND flash chip 131 may identify the received electrical level states of write DQ0 to write DQ7. In the above example, write DQ0 is at a high electrical level (carrying "1"), write DQ1 is at a high electrical level (carrying "1"), write DQ2 is at a low electrical level (carrying "0"), write DQ3 is at a high electrical level (carrying "1"), write DQ4 is at a low electrical level (carrying "0"), write DQ5 is at a low electrical level (carrying "0"), write DQ6 is at a high electrical level (carrying "1"), and write DQ7 is at a high electrical level (carrying "1"). The NAND flash chip 131 may store the target write data "11010011" based on the identified electrical level states of write DQ0 to write DQ7.

[0046] Scenario 2: The flash memory controller 113 reads data from the NAND flash chip 131.

[0047] The processor 110 may call the flash memory controller 113 to read data from the NAND flash chip 131. For the specific implementation form of calling the flash memory controller 113 by the processor 110, please refer to the prior art. This is not limited in this embodiment of the present application.

[0048] The flash memory controller 113 may be called by the processor 110 to instruct the NAND flash chip 131 to send the target read data to the flash memory controller 113. Thereby, the flash memory controller 113 reads the target read data in the NAND flash chip 131. For the specific implementation form of instructing the NAND flash chip 131 by the flash memory controller 113, please refer to the prior art. This is not limited in this embodiment of the present application.

[0049] The NAND flash chip 131 may send read DQ0 to read DQ7 to the flash memory controller 113 via the data signal lines L0 to L7. Read DQ0 to read DQ7 may carry the target read data sent to the flash memory controller 113. When the NAND flash chip 131 sends read DQ0 to read DQ7 to the flash memory controller 113, the NAND flash chip 131 further sends read DQS to the flash memory controller 113. The flash memory controller 113 may identify the electrical level states of read DQ0 to read DQ7 based on read DQS, and based on the identified electrical level states, obtain the target read data carried by read DQ0 to read DQ7, and read the data from the NAND flash chip 131.

[0050] The specific implementation forms of the read DQS and read DQ0 to read DQ7 are the same as those in the aforementioned Scenario 1. Details will not be described again here. The difference is that in the read DQS transmitted by the NAND flash chip 131 to the flash memory controller 113, the intermediate point between two adjacent cross points can generally be used as a trigger point to trigger the flash memory controller 113 for identifying the electrical level states of read DQ0 to read DQ7. In other words, when the NAND flash chip 131 determines that the received read DQS is at the intermediate point, the flash memory controller 113 may identify the current electrical level states of read DQ0 to read DQ7 and obtain the target read data carried by read DQ0 to read DQ7.

[0051] From the aforementioned Scenario 1 and the aforementioned Scenario 2, it can be learned that whether data can be accurately transmitted between the flash memory controller 113 and the NAND flash chip 131 is closely related to whether the relative timing positions of DQS and DQ transmitted in the same direction are aligned. DQS and DQ transmitted in the same direction may be understood as read DQS and read DQ, or may be understood as write DQS and write DQ.

[0052] The write DQS and write DQ shown in FIG. 3 are used as an example. The write DQ may be any one of write DQ0 to write DQ7. The cross point of the write DQS is used as a trigger point, and the cycle of the write DQ corresponding to the cross point becomes the write DQ cycle within which the time when the cross point occurs falls. As can be learned from FIG. 3, the trigger point (cross point) of the write DQS may divide the cycle of the write DQ corresponding to the trigger point into two parts. The part before the trigger point is the setup During programming interval, and the part after the trigger point is the hold During dopingThere is a time interval. Assume that the start time of any write DQ cycle received by the NAND flash chip 131 is t1, the end time of the write DQ cycle is t2, and between t1 and t2, the time when the write DQS received by the NAND flash chip 131 becomes the trigger point is t0. In this case, the period between t1 and t0 may be called the setup time, and the period between t0 and t2 may be called the hold time.

[0053] The setup time of the write DQ is sufficient. This helps to improve the accuracy of data transmission. Specifically, since the write DQ is a digital signal, the electrical level state of the write DQ is usually variable, that is, the write DQ can be at a low electrical level or a high electrical level in any cycle. Between two adjacent cycles, the electrical level state of the write DQ may remain unchanged, or may change from a low electrical level to a high electrical level, or may change from a high electrical level to a low electrical level.

[0054] Generally, the high electrical level and the low electrical level are relative to the reference voltage. That is, when the electrical level of the write DQ is lower than the reference voltage, the write DQ is at a low electrical level; or when the electrical level of the write DQ is higher than the reference voltage, the write DQ is at a high electrical level. When the electrical level state of the write DQ changes, a specific delay usually takes to complete the switching of the electrical level state. For example, as shown in Figure 3, at tmin and tmax, the electrical level of the write DQ reaches the reference voltage.

[0055] An example where the low electrical level of the previous cycle is switched to the high electrical level in the current cycle is used. If the setup time is insufficient, for example, when t0 is between t1 and tmin, the electrical level of the write DQ at t0 may not fully rise to a high electrical level greater than the reference voltage. In this case, the NAND flash chip 131 may erroneously consider that the write DQ is at a low electrical level in the current cycle. That is, the write DQ in the current cycle should be at a high electrical level, but since t0 is between t1 and tmin and the electrical level does not fully rise to be greater than the reference voltage, it is erroneously identified as a low electrical level. As a result, an error occurs in the data written to the NAND flash chip 131. Therefore, in order to ensure the accuracy of data transmission between the flash memory controller 113 and the NAND flash chip 131, it is necessary to ensure that the setup time is long enough. High level Since it does not fully rise to be greater than the reference voltage, it is erroneously identified as a low electrical level. As a result, an error occurs in the data written to the NAND flash chip 131. Therefore, in order to ensure the accuracy of data transmission between the flash memory controller 113 and the NAND flash chip 131, it is necessary to ensure that the setup time is long enough.

[0056] The hold time of the write DQ is sufficient. This also helps to improve the accuracy of data transmission. Specifically, the NAND flash chip 131 requires a specific delay to identify the electrical level state of the write DQ. For example, the high electrical level of the current cycle is switched to the low electrical level in the next cycle. At t0, the NAND flash chip 131 starts to identify the electrical level state of the write DQ. If the hold time is insufficient, for example, when t0 is between tmax and t2, when the NAND flash chip 131 identifies the electrical level state of the write DQ, the electrical level of the write DQ may be lower than the reference voltage (the write DQ is at a low electrical level in the next cycle), thereby causing the NAND flash chip 131 to misidentify the electrical level of the current cycle as a low electrical level, and an error occurs in the data written to the NAND flash chip 131. In other words, the electrical level of the write DQ in the current cycle must be at a high electrical level, but since t0 is between tmax and t2 and the electrical level is lower than the reference voltage, it is misinterpreted as a low electrical level. Therefore, to ensure the accuracy of data transmission between the flash memory controller 113 and the NAND flash chip 131, it is necessary to ensure that the hold time is long enough.

[0057] In conclusion, to improve the accuracy of data transmission between the flash memory controller 113 and the NAND flash chip 131, both the hold time and the setup time of the write DQ need to have a relatively long duration. If the duration of the hold time or the setup time of the write DQ is insufficient, the accuracy of data transmission between the flash memory controller 113 and the NAND flash chip 131 is reduced, and the bit error rate increases.

[0058] Generally, the reference voltage in the flash memory controller 113 is the same as the reference voltage in the NAND flash chip 131. That is, regarding the write DQS and write DQ shown in FIG. 3, the time interval between tmin and t1 may be called the minimum setup time applicable to the NAND flash chip 131, and the time interval between tmax and t2 is Flash memory chip To programming sometimes called the minimum hold time applicable.

[0059] In the cycle of write DQ, the difference between the setup time of write DQS and the minimum setup time applicable to the NAND flash chip 131 may be called the timing margin of the setup time of write DQ, and the difference between the hold time of write DQS and the minimum hold time applicable to the NAND flash chip 131 may be called the timing margin of the hold time of write DQ. The minimum value of the timing margin of the setup time of write DQ and the timing margin of the hold time may be understood as the timing margin of write DQ. For example, in FIG. 3, the timing margin of write DQ is the minimum value of the difference between t1 and tmin and the difference between tmax and t2.

[0060] Generally, the time interval between tmin and tmax is mainly determined by the performance of the NAND flash chip 131. In other words, for the flash memory controller 113, the setup time requirement and hold time requirement of the chip are determined by the performance of the chip and cannot be adjusted. The timing margin may be adjusted to an optimal value by timing training. Through timing training, the flash memory controller 113 can adjust the time point t0 corresponding to the cross point of the write DQS to an intermediate position between tmin and tmax, that is, a position where the timing margin of the setup time of the write DQ is equal to the timing margin of the hold time. Therefore, the timing margin of the write DQ may be enabled to reach the maximum value, and from the perspective of the timing margin, the accuracy of data transmission from the flash memory controller 113 to the NAND flash chip 131 can be optimized.

[0061] For the same reason, in the process of the flash memory controller 113 reading data from the NAND flash chip 131, the difference between the hold time of the read DQ transmitted by the NAND flash chip 131 to the flash memory controller 113 and the minimum hold time applicable to the flash memory controller 113 may be referred to as the timing margin of the hold time of the read DQ. The difference between the setup time of the read DQ and the minimum setup time applicable to the flash memory controller 113 may also be referred to as the timing margin of the setup time of the read DQ. The timing margin of the read DQ may be understood as the minimum value of the timing margin of the hold time of the read DQ and the timing margin of the setup time. When the timing margin of the hold time of the read DQ transmitted by the NAND flash chip 131 to the flash memory controller 113 is equal to the timing margin of the setup time, the timing margin of the read DQ may be made to reach the maximum value. In this case, the accuracy of data transmission from the NAND flash chip 131 to the flash memory controller 113 can be optimized from the perspective of the timing margin.

[0062] To improve the timing margins of the read DQ and the write DQ and improve the accuracy of data transmission between the flash memory controller 113 and the NAND flash chip 131, the relative timing positions of the DQ and the DQS transmitted in the same direction usually need to be aligned. This process is often also called memory training.

[0063] In this embodiment of the present application, "aligned" means that in DQS and DQ transmitted in the same direction, the timing margin of the hold time of DQ is equal to the timing margin of the setup time, or the timing margin of the hold time of DQ does not differ significantly from the timing margin of the setup time, whereby it can be understood that DQ has a relatively sufficient timing margin for the hold time and a relatively sufficient timing margin for the setup time. The timing margin of the setup time of DQ is with respect to the minimum setup time applicable to the receiving end, and similarly, the timing margin of the hold time of DQ is with respect to the minimum hold time applicable to the receiving end. That is, "aligned" may enable the setup time of DQ to be equal to or greater than the minimum setup time applicable to the receiving end, and enable the hold time of DQ to be equal to or greater than the minimum hold time applicable to the receiving end.

[0064] The receiving end may be the NAND flash chip 131 or the flash memory controller 113. The minimum setup time and the minimum hold time applicable to the receiving end can be obtained based on factors such as the structure and performance of the receiving end. If the setup time of DQ is less than the minimum setup time applicable to the receiving end, or the hold time of DQ is less than the minimum hold time applicable to the receiving end, the receiving end cannot correctly identify the data carried by DQ.

[0065] In addition, the aforementioned high electrical level and low electrical level are determined by comparing with a reference voltage. As shown in FIG. 4, starting from t0, the write electrical level is higher than the write reference voltage Vref. In this case, the NAND flash chip 131 may determine that the write electrical level is at a high electrical level and determine that the written data is 1. Starting from t1, the write electrical level is lower than the write reference voltage Vref. In this case, the NAND flash chip 131 may determine that the write electrical level is at a low electrical level and determine that the written data is 0. Starting from t2, the write electrical level is higher than the write reference voltage Vref. In this case, the NAND flash chip 131 may determine that the write electrical level is at a high electrical level and determine that the written data is 1.

[0066] Assume that the write reference voltage Vref is greater than the maximum value of the write electrical level (i.e., V1 shown in FIG. 4), and the NAND flash chip 131 regards the write electrical level as a low electrical level. In this case, the NAND flash chip 131 determines that all the written data is 0. Alternatively, assume that the write reference voltage Vref is less than the minimum value of the write electrical level (i.e., V2 shown in FIG. 4), and the NAND flash chip 131 regards the write electrical level as a high electrical level. In this case, the NAND flash chip 131 determines that all the written data is 1.

[0067] The voltage margin in the write direction is the difference between the reference voltage and the write electrical level. As shown in FIG. 4, the difference between Vref and V2 is the voltage margin in the write direction.

[0068] For the same reason, in the process of the flash memory controller 113 reading data from the NAND flash chip 131, the difference between the reference voltage and the read electrical level becomes the voltage margin in the read direction.

[0069] FIG. 5 is a schematic diagram of a NAND flash chip in the electronic device shown in FIG. 1.

[0070] Flash memory is , NOR flash and NAND flash can be classified into. Compared with NOR flash, NANO flash has advantages such as large capacity, low price, and fast read / write speed, so it is widely applied. Currently, NAND flash is used in solid state disks (S SD), Secure Digital (S D) cards, add-in cards (A ID), etc. NAND flash may also be used as a storage medium in electronic devices such as mobile phones or tablet computers.

[0071] The structure of NAND flash can be divided into, in descending order, device Steps, target TOs, die Is, plane Ns, block Cs, page Js, and sector To loop can be divided.

[0072] The NAND flash chip 131 shown in FIG. 5 is a device. A device is a packaged NAND flash cell, and may also be called a packaged flash memory chip, NAND flash chip, etc. One storage device (e.g., SSD) may include one or more devices, and one device may include one or more targets. One target may include one or more dies. Js, Flash memory chip, NAND flash chip, etc. One storage device (for example, SSD) may include one or more devices, and one device may include one or more targets. One target may include one or more dies.

[0073] For example, the NAND flash chip 131 shown in FIG. 5 includes two targets, target 510 and target 520. Each target includes four dies. Target 510 includes dies 511, 512, 513, and 514, and target 520 includes dies 521, 522, 523, and 524.

[0074] A die may also be called a logical unit (L (UN). One die may include one or more planes. Each plane may include a large number of block pages, each block page may include a large number of page pages, and each page may include a large number of cells.

[0075] The number of channels in the flash memory Of loop directly reflects the simultaneous read / write ability of the solid-state disk. One channel may have one or more dies. Each device supports one or more channels.

[0076] For example, the NAND flash chip 131 shown in FIG. 5 further includes an input / output interface 501, channels 502, 503, 504, and 505. Channel 502 is connected to dies 511 and 512, channel 503 is connected to dies 513 and 514, channel 504 is connected to dies 521 and 522, and channel 505 is connected to dies 523 and 524.

[0077] The input / output interface 501 of the NAND flash chip 131 is connected to the flash memory controller via the NFI bus, receives commands from the flash memory controller, and based on the received commands, may perform operations such as reading data stored in the NAND flash chip 131, writing data to the NAND flash chip 131, and deleting data from the NAND flash chip 131. For example, if the read command received by the NAND flash chip 131 is to read the data stored in die 511, the data stored in die 511 may be read via the channel 502, and then the read data is transmitted to the flash memory controller. As another example, if the write command received by the NAND flash chip 131 is to write data to die 524, the data may be written to die 524 via the channel 505.

[0078] The data interface of the NAND flash chip is not limited in this embodiment of the present application and may be SDR, NV-DDR, NV-DDR2, or NV-DDR3.

[0079] The ideal data width of the NFI bus refers to the time occupied for single-time data transmission in an ideal transmission environment. An ideal transmission environment means that transmission losses are not considered during data transmission. For example, if the transmission rate of the NFI bus is 400×1 million times / second (M T / s), the time occupied by each time data transmission is ( 1 / 400×10 8 ) seconds, that is, the ideal data width corresponding to each time data transmission is 2.5 ns.

[0080] The ideal data width of the NFI bus is related to the performance, capacity, rate specifications, etc. of the flash memory chip. The transmission rate of the NFI bus is interrelated with the ideal data width of the NFI bus. Therefore, when the transmission rate of the NFI bus increases, the ideal data width of the NFI bus decreases accordingly. For example, when the transmission rate of the NFI bus is 400MT / s having the ideal data width of the NFI bus is 2.5ns; when the transmission rate of the NFI bus is 800MT / s having the ideal data width of the NFI bus is 1.25ns; when the transmission rate of the NFI bus is 1,200MT / s having the ideal data width of the NFI bus is 0.83ns; or when the transmission rate of the NFI bus is 1,600MT / s having the ideal data width of the NFI bus is 0.625ns.

[0081] As shown in Figure 3, the difference between t2 and t1 is the effective width of the data. The smaller the ideal data width of the NFI bus, the smaller the difference between t2 and t1. Correspondingly, the differences between t1 and tmin and between tmax and t2 also decrease accordingly. As a result, the timing margin becomes smaller. In addition, in the actual data transmission process, after the data transmitted by the transmission end at the ideal data width is attenuated through the transmission channel, the data width actually obtained by the receiving end is reduced. In this case, the NFI bus is more susceptible to external factors such as temperature and voltage. As a result, reliability problems occur in the NFI bus channel and data transmission problems occur. For example, bit errors occur during data transmission.

[0082] Hereinafter, the concepts of effective width and margin effective width are described.

[0083] The effective width may be defined as the signal width at which the data actually acquired by the receiving end after the ideal-width data at the transmitting end has been attenuated when passing through the transmission channel arrives at the receiving end. The margin effective width is the signal width at which, at the ideal signal width at the transmitting end, the preset data at the receiving end is correctly sampled after being transmitted. When compared with the effective width, the margin effective width removes the time remaining after the data setup time and the data hold time.

[0084] For example, when a total of n bits can be transmitted in a DQS cycle, for example, when the transmission rate is 400 Mbps, that is, 4×10^8 bits are transmitted per second, the time occupied for transmitting each bit is 1 s / (4×10^8) = 2.5 ns, that is, the ideal signal width corresponding to each bit is 2.5 ns. After the signal arrives at the receiving end via the transmission channel, the ideal signal width is reduced, and the effective signal width actually correctly received by the receiving end is 2 ns.

[0085] Here, bps is the bit rate TO's unit, and the bit rate is the rate at which a signal (represented by digital binary bits) is processed or transmitted by a system (device, radio wave or wire), that is, the amount of data processed or transmitted within a unit time. The unit is "bits per second" (bit / s or bps). The bit rate can be used to indicate the connection speed, transmission speed, channel capacity, maximum throughput, digital bandwidth capacity, etc. in the communication field. In this application, the bit rate can be used to indicate the bus rate for transmission between the controller and the NAND flash.

[0086] In addition, the "margin effective width" may sometimes be called the effective width of the timing margin. This is equivalent to the aforementioned "timing margin", and the difference is only that in this application, the concept of "margin effective width" is defined to measure the "timing margin". Here, "margin" can be translated into English as "margin",In this application, "margin" may refer to the "effective width of the margin". Therefore, unless otherwise specified, the timing margin in this embodiment of this application can be understood as the effective width of the timing margin.

[0087] One embodiment of this application provides a method for optimizing a flash memory chip. According to this method, in order to reduce the data transmission bit error rate and improve the reliability of the flash memory chip, the voltage margin and the timing margin are optimized in the service execution process of the flash memory chip.

[0088] The technical solution of this application can be applied to a device provided with a NAND flash chip, and the device is assumed to have the structure shown in FIG. 2. In other words, in addition to the SSD shown in FIG. 1, the basic solution of this application is other devices that communicate with the NAND flash chip via the NFI bus, such as an add-in card (A IC), Secure Digital card (S D card), and may also be applied to an electronic device (such as a mobile phone, a tablet computer, a digital camera, or an ECU) that uses the NAND flash chip as a storage medium.

[0089] FIG. 6 is a schematic flowchart of a method for optimizing a flash memory chip according to an embodiment of this application.

[0090] As shown in FIG. 6, after completing power-on initialization, timing training, and voltage training, the flash memory chip starts the service execution phase (i.e., it may perform operations such as reading data stored in the flash memory chip, writing data to the flash memory chip, deleting data from the flash memory chip, etc.). In the service execution process, it is determined whether the trigger condition is met; if the trigger condition is not met, monitoring continues; if the trigger condition is met, one or more channels of the flash memory chip are selected and paused; and the selected Channel die of the Loop-shaped channel changes to the idle state, and a margin test is performed on the selected channel to determine whether the margin of the selected channel meets the requirements. If the margin of the selected channel does not meet the requirements, the channel may be optimized; or, if the margin of the selected channel meets the requirements, it is determined whether a margin test has been performed on all channels of the flash memory chip. If the answer is "no", the margin test continues to be performed on the remaining channels; or, if the margin test has been performed on all channels, it continues to be monitored whether the trigger condition is met.

[0091] Hereinafter, with reference to the NAND flash chip 131 shown in FIG. 5, a schematic flowchart of a method for optimizing the flash memory chip according to this embodiment of the present application shown in FIG. 6 will be described.

[0092] It is assumed that the power of the NAND flash chip 131 is turned on at time t0, the power-on initialization is completed at time t1, and the timing training and voltage training are completed at time t2. In this case, from time t2, the NAND flash chip 131 may be regarded as being in the service execution phase. In other words, from time t2, a read / write operation may be performed on the NAND flash chip 131, or the data in the NAND flash chip 131 may be deleted.

[0093] In some embodiments, the operating environment data may be monitored, and it may be determined whether a trigger condition is satisfied based on the monitored operating environment data. The operating environment data may include temperature and / or humidity. The temperature monitoring may be implemented using a temperature sensor, and the humidity monitoring may be implemented using a humidity sensor.

[0094] For example, a temperature upper limit may be set. If the monitored temperature is greater than the temperature upper limit, it may be determined that the trigger condition is satisfied. As another example, a temperature upper limit and a temperature lower limit may be set. If the monitored temperature is greater than the temperature upper limit or less than the temperature lower limit, it may be determined that the trigger condition is satisfied.

[0095] As another example, a temperature upper limit and a humidity upper limit may be set. If both the monitored temperature and the monitored humidity simultaneously satisfy the corresponding upper limits (i.e., the temperature satisfies the temperature upper limit and the humidity satisfies the humidity upper limit), it may be determined that the trigger condition is satisfied. If at least one of the monitored temperature and the monitored humidity does not satisfy the corresponding upper limit (for example, the temperature is greater than the temperature upper limit but the humidity is less than the humidity upper limit), it may be determined that the trigger condition is not satisfied.

[0096] The temperature compared with the temperature threshold may be the real-time temperature monitored by the temperature sensor, or the average temperature value over a certain period. Similarly, the humidity compared with the humidity threshold is the humiditySensor It may be the real-time humidity monitored by [[ID=]], or the average humidity value over a certain period.

[0097] In some other embodiments, the operating parameters of the NAND flash chip 131 may be monitored, and it is determined whether the trigger conditions are met based on the monitored operating parameters. The operating parameters may include one or more of the operating voltage, data transmission volume, current state of the channel, etc. The operating voltage may be the operating voltage of the NAND flash chip 131 or the interface voltage for transmitting data.

[0098] For example, a lower limit value of the data transmission volume may be set. If the data transmission volume of the NAND flash chip 131 is less than the lower limit value of the data transmission volume, it may be determined that the trigger conditions are met.

[0099] As another example, if it is determined that the NAND flash chip 131 has an idle channel or the number of idle channels is greater than a preset number, it may be determined that the trigger conditions are met.

[0100] In some other embodiments, a timer may be set. When the timer expires, it may be determined that the trigger conditions are met. In addition, the timer may be restarted after all channels have completed the margin test.

[0101] In some other embodiments, multiple operating environment data, operating parameters, or timers may be monitored simultaneously to determine whether the trigger conditions are met.

[0102] In some embodiments, the trigger condition may be determined to be satisfied only when a plurality of monitored data simultaneously meet their corresponding conditions. For example, the temperature of a memory device and a timer are monitored simultaneously. When the temperature of the memory device is greater than a preset upper limit temperature and the timer has expired, the trigger condition may be determined to be satisfied; or when the temperature of the memory device is greater than the preset upper limit temperature but the timer has not expired, the trigger condition may be determined not to be satisfied.

[0103] In some other embodiments, the trigger condition may be determined to be satisfied when any one of a plurality of monitored data meets its corresponding condition. For example, the temperature of a memory device and a timer are monitored simultaneously. When the temperature of the memory device is greater than a preset upper limit temperature and / or the timer has expired, the trigger condition may be determined to be satisfied; or when the temperature of the memory device is less than the preset upper limit temperature and the timer has not expired, the trigger condition may be determined not to be satisfied.

[0104] When the trigger condition is satisfied, one or more channels may be selected to be paused.

[0105] In some embodiments, the paused channels may be randomly selected.

[0106] In some other embodiments, the paused channels may be selected based on the data transmission volume of the channels. For example, idle channels may be selected first, and then channels performing service read / write may be selected. In another example, channels with a relatively low data transmission volume may be selected first, and then channels with a relatively high data service flow may be selected.

[0107] If the number of selected paused channels is less than the total number of channels, the unselected channels continue to operate normally.

[0108] It is assumed that the channels 502 and 503 shown in FIG. 5 are selected to be paused. In this case, normal read / write operations may be performed on die 521 to die 524 via the channels 504 and 505.

[0109] After the channels 502 and 503 are paused, the states of the die corresponding to the channels 502 and 503 may be changed to the idle state. It is assumed that the states of die 511 and die 512 may be changed to the idle state, and a margin test may be performed on the channel 502. After the margin test is performed on the channel 502, if die 513 and die 514 are in the idle state, the margin test may be performed on the channel 503.

[0110] The margin test can be classified into a timing margin test and a voltage margin test. The channel 502 is used as an example for explaining the margin test.

[0111] In some embodiments, performing a margin test on the channel 502 may be to perform only a timing margin test on the channel 502. In this case, if the channel 502 passes the timing margin test, it may be determined that the channel 502 does not need to be optimized; or if the channel 502 fails the timing margin test, the channel 502 may be determined to be the channel to be optimized.

[0112] In some other embodiments, performing a margin test on the channel 502 may be to perform only a voltage margin test on the channel 502. In this case, if the channel 502 passes the voltage margin test, it may be determined that the channel 502 does not need to be optimized; or if the channel 502 fails the voltage margin test, the channel 502 may be determined to be the channel to be optimized.

[0113] In some other embodiments, performing a margin test on channel 502 may be to perform a timing margin test and a voltage margin test on channel 502.

[0114] If both the timing margin test and the voltage margin test are performed on channel 502, whether channel 502 passes the margin test may be determined in a plurality of ways.

[0115] For example, in one implementation, channel 502 can be determined to have passed the margin test only if both tests pass. In other words, if channel 502 fails the timing margin test or channel 502 fails the voltage margin test, channel 502 may be determined to have failed the margin test.

[0116] As another example, in another implementation, twoIf one of the margin tests is passed, channel 502 may be determined to have passed the margin test. In other words, if channel 502 has passed the timing margin test or if channel 502 has passed the voltage margin test, channel 502 may be determined to have passed the margin test. In this case, the two margin tests may be performed in sequence. If the first margin test performed is passed, the other margin test may not need to be performed. For example, the timing margin test is performed first on channel 502. If channel 502 has passed the timing margin test, channel 502 may be directly determined to have passed the margin test, and there is no need to continue performing the voltage margin test on channel 502. If channel 502 has not passed the timing margin test, the voltage margin test is performed on channel 502. If channel 502 has passed the voltage margin test, channel 502 may be determined to have passed the margin test. If channel 502 has not passed the voltage margin test, channel 502 may be determined to have not passed the margin test.

[0117] Referring to FIGS. 7 to 10, the timing margin test and the voltage margin test will be described below.

[0118] FIG. 7 is a schematic diagram of the connection between the flash memory controller and the die. The input / output interface 701 shown in FIG. 7 is the input / output interface of the flash memory controller. The input / output interface 703 shown in FIG. 7 is the input / output interface of the die.

[0119] As shown in FIG. 7, the input / output interface 701 includes a voltage division module 702. The voltage division module 702 may implement the timing margin test.

[0120] FIG. 8 is a flowchart of a timing margin test. It is assumed that the voltage dividing module 702 may set reference voltages Vref at N levels (N is a positive integer of 2 or more). The voltages at the N levels may be represented as V1, V2, …, and V N respectively.

[0121] 801: Set the level of Vref to V1.

[0122] 802: Determine whether the current level of Vref is N or less. If the current level of Vref is at or below the maximum level V N of the reference voltage, continue with the subsequent steps of the timing margin test implement continuously.

[0123] 803: Write test data to the NAND flash chip.

[0124] Optionally, the test data may be written to the NAND flash chip at a relatively low rate. Thereby, the probability of an error during writing can be reduced. For example, Table 1 shows the correspondence between the NFI bus operation mode and the rate in this embodiment of the present application. Different operation modes correspond to different bus rates.

[0125]

Table 1

[0126] For example, the bus rate corresponding to the NV-DDR operation mode is 40 to 200 × 1 million bits per second (M bps), and the low rate corresponding to the NV-DDR operation mode may be 40 Mbps or 48 Mbps.

[0127] The data written to the NAND flash chip may be data that is prone to transmission errors, such as, for example, 0x5AA55AA5 or 0xA55AA55A. The test data may be written to the cache register of the NAND flash chip. To TA Writing to a deeper area (e.g., data register or NAND flash array) instead of the cache register of the NAND flash chip can reduce the probability of errors occurring during data transmission within the NAND flash chip. I) Writing test data to the cache register of the NAND flash chip instead of the data register or NAND flash array can reduce the probability of errors occurring during data transmission within the NAND flash chip.

[0128] 804: Perform a read direction timing margin test and record the effective width of the read direction timing margin.

[0129] After test data is written to the NAND flash chip, the test data written in step 803 may be read. In the process of reading the test data, the effective eye width in the write direction of the DQ signal is recorded in order to obtain the effective width Trx1 of the read direction timing margin at the current level.

[0130] 805: Perform a write direction timing margin test and record the effective width of the write direction timing margin.

[0131] After the read direction timing margin test is completed, test data is written at the normal rate in order to perform the write direction timing margin test. In the process of writing the test data, the effective eye width in the write direction of the DQ signal is recorded in order to obtain the effective width Ttx1 of the write direction timing margin at the current level.

[0132] 806: Set the level of Vref to the next level, i.e., Vref = V n+1 and continue to perform the read direction timing margin test and the write direction timing margin test to sequentially obtain the effective widths of the read direction timing for N levels and the effective widths of the write direction timing for N levels.

[0133] After the read direction timing valid widths of N levels and the write direction timing valid widths of N levels are obtained, it may be determined whether the timing margin test has passed based on the read direction timing valid widths of N levels and the write direction timing valid widths of N levels. For simplicity of explanation, the read direction timing valid widths of N levels may be referred to as the read timing valid widths of N levels, and the write direction timing valid widths of N levels may be referred to as the write timing valid widths of N levels.

[0134] In some embodiments, if both the read timing valid widths of N levels and the write timing valid widths of N levels pass the timing margin test, the channel may be considered to have passed the timing margin test. In other words, if either the read timing valid widths of N levels or the write timing valid widths of N levels do not pass the margin test, the channel may be considered to have not passed the timing margin test.

[0135] In some embodiments, the read - direction timing effective widths of N levels each correspond to a threshold range. For example, assume that the read - direction timing effective widths of N levels are Trx1, Trx2, …, and TrxN respectively. The threshold range of Trx1 is [Th1_Trx1, Th2_Trx1], the threshold range of Trx2 is [Th1_Trx2, Th2_Trx2], …, and the threshold range of TrxN is [Th1_TrxN, Th2_TrxN]. If the read - direction timing effective width of a certain level is within the corresponding threshold range, the read - direction timing effective width of this level may be regarded as passing the timing margin test. Similarly, the write - direction timing effective widths of N levels each correspond to a threshold range. For example, assume that the write - direction timing effective widths of N levels are Ttx1, Ttx2, …, and TtxN respectively. The threshold range of Ttx1 is [Th1_Ttx1, Th2_Ttx1], the threshold range of Ttx2 is [Th1_Ttx2, Th2_Ttx2], …, and the threshold range of TrxN is [Th1_TtxN, Th2_TtxN]. If the write - direction timing effective width of a certain level is within the corresponding threshold range, the write - direction timing effective width of this level may be regarded as passing the timing margin test.

[0136] In some other embodiments, the read - direction timing effective widths of N levels each have a lower limit value. If the read - direction timing effective width of a certain level exceeds the lower limit value corresponding to that level, the read - direction timing effective width at that level may be regarded as passing the timing margin test. Similarly, the write - direction timing effective widths of N levels each have a lower limit value. If the write - direction timing effective width of a certain level exceeds the lower limit value corresponding to that level, the write - direction timing effective width at that level may be regarded as passing the timing margin test.

[0137] In some other embodiments, if the level passing the timing margin test exceeds a preset ratio, the channel may be considered to have passed the timing margin test.

[0138] In some embodiments, the level ratios of the margin tests passed in the read direction and the write direction are counted separately. The two level ratios are compared separately with the preset ratio. If both of the two level ratios exceed the preset ratio, the channel may be considered to have passed the timing margin test.

[0139] For example, assume that the preset ratio is 50%, the read direction timing effective width at a level of 75% passes the timing margin test, and the write direction timing effective width at a level of 90% passes the timing margin test. In this case, the channel may be considered to have passed the timing margin test.

[0140] As another example, assume that the preset ratio is 50%, the read direction timing effective width at a level of 75% passes the timing margin test, and the write direction timing effective width at a level of 40% passes the timing margin test. In this case, the channel may be considered not to have passed the timing margin test.

[0141] In some other embodiments, the ratio of the total levels passing the timing margin test may be counted. If the ratio of the total levels exceeds the preset ratio, the channel may be considered to have passed the timing margin test. Otherwise, the channel is considered not to have passed the timing margin test.

[0142] For example, assume that N = 10, the preset ratio is 50%, the read direction timing valid widths of three levels pass the timing margin test, and the write direction timing valid widths of eight levels pass the timing margin test. The ratio of the total levels passing the timing margin test is (3 + 8) / (10 + 10) = 11 / 20. It can be learned that the ratio of the total levels passing the timing margin test is greater than 50%. Therefore, the channel may be regarded as passing the timing margin test.

[0143] In some other embodiments, two preset thresholds may be set, and the two preset thresholds may be respectively referred to as the preset timing threshold 1 and the preset timing threshold 2. After determining the N read timing valid widths and the N write timing valid widths, the maximum value of the N read timing valid widths (which may be represented by Max_rx) and the maximum value of the N write timing valid widths (which may be represented by Max_tx) may be determined. If Max_rx is less than or equal to the preset timing threshold 1 and Max_tx is less than or equal to the preset timing threshold 2, the channel may be regarded as passing the timing margin test. If Max_rx is greater than the preset timing threshold 1 or Max_tx is greater than the preset timing threshold 2, the channel may be regarded as not passing the timing margin test.

[0144] In some other embodiments, the maximum values of the N read timing valid widths and the N write timing valid widths may be determined. If the maximum value is less than or equal to the preset threshold, the channel may be regarded as passing the timing margin test; or if the maximum value is greater than the preset threshold, the channel may be regarded as not passing the timing margin test.

[0145] In the foregoing embodiments, the maximum value of the timing valid width is compared with a preset threshold value. In some other embodiments, the average value of the timing valid width may be further determined, and whether the channel passes the timing margin test is determined by comparing the determined average value with a preset threshold value.

[0146] For example, in some embodiments, the average value of the N read timing valid widths (which may be represented by Avg_rx) and the average value of the N write timing valid widths (which may be represented by Avg_tx) may be counted. If Avg_rx is less than or equal to a preset threshold value (which may be called the preset timing threshold 3), and Avg_tx is less than or equal to another preset threshold value (which may be called the preset timing threshold 4), the channel may be considered to have passed the timing margin test; or, if Avg_rx is greater than the preset timing threshold 3 or Avg_tx is greater than the preset timing threshold 4, the channel may be considered to have failed the timing margin test.

[0147] In some other embodiments, the average value of the N read timing valid widths and the N write timing valid widths may be counted. If the average value is less than or equal to a preset threshold value, the channel may be considered to have passed the timing margin test; or, if the average value is greater than the preset threshold value, the channel may be considered to have failed the timing margin test.

[0148] FIG. 9 is a schematic diagram of a flash memory controller. The voltage margin test may be implemented via a delay lock loop (D LL) and a delay line (D L) in the DLL / DL module within the flash memory controller shown in FIG. 9.

[0149] Figure 10 is a schematic flowchart of a voltage margin test. The DLL / DL module shown in Figure 10 is assumed to be able to set the number of DQS delay levels to N (where N is a positive integer greater than or equal to 2). The N levels of delay may be represented by T1, T2, …, and T N respectively.

[0150] 1001: Set the initial level of the DQS delay to T1.

[0151] 1002: Determine whether the current level of the DQS delay is T N or less. If the current level of the DQS delay is the maximum delay level T N or less, the subsequent steps of the voltage margin test are continued.

[0152] 1003: Write test data to the NAND flash chip.

[0153] Similar to the timing margin test process of Figure 8, the test data may also be written to the NAND flash chip at a relatively low rate. The test data may also be prone to errors. The location of the written test data may be a cache register within the NAND flash chip.

[0154] 1004: Perform a read direction timing margin test and record the read direction voltage margin.

[0155] After the test data is written to the NAND flash chip, the written test data may be read. In the process of reading the test data, the current level of the high electrical level Vrx1h and the low electrical level Vrx1l in the read direction are obtained, and the sum of Vrx1h and Vrx1l is determined as the voltage margin Vrx1 in the read direction at the current level.

[0156] 1005: Perform a write direction timing margin test and record the write direction voltage margin.

[0157] In the test data writing process, the high electrical level Vtx1h and the low electrical level Vtx1l in the writing direction at the current level are obtained, and the sum of Vtx1h and Vtx1l is determined as the voltage margin Vtx1 in the writing direction at the current level.

[0158] 1006: Set the DQS delay level to the next level, i.e., T n+1 and continue to perform the read direction voltage margin test and the write direction voltage margin test to sequentially obtain the read direction voltage margins of N levels and the write direction voltage margins of N levels.

[0159] After the read direction voltage margins of N levels and the write direction voltage margins of N levels are obtained, it may be determined whether the voltage margin test has passed based on the read direction voltage margins of N levels and the write direction voltage margins of N levels. For ease of explanation, the read direction voltage margins of N levels may sometimes be referred to as N read voltage margins, and the write direction voltage margins of N levels may sometimes be referred to as N write voltage margins.

[0160] The method for determining whether a channel has passed the voltage margin test is the same as the method for determining whether a channel has passed the timing margin test.

[0161] For example, in some embodiments, each voltage margin may have a corresponding threshold range. If both the N read voltage margins and the N write voltage margins are within the corresponding threshold range, the channel may be determined to have passed the voltage margin test; or if the voltage margin is not within the corresponding threshold range, the channel may be determined not to have passed the margin test.

[0162] As another example, in some embodiments, the maximum value of the N read voltage margins may be compared with a preset threshold, the maximum value of the N write voltage margins may be compared with a preset threshold, and based on the comparison results, it may be determined whether the channel passes the margin test.

[0163] As another example, in some other embodiments, the threshold may be compared with the average value of the voltage margins.

[0164] For the specific implementation of determining whether a channel passes the voltage margin test, refer to the description of determining whether a channel passes the timing margin test. For the sake of brevity, the details will not be described again here.

[0165] It is assumed that channel 502 passes the margin test and channel 503 fails the margin test. In this case, channel 503 may be determined as the channel to be optimized. In this case, channel 502 does not need to be optimized, and channel 503 needs to be optimized. Hereinafter, with reference to FIGS. 11 to 12, the channel optimization process will be described.

[0166] Channel optimization may be classified into voltage margin optimization and timing margin optimization.

[0167] In some embodiments, both voltage margin optimization and timing margin optimization may be performed on the channel to be optimized (e.g., channel 503).

[0168] In some other embodiments, only voltage margin optimization or only timing margin optimization may be performed on the channel to be optimized (e.g., channel 503).

[0169] For example, if channel 503 passes the voltage margin test but fails the timing margin test, timing margin optimization may be performed on channel 503.

[0170] In another example, if channel 503 passes the timing margin test but fails the voltage margin test, voltage margin optimization may be performed on channel 503.

[0171] FIG. 11 is a schematic flowchart of voltage margin optimization according to an embodiment of the present application.

[0172] 1101: Obtain K read margins and K write margins, where the K read margins correspond one-to-one to K levels, the K write margins correspond one-to-one to K levels, and K is a positive integer greater than 1.

[0173] As described above, in the process of performing the timing margin test, the read direction timing margin effective width of N voltage levels and the write direction timing margin effective width of N levels may be extracted.

[0174] In some embodiments, K voltage levels (K is a positive integer greater than 1 and less than N) and the read direction timing margin effective width and the write direction timing margin effective width corresponding to the K voltage levels may be selected from the N voltage levels. The selected K voltage levels are the K levels in step 1101, the read direction timing margin effective width corresponding to the K voltage levels is the K read margins in step 1101, and the write direction timing margin effective width corresponding to the K voltage levels is the K write margins in step 1101.

[0175] There may be multiple methods for selecting K voltage levels from N voltage levels. For example, the K voltage levels may be randomly selected. As another example, K voltage levels corresponding to the largest K read direction timing margin effective widths among the read direction timing margin effective widths may be selected, and K may be a preset value or a positive integer calculated based on a preset ratio. As another example, K voltage levels corresponding to the largest K write direction timing margin effective widths among the write direction timing margin effective widths may be selected, and K may be a preset value or a positive integer calculated based on a preset ratio.

[0176] In some other embodiments, the K levels may be the same as the N voltage levels. In other words, in step 1101, the N voltage levels obtained in the timing margin test, as well as the read direction timing margin effective width and the write direction timing margin effective width of each voltage level, may be directly used. In this case, the value of K is the same as the value of N.

[0177] When the K levels are K voltage levels, the K read margins may sometimes be referred to as K read timing margins, and the K write margins may sometimes be referred to as K write timing margins.

[0178] As described above, in the process of performing the voltage margin test, the read direction voltage margin and the write direction voltage margin of N DQS delay levels may be obtained.

[0179] Similarly, in some embodiments, K DQS delay levels (where K is a positive integer greater than 1 and less than N), as well as read direction voltage margins and write direction voltage margins corresponding to the K DQS delay levels, may be selected from the N DQS delay levels. The selected K DQS delay levels are the K levels of step 1101, the read direction voltage margins corresponding to the K DQS delay levels are the K read margins of step 1101, and the write direction voltage margins corresponding to the K DQS delay levels are the K write margins of step 1101.

[0180] Multiple methods may exist for selecting K DQS delay levels from the N DQS delay levels. For example, the K DQS delay levels may be randomly selected. As another example, K voltage levels corresponding to the largest K read direction voltage margins among the read direction voltage margins may be selected, where K may be a preset value or a positive integer calculated based on a preset ratio. As another example, K voltage levels corresponding to the largest K direction voltage margins among the write direction voltage margins may be selected, where K may be a preset value or a positive integer calculated based on a preset ratio.

[0181] In some other embodiments, the K levels may be the same as the N DQS delay levels. In other words, in step 1101, the N DQS delay levels obtained in the voltage margin test, as well as the read direction voltage margins and write direction voltage margins for each DQS delay level, may be directly used. In this case, the value of K is the same as the value of N.

[0182] When the K levels are the K DQS delay levels, the K read margins may sometimes be referred to as K read voltage margins, and the K write margins may sometimes be referred to as K write voltage margins.

[0183] 1102: Determine optimization parameters based on the K read margins and K write margins obtained in step 1101.

[0184] The read optimization voltage may be determined based on the K read margins, and the write read voltage may be determined based on the K write margins.

[0185] For example, the read optimization voltage may be determined by the following formula in accordance with and may be determined.

Equation

[0186] The write optimization voltage may be determined by the following formula in accordance with and may be determined.

Equation

[0187] As another example, the read optimization voltage may be the arithmetic mean of the K read direction voltage margins, that is, the read optimization voltage may be determined by the following formula in accordance with and may be determined.

Equation

[0188] The write optimization voltage may be the arithmetic mean of the K write direction voltage margins, that is, the write optimization voltage may be determined by the following formula in accordance with and may be determined.

Equation

[0189] In the foregoing embodiments, in the process of determining the read optimization voltage and the write optimization voltage, all the read margins and write margins determined in step 1101 are used. In some other embodiments, in the process of determining the read optimization voltage and the write optimization voltage, some of the read margins and write margins determined in step 1101 may be used. For example, after excluding the maximum read margin, the minimum read margin, the maximum write margin, and the minimum write margin, the remaining read margins are averaged to obtain the read optimization voltage, and the remaining write margins are averaged to obtain the write voltage margin.

[0190] In the foregoing embodiments, the read reference voltage and the write reference voltage can be optimized, the probability of errors in the transmission between the flash memory controller and the NAND flash chip is reduced, and the storage performance is improved.

[0191] FIG. 12 is a schematic flowchart of timing margin optimization according to an embodiment of the present application.

[0192] 1201: Write test data to the NAND flash chip.

[0193] Similar to the timing margin test process of FIG. 8, the test data may also be written to the NAND flash chip at a relatively low rate. The test data may also be likely to cause errors. The position of the written test data may be a cache register in the NAND flash chip.

[0194] 1202: Obtain the effective width of the timing margin of DQ.

[0195] 1203: Determine the left boundary (L_Boundary) and the right boundary (R_Boundary) based on the timing margin effective width, where the left boundary is the maximum value of the minimum values of the timing margin effective widths of all DQs, and the right boundary is the minimum value of the maximum values of all corresponding timing margin effective widths when all DQs are aligned with the left boundary.

[0196] 1204: Calculate the first center position based on the left boundary and the right boundary. During the training of the read data, the first center position is the center of the minimum margin effective width obtained after all DQs are aligned.

[0197] The first center position is the average value of the left boundary and the right boundary, that is, center point = -(L_Boundary - R_Boundary) / 2.

[0198] 1205: Adjust the delay line DL of DQS to the first center position so that the edge of the DQS signal is located at the center point ( center point ) of the margin effective width of DQ.

[0199] In addition, the method further includes the steps of assigning the delay line DL value corresponding to the first center position to the DQS register; and assigning the DL value of each DQ to the corresponding DQ register. The DL value of each DQ is a value obtained by converting the length that needs to be adjusted to align each DQ with the edge of DQS into the scale unit corresponding to DQ.

[0200] Optionally, the scale of DQS is different from that of DQ. Specifically, the DQS signal has a relatively large number of scale values. For example, there are a total of 1024 tap numbers, and the time represented by the unit scale is determined by the DQS cycle, that is, the DQS cycle measured by the DLL is divided into 1024. The DQ signal has a relatively small number of scale values. For example, there are a total of 20 taps, and the time represented by the unit scale is fixed (determined by the precision of the hardware circuit). Furthermore, the scale unit may be set to 5ps, 10ps, 20ps, etc.

[0201] The parameter used to adjust the delay line of DQS to the first center position may be called the read optimization DQS timing optimization parameter.

[0202] 1206: Perform write direction merge timing training to obtain the second center position. During the training of the write data, the second center position is the center of the minimum merge effective width obtained after all DQs are aligned.

[0203] After the read direction training is completed, preset data or custom data is written at the normal rate, then a read command is sent to read the just-written data, and the write direction timing training is performed.

[0204] The preset data or custom data to be written may be the same as or different from the preset data in the read direction. This is not limited in this embodiment of the present application.

[0205] After the write direction training is completed, the delay line DL corresponding to the second center position is assigned to the DQS register, and the DL value of each DQ is assigned to the corresponding DQ register. The DL value of each DQ is a value obtained by converting the length that needs to be adjusted to align each DQ with the edge of DQS into the scale unit corresponding to the DQ.

[0206] The parameters used to adjust the delay line of the DQS to the second center position may be called write optimization DQS timing optimization parameters.

[0207] In the above method, training data is written at a low rate, then a read command is sent to read the training data, and read direction timing training is performed. The first center position in the read training direction is determined using the values of the left and right boundaries of the margin effective width of DQ on the NFI bus, and the delay line of the DQ signal on the controller side is automatically adjusted, whereby the timing margin effective width of all DQ signals is maximized, the delay line of the DQS signal is adjusted to the first center position, and the DQS signal edge is positioned at the optimal sampling point of the DQ signal. Further, custom data is written at the normal rate, a read command is sent to read the data just written, and write direction timing training is performed to determine the second center position. Then, the delay line of the DQ signal of the controller is automatically adjusted, whereby the margin effective width of all received DQ signals is maximized, the controller adjusts the delay line of the DQS signal to the second center position, and the edge of the DQS signal received by the NAND flash receiving end is positioned at the optimal sampling point of the DQ signal. In conclusion, in the above solution, the timing margin effective width of the signal at the receiving end is maximized, and the timing margin can be optimized by adjusting the position of the delay line of the DQS signal to enable the setup time margin and the hold time margin to be maximized, thereby meeting the specification requirements and avoiding data loss caused by bit errors during data read / write.

[0208] The left and right boundaries may be determined in one of the following three specific implementation forms.

[0209] Method 1: The left and right boundaries are determined based on a preset boundary range [a, b].

[0210] Method 2: The left boundary and the right boundary are determined by using 1 / 4 of the DQS cycle as the starting position and adjusting the DQS position left and right.

[0211] Method 3: The left boundary and the right boundary are determined by gradually adjusting the DQS position from the initial scale value from left to right.

[0212] FIG. 13 is a schematic flowchart of a method for optimizing a flash memory chip according to an embodiment of the present application.

[0213] 1301: In the service execution process of the flash memory chip, N channels in the non-volatile flash interface NFI bus of the flash memory chip are temporarily stopped, where N is an integer greater than or equal to 1 and less than or equal to the total number of channels in the NFI bus.

[0214] 1302: Determine at least one channel to be optimized from the N channels.

[0215] 1303: Based on the training data of each channel to be optimized in at least one channel to be optimized, determine the optimization parameters of each channel to be optimized.

[0216] 1304: Optimize each channel to be optimized based on the optimization parameters of each channel to be optimized.

[0217] For the specific implementation forms of determining the channels to be optimized and optimizing the parameters, please refer to the foregoing embodiments. For the sake of brevity, the details are not described again here.

[0218] In the above technical solution, in the execution process of the flash memory chip, some channels in a plurality of channels are selected for detection and optimization. In other words, another part of the channels in the NFI bus is in a normal operating state. Therefore, the channel parameters can be optimized without disk disconnection. The dependence on the physical environment and operating state in the margin determination standard may be reduced, and the margin determination standard may be further compressed, whereby more margins are reserved for the interface link, and thereby a higher rate may be supported.

[0219] FIG. 14 is a schematic block diagram of the structure of an electronic device according to an embodiment of the present application. The electronic device 1400 shown in FIG. 14 may be the SSD 100 shown in FIG. 1, may be the SSD controller 110 shown in FIG. 1, or may be the flash memory controller 113 shown in FIG. 1.

[0220] The processing unit 1401 is configured to suspend N channels in the non-volatile flash interface NFI bus of the flash memory chip in the service execution process of the flash memory chip, where N is an integer greater than or equal to 1 and less than or equal to the total number of channels in the NFI bus.

[0221] The determination unit 1402 is configured to determine at least one optimization target channel from the N channels.

[0222] The determination unit 1402 is further configured to determine the optimization parameters of each optimization target channel based on the training data of each optimization target channel in at least one optimization target channel.

[0223] The optimization unit 1403 is configured to optimize each optimization target channel based on the optimization parameters of each optimization target channel.

[0224] For the specific functions and beneficial effects of the processing unit 1401, the determination unit 1402, and the optimization unit 1403, please refer to the foregoing embodiments. For the sake of brevity, the details will not be described again.

[0225] An embodiment of the present application further provides a chip system. The chip system includes a logic circuit. The logic circuit is coupled to the input / output interface and configured to transmit data through the input / output interface in order to implement the method shown in the foregoing embodiments.

[0226] The chip system may be the flash memory controller 113 shown in FIG. 1, or may be the SSD controller 110 shown in FIG. 1.

[0227] An embodiment of the present application further provides an SSD, and the SSD includes the foregoing chip system.

[0228] An embodiment of the present application further provides a computer-readable medium. The computer-readable medium stores computer program code, and when the program code is executed on a computer, the computer is enabled to implement the method of the foregoing embodiments.

[0229] During implementation, the steps in the foregoing method can be implemented by using the hardware integrated logic circuit in the processor or by using instructions in the form of software. The steps of the method disclosed with reference to the embodiments of the present application may be directly implemented by a hardware processor or may be implemented by using a combination of hardware and software modules in the processor. The software module may be located in a mature storage medium of the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or register. The storage medium is located in the memory, and the processor reads the information in the memory and combines it with the hardware of the processor to complete the steps of the foregoing method. To avoid repetition, details are not described again in this specification.

[0230] It should be noted that the processor of the embodiment of the present application may be an integrated circuit chip and has signal processing capabilities. During implementation, the steps in the foregoing method embodiments can be implemented by using the hardware integrated logic circuit in the processor or by using instructions in the form of software. The general-purpose processor may be a microprocessor, or the processor may be any conventional processor or the like. The steps of the method disclosed with reference to the embodiments of the present application may be directly achieved by a hardware decoding processor or may be achieved by using a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium of the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or register. The storage medium is located in the memory, and the processor reads the information in the memory and combines it with the hardware of the processor to complete the steps of the foregoing method.

[0231] The memory in the embodiments of the present application may be a volatile memory, a non-volatile memory, or may include a volatile memory and a non-volatile memory. The non-volatile memory may be a read-only memory (R OM), a programmable read-only memory (P ROM), an erasable programmable read-only memory (E PROM), an electrically erasable programmable read-only memory (E EPROM), or a flash memory. The volatile memory may be a random access memory (R AM) used as an external cache. By way of example and not limitation, multiple forms of RAM, such as static random access memory (S RAM), dynamic random access memory (D RAM), synchronous dynamic random access memory (S DRAM), double data rate synchronous dynamic random access memory (D DR SDRAM), extended synchronous dynamic random access memory (E SDRAM), synchronous link dynamic random access memory (S LDRAM), and direct rambus dynamic random access memory (D R RAM) may be used. It should be noted that the memory of the systems and methods described herein includes these memories and any other suitable type of memory, but is not limited thereto.

[0232] According to the method provided in the embodiments of the present application, the present application further provides a computer program product. The computer program product includes computer program code, and when the computer program code is executed on a computer, the computer is enabled to implement the method shown in the foregoing embodiments.

[0233] Those skilled in the art may recognize that, in combination with the examples described in the embodiments disclosed herein, the units and algorithm steps can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether the function is implemented by hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art may implement the described functions using different methods for each specific application, but such implementation should not be considered as exceeding the scope of this application.

[0234] For the sake of simplicity, it should be clearly understood by those skilled in the art that for the detailed operation processes of the aforementioned systems, devices, and units, reference should be made to the corresponding processes of the embodiments of the aforementioned methods. Details will not be described again here.

[0235] In some embodiments provided in this application, it should be understood that the disclosed systems, devices, and methods may be implemented in other ways. For example, the described embodiments of the device are merely examples. For example, the division into units is only a logical function division, and other divisions may be possible during actual implementation. For example, multiple units or components may be combined or integrated into other systems, or some features may be ignored or not implemented. In addition, the displayed or described mutual coupling, direct coupling, or communication connection may also be implemented via some interfaces. The indirect coupling or communication connection between devices or units may be implemented in electronic form, mechanical form, or other forms.

[0236] The units described as separate parts may or may not be physically separate, and the parts presented as units may or may not be physical units. They may be located at one position or distributed among multiple network units. To achieve the purpose of the solution of the embodiment, some or all of the units may be selected based on actual requirements.

[0237] In addition, the functional units of the embodiments of the present application may be integrated into one processing unit, each of the units may physically exist alone, or two or more units may be integrated into one unit.

[0238] When the function is implemented in the form of a software functional unit and sold or used as an independent product, the function may be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the present application as an essential part, the part contributing to the prior art, or a part of the technical solution may be implemented in the form of a software product. The software product is stored in a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, a server, or a network device) to implement all or part of the steps of the method described in the embodiments of the present application. The aforementioned storage medium includes any medium capable of storing program codes, such as a USB flash drive, a removable hard disk, a read-only memory (R OM), a random access memory (R AM), a magnetic disk, or an optical disk.

[0239] The foregoing description is only a specific implementation form of the present application and is not intended to limit the protection scope of the present application. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present application shall fall within the protection scope of the present application. Therefore, the protection scope of the present application shall follow the protection scope of the claims.

Description of Reference Numerals

[0240] 1 Timing threshold, scenario, method 2 Timing threshold, scenario, method 3 Timing threshold, method 4 Timing threshold 100 Solid State Disk, SSD 110 Processor, SSD Controller 111 Host Interface Controller 112 Processor 113 Flash Memory Controller 114 Bus 120 NFI Bus 130 NAND flash Memory 131 NAND flash Chip 501 Input / Output Interface 502 Channel 503 Channel 504 Channel 505 Channel 510 target 511 die 512 die 513 die 514 die 520 target 521 die 522 die 523 die 524 die 701 Input / Output Interface 702 Voltage Divider Module 703 Input / Output Interface 1400 Electronic Device 1401 Processing Unit 1402 Decision Unit 1403 Optimization Unit

Claims

1. A method for monitoring and retraining a non-volatile flash interface (NFI), comprising: determining whether a trigger condition for monitoring the NFI is satisfied after completing the write training of the NFI and establishing a data strobe signal (DQS) trigger point, wherein the DQS trigger point triggers the memory to identify the electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, and the trigger condition is related to the operating environment data of the NFI; when it is determined that the trigger condition for monitoring the NFI is satisfied, writing test data to the memory and performing the margin test on the NFI to determine whether the NFI passes the margin test; when it is determined that the NFI fails the margin test, starting interface retraining of the NFI; wherein the DQS trigger point divides the cycle of the write DQ into a period before the DQS trigger point as the setup time of the write DQ and a period after the DQS trigger point as the hold time of the write DQ; the margin test includes a timing margin test, and the timing margin test includes: setting N levels of reference voltages, where N is a positive integer greater than or equal to 2; for each of the N levels of the reference voltages, performing a read direction timing margin test on the test data written to the memory to record the effective width of the read direction timing margin as the read direction timing effective width of the level, and performing a write direction timing margin test on the test data written to the memory to record the effective width of the write direction timing margin as the write direction timing effective width of the level; determining whether the timing margin test passes based on the read direction timing effective widths of the N levels and the write direction timing effective widths of the N levels; For each of the N levels, determine whether the read direction timing effective width of the level is within a first corresponding threshold range, and if it is determined that the read direction timing effective width of the level is within the first corresponding threshold range, determine that the read direction timing effective width of the level has passed the timing margin test in the read direction; For each of the N levels, determine whether the write direction timing effective width of the level is within a second corresponding threshold range, and if it is determined that the write direction timing effective width of the level is within the second corresponding threshold range, determine that the write direction timing effective width of the level has passed the timing margin test in the write direction; Based on one or more of the N levels that have passed the timing margin test in the read direction and / or the write direction, determine whether the timing margin test has passed; including the step of determining; including; a method.

2. If it is determined that the NFI has passed the margin test, continue to check whether the trigger conditions for monitoring the NFI are satisfied; The method according to claim 1, further comprising.

3. The method according to claim 1, wherein the operating environment data includes data related to the temperature, operating voltage, humidity, data transmission volume, and / or current state of the NFI.

4. The method according to claim 3, wherein the operating environment data includes data related to temperature, and the trigger conditions for monitoring the NFI are satisfied when the monitored temperature is greater than the temperature upper limit or less than the temperature lower limit.

5. The margin test includes a voltage margin test, and the voltage margin test includes: setting N DQS delay levels, where N is a positive integer greater than or equal to 2; for each of the N DQS delay levels, performing a read direction voltage margin test on the test data written to the memory to record the read direction voltage margin of the level, and performing a write direction voltage margin test on the test data written to the memory to record the write direction voltage margin of the level; A step of determining whether the voltage margin test has passed based on the read direction voltage margin of the N DQS delay levels and the write direction voltage margin of the N DQS delay levels The method according to claim 1, comprising:

6. The step of determining whether the voltage margin test has passed based on the read direction voltage margin of the N DQS delay levels and the write direction voltage margin of the N DQS delay levels is For each of the N DQS delay levels, determining whether the read direction voltage margin of the level is within a first corresponding threshold range, and if it is determined that the read direction voltage margin of the level is within the first corresponding threshold range, determining that the read direction voltage margin of the level has passed the read direction voltage margin test; For each of the N DQS delay levels, determining whether the write direction voltage margin of the level is within a second corresponding threshold range, and if it is determined that the write direction voltage margin of the level is within the second corresponding threshold range, determining that the write direction voltage margin of the level has passed the write direction voltage margin test; A step of determining whether the voltage margin test has passed based on one or more of the N DQS delay levels that pass the voltage margin test in the read direction and / or the write direction The method according to claim 5, comprising:

7. The interface retraining of the NFI includes adjusting the DQS trigger point to reduce the difference between the timing margin of the setup time of the write data signal (DQ) and the timing margin of the hold time of the write DQ. The method according to claim 1

8. When the electrical level of the write DQ is lower than the reference voltage, the write DQ is at a low electrical level, and when the electrical level of the write DQ is higher than the reference voltage, the write DQ is at a high electrical level. The electrical level of the write DQ reaches the reference voltage at the minimum and maximum points. The time interval between the minimum time point and the start time point of the cycle of the write DQ is the minimum setup time applicable to the memory, and the time interval between the maximum time point and the end time point of the cycle of the write DQ is the minimum hold time applicable to the memory, and In the cycle of the write DQ, the difference between the setup time of the write DQS and the minimum setup time is the timing margin of the setup time of the write DQ, and the difference between the hold time of the write DQS and the minimum hold time is the timing margin of the hold time of the write DQ. The method according to claim 7

9. The interface retraining of the NFI is Adjusting the DQS trigger point to an intermediate position between the minimum time point and the maximum time point The method according to claim 8, comprising

10. The interface retraining of the NFI is Reading the data signal of the test data from the memory, and Sampling the data signal to obtain a plurality of timing margin effective widths of the data signal, and Determining a left boundary and a right boundary based on the timing margin effective widths, where the left boundary is the maximum value among a plurality of minimum values of the plurality of timing margin effective widths, and the right boundary is the minimum value among a plurality of maximum values of the plurality of timing margin effective widths when all the data signals are aligned to the left boundary, and Calculating a first center position based on the left boundary and the right boundary, and Adjusting the DQS trigger point to the first center position The method according to claim 1, comprising

11. The method according to claim 10, wherein the first center position is the average value of the left boundary and the right boundary

12. The interface retraining of the NFI is Performing write direction margin timing training based on the left boundary and the right boundary to obtain a second center position, and Adjusting the DQS trigger point to the second center position The method according to claim 10, further comprising

13. The interface retraining of the NFI is Obtaining K read margins and K write margins that correspond one-to-one to K levels, where K is a positive integer greater than 1, the step of, Determining the average value of the K read margins as the read optimization voltage, the step of, Determining the average value of the K write margins as the write optimization voltage, the step of, Performing training of the NFI based on the read optimization voltage and the write optimization voltage, the step of The method according to claim 1, comprising.

14. A solid state disk (SSD) controller that reads and executes instructions and / or program code in a flash memory coupled to the SSD controller via a non-volatile flash interface (NFI), After completing the write training of the NFI and establishing a data strobe signal (DQS) trigger point, determining whether a trigger condition for monitoring the NFI is satisfied, where the DQS trigger point triggers the flash memory to identify the electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, and the trigger condition is related to the operating environment data of the NFI, the step of determining, When it is determined that the trigger condition for monitoring the NFI is satisfied, writing test data to the flash memory and performing the margin test on the NFI to determine whether the NFI passes the margin test, the step of, When it is determined that the NFI fails the margin test, starting the interface retraining of the NFI, the step of Configured to perform operations including, The DQS trigger point divides the cycle of the write DQ into a period before the DQS trigger point as the setup time of the write DQ and a period after the DQS trigger point as the hold time of the write DQ, The margin test includes a timing margin test, and the timing margin test, Setting reference voltages for N levels, where N is a positive integer greater than or equal to 2, the step of, For each of the N levels of the reference voltage, perform a read-direction timing margin test on the test data written to the flash memory, record the effective width of the read-direction timing margin as the read-direction timing effective width of the level, and perform a write-direction timing margin test on the test data written to the flash memory, and record the effective width of the write-direction timing margin as the write-direction timing effective width of the level; Based on the read-direction timing effective widths of the N levels and the write-direction timing effective widths of the N levels, determining whether the timing margin test has passed, For each of the N levels, determining whether the read-direction timing effective width of the level is within a first corresponding threshold range, and if it is determined that the read-direction timing effective width of the level is within the first corresponding threshold range, determining that the read-direction timing effective width of the level has passed the read-direction timing margin test; For each of the N levels, determining whether the write-direction timing effective width of the level is within a second corresponding threshold range, and if it is determined that the write-direction timing effective width of the level is within the second corresponding threshold range, determining that the write-direction timing effective width of the level has passed the write-direction timing margin test; Based on one or more of the N levels that have passed the timing margin test in the read direction and / or the write direction, determining whether the timing margin test has passed including the step of determining including SSD controller.

15. The operation is continuing to check whether the trigger condition for monitoring the NFI is satisfied when it is determined that the NFI has passed the margin test The SSD controller according to claim 14, further comprising.

16. A solid state drive (SSD) comprising an SSD controller coupled to a flash memory via a non-volatile flash interface (NFI), wherein the SSD controller determines whether a trigger condition for monitoring the NFI is satisfied after completing the write training of the NFI and establishing a data strobe signal (DQS) trigger point, wherein the DQS trigger point triggers the flash memory to identify the electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, and the trigger condition is related to the operating environment data of the NFI; when it is determined that the trigger condition for monitoring the NFI is satisfied, writes test data to the flash memory and performs the margin test on the NFI to determine whether the NFI passes the margin test; when it is determined that the NFI fails the margin test, starts interface retraining of the NFI is configured to perform operations including the DQS trigger point divides the cycle of the write DQ into a period before the DQS trigger point as the setup time of the write DQ and a period after the DQS trigger point as the hold time of the write DQ; the margin test includes a timing margin test, and the timing margin test includes the step of setting N reference voltage levels, where N is a positive integer greater than or equal to 2; for each of the N levels of the reference voltage, performing a read direction timing margin test on the test data written to the flash memory to record the effective width of the read direction timing margin as the read direction timing effective width of the level, and performing a write direction timing margin test on the test data written to the flash memory to record the effective width of the write direction timing margin as the write direction timing effective width of the level; based on the read direction timing effective widths of the N levels and the write direction timing effective widths of the N levels, determining whether the timing margin test passes For each of the N levels, determine whether the read direction timing effective width of the level is within a first corresponding threshold range, and if it is determined that the read direction timing effective width of the level is within the first corresponding threshold range, determine that the read direction timing effective width of the level has passed the timing margin test in the read direction; For each of the N levels, determine whether the write direction timing effective width of the level is within a second corresponding threshold range, and if it is determined that the write direction timing effective width of the level is within the second corresponding threshold range, determine that the write direction timing effective width of the level has passed the timing margin test in the write direction; Based on one or more of the N levels that have passed the timing margin test in the read direction and / or the write direction, determine whether the timing margin test has passed; Including the step of determining; Including; SSD.

17. The operation is; When it is determined that the NFI has passed the margin test, continuously check whether the trigger condition for monitoring the NFI is satisfied; The SSD according to claim 16, further including this.

18. An electronic device comprising a solid state drive (SSD) including an SSD controller coupled to a flash memory via a non-volatile flash interface (NFI), wherein the SSD controller is; After completing the write training of the NFI and establishing a data strobe signal (DQS) trigger point, determining whether a trigger condition for monitoring the NFI is satisfied, wherein the DQS trigger point triggers the flash memory to identify the electrical level state of a write data signal (DQ) corresponding to the DQS trigger point, and the trigger condition is related to the operating environment data of the NFI; When it is determined that the trigger condition for monitoring the NFI is satisfied, writing test data to the flash memory and performing the margin test on the NFI to determine whether the NFI has passed the margin test; When it is determined that the NFI fails the margin test, start the interface retraining of the NFI and is configured to perform operations including The DQS trigger point divides the write DQ cycle into a period before the DQS trigger point as the setup time of the write DQ and a period after the DQS trigger point as the hold time of the write DQ. The margin test includes a timing margin test, and the timing margin test is a step of setting N levels of reference voltages, where N is a positive integer greater than or equal to 2. For each of the N levels of the reference voltage, perform a read-direction timing margin test on the test data written to the flash memory, record the effective width of the read-direction timing margin as the read-direction timing effective width of the level, and perform a write-direction timing margin test on the test data written to the flash memory, and record the effective width of the write-direction timing margin as the write-direction timing effective width of the level. Based on the read-direction timing effective widths of the N levels and the write-direction timing effective widths of the N levels, determine whether the timing margin test has passed. For each of the N levels, determine whether the read-direction timing effective width of the level is within a first corresponding threshold range, and if it is determined that the read-direction timing effective width of the level is within the first corresponding threshold range, determine that the read-direction timing effective width of the level has passed the read-direction timing margin test. For each of the N levels, determine whether the write-direction timing effective width of the level is within a second corresponding threshold range, and if it is determined that the write-direction timing effective width of the level is within the second corresponding threshold range, determine that the write-direction timing effective width of the level has passed the write-direction timing margin test. Based on one or more of the N levels that have passed the timing margin test in the read direction and / or the write direction, determining whether the timing margin test has passed A step of determining, including Including An electronic device

19. The operation is When it is determined that the NFI has passed the margin test, continuously checking whether the trigger condition for monitoring the NFI is satisfied The electronic device according to claim 18, further including

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