Hybrid Conductive Volatile Memory Element for Accelerated Writing of Non-Volatile Memristive Devices

Abstract

Embodiments herein may include analog memory structures including volatile memory elements in series with non-volatile memory elements, and methods for writing to such structures. The analog memory structures may change resistance upon application of a voltage, which may accelerate writing to the analog memory structures.

Description

Technical Field

[0001] The present invention relates to a memory device, and more specifically, to a memristive device.

Background Art

[0002] "Machine learning" is used as a form of artificial intelligence to broadly represent the main functions of electronic computer systems that learn from data. In machine learning and cognitive science, an artificial neural network (ANN) is a family of statistical learning models and algorithms inspired by the biological neural networks (especially the brain) of animals. ANNs often include analog devices that mimic artificial neurons for machine learning. In supervised machine learning, the artificial neurons of an ANN can be used to estimate or approximate systems or functions that depend on a large number of learning inputs. Subsequently, the trained ANN is used in the inference process to calculate some output based on the initial or continuous input training of the ANN's neurons. ANNs may also be used for self-learning in the processes of reinforcement machine learning and unsupervised learning. ANN architectures, neuromorphic microchips, and ultra-high density non-volatile memories can be formed from high-density, low-cost, low-power circuit architectures such as crossbar arrays. A basic crossbar array configuration includes a set of conductive row wires and a set of conductive column wires formed to intersect the set of conductive row wires. The intersections between the two sets of wires are separated by so-called cross-point devices that can be formed from thin film materials. The cross-point devices can be implemented as so-called resistive memory (commonly referred to as memristive) devices. The characteristics of memristive devices can include non-volatility, the ability to store variable analog resistance values, the ability to determine analog resistance values without disturbing the state of the memristive device, and the ability to tune the resistance up or down using current or voltage pulses. These memristive devices can be used in hardware to simulate the artificial neurons of an ANN.

SUMMARY OF THE INVENTION

[0003] Embodiments can include a memory structure including a volatile memory element in series with a non-volatile memory element. This may accelerate the writing of an analog memory structure in some cases.

[0004] Embodiments can include a memristive device as the non-volatile memory element. This may accelerate the writing of an analog memory structure for use in analog computing in some cases.

[0005] Embodiments can include that the volatile memory element is a substance whose resistance temporarily changes when a potential is applied to the substance. This may accelerate the writing of an analog memory structure in some cases.

[0006] Embodiments can include that the volatile memory element is a substance that becomes highly conductive when a potential is applied to the substance and returns to a relaxed state when the potential is removed. This may accelerate the writing of an analog memory structure in some cases.

[0007] Embodiments can include a volatile memory element located between a first metal layer and a second metal layer. This can improve the stability of the device by reducing the movement of ions from the volatile memory, and may accelerate the writing of an analog memory structure in some cases.

[0008] Embodiments can include a volatile memory layer including a mixed ionic-electron conduction (MIEC) material that undergoes a metal-insulator transition (MIT) depending on the local ion concentration within the volatile memory layer. This may accelerate the writing of an analog memory structure in some cases.

[0009] Embodiments are XCoO2, XNbO2, XVO2, XNbO3, X 4x Ti5O 12、 or include a volatile memory layer containing XSmNiO3 or a combination thereof, where X can be an alkali metal such as Li, Na, K, etc. This may accelerate the writing of the analog memory structure.

[0010] Embodiments can include a volatile memory layer in the write path of a three-terminal device. This may accelerate the writing of the three-contact device.

[0011] Embodiments may include bidirectional non-volatile memory. This may accelerate the writing of the bidirectional memory.

[0012] Embodiments may include unidirectional non-volatile memory. This may accelerate the writing of the unidirectional memory.

[0013] Embodiments can include resistive random access memory (RRAM) non-volatile memory. This may accelerate the writing of RRAM.

[0014] Embodiments can include conductive bridging random access memory (CBRAM) non-volatile memory. This may accelerate the writing of CBRAM.

[0015] Embodiments can include electrochemical random access memory (ECRAM) non-volatile memory. This may accelerate the writing of ECRAM.

[0016] Embodiments can include phase change memory (PCM) non-volatile memory. This may accelerate the writing of PCM.

[0017] An embodiment can include writing to a memory structure including a volatile memory element arranged in series with a non-volatile memory element. Writing to an analog memory structure may include a first pulse to the analog memory structure and a second pulse to the analog memory structure. Writing to the analog memory structure may be performed such that a period between the first pulse and the second pulse is smaller than a relaxation rate of the volatile memory element. Thereby, it may be possible to accelerate writing to the analog memory structure.

[0018] An embodiment can include writing to a memory structure including a volatile memory element arranged in series with a non-volatile memory element. Writing to an analog memory structure can include a first pulse to the analog memory structure, a second pulse to the analog memory structure, and a third negative pulse to the analog memory structure. Writing to the analog memory structure may be performed such that a period between the first pulse and the second pulse is smaller than a relaxation rate of the volatile memory element, a period between the second pulse and the third negative pulse is smaller than a relaxation rate of the volatile memory element, and is larger than the first period. Thereby, it may be possible to perform a reset operation of the analog memory structure.

[0019] An embodiment can include writing to a memory structure including a volatile memory element arranged in series with a non-volatile memory element. Writing to an analog memory structure can include a first pulse to the analog memory structure, a second pulse to the analog memory structure, and a third pulse to the analog memory structure. Writing to the analog memory structure may be performed such that a period between the first pulse and the second pulse is smaller than a relaxation rate of the volatile memory element, a period between the second pulse and the third pulse is smaller than a relaxation rate of the volatile memory element, and is larger than the first period. Thereby, it may be possible to approach an analog weight stored in the analog memory structure.

Brief Description of the Drawings

[0020]

Figure 1

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[0021] The elements of the figures are not necessarily to scale and are not intended to depict specific parameters of the present invention. For clarity and ease of illustration, the dimensions of the elements may be exaggerated. For exact dimensions, reference should be made to the detailed description. The drawings are intended to depict only typical embodiments of the present invention and should not be considered as limiting the scope of the present invention. In the drawings, like numerals represent like elements.

Best Mode for Carrying Out the Invention

[0022] Here, the exemplary embodiments will be described more fully herein with reference to the accompanying drawings in which the exemplary embodiments are shown. However, the present disclosure may be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these exemplary embodiments are provided so that this disclosure will be thorough and complete and will fully convey the scope of the disclosure to those skilled in the art. In the description, well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0023] For the following description, terms such as "upper", "lower", "right", "left", "vertical", "horizontal", "top", "bottom", and their derivatives are related to the disclosed structures and methods associated with the drawings. Terms such as "above", "overlying", "atop", "on top", "positioned on", or "positioned atop" mean that a first element, such as a first structure, is present above a second element, such as a second structure, and there may be intervening elements, such as an interface structure, between the first element and the second element. "Direct contact" means that a first element, such as a first structure, and a second element, such as a second structure, are connected without an intermediate conductive layer, insulating layer, or semiconductor layer at the interface of the two elements.

[0024] In order not to obscure the presentation of the embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined together for presentation and explanation, and in some examples, they may not be described in detail. In other examples, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the characteristic features or elements of the various embodiments of the present invention.

[0025] The present invention describes a method and structure for a volatile memristive device, such as a layer of a mixed ionic electronic conduction (MIEC) material, that can be integrated in series with a non-volatile memristive device for neuromorphic computing with accelerated weight updates implemented by hardware. The volatile memory element is composed of a material that causes a conductive transition (such as a metal-insulator transition like a Mott transition) when ions are depleted, resulting in a higher conductivity region. Thereafter, by applying an electric field, the ions in the MIEC layer are polarized, and higher and higher conductivity is obtained.

[0026] When a voltage is applied to the device, the ions are polarized either way by the drift of the electric field. As a result, ions are depleted at one interface and supersaturated at the opposite interface. Specific MIEC materials such as LiCoO 2-x undergo a change in electrical conductivity, becoming metallic due to depletion, and the supersaturated and saturated regions maintain their insulating properties. The entire layer becomes more conductive. When no bias is applied, the ions relax to equilibrium at a rate slower than the time frame of the write cycle (in LiCoO 2-x , 1 ns write, relaxation ~10 - 100 ns).

[0027] For writing to non-volatile memristive devices (such as RRAM), probabilistic pulses can be used. When using consecutive pulses, the volatile memory element becomes polarized, a large current flows through the non-volatile memristive device, enabling "accelerated writing" of the non-volatile element. After writing, the ions begin to relax and the conductivity of the MIEC decreases. If the weight is overvoltage and the polarity of the write pulse switches before complete relaxation, the "rewrite" decelerates before accelerating in the reverse direction and operates to write the weight as if it had inertia.

[0028] Figures 1(A) to 1(C) are diagrams showing the operation of an analog memory structure. Figure 1(A) depicts a memory structure including a first contact 10, a volatile memory element 20, a non-volatile memristive element 30, and a second contact 40. The first contact 10 and the second contact 40 may be vias having any type of conductive line or liner, and may be made of any conductive material such as Cu, W, TiN, TaN, or Ta, for example.

[0029] The non-volatile memristive element 30 may be a bidirectional non-volatile memristive device such as RRAM, CBRAM, ECRAM, or other similar structures. Further, the non-volatile memristive element 30 may be a non-volatile memristive device with a unidirectional structure such as PCM, or other unidirectional structures. Further, although the non-volatile memristive element 30 is depicted as a two-terminal device, if the memristive element has additional terminals (for example, a three-terminal device having different terminals for the read path and the write path), it is desirable to arrange the MIEC material in series with the flow of current in the write path of the memristive element.

[0030] The volatile memory element 20 may be any substance that temporarily changes its resistance when a potential is applied to the substance and returns to its original relaxed resistance state when the potential is removed from the cell. For example, a volatile memory element may become more conductive when a potential is applied to the substance and may return to a relaxed state when the potential is removed from the cell. In an exemplary embodiment, when a potential is applied to the MITMIEC substance, ions may move from one surface to the other surface of the structure and become accelerated, thereby possibly forming depletion regions and saturation regions in the substance. When these regions are formed, the entire layer becomes more conductive, thereby increasing the flow of current across the cell during a write cycle and reducing the number of write cycles required to achieve the desired resistance state of the non-volatile memristive element 30.

[0031] For example, FIG. 1(A) depicts an analog memory structure when the volatile memory element 20 is in a relaxed state because there is no potential between the first contact 10 and the second contact 40. A plurality of mobile ions 50 are depicted as positive charges randomly arranged in the volatile memory element 20. In FIG. 1(B), following the application of a potential across the first contact 10 and the second contact 40, the mobile ions 50 move towards the first contact 10, thereby reducing the resistance of the entire analog memory structure and improving its conductivity. In FIG. 1(C), further movement of the mobile ions 50 towards the surface of the first contact 10 occurs either by a sustained potential across the first contact 10 and the second contact 40 or by additional pulses executed continuously (i.e., in a time shorter than the time required for the volatile memory element 20 to return to the state of FIG. 1(A) and relax), resulting in a further reduction in resistance compared to FIG. 1(B).

[0032] Referring to FIG. 2, an exemplary layout of a material stack is depicted for one embodiment of an analog memory structure. The analog memory structure includes a first contact 10, a volatile memory element 20, a non-volatile memristive element 30, and a second contact 40. The first contact 10 and the second contact may be conductive elements that connect the analog memory structure to other functional elements of a semiconductor structure. For example, the contacts may be word lines, bit lines, vias, or any other conductive structure. The materials of the first contact 10 and the second contact 40 may include copper, aluminum, titanium nitride, tantalum nitride, or tungsten. The volatile memory element 20 can include a first metal layer 21, a volatile memory material layer 22, and a second metal layer 23, but must include at least the volatile memory layer 22.

[0033] The volatile memory material layer 22 may be any material that becomes conductive when a potential is applied to the material and returns to a relaxed state when the potential is removed from the cell. The volatile memory material layer 22 may be defined by the time it takes for the material to return to a relaxed state after the removal of the potential. In an exemplary embodiment, the volatile memory element 20 can return to a relaxed state in less than 1000 ns, more preferably less than 200 ns. The volatile memory material layer 22 may be, for example, an MIEC material including a metal-insulator transition (MIT) MIEC material such as XCoO2, XNbO2, XVO2, XNbO3, X 4x Ti5O 12 , or XSmNiO3 or a combination thereof, where X may be an alkali metal such as Li, Na, or K. The volatile memory element 20 may be about 1 / 10 to about 1 / 1000 of the total thickness of the non-volatile memristive element 30.

[0034] The first metal layer 21 and the second metal layer 23 may be used to prevent ions in the volatile memory material layer 22 from moving out of the layer. The materials of the first metal layer 21 and the second metal layer 23 may include metals, metal nitrides, or other conductive materials. Although the second metal layer 23 is shown separated from the non-volatile memory element 30, it should be noted that this layer (or from another perspective, the first metal layer 21) may also be a metal that functions as part of the non-volatile memory element 30. Further, the first metal layer 21 and the second metal layer 23 may be the same material or different materials depending on the device characteristics. In some embodiments, the second metal layer 23 may include a wiring form portion to another part of the device, or alternatively may be connected to the device wiring, and for this reason, the non-volatile memory element 30 and the volatile memory element 20 are not juxtaposed within a single memory cell.

[0035] Referring to FIG. 3A, a method of using the analog memory structures of FIGS. 1(A) and 2 for accelerated writing is depicted. In step S110, a first electrical pulse is applied to the analog memory structure. The characteristics of the electrical pulse may be based on the characteristics of the write pulse according to the type of non-volatile memristive element 30 used in the analog memory structure. For example, the electrical pulse may be a write pulse of 1 to 10V, 1 to 50ns, a read pulse of 0.05V to 1V, 10 to 100ns, but the voltage and duration may deviate from these ranges based on the type of non-volatile memristive element 30 selected.

[0036] In step S120, before the volatile memory element 20 returns to the relaxed state, a second electrical pulse is applied to the analog memory structure. For example, the second electrical pulse may be applied within about 10 ns after the end of the first electrical pulse and may be performed using the same characteristics as the first electrical pulse. By sending the second electrical pulse closely continuously (i.e., before the relaxation of the volatile memory element 20), the non-volatile memristive element 30 can undergo a greater state change than that which occurred during the first electrical pulse.

[0037] In step S130, before the volatile memory element 20 returns to the relaxed state, a third electrical pulse is applied to the analog memory structure. For example, the third electrical pulse may be applied within less than about 10 ns after the end of the second electrical pulse, and may be performed using the same characteristics as the second electrical pulse. By closely sending the third electrical pulse continuously (i.e., before the relaxation of the volatile memory element 20), the non-volatile memristive element 30 can undergo an increased state change compared to that which occurred during the second electrical pulse.

[0038] Although the method depicted in FIG. 3A shows only three electrical pulses, each pulse changes (i.e., writes to) the state of the non-volatile memristive element 30 more than the pulse before the current pulse including the first pulse until the maximum write speed is achieved when the volatile memory element is given the maximum potential difference. It should be noted that additional pulses can be applied in the manner described above (i.e., before relaxing the volatile memory element 20). Thus, the method of FIG. 3A in combination with the structures of FIGS. 1 and 2A accelerates the write process of the analog memory when performing the write process using write pulses that are executed without giving the volatile memory element 20 time to relax.

[0039] Referring to FIG. 3B, a method of using the analog memory structures of FIGS. 1(A) and 2 for non-accelerated writing is depicted. In step S113, a first electrical pulse is applied to the analog memory structure. The characteristics of the electrical pulse may be based on the characteristics of the write pulse according to the type of non-volatile memristive element 30 used in the analog memory structure. For example, the write pulse is 1 - 10 V, 1 - 100 ns, and the read pulse is 0.05 V - 1 V, 10 - 100 ns, but the voltage and duration may deviate from these ranges based on the type of non-volatile memristive element 30 selected.

[0040] In step S123, after the volatile memory element 20 returns to the relaxed state, a second electrical pulse is applied to the analog memory structure. For example, the second electrical pulse may be applied for at least about 10 ns after the end of the first electrical pulse. By sending the second electrical pulse after the volatile memory element 20 returns to the relaxed state, the non-volatile memristive element 30 can undergo a state change similar to that which occurred during the first electrical pulse.

[0041] It should be noted that the comparison between the method of FIG. 3A and the method of FIG. 3B shows that the analog memory structure achieves a written state accelerated by pulses that continue closely in succession (i.e., before relaxation of the volatile memory element 20), and is not due to a permanent change in the structure of the volatile memory element 20.

[0042] Referring to FIG. 3C, a method of using the analog memory structures of FIGS. 1(A) and 2 to provide a negative pulse is depicted. In step S115, a series of first electrical pulses are applied to the analog memory structure. The characteristics of the electrical pulses may be based on the characteristics of the write pulses according to the type of non-volatile memristive element 30 used in the analog memory structure. For example, the write pulses are 1 - 10 V, 1 - 50 ns, and the read pulses are 0.05 V - 1 V, 10 - 100 ns, although the voltage and duration may deviate from these ranges based on the type of non-volatile memristive element 30 selected. The series of first electrical pulses may be executed 1 ns apart from each other.

[0043] In step S125, after the volatile memory element 20 returns to the relaxed state, a second electrical pulse having a polarity opposite to that of the series of first electrical pulses is applied to the analog memory structure. For example, when the second electrical pulse is applied, it may be applied for at least 10 ns after the end of the series of first electrical pulses. By sending the second electrical pulse after the volatile memory element 20 returns to the relaxed state, the non-volatile memristive element 30 can undergo a state change (in the reverse direction) similar to that which occurred during the first electrical pulse.

[0044] Referring to FIG. 3D, a method of using the analog memory structures of FIGS. 1(A) and 2 during the convergence of the non-volatile memristive element 30 to a weight value is shown. In step S117, a first electrical pulse is applied to the analog memory structure. The characteristics of the electrical pulse may be based on the characteristics of the write pulse according to the type of the non-volatile memristive element 30 used in the analog memory structure. For example, the electrical pulse may be 1 to 10 V and 1 to 50 ns for the write pulse, and 0.05 V to 1 V and 10 to 100 ns for the read pulse, but the voltage and duration may deviate from these ranges based on the type of the non-volatile memristive element 30 selected.

[0045] In step S127, a second electrical pulse is applied to the analog memory structure during a first period after the first pulse. The characteristics of the electrical pulse may be based on the characteristics of the write pulse according to the type of the non-volatile memristive element 30 used in the analog memory structure. For example, the electrical pulse may be 1 to 10 V and 1 to 50 ns for the write pulse, and 0.05 V to 1 V and 10 to 100 ns for the read pulse, but the voltage and duration may deviate from these ranges based on the type of the non-volatile memristive element 30 selected. The first period may be, for example, 1 ns between the first pulse and the second pulse.

[0046] In step S137, a third electrical pulse is applied to the analog memory structure during a second period after the second pulse. The characteristics of the electrical pulse may be based on the characteristics of the write pulse according to the type of the non-volatile memristive element 30 used in the analog memory structure. For example, the electrical pulse may be 1 to 10 V and 1 to 50 ns for the write pulse, and 0.05 V to 1 V and 10 to 100 ns for the read pulse, but the voltage and duration may deviate from these ranges based on the type of the non-volatile memristive element 30 selected. The second period may be, for example, 2 ns between the first pulse and the second pulse. This period may be longer than the first period, but may also be shorter than the relaxation time of the volatile memory element 20.

[0047] Referring to the methods of FIGS. 3A - 3D, each is an exemplary methodology that can be achieved alone or in combination with each other during the writing process.

[0048] Referring to FIGS. 4A - 4B, FIGS. 5A - 5B, FIGS. 6A - 6B, and FIGS. 7A - 7B, exemplary embodiments of volatile memory elements included in non - volatile memristive devices are depicted. The following non - exhaustive examples are suggestive of how a volatile memory element can be introduced into a typical shape of an existing non - volatile memristive device, but one of ordinary skill in the art will understand how to apply such concepts to other structures. Further, such non - volatile memristive devices can be used as part of a cross - point array powered using a transistor or any other arrangement of analog memory cells.

[0049] Referring to FIGS. 4A and 4B, an exemplary embodiment of a bidirectional analog memory structure used in a resistive random access memory (RRAM) is depicted, but the concepts shown in the exemplary RRAM embodiments are understood to be applicable to all bidirectional analog memory structures. A structure having a volatile memory element 320 is depicted. The RRAM device includes a conductive element 331 and a dielectric switching layer 330. The depicted RRAM structure has a bottom contact 310 and a top contact 340 located between insulating dielectrics 300. The RRAM device can have the volatile memory element 320 either between the bottom contact 310 and the dielectric switching layer 330 as depicted in FIG. 4A or between the top contact 340 and the conductive element 331 as depicted in the volatile memory element of FIG. 4B. The volatile memory element 320 can include a metal layer similar to that depicted in FIG. 2, but must include at least a volatile memory layer.

[0050] Referring to FIGS. 5A and 5B, the bidirectional analog memory structure is depicted as being used in an electrochemical random access memory (ECRAM), although the concepts shown in the exemplary ECRAM embodiments are understood to apply to all bidirectional analog memory structures. Further, FIG. 5B is shown to explain the use of volatile memory elements in a symmetric device. The ECRAM structure includes an ion gate material 431 sandwiched between a first ion reservoir 430 and a second ion reservoir 432. The first ion reservoir 430 and the second ion reservoir 432 can be made of materials having the same chemical composition, different chemical compositions, or similar chemical compositions with different ion or dopant concentrations. The depicted ECRAM structure has a bottom contact 410 and a top contact 440 located between insulating dielectrics 400. The ECRAM structure may have a volatile memory element 420 anywhere between the ion reservoir 430 / 432 and the contact, such as between the first ion reservoir 430 and the bottom contact 410 as depicted in FIG. 5A. Further, the volatile memory element 420 may be between the first ion reservoir 430 and the second ion reservoir 432 and their respective contacts, as depicted in FIG. 5B, thereby forming a symmetric structure. The volatile memory element 420 may include a metal layer similar to that depicted in FIG. 2, but must include at least a volatile memory layer.

[0051] Referring to FIGS. 6A and 6B, an exemplary embodiment of a unidirectional analog memory structure is depicted as being used in a mushroom PCM structure, although the concepts shown in the exemplary mushroom PCM embodiments are understood to apply to all unidirectional analog memory structures. The mushroom PCM device includes a heating element 531 and a dielectric layer 532 located beneath a phase change material 530. The depicted mushroom PCM structure has a bottom contact 510 and a top contact 540 located between insulating dielectrics 550. The mushroom PCM device may have a volatile memory element 520 between the bottom contact 510 and the heating element 531, as depicted in FIG. 6A, or may have a volatile memory element 520 between the top contact 540 and the phase change material 530, as depicted in FIG. 6B. The volatile memory element 520 can include metal layers similar to those depicted in FIG. 2, but must include at least a volatile memory layer.

[0052] Referring to FIGS. 7A and 7B, an exemplary embodiment of a three-terminal analog memory structure as used in an electrochemically random access memory (ECRAM) structure having a volatile memory element is depicted. However, the concepts shown in the exemplary three-terminal ECRAM are understood to be applicable to all three-terminal analog memory structures. The depicted ECRAM structure has drain contacts 610, read contacts 641, and write contacts 640 located between insulating dielectrics 650, 651. The ECRAM structure may have an electrolyte layer 631 and a channel 630. In such an embodiment where the read path (i.e., the flow of current from the read contact 641 to the drain contact 610) and the write path (i.e., the flow of current from the write contact 640 to the drain contact 610) are different, the volatile memory element 620 will be disposed at least in the write path. For example, as depicted in FIG. 7A, the volatile memory element 620 is located between the write contact 640 and the electrolyte layer 631 and can thus be located only in the write path. Alternatively, as depicted in FIG. 7B, the volatile memory element 620 is located at the drain contact 610 and can thus be located in both the read path and the write path. The volatile memory element 620 may include a metal layer similar to that depicted in FIG. 2 but must include at least a volatile memory layer.

[0053] The formation of the volatile memory element as part of the overall formation process of each non-volatile memristive device structure may be achieved by depositing the volatile memory element at the appropriate location (e.g., before the deposition of the non-volatile memristive device layer as depicted in FIG. 5A, after the non-volatile memristive device layer as depicted in FIG. 5B) prior to patterning the structure to form the contacts. The deposition of the volatile memory element may be achieved by PVD depositions such as pulsed laser deposition, sputter deposition, chemical vapor deposition, MOCVD, solution deposition, etc.

[0054] The descriptions of the various embodiments of the present invention are presented for illustrative purposes, but are not intended to be exhaustive or to limit the invention to the disclosed embodiments. It will be apparent to those skilled in the art that many modifications and variations can be made without departing from the scope of the described embodiments. The terms used herein are chosen to best explain the principles of the embodiments, the practical application to or technical improvement of technologies seen in the market, or to enable those skilled in the art to understand the embodiments disclosed herein. Therefore, the present invention is not intended to be limited to the exact forms and details described and illustrated, but is intended to fall within the scope of the appended claims.

Claims

1. Comprising a volatile memory element in series with a non-volatile memory element, The volatile memory element has a structure including a MITMIEC material that temporarily changes resistance when a potential is applied to the material and returns to a relaxed state when the potential is removed.

2. The structure according to claim 1, wherein the non-volatile memory element includes a memristive device.

3. The structure according to claim 1, wherein the volatile memory element includes the MITMIEC material whose conductivity increases when a potential is applied to the material.

4. The structure according to claim 1, wherein the volatile memory element includes a volatile memory layer located between a first conductive layer and a second conductive layer.

5. The structure according to claim 1, wherein the volatile memory element includes a volatile memory layer, and the material of the volatile memory layer includes the MITMIEC material.

6. The volatile memory element includes a volatile memory layer, and the material of the volatile memory layer is XCoO ２ , XNbO ２ , XVO ２ , XNbO ３ , X4nTi5O12, or XSmNiO ３ The structure according to claim 1, wherein X is an alkali metal and is selected from the group consisting of or a combination thereof.

7. The structure according to claim 1, wherein the non-volatile memory element is part of a three-terminal device, and the volatile memory element is arranged in a writing path of the three-terminal device.

8. The structure according to claim 2, wherein the non-volatile memory element includes a bidirectional non-volatile memory.

9. The structure according to claim 2, wherein the non-volatile memory element includes a unidirectional non-volatile memory.

10. The structure according to claim 2, wherein the non-volatile memory element includes a resistive random access memory (RRAM).

11. The structure according to claim 2, wherein the non-volatile memory element includes a conductive bridging random access memory (CBRAM).

12. The structure according to claim 2, wherein the non-volatile memory element includes an electrochemical random access memory (ECRAM).

13. The structure according to claim 2, wherein the non-volatile memory element includes a phase change memory (PCM).

14. Comprising a volatile memory layer in series with a non-volatile memristive element, The volatile memory layer has a structure including a MITMIEC material that temporarily changes resistance when a potential is applied to the material and returns to a relaxed state when the potential is removed.

15. The structure according to claim 14, wherein the volatile memory layer includes the MITMIEC material whose conductivity increases when a potential is applied to the material.

16. The structure according to claim 14, wherein the volatile memory layer is located between a first conductive layer and a second conductive layer.

17. The material of the volatile memory layer is XCoO ２ , XNbO ２ , XVO ２ , XNbO ３ , X4nTi5O12, or XSmNiO ３ The structure according to claim 14, selected from the group comprising or a combination thereof, wherein X is an alkali metal.

18. A three-terminal analog memory structure including a volatile memory element connected in series with a non-volatile memory element, wherein the volatile memory element contains a MITMIEC substance that temporarily changes its resistance when a potential is applied to the substance and returns to a relaxed state when the potential is removed, the three-terminal analog memory structure includes a drain contact, a read contact, and a write contact, and the current flow along the write path of the three-terminal analog memory structure is different from the current flow along the read path of the three-terminal analog memory structure.

19. Applying a first pulse to the analog memory structure, wherein the analog memory structure includes a volatile memory element and a non-volatile memristive element arranged in series, and the volatile memory element contains a MITMIEC substance that temporarily changes its resistance when a potential is applied to the substance and returns to a relaxed state when the potential is removed. Applying a second pulse to the analog memory structure, wherein the period between the first pulse and the second pulse is smaller than the relaxation rate of the volatile memory element. A method of writing to a memory structure including the above.

20. Applying a third pulse to the analog memory structure, wherein the period between the second pulse and the third pulse is substantially the same as the period between the first pulse and the second pulse. The method according to claim 19, further including this.

21. Applying a first pulse to the analog memory structure, wherein the analog memory structure includes a volatile memory element and a non-volatile memristive element arranged in series, and the volatile memory element contains a MITMIEC substance that temporarily changes its resistance when a potential is applied to the substance and returns to a relaxed state when the potential is removed. Applying a second pulse to the analog memory structure, wherein a first period between the first pulse and the second pulse is smaller than the relaxation rate of the volatile memory element. Applying a third negative pulse to the analog memory structure, wherein a second period between the second pulse and the third negative pulse is smaller than the relaxation rate of the volatile memory element and larger than the first period. A method of writing to a memory structure including the above.

22. Before the first pulse, applying a plurality of pulses to the analog memory structure, wherein each pulse is substantially the same and the pulse intervals are substantially the same, the method according to claim 21, further comprising applying.

23. Applying a first pulse to an analog memory structure, wherein the analog memory structure includes a volatile memory element and a non-volatile memristive element arranged in series, and the volatile memory element includes a MITMIECC substance that temporarily changes resistance when a potential is applied to the substance and returns to a relaxed state when the potential is removed, applying. Applying a second pulse to the analog memory structure, wherein a first period between the first pulse and the second pulse is smaller than a relaxation rate of the volatile memory element, applying. Applying a third pulse to the analog memory structure, wherein a second period between the second pulse and the third pulse is smaller than the relaxation rate of the volatile memory element and larger than the first period, a method of writing to an analog memory structure including applying.

24. Before the first pulse, applying a plurality of pulses to the analog memory structure, wherein each pulse is substantially the same and the pulse intervals are substantially the same, applying, the method according to claim 23, further comprising applying.

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